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Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll')
-rw-r--r--llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll72
1 files changed, 0 insertions, 72 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
index 5cf9c9faa693..ad0babd74f9c 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
@@ -185,8 +185,6 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX11W64-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: add_i32_constant:
@@ -216,8 +214,6 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX11W32-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: add_i32_constant:
@@ -250,8 +246,6 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: add_i32_constant:
@@ -284,8 +278,6 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: v_mad_u32_u24 v0, v0, 5, s2
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -471,8 +463,6 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W64-NEXT: v_mad_u64_u32 v[1:2], null, s6, v0, s[2:3]
; GFX11W64-NEXT: v_mov_b32_e32 v0, 0
; GFX11W64-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: add_i32_uniform:
@@ -503,8 +493,6 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W32-NEXT: v_mad_u64_u32 v[1:2], null, s0, v0, s[4:5]
; GFX11W32-NEXT: v_mov_b32_e32 v0, 0
; GFX11W32-NEXT: global_store_b32 v0, v1, s[2:3]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: add_i32_uniform:
@@ -538,8 +526,6 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
; GFX12W64-NEXT: v_mov_b32_e32 v1, 0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: add_i32_uniform:
@@ -573,8 +559,6 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 %additive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -831,8 +815,6 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX11W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: add_i32_varying_vdata:
@@ -875,8 +857,6 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX11W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: add_i32_varying_vdata:
@@ -923,8 +903,6 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: add_i32_varying_vdata:
@@ -971,8 +949,6 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1245,8 +1221,6 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX11W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: struct_add_i32_varying_vdata:
@@ -1291,8 +1265,6 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX11W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: struct_add_i32_varying_vdata:
@@ -1342,8 +1314,6 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: struct_add_i32_varying_vdata:
@@ -1392,8 +1362,6 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1466,8 +1434,6 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX11W64-NEXT: v_mov_b32_e32 v0, 0
; GFX11W64-NEXT: s_waitcnt vmcnt(0)
; GFX11W64-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: add_i32_varying_offset:
@@ -1481,8 +1447,6 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX11W32-NEXT: v_mov_b32_e32 v0, 0
; GFX11W32-NEXT: s_waitcnt vmcnt(0)
; GFX11W32-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: add_i32_varying_offset:
@@ -1497,8 +1461,6 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W64-NEXT: v_mov_b32_e32 v0, 0
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: add_i32_varying_offset:
@@ -1512,8 +1474,6 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: v_mov_b32_e32 v0, 0
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1697,8 +1657,6 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX11W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: sub_i32_constant:
@@ -1729,8 +1687,6 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX11W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: sub_i32_constant:
@@ -1764,8 +1720,6 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: sub_i32_constant:
@@ -1799,8 +1753,6 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -1987,8 +1939,6 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: sub_i32_uniform:
@@ -2020,8 +1970,6 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX11W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX11W32-NEXT: global_store_b32 v1, v0, s[2:3]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: sub_i32_uniform:
@@ -2056,8 +2004,6 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: sub_i32_uniform:
@@ -2091,8 +2037,6 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 %subitive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -2349,8 +2293,6 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX11W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX11W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: sub_i32_varying_vdata:
@@ -2394,8 +2336,6 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX11W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX11W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX11W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: sub_i32_varying_vdata:
@@ -2442,8 +2382,6 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W64-NEXT: s_wait_kmcnt 0x0
; GFX12W64-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: sub_i32_varying_vdata:
@@ -2491,8 +2429,6 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s2, v0
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
@@ -2565,8 +2501,6 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX11W64-NEXT: v_mov_b32_e32 v0, 0
; GFX11W64-NEXT: s_waitcnt vmcnt(0)
; GFX11W64-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11W64-NEXT: s_nop 0
-; GFX11W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W64-NEXT: s_endpgm
;
; GFX11W32-LABEL: sub_i32_varying_offset:
@@ -2580,8 +2514,6 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX11W32-NEXT: v_mov_b32_e32 v0, 0
; GFX11W32-NEXT: s_waitcnt vmcnt(0)
; GFX11W32-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX11W32-NEXT: s_nop 0
-; GFX11W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX11W32-NEXT: s_endpgm
;
; GFX12W64-LABEL: sub_i32_varying_offset:
@@ -2596,8 +2528,6 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W64-NEXT: v_mov_b32_e32 v0, 0
; GFX12W64-NEXT: s_wait_loadcnt 0x0
; GFX12W64-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12W64-NEXT: s_nop 0
-; GFX12W64-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W64-NEXT: s_endpgm
;
; GFX12W32-LABEL: sub_i32_varying_offset:
@@ -2611,8 +2541,6 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: v_mov_b32_e32 v0, 0
; GFX12W32-NEXT: s_wait_loadcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
-; GFX12W32-NEXT: s_nop 0
-; GFX12W32-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
; GFX12W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 10:04:01 +0000