diff options
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll | 3647 |
1 files changed, 3038 insertions, 609 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll index 2226fd20fb77..302b2395642d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll @@ -7,12 +7,215 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1 ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; CI-NEXT: ; implicit-def: $vgpr1 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_load_dword s2, s[2:3], 0x0 ; CI-NEXT: s_load_dword s3, s[4:5], 0x2 +; CI-NEXT: s_mov_b32 s4, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_cvt_f32_f16_e32 v0, s2 -; CI-NEXT: v_cvt_f32_f16_e32 v1, s3 +; CI-NEXT: v_cvt_f32_f16_e64 v2, |s2| +; CI-NEXT: v_cvt_f32_f16_e64 v0, |s3| +; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v0 +; CI-NEXT: s_cbranch_vccz .LBB0_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: s_and_b32 s4, s2, 0x8000 +; CI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v0 +; CI-NEXT: v_mov_b32_e32 v1, s4 +; CI-NEXT: v_mov_b32_e32 v3, s2 +; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; CI-NEXT: s_mov_b32 s4, 0 +; CI-NEXT: .LBB0_2: ; %Flow18 +; CI-NEXT: s_xor_b32 s4, s4, 1 +; CI-NEXT: s_cmp_lg_u32 s4, 0 +; CI-NEXT: s_cbranch_scc1 .LBB0_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f32_e32 v1, v2 +; CI-NEXT: v_ldexp_f32_e64 v4, v1, 11 +; CI-NEXT: v_frexp_mant_f32_e32 v1, v0 +; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1 +; CI-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v0 +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5 +; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0 +; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; CI-NEXT: v_rcp_f32_e32 v8, v3 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; CI-NEXT: v_fma_f32 v8, v9, v8, v8 +; CI-NEXT: v_mul_f32_e32 v9, v7, v8 +; CI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; CI-NEXT: v_fma_f32 v9, v10, v8, v9 +; CI-NEXT: v_fma_f32 v3, -v3, v9, v7 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2 +; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB0_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v2, vcc, 11, v5 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CI-NEXT: .LBB0_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: v_mul_f32_e32 v4, v5, v3 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v6, v4, v1 +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2 +; CI-NEXT: v_ldexp_f32_e64 v4, v4, 11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2 +; CI-NEXT: s_cbranch_vccnz .LBB0_5 +; CI-NEXT: s_branch .LBB0_7 +; CI-NEXT: .LBB0_6: +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: .LBB0_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v2, vcc, -10, v2 +; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2 +; CI-NEXT: v_mul_f32_e32 v3, v2, v3 +; CI-NEXT: v_rndne_f32_e32 v3, v3 +; CI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; CI-NEXT: v_add_f32_e32 v1, v2, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0 +; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; CI-NEXT: s_and_b32 s4, s2, 0x8000 +; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; CI-NEXT: v_or_b32_e32 v1, s4, v0 +; CI-NEXT: .LBB0_8: ; %Flow19 +; CI-NEXT: v_cvt_f32_f16_e32 v0, s3 +; CI-NEXT: v_cvt_f32_f16_e32 v2, 0 +; CI-NEXT: s_and_b32 s2, s2, 0x7fff +; CI-NEXT: s_cmpk_lg_i32 s2, 0x7c00 +; CI-NEXT: s_cselect_b32 s2, 1, 0 +; CI-NEXT: v_cmp_nlg_f32_e32 vcc, v0, v2 +; CI-NEXT: v_mov_b32_e32 v0, 0x7e00 +; CI-NEXT: s_and_b32 s2, 1, s2 +; CI-NEXT: v_cndmask_b32_e32 v1, v1, v0, vcc +; CI-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CI-NEXT: s_mov_b32 s2, -1 +; CI-NEXT: s_mov_b32 s3, 0xf000 +; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; CI-NEXT: s_endpgm +; +; VI-LABEL: frem_f16: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34 +; VI-NEXT: ; implicit-def: $vgpr2 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: s_load_dword s0, s[10:11], 0x0 +; VI-NEXT: s_load_dword s1, s[2:3], 0x8 +; VI-NEXT: s_mov_b32 s2, 1 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_cvt_f32_f16_e64 v1, |s0| +; VI-NEXT: v_cvt_f32_f16_e64 v0, |s1| +; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v1, v0 +; VI-NEXT: s_cbranch_vccz .LBB0_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: s_and_b32 s2, s0, 0x8000 +; VI-NEXT: v_cmp_eq_f32_e32 vcc, v1, v0 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB0_2: ; %Flow18 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB0_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f32_e32 v2, v1 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v5, v1 +; VI-NEXT: v_frexp_mant_f32_e32 v1, v0 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v0 +; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v5 +; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6 +; VI-NEXT: v_ldexp_f32 v1, v1, 1 +; VI-NEXT: v_ldexp_f32 v4, v2, 11 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v3, v0 +; VI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0 +; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; VI-NEXT: v_rcp_f32_e32 v8, v3 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; VI-NEXT: v_fma_f32 v8, v9, v8, v8 +; VI-NEXT: v_mul_f32_e32 v9, v7, v8 +; VI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; VI-NEXT: v_fma_f32 v9, v10, v8, v9 +; VI-NEXT: v_fma_f32 v3, -v3, v9, v7 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2 +; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB0_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v2, vcc, 11, v5 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6 +; VI-NEXT: .LBB0_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: v_mul_f32_e32 v4, v5, v3 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v6, v4, v1 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2 +; VI-NEXT: v_ldexp_f32 v4, v4, 11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2 +; VI-NEXT: s_cbranch_vccnz .LBB0_5 +; VI-NEXT: s_branch .LBB0_7 +; VI-NEXT: .LBB0_6: +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: .LBB0_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v2, vcc, -10, v2 +; VI-NEXT: v_ldexp_f32 v2, v5, v2 +; VI-NEXT: v_mul_f32_e32 v3, v2, v3 +; VI-NEXT: v_rndne_f32_e32 v3, v3 +; VI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; VI-NEXT: v_add_f32_e32 v1, v2, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; VI-NEXT: v_ldexp_f32 v0, v1, v0 +; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; VI-NEXT: s_and_b32 s2, s0, 0x8000 +; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; VI-NEXT: v_or_b32_e32 v2, s2, v0 +; VI-NEXT: .LBB0_8: ; %Flow19 +; VI-NEXT: v_mov_b32_e32 v0, 0x7c00 +; VI-NEXT: v_cmp_nlg_f16_e64 vcc, s1, 0 +; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |s0|, v0 +; VI-NEXT: v_mov_b32_e32 v0, 0x7e00 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v0, vcc +; VI-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1] +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: s_endpgm + %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4 + %r0 = load half, ptr addrspace(1) %in1, align 4 + %r1 = load half, ptr addrspace(1) %gep2, align 4 + %r2 = frem half %r0, %r1 + store half %r2, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { +; CI-LABEL: fast_frem_f16: +; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: s_load_dword s6, s[2:3], 0x0 +; CI-NEXT: s_load_dword s4, s[4:5], 0x2 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_cvt_f32_f16_e32 v0, s6 +; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 ; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 ; CI-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0 ; CI-NEXT: v_rcp_f32_e32 v4, v2 @@ -27,15 +230,21 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1 ; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_div_fixup_f32 v2, v2, v1, v0 -; CI-NEXT: v_trunc_f32_e32 v2, v2 -; CI-NEXT: v_fma_f32 v0, -v2, v1, v0 +; CI-NEXT: v_div_fixup_f32 v0, v2, v1, v0 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; CI-NEXT: v_cvt_f16_f32_e64 v0, -v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 +; CI-NEXT: v_cvt_f32_f16_e32 v2, s6 +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_trunc_f32_e32 v0, v0 +; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_fma_f32 v0, v0, v1, v2 ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; CI-NEXT: s_endpgm ; -; VI-LABEL: frem_f16: +; VI-LABEL: fast_frem_f16: ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 @@ -65,33 +274,51 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1 %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4 %r0 = load half, ptr addrspace(1) %in1, align 4 %r1 = load half, ptr addrspace(1) %gep2, align 4 - %r2 = frem half %r0, %r1 + %r2 = frem fast half %r0, %r1 store half %r2, ptr addrspace(1) %out, align 4 ret void } -define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { -; CI-LABEL: fast_frem_f16: +define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #1 { +; CI-LABEL: unsafe_frem_f16: ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: s_load_dword s2, s[2:3], 0x0 -; CI-NEXT: s_load_dword s3, s[4:5], 0x2 +; CI-NEXT: s_load_dword s6, s[2:3], 0x0 +; CI-NEXT: s_load_dword s4, s[4:5], 0x2 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_cvt_f32_f16_e32 v0, s2 -; CI-NEXT: v_cvt_f32_f16_e32 v1, s3 +; CI-NEXT: v_cvt_f32_f16_e32 v0, s6 +; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 +; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 +; CI-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0 +; CI-NEXT: v_rcp_f32_e32 v4, v2 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 +; CI-NEXT: v_fma_f32 v4, v5, v4, v4 +; CI-NEXT: v_mul_f32_e32 v5, v3, v4 +; CI-NEXT: v_fma_f32 v6, -v2, v5, v3 +; CI-NEXT: v_fma_f32 v5, v6, v4, v5 +; CI-NEXT: v_fma_f32 v2, -v2, v5, v3 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_rcp_f32_e32 v2, v1 -; CI-NEXT: v_mul_f32_e32 v2, v0, v2 -; CI-NEXT: v_trunc_f32_e32 v2, v2 -; CI-NEXT: v_fma_f32 v0, -v2, v1, v0 +; CI-NEXT: v_div_fixup_f32 v0, v2, v1, v0 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; CI-NEXT: v_cvt_f16_f32_e64 v0, -v0 +; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 +; CI-NEXT: v_cvt_f32_f16_e32 v2, s6 +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_trunc_f32_e32 v0, v0 +; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 +; CI-NEXT: v_fma_f32 v0, v0, v1, v2 ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; CI-NEXT: s_endpgm ; -; VI-LABEL: fast_frem_f16: +; VI-LABEL: unsafe_frem_f16: ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 @@ -99,11 +326,21 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) ; VI-NEXT: s_load_dword s2, s[2:3], 0x0 ; VI-NEXT: s_load_dword s3, s[4:5], 0x8 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v1, s2 -; VI-NEXT: v_rcp_f16_e32 v0, s3 -; VI-NEXT: v_mul_f16_e32 v0, s2, v0 +; VI-NEXT: v_cvt_f32_f16_e32 v0, s2 +; VI-NEXT: v_cvt_f32_f16_e32 v2, s3 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_rcp_f32_e32 v3, v2 +; VI-NEXT: v_mul_f32_e32 v4, v0, v3 +; VI-NEXT: v_mad_f32 v5, -v2, v4, v0 +; VI-NEXT: v_mac_f32_e32 v4, v5, v3 +; VI-NEXT: v_mad_f32 v0, -v2, v4, v0 +; VI-NEXT: v_mul_f32_e32 v0, v0, v3 +; VI-NEXT: v_and_b32_e32 v0, 0xff800000, v0 +; VI-NEXT: v_add_f32_e32 v0, v0, v4 +; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 +; VI-NEXT: v_div_fixup_f16 v0, v0, v1, s2 ; VI-NEXT: v_trunc_f16_e32 v0, v0 -; VI-NEXT: v_fma_f16 v2, -v0, s3, v1 +; VI-NEXT: v_fma_f16 v2, -v0, v1, s2 ; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: flat_store_short v[0:1], v2 @@ -111,59 +348,209 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4 %r0 = load half, ptr addrspace(1) %in1, align 4 %r1 = load half, ptr addrspace(1) %gep2, align 4 - %r2 = frem fast half %r0, %r1 + %r2 = frem afn half %r0, %r1 store half %r2, ptr addrspace(1) %out, align 4 ret void } -define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #1 { -; CI-LABEL: unsafe_frem_f16: +define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { +; CI-LABEL: frem_f32: ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_load_dword s2, s[2:3], 0x0 -; CI-NEXT: s_load_dword s3, s[4:5], 0x2 +; CI-NEXT: s_load_dword s3, s[4:5], 0x4 +; CI-NEXT: s_mov_b32 s4, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_cvt_f32_f16_e32 v0, s2 -; CI-NEXT: v_cvt_f32_f16_e32 v1, s3 +; CI-NEXT: v_mov_b32_e32 v0, s3 +; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0| +; CI-NEXT: ; implicit-def: $vgpr0 +; CI-NEXT: s_cbranch_vccz .LBB3_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: s_and_b32 s4, s2, 0x80000000 +; CI-NEXT: v_mov_b32_e32 v1, s3 +; CI-NEXT: v_mov_b32_e32 v0, s2 +; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1| +; CI-NEXT: v_mov_b32_e32 v1, s4 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CI-NEXT: s_mov_b32 s4, 0 +; CI-NEXT: .LBB3_2: ; %Flow16 +; CI-NEXT: s_xor_b32 s4, s4, 1 +; CI-NEXT: s_cmp_lg_u32 s4, 0 +; CI-NEXT: s_cbranch_scc1 .LBB3_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f32_e64 v1, |s3| +; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1 +; CI-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0 +; CI-NEXT: v_frexp_mant_f32_e64 v0, |s2| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3| +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5 +; CI-NEXT: v_ldexp_f32_e64 v4, v0, 12 +; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0 +; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; CI-NEXT: v_rcp_f32_e32 v8, v3 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; CI-NEXT: v_fma_f32 v8, v9, v8, v8 +; CI-NEXT: v_mul_f32_e32 v9, v7, v8 +; CI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; CI-NEXT: v_fma_f32 v9, v10, v8, v9 +; CI-NEXT: v_fma_f32 v3, -v3, v9, v7 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2 +; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB3_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v2, vcc, 12, v5 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CI-NEXT: .LBB3_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: v_mul_f32_e32 v4, v5, v3 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v6, v4, v1 +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; CI-NEXT: v_add_i32_e32 v2, vcc, -12, v2 +; CI-NEXT: v_ldexp_f32_e64 v4, v4, 12 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2 +; CI-NEXT: s_cbranch_vccnz .LBB3_5 +; CI-NEXT: s_branch .LBB3_7 +; CI-NEXT: .LBB3_6: +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: .LBB3_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2 +; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2 +; CI-NEXT: v_mul_f32_e32 v3, v2, v3 +; CI-NEXT: v_rndne_f32_e32 v3, v3 +; CI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; CI-NEXT: v_add_f32_e32 v1, v2, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0 +; CI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; CI-NEXT: s_and_b32 s4, s2, 0x80000000 +; CI-NEXT: v_or_b32_e32 v0, s4, v0 +; CI-NEXT: .LBB3_8: ; %Flow17 +; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s3, 0 +; CI-NEXT: v_mov_b32_e32 v1, 0x7fc00000 +; CI-NEXT: v_mov_b32_e32 v2, 0x7f800000 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v2 +; CI-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_rcp_f32_e32 v2, v1 -; CI-NEXT: v_mul_f32_e32 v2, v0, v2 -; CI-NEXT: v_trunc_f32_e32 v2, v2 -; CI-NEXT: v_fma_f32 v0, -v2, v1, v0 -; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 -; CI-NEXT: buffer_store_short v0, off, s[0:3], 0 +; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; CI-NEXT: s_endpgm ; -; VI-LABEL: unsafe_frem_f16: +; VI-LABEL: frem_f32: ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_load_dword s2, s[2:3], 0x0 -; VI-NEXT: s_load_dword s3, s[4:5], 0x8 +; VI-NEXT: s_load_dword s3, s[4:5], 0x10 +; VI-NEXT: s_mov_b32 s4, 1 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v1, s2 -; VI-NEXT: v_rcp_f16_e32 v0, s3 -; VI-NEXT: v_mul_f16_e32 v0, s2, v0 -; VI-NEXT: v_trunc_f16_e32 v0, v0 -; VI-NEXT: v_fma_f16 v2, -v0, s3, v1 +; VI-NEXT: v_mov_b32_e32 v0, s3 +; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0| +; VI-NEXT: ; implicit-def: $vgpr0 +; VI-NEXT: s_cbranch_vccz .LBB3_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: s_and_b32 s4, s2, 0x80000000 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1| +; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; VI-NEXT: s_mov_b32 s4, 0 +; VI-NEXT: .LBB3_2: ; %Flow16 +; VI-NEXT: s_xor_b32 s4, s4, 1 +; VI-NEXT: s_cmp_lg_u32 s4, 0 +; VI-NEXT: s_cbranch_scc1 .LBB3_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f32_e64 v1, |s3| +; VI-NEXT: v_ldexp_f32 v1, v1, 1 +; VI-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0 +; VI-NEXT: v_frexp_mant_f32_e64 v0, |s2| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3| +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5 +; VI-NEXT: v_ldexp_f32 v4, v0, 12 +; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0 +; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; VI-NEXT: v_rcp_f32_e32 v8, v3 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; VI-NEXT: v_fma_f32 v8, v9, v8, v8 +; VI-NEXT: v_mul_f32_e32 v9, v7, v8 +; VI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; VI-NEXT: v_fma_f32 v9, v10, v8, v9 +; VI-NEXT: v_fma_f32 v3, -v3, v9, v7 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2 +; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB3_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v5 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6 +; VI-NEXT: .LBB3_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: v_mul_f32_e32 v4, v5, v3 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v6, v4, v1 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, -12, v2 +; VI-NEXT: v_ldexp_f32 v4, v4, 12 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2 +; VI-NEXT: s_cbranch_vccnz .LBB3_5 +; VI-NEXT: s_branch .LBB3_7 +; VI-NEXT: .LBB3_6: +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: .LBB3_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2 +; VI-NEXT: v_ldexp_f32 v2, v5, v2 +; VI-NEXT: v_mul_f32_e32 v3, v2, v3 +; VI-NEXT: v_rndne_f32_e32 v3, v3 +; VI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; VI-NEXT: v_add_f32_e32 v1, v2, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; VI-NEXT: v_ldexp_f32 v0, v1, v0 +; VI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; VI-NEXT: s_and_b32 s4, s2, 0x80000000 +; VI-NEXT: v_or_b32_e32 v0, s4, v0 +; VI-NEXT: .LBB3_8: ; %Flow17 +; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s3, 0 +; VI-NEXT: v_mov_b32_e32 v1, 0x7fc00000 +; VI-NEXT: v_mov_b32_e32 v2, 0x7f800000 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v2 +; VI-NEXT: v_cndmask_b32_e32 v2, v1, v0, vcc ; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: flat_store_short v[0:1], v2 +; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: s_endpgm - %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4 - %r0 = load half, ptr addrspace(1) %in1, align 4 - %r1 = load half, ptr addrspace(1) %gep2, align 4 - %r2 = frem afn half %r0, %r1 - store half %r2, ptr addrspace(1) %out, align 4 + %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4 + %r0 = load float, ptr addrspace(1) %in1, align 4 + %r1 = load float, ptr addrspace(1) %gep2, align 4 + %r2 = frem float %r0, %r1 + store float %r2, ptr addrspace(1) %out, align 4 ret void } -define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { -; CI-LABEL: frem_f32: +define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { +; CI-LABEL: fast_frem_f32: ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd @@ -192,7 +579,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; CI-NEXT: s_endpgm ; -; VI-LABEL: frem_f32: +; VI-LABEL: fast_frem_f32: ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 @@ -223,43 +610,65 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1 %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4 %r0 = load float, ptr addrspace(1) %in1, align 4 %r1 = load float, ptr addrspace(1) %gep2, align 4 - %r2 = frem float %r0, %r1 + %r2 = frem fast float %r0, %r1 store float %r2, ptr addrspace(1) %out, align 4 ret void } -define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { -; CI-LABEL: fast_frem_f32: +define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #1 { +; CI-LABEL: unsafe_frem_f32: ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: s_load_dword s2, s[2:3], 0x0 -; CI-NEXT: s_load_dword s3, s[4:5], 0x4 +; CI-NEXT: s_load_dword s6, s[2:3], 0x0 +; CI-NEXT: s_load_dword s2, s[4:5], 0x4 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_mov_b32_e32 v1, s2 -; CI-NEXT: v_rcp_f32_e32 v0, s3 -; CI-NEXT: v_mul_f32_e32 v0, s2, v0 -; CI-NEXT: v_trunc_f32_e32 v0, v0 -; CI-NEXT: v_fma_f32 v0, -v0, s3, v1 +; CI-NEXT: v_mov_b32_e32 v0, s2 +; CI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6 +; CI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6 +; CI-NEXT: v_rcp_f32_e32 v3, v1 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 +; CI-NEXT: v_fma_f32 v3, v4, v3, v3 +; CI-NEXT: v_mul_f32_e32 v4, v2, v3 +; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 +; CI-NEXT: v_fma_f32 v4, v5, v3, v4 +; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 +; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 +; CI-NEXT: v_div_fixup_f32 v1, v1, v0, s6 +; CI-NEXT: v_trunc_f32_e32 v1, v1 +; CI-NEXT: v_fma_f32 v0, -v1, v0, s6 ; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; CI-NEXT: s_endpgm ; -; VI-LABEL: fast_frem_f32: +; VI-LABEL: unsafe_frem_f32: ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_load_dword s2, s[2:3], 0x0 -; VI-NEXT: s_load_dword s3, s[4:5], 0x10 +; VI-NEXT: s_load_dword s6, s[2:3], 0x0 +; VI-NEXT: s_load_dword s2, s[4:5], 0x10 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v1, s2 -; VI-NEXT: v_rcp_f32_e32 v0, s3 -; VI-NEXT: v_mul_f32_e32 v0, s2, v0 -; VI-NEXT: v_trunc_f32_e32 v0, v0 -; VI-NEXT: v_fma_f32 v2, -v0, s3, v1 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s6 +; VI-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6 +; VI-NEXT: v_rcp_f32_e32 v3, v1 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 +; VI-NEXT: v_fma_f32 v3, v4, v3, v3 +; VI-NEXT: v_mul_f32_e32 v4, v2, v3 +; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 +; VI-NEXT: v_fma_f32 v4, v5, v3, v4 +; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 +; VI-NEXT: v_div_fixup_f32 v1, v1, v0, s6 +; VI-NEXT: v_trunc_f32_e32 v1, v1 +; VI-NEXT: v_fma_f32 v2, -v1, v0, s6 ; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: flat_store_dword v[0:1], v2 @@ -267,57 +676,238 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4 %r0 = load float, ptr addrspace(1) %in1, align 4 %r1 = load float, ptr addrspace(1) %gep2, align 4 - %r2 = frem fast float %r0, %r1 + %r2 = frem afn float %r0, %r1 store float %r2, ptr addrspace(1) %out, align 4 ret void } -define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #1 { -; CI-LABEL: unsafe_frem_f32: +define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { +; CI-LABEL: frem_f64: ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; CI-NEXT: s_mov_b32 s6, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: s_load_dword s2, s[2:3], 0x0 -; CI-NEXT: s_load_dword s3, s[4:5], 0x4 +; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_mov_b32_e32 v1, s2 -; CI-NEXT: v_rcp_f32_e32 v0, s3 -; CI-NEXT: v_mul_f32_e32 v0, s2, v0 -; CI-NEXT: v_trunc_f32_e32 v0, v0 -; CI-NEXT: v_fma_f32 v0, -v0, s3, v1 +; CI-NEXT: v_mov_b32_e32 v0, s4 +; CI-NEXT: v_mov_b32_e32 v1, s5 +; CI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[2:3]|, |v[0:1]| +; CI-NEXT: ; implicit-def: $vgpr0_vgpr1 +; CI-NEXT: s_cbranch_vccz .LBB6_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: v_mov_b32_e32 v0, s4 +; CI-NEXT: v_mov_b32_e32 v1, s5 +; CI-NEXT: v_cmp_eq_f64_e64 vcc, |s[2:3]|, |v[0:1]| +; CI-NEXT: s_mov_b32 s6, 0 +; CI-NEXT: s_brev_b32 s7, 1 +; CI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7] +; CI-NEXT: v_mov_b32_e32 v0, s6 +; CI-NEXT: v_mov_b32_e32 v1, s7 +; CI-NEXT: v_mov_b32_e32 v2, s2 +; CI-NEXT: v_mov_b32_e32 v3, s3 +; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; CI-NEXT: s_mov_b32 s6, 0 +; CI-NEXT: .LBB6_2: ; %Flow16 +; CI-NEXT: s_xor_b32 s6, s6, 1 +; CI-NEXT: s_cmp_lg_u32 s6, 0 +; CI-NEXT: s_cbranch_scc1 .LBB6_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]| +; CI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[2:3]| +; CI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[4:5]| +; CI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26 +; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v6 +; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v7 +; CI-NEXT: v_sub_i32_e32 v9, vcc, v2, v8 +; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 +; CI-NEXT: v_div_scale_f64 v[2:3], s[6:7], v[0:1], v[0:1], 1.0 +; CI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0 +; CI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3] +; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; CI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11] +; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15] +; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13] +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9 +; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB6_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v6, vcc, 26, v6 +; CI-NEXT: v_sub_i32_e32 v9, vcc, v6, v7 +; CI-NEXT: .LBB6_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v7, v5 +; CI-NEXT: v_mov_b32_e32 v6, v4 +; CI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3] +; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] +; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7] +; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] +; CI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1] +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc +; CI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc +; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26 +; CI-NEXT: v_add_i32_e32 v9, vcc, 0xffffffe6, v9 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9 +; CI-NEXT: s_cbranch_vccnz .LBB6_5 +; CI-NEXT: s_branch .LBB6_7 +; CI-NEXT: .LBB6_6: +; CI-NEXT: v_mov_b32_e32 v7, v5 +; CI-NEXT: v_mov_b32_e32 v6, v4 +; CI-NEXT: .LBB6_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v4, vcc, 0xffffffe7, v9 +; CI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4 +; CI-NEXT: s_mov_b32 s6, 0 +; CI-NEXT: s_brev_b32 s7, 1 +; CI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7] +; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] +; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] +; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] +; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] +; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] +; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8 +; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; CI-NEXT: v_or_b32_e32 v0, s6, v0 +; CI-NEXT: v_or_b32_e32 v1, s7, v1 +; CI-NEXT: .LBB6_8: ; %Flow17 +; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[4:5], 0 +; CI-NEXT: v_mov_b32_e32 v2, 0x7ff80000 +; CI-NEXT: v_cndmask_b32_e64 v3, v0, 0, vcc +; CI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc +; CI-NEXT: v_mov_b32_e32 v0, 0 +; CI-NEXT: v_mov_b32_e32 v1, 0x7ff00000 +; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[0:1] ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc +; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; CI-NEXT: s_endpgm ; -; VI-LABEL: unsafe_frem_f32: +; VI-LABEL: frem_f64: ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 +; VI-NEXT: s_mov_b32 s6, 1 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_load_dword s2, s[2:3], 0x0 -; VI-NEXT: s_load_dword s3, s[4:5], 0x10 +; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v1, s2 -; VI-NEXT: v_rcp_f32_e32 v0, s3 -; VI-NEXT: v_mul_f32_e32 v0, s2, v0 -; VI-NEXT: v_trunc_f32_e32 v0, v0 -; VI-NEXT: v_fma_f32 v2, -v0, s3, v1 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: flat_store_dword v[0:1], v2 +; VI-NEXT: v_mov_b32_e32 v0, s4 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[2:3]|, |v[0:1]| +; VI-NEXT: ; implicit-def: $vgpr0_vgpr1 +; VI-NEXT: s_cbranch_vccz .LBB6_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: v_mov_b32_e32 v0, s4 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: v_cmp_eq_f64_e64 vcc, |s[2:3]|, |v[0:1]| +; VI-NEXT: s_mov_b32 s6, 0 +; VI-NEXT: s_brev_b32 s7, 1 +; VI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7] +; VI-NEXT: v_mov_b32_e32 v0, s6 +; VI-NEXT: v_mov_b32_e32 v1, s7 +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; VI-NEXT: s_mov_b32 s6, 0 +; VI-NEXT: .LBB6_2: ; %Flow16 +; VI-NEXT: s_xor_b32 s6, s6, 1 +; VI-NEXT: s_cmp_lg_u32 s6, 0 +; VI-NEXT: s_cbranch_scc1 .LBB6_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[2:3]| +; VI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[2:3]| +; VI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[4:5]| +; VI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26 +; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v6 +; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v7 +; VI-NEXT: v_sub_u32_e32 v9, vcc, v2, v8 +; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 +; VI-NEXT: v_div_scale_f64 v[2:3], s[6:7], v[0:1], v[0:1], 1.0 +; VI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0 +; VI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3] +; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; VI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11] +; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15] +; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13] +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9 +; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB6_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v6, vcc, 26, v6 +; VI-NEXT: v_sub_u32_e32 v9, vcc, v6, v7 +; VI-NEXT: .LBB6_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v7, v5 +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3] +; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] +; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7] +; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] +; VI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1] +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc +; VI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc +; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0xffffffe6, v9 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9 +; VI-NEXT: s_cbranch_vccnz .LBB6_5 +; VI-NEXT: s_branch .LBB6_7 +; VI-NEXT: .LBB6_6: +; VI-NEXT: v_mov_b32_e32 v7, v5 +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: .LBB6_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v4, vcc, 0xffffffe7, v9 +; VI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4 +; VI-NEXT: s_mov_b32 s6, 0 +; VI-NEXT: s_brev_b32 s7, 1 +; VI-NEXT: s_and_b64 s[6:7], s[2:3], s[6:7] +; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] +; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] +; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] +; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] +; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] +; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8 +; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; VI-NEXT: v_or_b32_e32 v0, s6, v0 +; VI-NEXT: v_or_b32_e32 v1, s7, v1 +; VI-NEXT: .LBB6_8: ; %Flow17 +; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[4:5], 0 +; VI-NEXT: v_mov_b32_e32 v2, 0x7ff80000 +; VI-NEXT: v_cndmask_b32_e64 v3, v0, 0, vcc +; VI-NEXT: v_cndmask_b32_e32 v4, v1, v2, vcc +; VI-NEXT: v_mov_b32_e32 v0, 0 +; VI-NEXT: v_mov_b32_e32 v1, 0x7ff00000 +; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[2:3]|, v[0:1] +; VI-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: s_endpgm - %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4 - %r0 = load float, ptr addrspace(1) %in1, align 4 - %r1 = load float, ptr addrspace(1) %gep2, align 4 - %r2 = frem afn float %r0, %r1 - store float %r2, ptr addrspace(1) %out, align 4 + %r0 = load double, ptr addrspace(1) %in1, align 8 + %r1 = load double, ptr addrspace(1) %in2, align 8 + %r2 = frem double %r0, %r1 + store double %r2, ptr addrspace(1) %out, align 8 ret void } -define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { -; CI-LABEL: frem_f64: +define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { +; CI-LABEL: fast_frem_f64: ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd @@ -345,7 +935,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1 ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; CI-NEXT: s_endpgm ; -; VI-LABEL: frem_f64: +; VI-LABEL: fast_frem_f64: ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 @@ -374,63 +964,6 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1 ; VI-NEXT: s_endpgm %r0 = load double, ptr addrspace(1) %in1, align 8 %r1 = load double, ptr addrspace(1) %in2, align 8 - %r2 = frem double %r0, %r1 - store double %r2, ptr addrspace(1) %out, align 8 - ret void -} - -define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { -; CI-LABEL: fast_frem_f64: -; CI: ; %bb.0: -; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd -; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 -; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_rcp_f64_e32 v[0:1], s[4:5] -; CI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; CI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; CI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; CI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; CI-NEXT: v_mov_b32_e32 v2, s2 -; CI-NEXT: v_mov_b32_e32 v3, s3 -; CI-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1] -; CI-NEXT: s_mov_b32 s2, -1 -; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_fma_f64 v[6:7], -s[4:5], v[4:5], v[2:3] -; CI-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], v[4:5] -; CI-NEXT: v_trunc_f64_e32 v[0:1], v[0:1] -; CI-NEXT: v_fma_f64 v[0:1], -v[0:1], s[4:5], v[2:3] -; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 -; CI-NEXT: s_endpgm -; -; VI-LABEL: fast_frem_f64: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 -; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_rcp_f64_e32 v[0:1], s[4:5] -; VI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; VI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1] -; VI-NEXT: v_fma_f64 v[6:7], -s[4:5], v[4:5], v[2:3] -; VI-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], v[4:5] -; VI-NEXT: v_trunc_f64_e32 v[0:1], v[0:1] -; VI-NEXT: v_fma_f64 v[0:1], -v[0:1], s[4:5], v[2:3] -; VI-NEXT: v_mov_b32_e32 v3, s1 -; VI-NEXT: v_mov_b32_e32 v2, s0 -; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] -; VI-NEXT: s_endpgm - %r0 = load double, ptr addrspace(1) %in1, align 8 - %r1 = load double, ptr addrspace(1) %in2, align 8 %r2 = frem fast double %r0, %r1 store double %r2, ptr addrspace(1) %out, align 8 ret void @@ -445,20 +978,23 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace( ; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_rcp_f64_e32 v[0:1], s[4:5] -; CI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; CI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; CI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; CI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; CI-NEXT: v_mov_b32_e32 v2, s2 -; CI-NEXT: v_mov_b32_e32 v3, s3 -; CI-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1] +; CI-NEXT: v_mov_b32_e32 v0, s4 +; CI-NEXT: v_mov_b32_e32 v1, s5 +; CI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3] +; CI-NEXT: v_div_scale_f64 v[8:9], vcc, s[2:3], v[0:1], s[2:3] +; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] +; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] +; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] +; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[2:3] +; CI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] +; CI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[2:3] ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_fma_f64 v[6:7], -s[4:5], v[4:5], v[2:3] -; CI-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], v[4:5] -; CI-NEXT: v_trunc_f64_e32 v[0:1], v[0:1] -; CI-NEXT: v_fma_f64 v[0:1], -v[0:1], s[4:5], v[2:3] ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; CI-NEXT: s_endpgm ; @@ -470,18 +1006,21 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace( ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_rcp_f64_e32 v[0:1], s[4:5] -; VI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; VI-NEXT: v_fma_f64 v[2:3], -s[4:5], v[0:1], 1.0 -; VI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], v[0:1] -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: v_mul_f64 v[4:5], s[2:3], v[0:1] -; VI-NEXT: v_fma_f64 v[6:7], -s[4:5], v[4:5], v[2:3] -; VI-NEXT: v_fma_f64 v[0:1], v[6:7], v[0:1], v[4:5] -; VI-NEXT: v_trunc_f64_e32 v[0:1], v[0:1] -; VI-NEXT: v_fma_f64 v[0:1], -v[0:1], s[4:5], v[2:3] +; VI-NEXT: v_mov_b32_e32 v0, s4 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: v_div_scale_f64 v[2:3], s[4:5], v[0:1], v[0:1], s[2:3] +; VI-NEXT: v_div_scale_f64 v[8:9], vcc, s[2:3], v[0:1], s[2:3] +; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] +; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 +; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] +; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] +; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] +; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] +; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[2:3] +; VI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] +; VI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[2:3] ; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] @@ -497,102 +1036,372 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace( define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { ; CI-LABEL: frem_v2f16: ; CI: ; %bb.0: -; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; CI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9 +; CI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0xd +; CI-NEXT: ; implicit-def: $vgpr0 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: s_load_dword s2, s[2:3], 0x0 -; CI-NEXT: s_load_dword s3, s[4:5], 0x4 +; CI-NEXT: s_load_dword s0, s[10:11], 0x0 +; CI-NEXT: s_load_dword s1, s[2:3], 0x4 +; CI-NEXT: s_mov_b32 s2, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_cvt_f32_f16_e32 v0, s2 -; CI-NEXT: v_cvt_f32_f16_e32 v1, s3 -; CI-NEXT: s_lshr_b32 s4, s2, 16 -; CI-NEXT: s_lshr_b32 s5, s3, 16 -; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 -; CI-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0 -; CI-NEXT: v_rcp_f32_e32 v4, v2 +; CI-NEXT: v_cvt_f32_f16_e64 v2, |s0| +; CI-NEXT: v_cvt_f32_f16_e64 v1, |s1| +; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1 +; CI-NEXT: s_cbranch_vccz .LBB9_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: s_and_b32 s2, s0, 0x8000 +; CI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1 +; CI-NEXT: v_mov_b32_e32 v0, s2 +; CI-NEXT: v_mov_b32_e32 v3, s0 +; CI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: .LBB9_2: ; %Flow57 +; CI-NEXT: s_xor_b32 s2, s2, 1 +; CI-NEXT: s_cmp_lg_u32 s2, 0 +; CI-NEXT: s_cbranch_scc1 .LBB9_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f32_e32 v3, v1 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 +; CI-NEXT: v_ldexp_f32_e64 v1, v3, 1 +; CI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0 +; CI-NEXT: v_frexp_mant_f32_e32 v0, v2 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2 +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5 +; CI-NEXT: v_ldexp_f32_e64 v4, v0, 11 +; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0 +; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; CI-NEXT: v_rcp_f32_e32 v8, v3 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 -; CI-NEXT: v_fma_f32 v4, v5, v4, v4 -; CI-NEXT: v_mul_f32_e32 v5, v3, v4 -; CI-NEXT: v_fma_f32 v6, -v2, v5, v3 -; CI-NEXT: v_fma_f32 v5, v6, v4, v5 -; CI-NEXT: v_fma_f32 v2, -v2, v5, v3 +; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; CI-NEXT: v_fma_f32 v8, v9, v8, v8 +; CI-NEXT: v_mul_f32_e32 v9, v7, v8 +; CI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; CI-NEXT: v_fma_f32 v9, v10, v8, v9 +; CI-NEXT: v_fma_f32 v3, -v3, v9, v7 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 -; CI-NEXT: v_div_fixup_f32 v2, v2, v1, v0 -; CI-NEXT: v_trunc_f32_e32 v2, v2 -; CI-NEXT: v_fma_f32 v0, -v2, v1, v0 -; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 -; CI-NEXT: v_cvt_f32_f16_e32 v2, s5 -; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2 +; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB9_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v2, vcc, 11, v5 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CI-NEXT: .LBB9_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: v_mul_f32_e32 v4, v5, v3 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v6, v4, v1 +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2 +; CI-NEXT: v_ldexp_f32_e64 v4, v4, 11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2 +; CI-NEXT: s_cbranch_vccnz .LBB9_5 +; CI-NEXT: s_branch .LBB9_7 +; CI-NEXT: .LBB9_6: +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: .LBB9_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v2, vcc, -10, v2 +; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2 +; CI-NEXT: v_mul_f32_e32 v3, v2, v3 +; CI-NEXT: v_rndne_f32_e32 v3, v3 +; CI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; CI-NEXT: v_add_f32_e32 v1, v2, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0 ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 -; CI-NEXT: v_div_scale_f32 v3, s[2:3], v2, v2, v1 -; CI-NEXT: v_div_scale_f32 v4, vcc, v1, v2, v1 -; CI-NEXT: v_rcp_f32_e32 v5, v3 +; CI-NEXT: s_and_b32 s2, s0, 0x8000 +; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; CI-NEXT: v_or_b32_e32 v0, s2, v0 +; CI-NEXT: .LBB9_8: ; %Flow58 +; CI-NEXT: s_lshr_b32 s2, s0, 16 +; CI-NEXT: s_lshr_b32 s3, s1, 16 +; CI-NEXT: v_cvt_f32_f16_e64 v3, |s2| +; CI-NEXT: v_cvt_f32_f16_e64 v2, |s3| +; CI-NEXT: s_mov_b32 s4, 1 +; CI-NEXT: ; implicit-def: $vgpr1 +; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2 +; CI-NEXT: s_cbranch_vccz .LBB9_10 +; CI-NEXT: ; %bb.9: ; %frem.else20 +; CI-NEXT: s_and_b32 s4, s2, 0x8000 +; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2 +; CI-NEXT: v_mov_b32_e32 v1, s4 +; CI-NEXT: v_mov_b32_e32 v4, s2 +; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; CI-NEXT: s_mov_b32 s4, 0 +; CI-NEXT: .LBB9_10: ; %Flow53 +; CI-NEXT: s_xor_b32 s4, s4, 1 +; CI-NEXT: s_cmp_lg_u32 s4, 0 +; CI-NEXT: s_cbranch_scc1 .LBB9_16 +; CI-NEXT: ; %bb.11: ; %frem.compute19 +; CI-NEXT: v_frexp_mant_f32_e32 v4, v2 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2 +; CI-NEXT: v_ldexp_f32_e64 v2, v4, 1 +; CI-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, 1.0 +; CI-NEXT: v_frexp_mant_f32_e32 v1, v3 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3 +; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6 +; CI-NEXT: v_ldexp_f32_e64 v5, v1, 11 +; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1 +; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; CI-NEXT: v_rcp_f32_e32 v9, v4 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v6, -v3, v5, 1.0 -; CI-NEXT: v_fma_f32 v5, v6, v5, v5 -; CI-NEXT: v_mul_f32_e32 v6, v4, v5 -; CI-NEXT: v_fma_f32 v7, -v3, v6, v4 -; CI-NEXT: v_fma_f32 v6, v7, v5, v6 -; CI-NEXT: v_fma_f32 v3, -v3, v6, v4 +; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; CI-NEXT: v_fma_f32 v9, v10, v9, v9 +; CI-NEXT: v_mul_f32_e32 v10, v8, v9 +; CI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; CI-NEXT: v_fma_f32 v10, v11, v9, v10 +; CI-NEXT: v_fma_f32 v4, -v4, v10, v8 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v3, v3, v5, v6 -; CI-NEXT: s_mov_b32 s2, -1 -; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_div_fixup_f32 v3, v3, v2, v1 -; CI-NEXT: v_trunc_f32_e32 v3, v3 -; CI-NEXT: v_fma_f32 v1, -v3, v2, v1 +; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3 +; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB9_14 +; CI-NEXT: ; %bb.12: ; %frem.loop_body27.preheader +; CI-NEXT: v_add_i32_e32 v3, vcc, 11, v6 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7 +; CI-NEXT: .LBB9_13: ; %frem.loop_body27 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: v_mul_f32_e32 v5, v6, v4 +; CI-NEXT: v_rndne_f32_e32 v5, v5 +; CI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; CI-NEXT: v_add_f32_e32 v7, v5, v2 +; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3 +; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3 +; CI-NEXT: s_cbranch_vccnz .LBB9_13 +; CI-NEXT: s_branch .LBB9_15 +; CI-NEXT: .LBB9_14: +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: .LBB9_15: ; %frem.loop_exit28 +; CI-NEXT: v_add_i32_e32 v3, vcc, -10, v3 +; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3 +; CI-NEXT: v_mul_f32_e32 v4, v3, v4 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; CI-NEXT: v_add_f32_e32 v2, v3, v2 +; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; CI-NEXT: v_cvt_f16_f32_e32 v1, v1 +; CI-NEXT: s_and_b32 s4, s2, 0x8000 +; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1 +; CI-NEXT: v_or_b32_e32 v1, s4, v1 +; CI-NEXT: .LBB9_16: ; %Flow54 +; CI-NEXT: v_cvt_f32_f16_e32 v2, s1 +; CI-NEXT: v_cvt_f32_f16_e32 v3, 0 +; CI-NEXT: s_and_b32 s0, s0, 0x7fff +; CI-NEXT: s_cmpk_lg_i32 s0, 0x7c00 +; CI-NEXT: s_cselect_b32 s4, 1, 0 +; CI-NEXT: v_cmp_nlg_f32_e32 vcc, v2, v3 +; CI-NEXT: v_cvt_f32_f16_e32 v2, s3 +; CI-NEXT: s_and_b32 s2, s2, 0x7fff +; CI-NEXT: s_cmpk_lg_i32 s2, 0x7c00 +; CI-NEXT: s_cselect_b32 s2, 1, 0 +; CI-NEXT: v_cmp_nlg_f32_e64 s[0:1], v2, v3 +; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; CI-NEXT: v_mov_b32_e32 v2, 0x7e00 +; CI-NEXT: s_and_b32 s3, 1, s4 +; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; CI-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 +; CI-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1] +; CI-NEXT: s_and_b32 s0, 1, s2 +; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; CI-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; CI-NEXT: v_or_b32_e32 v0, v0, v1 -; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; CI-NEXT: s_mov_b32 s10, -1 +; CI-NEXT: s_mov_b32 s11, 0xf000 +; CI-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; CI-NEXT: s_endpgm ; ; VI-LABEL: frem_v2f16: ; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 +; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34 +; VI-NEXT: ; implicit-def: $vgpr0 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_load_dword s2, s[2:3], 0x0 -; VI-NEXT: s_load_dword s3, s[4:5], 0x10 +; VI-NEXT: s_load_dword s0, s[10:11], 0x0 +; VI-NEXT: s_load_dword s1, s[2:3], 0x10 +; VI-NEXT: s_mov_b32 s2, 1 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cvt_f32_f16_e32 v0, s2 -; VI-NEXT: v_cvt_f32_f16_e32 v2, s3 -; VI-NEXT: s_lshr_b32 s5, s3, 16 -; VI-NEXT: v_mov_b32_e32 v1, s3 -; VI-NEXT: s_lshr_b32 s4, s2, 16 -; VI-NEXT: v_rcp_f32_e32 v3, v2 -; VI-NEXT: v_mul_f32_e32 v4, v0, v3 -; VI-NEXT: v_mad_f32 v5, -v2, v4, v0 -; VI-NEXT: v_mac_f32_e32 v4, v5, v3 -; VI-NEXT: v_mad_f32 v0, -v2, v4, v0 -; VI-NEXT: v_mul_f32_e32 v0, v0, v3 -; VI-NEXT: v_and_b32_e32 v0, 0xff800000, v0 -; VI-NEXT: v_add_f32_e32 v0, v0, v4 +; VI-NEXT: v_cvt_f32_f16_e64 v2, |s0| +; VI-NEXT: v_cvt_f32_f16_e64 v1, |s1| +; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1 +; VI-NEXT: s_cbranch_vccz .LBB9_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: s_and_b32 s2, s0, 0x8000 +; VI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB9_2: ; %Flow57 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB9_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f32_e32 v3, v1 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 +; VI-NEXT: v_ldexp_f32 v1, v3, 1 +; VI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0 +; VI-NEXT: v_frexp_mant_f32_e32 v0, v2 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2 +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5 +; VI-NEXT: v_ldexp_f32 v4, v0, 11 +; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0 +; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; VI-NEXT: v_rcp_f32_e32 v8, v3 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; VI-NEXT: v_fma_f32 v8, v9, v8, v8 +; VI-NEXT: v_mul_f32_e32 v9, v7, v8 +; VI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; VI-NEXT: v_fma_f32 v9, v10, v8, v9 +; VI-NEXT: v_fma_f32 v3, -v3, v9, v7 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2 +; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB9_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v2, vcc, 11, v5 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6 +; VI-NEXT: .LBB9_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: v_mul_f32_e32 v4, v5, v3 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v6, v4, v1 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2 +; VI-NEXT: v_ldexp_f32 v4, v4, 11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2 +; VI-NEXT: s_cbranch_vccnz .LBB9_5 +; VI-NEXT: s_branch .LBB9_7 +; VI-NEXT: .LBB9_6: +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: .LBB9_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v2, vcc, -10, v2 +; VI-NEXT: v_ldexp_f32 v2, v5, v2 +; VI-NEXT: v_mul_f32_e32 v3, v2, v3 +; VI-NEXT: v_rndne_f32_e32 v3, v3 +; VI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; VI-NEXT: v_add_f32_e32 v1, v2, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; VI-NEXT: v_ldexp_f32 v0, v1, v0 ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 -; VI-NEXT: v_cvt_f32_f16_e32 v3, s5 -; VI-NEXT: v_mov_b32_e32 v2, s5 -; VI-NEXT: v_div_fixup_f16 v0, v0, v1, s2 -; VI-NEXT: v_trunc_f16_e32 v0, v0 -; VI-NEXT: v_fma_f16 v0, -v0, v1, s2 -; VI-NEXT: v_cvt_f32_f16_e32 v1, s4 -; VI-NEXT: v_rcp_f32_e32 v4, v3 -; VI-NEXT: v_mul_f32_e32 v5, v1, v4 -; VI-NEXT: v_mad_f32 v6, -v3, v5, v1 -; VI-NEXT: v_mac_f32_e32 v5, v6, v4 -; VI-NEXT: v_mad_f32 v1, -v3, v5, v1 -; VI-NEXT: v_mul_f32_e32 v1, v1, v4 -; VI-NEXT: v_and_b32_e32 v1, 0xff800000, v1 -; VI-NEXT: v_add_f32_e32 v1, v1, v5 +; VI-NEXT: s_and_b32 s2, s0, 0x8000 +; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; VI-NEXT: v_or_b32_e32 v0, s2, v0 +; VI-NEXT: .LBB9_8: ; %Flow58 +; VI-NEXT: s_lshr_b32 s4, s0, 16 +; VI-NEXT: s_lshr_b32 s2, s1, 16 +; VI-NEXT: v_cvt_f32_f16_e64 v3, |s4| +; VI-NEXT: v_cvt_f32_f16_e64 v2, |s2| +; VI-NEXT: s_mov_b32 s3, 1 +; VI-NEXT: ; implicit-def: $vgpr1 +; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2 +; VI-NEXT: s_cbranch_vccz .LBB9_10 +; VI-NEXT: ; %bb.9: ; %frem.else20 +; VI-NEXT: s_and_b32 s3, s4, 0x8000 +; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; VI-NEXT: s_mov_b32 s3, 0 +; VI-NEXT: .LBB9_10: ; %Flow53 +; VI-NEXT: s_xor_b32 s3, s3, 1 +; VI-NEXT: s_cmp_lg_u32 s3, 0 +; VI-NEXT: s_cbranch_scc1 .LBB9_16 +; VI-NEXT: ; %bb.11: ; %frem.compute19 +; VI-NEXT: v_frexp_mant_f32_e32 v4, v2 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2 +; VI-NEXT: v_ldexp_f32 v2, v4, 1 +; VI-NEXT: v_div_scale_f32 v4, s[6:7], v2, v2, 1.0 +; VI-NEXT: v_frexp_mant_f32_e32 v1, v3 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3 +; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6 +; VI-NEXT: v_ldexp_f32 v5, v1, 11 +; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; VI-NEXT: v_rcp_f32_e32 v9, v4 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; VI-NEXT: v_fma_f32 v9, v10, v9, v9 +; VI-NEXT: v_mul_f32_e32 v10, v8, v9 +; VI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; VI-NEXT: v_fma_f32 v10, v11, v9, v10 +; VI-NEXT: v_fma_f32 v4, -v4, v10, v8 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3 +; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB9_14 +; VI-NEXT: ; %bb.12: ; %frem.loop_body27.preheader +; VI-NEXT: v_add_u32_e32 v3, vcc, 11, v6 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7 +; VI-NEXT: .LBB9_13: ; %frem.loop_body27 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: v_mul_f32_e32 v5, v6, v4 +; VI-NEXT: v_rndne_f32_e32 v5, v5 +; VI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; VI-NEXT: v_add_f32_e32 v7, v5, v2 +; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3 +; VI-NEXT: v_ldexp_f32 v5, v5, 11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3 +; VI-NEXT: s_cbranch_vccnz .LBB9_13 +; VI-NEXT: s_branch .LBB9_15 +; VI-NEXT: .LBB9_14: +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: .LBB9_15: ; %frem.loop_exit28 +; VI-NEXT: v_add_u32_e32 v3, vcc, -10, v3 +; VI-NEXT: v_ldexp_f32 v3, v6, v3 +; VI-NEXT: v_mul_f32_e32 v4, v3, v4 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; VI-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; VI-NEXT: v_ldexp_f32 v1, v2, v1 ; VI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; VI-NEXT: v_div_fixup_f16 v1, v1, v2, s4 -; VI-NEXT: v_trunc_f16_e32 v1, v1 -; VI-NEXT: v_fma_f16 v1, -v1, v2, s4 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; VI-NEXT: s_and_b32 s3, s4, 0x8000 +; VI-NEXT: v_and_b32_e32 v1, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v1, s3, v1 +; VI-NEXT: .LBB9_16: ; %Flow54 +; VI-NEXT: v_mov_b32_e32 v2, 0x7c00 +; VI-NEXT: v_cmp_nlg_f16_e64 vcc, s1, 0 +; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |s0|, v2 +; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, 0 +; VI-NEXT: v_cmp_nge_f16_e64 s[4:5], |s4|, v2 +; VI-NEXT: v_mov_b32_e32 v2, 0x7e00 +; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_mov_b64 vcc, s[2:3] +; VI-NEXT: v_cndmask_b32_sdwa v1, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_mov_b64 vcc, s[4:5] +; VI-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] +; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-NEXT: v_or_b32_e32 v2, v0, v1 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v1, s9 ; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: s_endpgm %gep2 = getelementptr <2 x half>, ptr addrspace(1) %in2, i32 4 @@ -606,176 +1415,714 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in1, ptr addrspace(1) %in2) #0 { ; CI-LABEL: frem_v4f16: ; CI: ; %bb.0: -; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; CI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9 +; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd +; CI-NEXT: ; implicit-def: $vgpr0 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 -; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x8 +; CI-NEXT: s_load_dwordx2 s[4:5], s[10:11], 0x0 +; CI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8 +; CI-NEXT: s_mov_b32 s0, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) -; CI-NEXT: v_cvt_f32_f16_e32 v0, s2 -; CI-NEXT: v_cvt_f32_f16_e32 v1, s4 -; CI-NEXT: s_lshr_b32 s8, s2, 16 -; CI-NEXT: s_lshr_b32 s9, s3, 16 -; CI-NEXT: s_lshr_b32 s10, s4, 16 -; CI-NEXT: v_div_scale_f32 v2, s[6:7], v1, v1, v0 -; CI-NEXT: s_lshr_b32 s11, s5, 16 -; CI-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0 -; CI-NEXT: v_rcp_f32_e32 v4, v2 +; CI-NEXT: v_cvt_f32_f16_e64 v2, |s4| +; CI-NEXT: v_cvt_f32_f16_e64 v1, |s2| +; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1 +; CI-NEXT: s_cbranch_vccz .LBB10_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: s_and_b32 s0, s4, 0x8000 +; CI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1 +; CI-NEXT: v_mov_b32_e32 v0, s0 +; CI-NEXT: v_mov_b32_e32 v3, s4 +; CI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; CI-NEXT: s_mov_b32 s0, 0 +; CI-NEXT: .LBB10_2: ; %Flow135 +; CI-NEXT: s_xor_b32 s0, s0, 1 +; CI-NEXT: s_cmp_lg_u32 s0, 0 +; CI-NEXT: s_cbranch_scc1 .LBB10_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f32_e32 v3, v1 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 +; CI-NEXT: v_ldexp_f32_e64 v1, v3, 1 +; CI-NEXT: v_div_scale_f32 v3, s[0:1], v1, v1, 1.0 +; CI-NEXT: v_frexp_mant_f32_e32 v0, v2 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2 +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5 +; CI-NEXT: v_ldexp_f32_e64 v4, v0, 11 +; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0 +; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; CI-NEXT: v_rcp_f32_e32 v8, v3 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 -; CI-NEXT: v_fma_f32 v4, v5, v4, v4 -; CI-NEXT: v_mul_f32_e32 v5, v3, v4 -; CI-NEXT: v_fma_f32 v6, -v2, v5, v3 -; CI-NEXT: v_fma_f32 v5, v6, v4, v5 -; CI-NEXT: v_fma_f32 v2, -v2, v5, v3 +; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; CI-NEXT: v_fma_f32 v8, v9, v8, v8 +; CI-NEXT: v_mul_f32_e32 v9, v7, v8 +; CI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; CI-NEXT: v_fma_f32 v9, v10, v8, v9 +; CI-NEXT: v_fma_f32 v3, -v3, v9, v7 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 -; CI-NEXT: v_div_fixup_f32 v2, v2, v1, v0 -; CI-NEXT: v_trunc_f32_e32 v2, v2 -; CI-NEXT: v_fma_f32 v0, -v2, v1, v0 -; CI-NEXT: v_cvt_f32_f16_e32 v1, s8 -; CI-NEXT: v_cvt_f32_f16_e32 v2, s10 -; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0 +; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2 +; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB10_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v2, vcc, 11, v5 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CI-NEXT: .LBB10_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: v_mul_f32_e32 v4, v5, v3 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v6, v4, v1 +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2 +; CI-NEXT: v_ldexp_f32_e64 v4, v4, 11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2 +; CI-NEXT: s_cbranch_vccnz .LBB10_5 +; CI-NEXT: s_branch .LBB10_7 +; CI-NEXT: .LBB10_6: +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: .LBB10_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v2, vcc, -10, v2 +; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2 +; CI-NEXT: v_mul_f32_e32 v3, v2, v3 +; CI-NEXT: v_rndne_f32_e32 v3, v3 +; CI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; CI-NEXT: v_add_f32_e32 v1, v2, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0 ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 -; CI-NEXT: v_div_scale_f32 v3, s[6:7], v2, v2, v1 -; CI-NEXT: v_div_scale_f32 v4, vcc, v1, v2, v1 -; CI-NEXT: v_rcp_f32_e32 v5, v3 +; CI-NEXT: s_and_b32 s0, s4, 0x8000 +; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; CI-NEXT: v_or_b32_e32 v0, s0, v0 +; CI-NEXT: .LBB10_8: ; %Flow136 +; CI-NEXT: s_lshr_b32 s6, s4, 16 +; CI-NEXT: s_lshr_b32 s0, s2, 16 +; CI-NEXT: v_cvt_f32_f16_e64 v3, |s6| +; CI-NEXT: v_cvt_f32_f16_e64 v2, |s0| +; CI-NEXT: s_mov_b32 s1, 1 +; CI-NEXT: ; implicit-def: $vgpr1 +; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2 +; CI-NEXT: s_cbranch_vccz .LBB10_10 +; CI-NEXT: ; %bb.9: ; %frem.else20 +; CI-NEXT: s_and_b32 s1, s6, 0x8000 +; CI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2 +; CI-NEXT: v_mov_b32_e32 v1, s1 +; CI-NEXT: v_mov_b32_e32 v4, s6 +; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; CI-NEXT: s_mov_b32 s1, 0 +; CI-NEXT: .LBB10_10: ; %Flow131 +; CI-NEXT: s_xor_b32 s1, s1, 1 +; CI-NEXT: s_cmp_lg_u32 s1, 0 +; CI-NEXT: s_cbranch_scc1 .LBB10_16 +; CI-NEXT: ; %bb.11: ; %frem.compute19 +; CI-NEXT: v_frexp_mant_f32_e32 v4, v2 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2 +; CI-NEXT: v_ldexp_f32_e64 v2, v4, 1 +; CI-NEXT: v_div_scale_f32 v4, s[10:11], v2, v2, 1.0 +; CI-NEXT: v_frexp_mant_f32_e32 v1, v3 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3 +; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6 +; CI-NEXT: v_ldexp_f32_e64 v5, v1, 11 +; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1 +; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; CI-NEXT: v_rcp_f32_e32 v9, v4 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v6, -v3, v5, 1.0 -; CI-NEXT: v_fma_f32 v5, v6, v5, v5 -; CI-NEXT: v_mul_f32_e32 v6, v4, v5 -; CI-NEXT: v_fma_f32 v7, -v3, v6, v4 -; CI-NEXT: v_fma_f32 v6, v7, v5, v6 -; CI-NEXT: v_fma_f32 v3, -v3, v6, v4 +; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; CI-NEXT: v_fma_f32 v9, v10, v9, v9 +; CI-NEXT: v_mul_f32_e32 v10, v8, v9 +; CI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; CI-NEXT: v_fma_f32 v10, v11, v9, v10 +; CI-NEXT: v_fma_f32 v4, -v4, v10, v8 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v3, v3, v5, v6 -; CI-NEXT: v_div_fixup_f32 v3, v3, v2, v1 -; CI-NEXT: v_trunc_f32_e32 v3, v3 -; CI-NEXT: v_fma_f32 v1, -v3, v2, v1 -; CI-NEXT: v_cvt_f32_f16_e32 v2, s3 -; CI-NEXT: v_cvt_f32_f16_e32 v3, s5 +; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3 +; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB10_14 +; CI-NEXT: ; %bb.12: ; %frem.loop_body27.preheader +; CI-NEXT: v_add_i32_e32 v3, vcc, 11, v6 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7 +; CI-NEXT: .LBB10_13: ; %frem.loop_body27 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: v_mul_f32_e32 v5, v6, v4 +; CI-NEXT: v_rndne_f32_e32 v5, v5 +; CI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; CI-NEXT: v_add_f32_e32 v7, v5, v2 +; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3 +; CI-NEXT: v_ldexp_f32_e64 v5, v5, 11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3 +; CI-NEXT: s_cbranch_vccnz .LBB10_13 +; CI-NEXT: s_branch .LBB10_15 +; CI-NEXT: .LBB10_14: +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: .LBB10_15: ; %frem.loop_exit28 +; CI-NEXT: v_add_i32_e32 v3, vcc, -10, v3 +; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3 +; CI-NEXT: v_mul_f32_e32 v4, v3, v4 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; CI-NEXT: v_add_f32_e32 v2, v3, v2 +; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1 ; CI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; CI-NEXT: v_div_scale_f32 v4, s[2:3], v3, v3, v2 -; CI-NEXT: v_div_scale_f32 v5, vcc, v2, v3, v2 -; CI-NEXT: v_rcp_f32_e32 v6, v4 +; CI-NEXT: s_and_b32 s1, s6, 0x8000 +; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1 +; CI-NEXT: v_or_b32_e32 v1, s1, v1 +; CI-NEXT: .LBB10_16: ; %Flow132 +; CI-NEXT: v_cvt_f32_f16_e64 v4, |s5| +; CI-NEXT: v_cvt_f32_f16_e64 v3, |s3| +; CI-NEXT: s_mov_b32 s1, 1 +; CI-NEXT: ; implicit-def: $vgpr2 +; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3 +; CI-NEXT: s_cbranch_vccz .LBB10_18 +; CI-NEXT: ; %bb.17: ; %frem.else53 +; CI-NEXT: s_and_b32 s1, s5, 0x8000 +; CI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3 +; CI-NEXT: v_mov_b32_e32 v2, s1 +; CI-NEXT: v_mov_b32_e32 v5, s5 +; CI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; CI-NEXT: s_mov_b32 s1, 0 +; CI-NEXT: .LBB10_18: ; %Flow127 +; CI-NEXT: s_xor_b32 s1, s1, 1 +; CI-NEXT: s_cmp_lg_u32 s1, 0 +; CI-NEXT: s_cbranch_scc1 .LBB10_24 +; CI-NEXT: ; %bb.19: ; %frem.compute52 +; CI-NEXT: v_frexp_mant_f32_e32 v5, v3 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3 +; CI-NEXT: v_ldexp_f32_e64 v3, v5, 1 +; CI-NEXT: v_div_scale_f32 v5, s[10:11], v3, v3, 1.0 +; CI-NEXT: v_frexp_mant_f32_e32 v2, v4 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4 +; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v7 +; CI-NEXT: v_ldexp_f32_e64 v6, v2, 11 +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8 +; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v2 +; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0 +; CI-NEXT: v_rcp_f32_e32 v10, v5 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v7, -v4, v6, 1.0 -; CI-NEXT: v_fma_f32 v6, v7, v6, v6 -; CI-NEXT: v_mul_f32_e32 v7, v5, v6 -; CI-NEXT: v_fma_f32 v8, -v4, v7, v5 -; CI-NEXT: v_fma_f32 v7, v8, v6, v7 -; CI-NEXT: v_fma_f32 v4, -v4, v7, v5 +; CI-NEXT: v_fma_f32 v11, -v5, v10, 1.0 +; CI-NEXT: v_fma_f32 v10, v11, v10, v10 +; CI-NEXT: v_mul_f32_e32 v11, v9, v10 +; CI-NEXT: v_fma_f32 v12, -v5, v11, v9 +; CI-NEXT: v_fma_f32 v11, v12, v10, v11 +; CI-NEXT: v_fma_f32 v5, -v5, v11, v9 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v4, v4, v6, v7 -; CI-NEXT: v_div_fixup_f32 v4, v4, v3, v2 -; CI-NEXT: v_trunc_f32_e32 v4, v4 -; CI-NEXT: v_fma_f32 v2, -v4, v3, v2 -; CI-NEXT: v_cvt_f32_f16_e32 v3, s9 -; CI-NEXT: v_cvt_f32_f16_e32 v4, s11 +; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v4 +; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB10_22 +; CI-NEXT: ; %bb.20: ; %frem.loop_body60.preheader +; CI-NEXT: v_add_i32_e32 v4, vcc, 11, v7 +; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v8 +; CI-NEXT: .LBB10_21: ; %frem.loop_body60 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v7, v6 +; CI-NEXT: v_mul_f32_e32 v6, v7, v5 +; CI-NEXT: v_rndne_f32_e32 v6, v6 +; CI-NEXT: v_fma_f32 v6, -v6, v3, v7 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6 +; CI-NEXT: v_add_f32_e32 v8, v6, v3 +; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc +; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4 +; CI-NEXT: v_ldexp_f32_e64 v6, v6, 11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4 +; CI-NEXT: s_cbranch_vccnz .LBB10_21 +; CI-NEXT: s_branch .LBB10_23 +; CI-NEXT: .LBB10_22: +; CI-NEXT: v_mov_b32_e32 v7, v6 +; CI-NEXT: .LBB10_23: ; %frem.loop_exit61 +; CI-NEXT: v_add_i32_e32 v4, vcc, -10, v4 +; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4 +; CI-NEXT: v_mul_f32_e32 v5, v4, v5 +; CI-NEXT: v_rndne_f32_e32 v5, v5 +; CI-NEXT: v_fma_f32 v4, -v5, v3, v4 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v3, v4, v3 +; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2 ; CI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; CI-NEXT: v_div_scale_f32 v5, s[2:3], v4, v4, v3 -; CI-NEXT: v_div_scale_f32 v6, vcc, v3, v4, v3 -; CI-NEXT: v_rcp_f32_e32 v7, v5 +; CI-NEXT: s_and_b32 s1, s5, 0x8000 +; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2 +; CI-NEXT: v_or_b32_e32 v2, s1, v2 +; CI-NEXT: .LBB10_24: ; %Flow128 +; CI-NEXT: s_lshr_b32 s7, s5, 16 +; CI-NEXT: s_lshr_b32 s10, s3, 16 +; CI-NEXT: v_cvt_f32_f16_e64 v5, |s7| +; CI-NEXT: v_cvt_f32_f16_e64 v4, |s10| +; CI-NEXT: s_mov_b32 s1, 1 +; CI-NEXT: ; implicit-def: $vgpr3 +; CI-NEXT: v_cmp_ngt_f32_e32 vcc, v5, v4 +; CI-NEXT: s_cbranch_vccz .LBB10_26 +; CI-NEXT: ; %bb.25: ; %frem.else86 +; CI-NEXT: s_and_b32 s1, s7, 0x8000 +; CI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4 +; CI-NEXT: v_mov_b32_e32 v3, s1 +; CI-NEXT: v_mov_b32_e32 v6, s7 +; CI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc +; CI-NEXT: s_mov_b32 s1, 0 +; CI-NEXT: .LBB10_26: ; %Flow123 +; CI-NEXT: s_xor_b32 s1, s1, 1 +; CI-NEXT: s_cmp_lg_u32 s1, 0 +; CI-NEXT: s_cbranch_scc1 .LBB10_32 +; CI-NEXT: ; %bb.27: ; %frem.compute85 +; CI-NEXT: v_frexp_mant_f32_e32 v6, v4 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v9, v4 +; CI-NEXT: v_ldexp_f32_e64 v4, v6, 1 +; CI-NEXT: v_div_scale_f32 v6, s[12:13], v4, v4, 1.0 +; CI-NEXT: v_frexp_mant_f32_e32 v3, v5 +; CI-NEXT: v_frexp_exp_i32_f32_e32 v8, v5 +; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v8 +; CI-NEXT: v_ldexp_f32_e64 v7, v3, 11 +; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v9 +; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v3 +; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0 +; CI-NEXT: v_rcp_f32_e32 v11, v6 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v8, -v5, v7, 1.0 -; CI-NEXT: v_fma_f32 v7, v8, v7, v7 -; CI-NEXT: v_mul_f32_e32 v8, v6, v7 -; CI-NEXT: v_fma_f32 v9, -v5, v8, v6 -; CI-NEXT: v_fma_f32 v8, v9, v7, v8 -; CI-NEXT: v_fma_f32 v5, -v5, v8, v6 +; CI-NEXT: v_fma_f32 v12, -v6, v11, 1.0 +; CI-NEXT: v_fma_f32 v11, v12, v11, v11 +; CI-NEXT: v_mul_f32_e32 v12, v10, v11 +; CI-NEXT: v_fma_f32 v13, -v6, v12, v10 +; CI-NEXT: v_fma_f32 v12, v13, v11, v12 +; CI-NEXT: v_fma_f32 v6, -v6, v12, v10 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v5, v5, v7, v8 +; CI-NEXT: v_div_fmas_f32 v6, v6, v11, v12 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v5 +; CI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB10_30 +; CI-NEXT: ; %bb.28: ; %frem.loop_body93.preheader +; CI-NEXT: v_add_i32_e32 v5, vcc, 11, v8 +; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v9 +; CI-NEXT: .LBB10_29: ; %frem.loop_body93 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v8, v7 +; CI-NEXT: v_mul_f32_e32 v7, v8, v6 +; CI-NEXT: v_rndne_f32_e32 v7, v7 +; CI-NEXT: v_fma_f32 v7, -v7, v4, v8 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7 +; CI-NEXT: v_add_f32_e32 v9, v7, v4 +; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc +; CI-NEXT: v_add_i32_e32 v5, vcc, -11, v5 +; CI-NEXT: v_ldexp_f32_e64 v7, v7, 11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v5 +; CI-NEXT: s_cbranch_vccnz .LBB10_29 +; CI-NEXT: s_branch .LBB10_31 +; CI-NEXT: .LBB10_30: +; CI-NEXT: v_mov_b32_e32 v8, v7 +; CI-NEXT: .LBB10_31: ; %frem.loop_exit94 +; CI-NEXT: v_add_i32_e32 v5, vcc, -10, v5 +; CI-NEXT: v_ldexp_f32_e32 v5, v8, v5 +; CI-NEXT: v_mul_f32_e32 v6, v5, v6 +; CI-NEXT: v_rndne_f32_e32 v6, v6 +; CI-NEXT: v_fma_f32 v5, -v6, v4, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; CI-NEXT: v_add_f32_e32 v4, v5, v4 +; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; CI-NEXT: v_ldexp_f32_e32 v3, v4, v3 +; CI-NEXT: v_cvt_f16_f32_e32 v3, v3 +; CI-NEXT: s_and_b32 s1, s7, 0x8000 +; CI-NEXT: v_and_b32_e32 v3, 0x7fff, v3 +; CI-NEXT: v_or_b32_e32 v3, s1, v3 +; CI-NEXT: .LBB10_32: ; %Flow124 +; CI-NEXT: v_cvt_f32_f16_e32 v4, s2 +; CI-NEXT: v_cvt_f32_f16_e32 v5, 0 +; CI-NEXT: s_and_b32 s1, s4, 0x7fff +; CI-NEXT: s_cmpk_lg_i32 s1, 0x7c00 +; CI-NEXT: s_cselect_b32 s11, 1, 0 +; CI-NEXT: v_cmp_nlg_f32_e32 vcc, v4, v5 +; CI-NEXT: v_cvt_f32_f16_e32 v4, s0 +; CI-NEXT: s_and_b32 s2, s6, 0x7fff +; CI-NEXT: s_cmpk_lg_i32 s2, 0x7c00 +; CI-NEXT: s_cselect_b32 s6, 1, 0 +; CI-NEXT: v_cmp_nlg_f32_e64 s[0:1], v4, v5 +; CI-NEXT: v_cvt_f32_f16_e32 v4, s3 +; CI-NEXT: s_and_b32 s4, s5, 0x7fff +; CI-NEXT: s_cmpk_lg_i32 s4, 0x7c00 +; CI-NEXT: s_cselect_b32 s12, 1, 0 +; CI-NEXT: v_cmp_nlg_f32_e64 s[2:3], v4, v5 +; CI-NEXT: v_cvt_f32_f16_e32 v4, s10 +; CI-NEXT: s_and_b32 s7, s7, 0x7fff +; CI-NEXT: s_cmpk_lg_i32 s7, 0x7c00 +; CI-NEXT: s_cselect_b32 s7, 1, 0 +; CI-NEXT: v_cmp_nlg_f32_e64 s[4:5], v4, v5 +; CI-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; CI-NEXT: v_mov_b32_e32 v4, 0x7e00 +; CI-NEXT: s_and_b32 s10, 1, s11 +; CI-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; CI-NEXT: v_cmp_ne_u32_e64 vcc, 0, s10 +; CI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] +; CI-NEXT: s_and_b32 s0, 1, s6 +; CI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; CI-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc ; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; CI-NEXT: v_or_b32_e32 v0, v0, v1 -; CI-NEXT: s_mov_b32 s2, -1 -; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_div_fixup_f32 v5, v5, v4, v3 -; CI-NEXT: v_trunc_f32_e32 v5, v5 -; CI-NEXT: v_fma_f32 v3, -v5, v4, v3 -; CI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; CI-NEXT: v_lshlrev_b32_e32 v1, 16, v3 -; CI-NEXT: v_or_b32_e32 v1, v2, v1 -; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; CI-NEXT: v_and_b32_e32 v1, 0xffff, v2 +; CI-NEXT: s_and_b32 s0, 1, s12 +; CI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[2:3] +; CI-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; CI-NEXT: v_and_b32_e32 v2, 0xffff, v3 +; CI-NEXT: s_and_b32 s0, 1, s7 +; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; CI-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5] +; CI-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 +; CI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; CI-NEXT: v_or_b32_e32 v1, v1, v2 +; CI-NEXT: s_mov_b32 s10, -1 +; CI-NEXT: s_mov_b32 s11, 0xf000 +; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; CI-NEXT: s_endpgm ; ; VI-LABEL: frem_v4f16: ; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 -; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 +; VI-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34 +; VI-NEXT: ; implicit-def: $vgpr0 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 -; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x20 +; VI-NEXT: s_load_dwordx2 s[8:9], s[18:19], 0x0 +; VI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x20 +; VI-NEXT: s_mov_b32 s0, 1 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cvt_f32_f16_e32 v0, s2 -; VI-NEXT: v_cvt_f32_f16_e32 v2, s4 -; VI-NEXT: s_lshr_b32 s8, s4, 16 -; VI-NEXT: v_mov_b32_e32 v1, s4 -; VI-NEXT: s_lshr_b32 s6, s2, 16 -; VI-NEXT: v_rcp_f32_e32 v3, v2 -; VI-NEXT: s_lshr_b32 s9, s5, 16 -; VI-NEXT: s_lshr_b32 s7, s3, 16 -; VI-NEXT: v_mul_f32_e32 v4, v0, v3 -; VI-NEXT: v_mad_f32 v5, -v2, v4, v0 -; VI-NEXT: v_mac_f32_e32 v4, v5, v3 -; VI-NEXT: v_mad_f32 v0, -v2, v4, v0 -; VI-NEXT: v_mul_f32_e32 v0, v0, v3 -; VI-NEXT: v_and_b32_e32 v0, 0xff800000, v0 -; VI-NEXT: v_add_f32_e32 v0, v0, v4 +; VI-NEXT: v_cvt_f32_f16_e64 v2, |s8| +; VI-NEXT: v_cvt_f32_f16_e64 v1, |s6| +; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v2, v1 +; VI-NEXT: s_cbranch_vccz .LBB10_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: s_and_b32 s0, s8, 0x8000 +; VI-NEXT: v_cmp_eq_f32_e32 vcc, v2, v1 +; VI-NEXT: v_mov_b32_e32 v0, s0 +; VI-NEXT: v_mov_b32_e32 v3, s8 +; VI-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: .LBB10_2: ; %Flow135 +; VI-NEXT: s_xor_b32 s0, s0, 1 +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_cbranch_scc1 .LBB10_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f32_e32 v3, v1 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v1 +; VI-NEXT: v_ldexp_f32 v1, v3, 1 +; VI-NEXT: v_div_scale_f32 v3, s[0:1], v1, v1, 1.0 +; VI-NEXT: v_frexp_mant_f32_e32 v0, v2 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v5, v2 +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5 +; VI-NEXT: v_ldexp_f32 v4, v0, 11 +; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0 +; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; VI-NEXT: v_rcp_f32_e32 v8, v3 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; VI-NEXT: v_fma_f32 v8, v9, v8, v8 +; VI-NEXT: v_mul_f32_e32 v9, v7, v8 +; VI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; VI-NEXT: v_fma_f32 v9, v10, v8, v9 +; VI-NEXT: v_fma_f32 v3, -v3, v9, v7 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v2 +; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB10_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v2, vcc, 11, v5 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6 +; VI-NEXT: .LBB10_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: v_mul_f32_e32 v4, v5, v3 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v6, v4, v1 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2 +; VI-NEXT: v_ldexp_f32 v4, v4, 11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v2 +; VI-NEXT: s_cbranch_vccnz .LBB10_5 +; VI-NEXT: s_branch .LBB10_7 +; VI-NEXT: .LBB10_6: +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: .LBB10_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v2, vcc, -10, v2 +; VI-NEXT: v_ldexp_f32 v2, v5, v2 +; VI-NEXT: v_mul_f32_e32 v3, v2, v3 +; VI-NEXT: v_rndne_f32_e32 v3, v3 +; VI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; VI-NEXT: v_add_f32_e32 v1, v2, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; VI-NEXT: v_ldexp_f32 v0, v1, v0 ; VI-NEXT: v_cvt_f16_f32_e32 v0, v0 -; VI-NEXT: v_cvt_f32_f16_e32 v3, s8 -; VI-NEXT: v_mov_b32_e32 v2, s8 -; VI-NEXT: v_div_fixup_f16 v0, v0, v1, s2 -; VI-NEXT: v_trunc_f16_e32 v0, v0 -; VI-NEXT: v_fma_f16 v0, -v0, v1, s2 -; VI-NEXT: v_cvt_f32_f16_e32 v1, s6 -; VI-NEXT: v_rcp_f32_e32 v4, v3 -; VI-NEXT: v_mul_f32_e32 v5, v1, v4 -; VI-NEXT: v_mad_f32 v6, -v3, v5, v1 -; VI-NEXT: v_mac_f32_e32 v5, v6, v4 -; VI-NEXT: v_mad_f32 v1, -v3, v5, v1 -; VI-NEXT: v_mul_f32_e32 v1, v1, v4 -; VI-NEXT: v_and_b32_e32 v1, 0xff800000, v1 -; VI-NEXT: v_add_f32_e32 v1, v1, v5 +; VI-NEXT: s_and_b32 s0, s8, 0x8000 +; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0 +; VI-NEXT: v_or_b32_e32 v0, s0, v0 +; VI-NEXT: .LBB10_8: ; %Flow136 +; VI-NEXT: s_lshr_b32 s4, s8, 16 +; VI-NEXT: s_lshr_b32 s2, s6, 16 +; VI-NEXT: v_cvt_f32_f16_e64 v3, |s4| +; VI-NEXT: v_cvt_f32_f16_e64 v2, |s2| +; VI-NEXT: s_mov_b32 s0, 1 +; VI-NEXT: ; implicit-def: $vgpr1 +; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v3, v2 +; VI-NEXT: s_cbranch_vccz .LBB10_10 +; VI-NEXT: ; %bb.9: ; %frem.else20 +; VI-NEXT: s_and_b32 s0, s4, 0x8000 +; VI-NEXT: v_cmp_eq_f32_e32 vcc, v3, v2 +; VI-NEXT: v_mov_b32_e32 v1, s0 +; VI-NEXT: v_mov_b32_e32 v4, s4 +; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: .LBB10_10: ; %Flow131 +; VI-NEXT: s_xor_b32 s0, s0, 1 +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_cbranch_scc1 .LBB10_16 +; VI-NEXT: ; %bb.11: ; %frem.compute19 +; VI-NEXT: v_frexp_mant_f32_e32 v4, v2 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v2 +; VI-NEXT: v_ldexp_f32 v2, v4, 1 +; VI-NEXT: v_div_scale_f32 v4, s[0:1], v2, v2, 1.0 +; VI-NEXT: v_frexp_mant_f32_e32 v1, v3 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v6, v3 +; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6 +; VI-NEXT: v_ldexp_f32 v5, v1, 11 +; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; VI-NEXT: v_rcp_f32_e32 v9, v4 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; VI-NEXT: v_fma_f32 v9, v10, v9, v9 +; VI-NEXT: v_mul_f32_e32 v10, v8, v9 +; VI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; VI-NEXT: v_fma_f32 v10, v11, v9, v10 +; VI-NEXT: v_fma_f32 v4, -v4, v10, v8 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v3 +; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB10_14 +; VI-NEXT: ; %bb.12: ; %frem.loop_body27.preheader +; VI-NEXT: v_add_u32_e32 v3, vcc, 11, v6 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7 +; VI-NEXT: .LBB10_13: ; %frem.loop_body27 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: v_mul_f32_e32 v5, v6, v4 +; VI-NEXT: v_rndne_f32_e32 v5, v5 +; VI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; VI-NEXT: v_add_f32_e32 v7, v5, v2 +; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3 +; VI-NEXT: v_ldexp_f32 v5, v5, 11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v3 +; VI-NEXT: s_cbranch_vccnz .LBB10_13 +; VI-NEXT: s_branch .LBB10_15 +; VI-NEXT: .LBB10_14: +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: .LBB10_15: ; %frem.loop_exit28 +; VI-NEXT: v_add_u32_e32 v3, vcc, -10, v3 +; VI-NEXT: v_ldexp_f32 v3, v6, v3 +; VI-NEXT: v_mul_f32_e32 v4, v3, v4 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; VI-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; VI-NEXT: v_ldexp_f32 v1, v2, v1 ; VI-NEXT: v_cvt_f16_f32_e32 v1, v1 -; VI-NEXT: v_cvt_f32_f16_e32 v4, s5 -; VI-NEXT: v_mov_b32_e32 v3, s5 -; VI-NEXT: v_div_fixup_f16 v1, v1, v2, s6 -; VI-NEXT: v_trunc_f16_e32 v1, v1 -; VI-NEXT: v_fma_f16 v1, -v1, v2, s6 -; VI-NEXT: v_cvt_f32_f16_e32 v2, s3 -; VI-NEXT: v_rcp_f32_e32 v5, v4 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1 -; VI-NEXT: v_or_b32_e32 v0, v0, v1 -; VI-NEXT: v_mul_f32_e32 v6, v2, v5 -; VI-NEXT: v_mad_f32 v7, -v4, v6, v2 -; VI-NEXT: v_mac_f32_e32 v6, v7, v5 -; VI-NEXT: v_mad_f32 v2, -v4, v6, v2 -; VI-NEXT: v_mul_f32_e32 v2, v2, v5 -; VI-NEXT: v_and_b32_e32 v2, 0xff800000, v2 -; VI-NEXT: v_add_f32_e32 v2, v2, v6 +; VI-NEXT: s_and_b32 s0, s4, 0x8000 +; VI-NEXT: v_and_b32_e32 v1, 0x7fff, v1 +; VI-NEXT: v_or_b32_e32 v1, s0, v1 +; VI-NEXT: .LBB10_16: ; %Flow132 +; VI-NEXT: v_cvt_f32_f16_e64 v4, |s9| +; VI-NEXT: v_cvt_f32_f16_e64 v3, |s7| +; VI-NEXT: s_mov_b32 s0, 1 +; VI-NEXT: ; implicit-def: $vgpr2 +; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v4, v3 +; VI-NEXT: s_cbranch_vccz .LBB10_18 +; VI-NEXT: ; %bb.17: ; %frem.else53 +; VI-NEXT: s_and_b32 s0, s9, 0x8000 +; VI-NEXT: v_cmp_eq_f32_e32 vcc, v4, v3 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v5, s9 +; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: .LBB10_18: ; %Flow127 +; VI-NEXT: s_xor_b32 s0, s0, 1 +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_cbranch_scc1 .LBB10_24 +; VI-NEXT: ; %bb.19: ; %frem.compute52 +; VI-NEXT: v_frexp_mant_f32_e32 v5, v3 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v3 +; VI-NEXT: v_ldexp_f32 v3, v5, 1 +; VI-NEXT: v_div_scale_f32 v5, s[0:1], v3, v3, 1.0 +; VI-NEXT: v_frexp_mant_f32_e32 v2, v4 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v7, v4 +; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v7 +; VI-NEXT: v_ldexp_f32 v6, v2, 11 +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8 +; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v2 +; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0 +; VI-NEXT: v_rcp_f32_e32 v10, v5 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v11, -v5, v10, 1.0 +; VI-NEXT: v_fma_f32 v10, v11, v10, v10 +; VI-NEXT: v_mul_f32_e32 v11, v9, v10 +; VI-NEXT: v_fma_f32 v12, -v5, v11, v9 +; VI-NEXT: v_fma_f32 v11, v12, v10, v11 +; VI-NEXT: v_fma_f32 v5, -v5, v11, v9 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v4 +; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB10_22 +; VI-NEXT: ; %bb.20: ; %frem.loop_body60.preheader +; VI-NEXT: v_add_u32_e32 v4, vcc, 11, v7 +; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v8 +; VI-NEXT: .LBB10_21: ; %frem.loop_body60 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: v_mul_f32_e32 v6, v7, v5 +; VI-NEXT: v_rndne_f32_e32 v6, v6 +; VI-NEXT: v_fma_f32 v6, -v6, v3, v7 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6 +; VI-NEXT: v_add_f32_e32 v8, v6, v3 +; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4 +; VI-NEXT: v_ldexp_f32 v6, v6, 11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v4 +; VI-NEXT: s_cbranch_vccnz .LBB10_21 +; VI-NEXT: s_branch .LBB10_23 +; VI-NEXT: .LBB10_22: +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: .LBB10_23: ; %frem.loop_exit61 +; VI-NEXT: v_add_u32_e32 v4, vcc, -10, v4 +; VI-NEXT: v_ldexp_f32 v4, v7, v4 +; VI-NEXT: v_mul_f32_e32 v5, v4, v5 +; VI-NEXT: v_rndne_f32_e32 v5, v5 +; VI-NEXT: v_fma_f32 v4, -v5, v3, v4 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; VI-NEXT: v_ldexp_f32 v2, v3, v2 ; VI-NEXT: v_cvt_f16_f32_e32 v2, v2 -; VI-NEXT: v_cvt_f32_f16_e32 v5, s9 -; VI-NEXT: v_mov_b32_e32 v4, s9 -; VI-NEXT: v_div_fixup_f16 v2, v2, v3, s3 -; VI-NEXT: v_trunc_f16_e32 v2, v2 -; VI-NEXT: v_fma_f16 v2, -v2, v3, s3 -; VI-NEXT: v_cvt_f32_f16_e32 v3, s7 -; VI-NEXT: v_rcp_f32_e32 v6, v5 -; VI-NEXT: v_mul_f32_e32 v7, v3, v6 -; VI-NEXT: v_mad_f32 v8, -v5, v7, v3 -; VI-NEXT: v_mac_f32_e32 v7, v8, v6 -; VI-NEXT: v_mad_f32 v3, -v5, v7, v3 -; VI-NEXT: v_mul_f32_e32 v3, v3, v6 -; VI-NEXT: v_and_b32_e32 v3, 0xff800000, v3 -; VI-NEXT: v_add_f32_e32 v3, v3, v7 +; VI-NEXT: s_and_b32 s0, s9, 0x8000 +; VI-NEXT: v_and_b32_e32 v2, 0x7fff, v2 +; VI-NEXT: v_or_b32_e32 v2, s0, v2 +; VI-NEXT: .LBB10_24: ; %Flow128 +; VI-NEXT: s_lshr_b32 s12, s9, 16 +; VI-NEXT: s_lshr_b32 s10, s7, 16 +; VI-NEXT: v_cvt_f32_f16_e64 v5, |s12| +; VI-NEXT: v_cvt_f32_f16_e64 v4, |s10| +; VI-NEXT: s_mov_b32 s0, 1 +; VI-NEXT: ; implicit-def: $vgpr3 +; VI-NEXT: v_cmp_ngt_f32_e32 vcc, v5, v4 +; VI-NEXT: s_cbranch_vccz .LBB10_26 +; VI-NEXT: ; %bb.25: ; %frem.else86 +; VI-NEXT: s_and_b32 s0, s12, 0x8000 +; VI-NEXT: v_cmp_eq_f32_e32 vcc, v5, v4 +; VI-NEXT: v_mov_b32_e32 v3, s0 +; VI-NEXT: v_mov_b32_e32 v6, s12 +; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc +; VI-NEXT: s_mov_b32 s0, 0 +; VI-NEXT: .LBB10_26: ; %Flow123 +; VI-NEXT: s_xor_b32 s0, s0, 1 +; VI-NEXT: s_cmp_lg_u32 s0, 0 +; VI-NEXT: s_cbranch_scc1 .LBB10_32 +; VI-NEXT: ; %bb.27: ; %frem.compute85 +; VI-NEXT: v_frexp_mant_f32_e32 v6, v4 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v9, v4 +; VI-NEXT: v_ldexp_f32 v4, v6, 1 +; VI-NEXT: v_div_scale_f32 v6, s[0:1], v4, v4, 1.0 +; VI-NEXT: v_frexp_mant_f32_e32 v3, v5 +; VI-NEXT: v_frexp_exp_i32_f32_e32 v8, v5 +; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v8 +; VI-NEXT: v_ldexp_f32 v7, v3, 11 +; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v9 +; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0 +; VI-NEXT: v_rcp_f32_e32 v11, v6 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 +; VI-NEXT: v_fma_f32 v12, -v6, v11, 1.0 +; VI-NEXT: v_fma_f32 v11, v12, v11, v11 +; VI-NEXT: v_mul_f32_e32 v12, v10, v11 +; VI-NEXT: v_fma_f32 v13, -v6, v12, v10 +; VI-NEXT: v_fma_f32 v12, v13, v11, v12 +; VI-NEXT: v_fma_f32 v6, -v6, v12, v10 +; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 +; VI-NEXT: v_div_fmas_f32 v6, v6, v11, v12 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 11, v5 +; VI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB10_30 +; VI-NEXT: ; %bb.28: ; %frem.loop_body93.preheader +; VI-NEXT: v_add_u32_e32 v5, vcc, 11, v8 +; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v9 +; VI-NEXT: .LBB10_29: ; %frem.loop_body93 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mul_f32_e32 v7, v8, v6 +; VI-NEXT: v_rndne_f32_e32 v7, v7 +; VI-NEXT: v_fma_f32 v7, -v7, v4, v8 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7 +; VI-NEXT: v_add_f32_e32 v9, v7, v4 +; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, -11, v5 +; VI-NEXT: v_ldexp_f32 v7, v7, 11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 11, v5 +; VI-NEXT: s_cbranch_vccnz .LBB10_29 +; VI-NEXT: s_branch .LBB10_31 +; VI-NEXT: .LBB10_30: +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: .LBB10_31: ; %frem.loop_exit94 +; VI-NEXT: v_add_u32_e32 v5, vcc, -10, v5 +; VI-NEXT: v_ldexp_f32 v5, v8, v5 +; VI-NEXT: v_mul_f32_e32 v6, v5, v6 +; VI-NEXT: v_rndne_f32_e32 v6, v6 +; VI-NEXT: v_fma_f32 v5, -v6, v4, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; VI-NEXT: v_add_f32_e32 v4, v5, v4 +; VI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; VI-NEXT: v_ldexp_f32 v3, v4, v3 ; VI-NEXT: v_cvt_f16_f32_e32 v3, v3 -; VI-NEXT: v_div_fixup_f16 v3, v3, v4, s7 -; VI-NEXT: v_trunc_f16_e32 v3, v3 -; VI-NEXT: v_fma_f16 v3, -v3, v4, s7 -; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v3 -; VI-NEXT: v_or_b32_e32 v1, v2, v1 -; VI-NEXT: v_mov_b32_e32 v3, s1 -; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: s_and_b32 s0, s12, 0x8000 +; VI-NEXT: v_and_b32_e32 v3, 0x7fff, v3 +; VI-NEXT: v_or_b32_e32 v3, s0, v3 +; VI-NEXT: .LBB10_32: ; %Flow124 +; VI-NEXT: v_mov_b32_e32 v4, 0x7c00 +; VI-NEXT: v_cmp_nlg_f16_e64 vcc, s6, 0 +; VI-NEXT: v_cmp_nge_f16_e64 s[0:1], |s8|, v4 +; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, 0 +; VI-NEXT: v_cmp_nge_f16_e64 s[4:5], |s4|, v4 +; VI-NEXT: v_cmp_nge_f16_e64 s[8:9], |s9|, v4 +; VI-NEXT: v_cmp_nge_f16_e64 s[12:13], |s12|, v4 +; VI-NEXT: v_mov_b32_e32 v4, 0x7e00 +; VI-NEXT: v_cndmask_b32_sdwa v0, v0, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_mov_b64 vcc, s[2:3] +; VI-NEXT: v_cmp_nlg_f16_e64 s[6:7], s7, 0 +; VI-NEXT: v_cndmask_b32_sdwa v1, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_mov_b64 vcc, s[4:5] +; VI-NEXT: v_cmp_nlg_f16_e64 s[10:11], s10, 0 +; VI-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[0:1] +; VI-NEXT: v_cndmask_b32_sdwa v1, v4, v1, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: s_mov_b64 vcc, s[6:7] +; VI-NEXT: v_or_b32_e32 v0, v0, v1 +; VI-NEXT: v_cndmask_b32_sdwa v1, v2, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_mov_b64 vcc, s[10:11] +; VI-NEXT: v_cndmask_b32_sdwa v2, v3, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; VI-NEXT: s_mov_b64 vcc, s[12:13] +; VI-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[8:9] +; VI-NEXT: v_cndmask_b32_sdwa v2, v4, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; VI-NEXT: v_or_b32_e32 v1, v1, v2 +; VI-NEXT: v_mov_b32_e32 v2, s16 +; VI-NEXT: v_mov_b32_e32 v3, s17 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: s_endpgm %gep2 = getelementptr <4 x half>, ptr addrspace(1) %in2, i32 4 @@ -791,43 +2138,171 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i ; CI: ; %bb.0: ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; CI-NEXT: s_mov_b32 s6, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x8 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v0, s4 -; CI-NEXT: v_div_scale_f32 v1, s[6:7], v0, v0, s2 -; CI-NEXT: v_div_scale_f32 v2, vcc, s2, v0, s2 -; CI-NEXT: v_rcp_f32_e32 v3, v1 +; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0| +; CI-NEXT: ; implicit-def: $vgpr0 +; CI-NEXT: s_cbranch_vccz .LBB11_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: s_and_b32 s6, s2, 0x80000000 +; CI-NEXT: v_mov_b32_e32 v1, s4 +; CI-NEXT: v_mov_b32_e32 v0, s2 +; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1| +; CI-NEXT: v_mov_b32_e32 v1, s6 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CI-NEXT: s_mov_b32 s6, 0 +; CI-NEXT: .LBB11_2: ; %Flow53 +; CI-NEXT: s_xor_b32 s6, s6, 1 +; CI-NEXT: s_cmp_lg_u32 s6, 0 +; CI-NEXT: s_cbranch_scc1 .LBB11_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f32_e64 v1, |s4| +; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1 +; CI-NEXT: v_div_scale_f32 v3, s[6:7], v1, v1, 1.0 +; CI-NEXT: v_frexp_mant_f32_e64 v0, |s2| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s4| +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5 +; CI-NEXT: v_ldexp_f32_e64 v4, v0, 12 +; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0 +; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; CI-NEXT: v_rcp_f32_e32 v8, v3 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 -; CI-NEXT: v_fma_f32 v3, v4, v3, v3 -; CI-NEXT: v_mul_f32_e32 v4, v2, v3 -; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 -; CI-NEXT: v_fma_f32 v4, v5, v3, v4 -; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 +; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; CI-NEXT: v_fma_f32 v8, v9, v8, v8 +; CI-NEXT: v_mul_f32_e32 v9, v7, v8 +; CI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; CI-NEXT: v_fma_f32 v9, v10, v8, v9 +; CI-NEXT: v_fma_f32 v3, -v3, v9, v7 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 -; CI-NEXT: v_div_fixup_f32 v1, v1, v0, s2 -; CI-NEXT: v_trunc_f32_e32 v1, v1 -; CI-NEXT: v_fma_f32 v0, -v1, v0, s2 +; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2 +; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB11_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v2, vcc, 12, v5 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CI-NEXT: .LBB11_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: v_mul_f32_e32 v4, v5, v3 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v6, v4, v1 +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; CI-NEXT: v_add_i32_e32 v2, vcc, -12, v2 +; CI-NEXT: v_ldexp_f32_e64 v4, v4, 12 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2 +; CI-NEXT: s_cbranch_vccnz .LBB11_5 +; CI-NEXT: s_branch .LBB11_7 +; CI-NEXT: .LBB11_6: +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: .LBB11_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2 +; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2 +; CI-NEXT: v_mul_f32_e32 v3, v2, v3 +; CI-NEXT: v_rndne_f32_e32 v3, v3 +; CI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; CI-NEXT: v_add_f32_e32 v1, v2, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0 +; CI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; CI-NEXT: s_and_b32 s6, s2, 0x80000000 +; CI-NEXT: v_or_b32_e32 v0, s6, v0 +; CI-NEXT: .LBB11_8: ; %Flow54 ; CI-NEXT: v_mov_b32_e32 v1, s5 -; CI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, s3 -; CI-NEXT: v_div_scale_f32 v3, vcc, s3, v1, s3 -; CI-NEXT: v_rcp_f32_e32 v4, v2 +; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s3|, |v1| +; CI-NEXT: s_mov_b32 s6, 1 +; CI-NEXT: ; implicit-def: $vgpr1 +; CI-NEXT: s_cbranch_vccz .LBB11_10 +; CI-NEXT: ; %bb.9: ; %frem.else16 +; CI-NEXT: s_and_b32 s6, s3, 0x80000000 +; CI-NEXT: v_mov_b32_e32 v2, s5 +; CI-NEXT: v_mov_b32_e32 v1, s3 +; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s3|, |v2| +; CI-NEXT: v_mov_b32_e32 v2, s6 +; CI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CI-NEXT: s_mov_b32 s6, 0 +; CI-NEXT: .LBB11_10: ; %Flow49 +; CI-NEXT: s_xor_b32 s6, s6, 1 +; CI-NEXT: s_cmp_lg_u32 s6, 0 +; CI-NEXT: s_cbranch_scc1 .LBB11_16 +; CI-NEXT: ; %bb.11: ; %frem.compute15 +; CI-NEXT: v_frexp_mant_f32_e64 v2, |s5| +; CI-NEXT: v_ldexp_f32_e64 v2, v2, 1 +; CI-NEXT: v_div_scale_f32 v4, s[6:7], v2, v2, 1.0 +; CI-NEXT: v_frexp_mant_f32_e64 v1, |s3| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s5| +; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6 +; CI-NEXT: v_ldexp_f32_e64 v5, v1, 12 +; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1 +; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; CI-NEXT: v_rcp_f32_e32 v9, v4 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 -; CI-NEXT: v_fma_f32 v4, v5, v4, v4 -; CI-NEXT: v_mul_f32_e32 v5, v3, v4 -; CI-NEXT: v_fma_f32 v6, -v2, v5, v3 -; CI-NEXT: v_fma_f32 v5, v6, v4, v5 -; CI-NEXT: v_fma_f32 v2, -v2, v5, v3 +; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; CI-NEXT: v_fma_f32 v9, v10, v9, v9 +; CI-NEXT: v_mul_f32_e32 v10, v8, v9 +; CI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; CI-NEXT: v_fma_f32 v10, v11, v9, v10 +; CI-NEXT: v_fma_f32 v4, -v4, v10, v8 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 +; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3 +; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB11_14 +; CI-NEXT: ; %bb.12: ; %frem.loop_body23.preheader +; CI-NEXT: v_add_i32_e32 v3, vcc, 12, v6 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7 +; CI-NEXT: .LBB11_13: ; %frem.loop_body23 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: v_mul_f32_e32 v5, v6, v4 +; CI-NEXT: v_rndne_f32_e32 v5, v5 +; CI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; CI-NEXT: v_add_f32_e32 v7, v5, v2 +; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; CI-NEXT: v_add_i32_e32 v3, vcc, -12, v3 +; CI-NEXT: v_ldexp_f32_e64 v5, v5, 12 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3 +; CI-NEXT: s_cbranch_vccnz .LBB11_13 +; CI-NEXT: s_branch .LBB11_15 +; CI-NEXT: .LBB11_14: +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: .LBB11_15: ; %frem.loop_exit24 +; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3 +; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3 +; CI-NEXT: v_mul_f32_e32 v4, v3, v4 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; CI-NEXT: v_add_f32_e32 v2, v3, v2 +; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1 +; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; CI-NEXT: s_and_b32 s6, s3, 0x80000000 +; CI-NEXT: v_or_b32_e32 v1, s6, v1 +; CI-NEXT: .LBB11_16: ; %Flow50 +; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s4, 0 +; CI-NEXT: v_mov_b32_e32 v2, 0x7fc00000 +; CI-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v3 +; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s5, 0 +; CI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s3|, v3 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; CI-NEXT: s_mov_b32 s2, -1 -; CI-NEXT: v_div_fixup_f32 v2, v2, v1, s3 -; CI-NEXT: v_trunc_f32_e32 v2, v2 -; CI-NEXT: v_fma_f32 v1, -v2, v1, s3 ; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; CI-NEXT: s_endpgm @@ -836,42 +2311,170 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 +; VI-NEXT: s_mov_b32 s6, 1 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x20 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v0, s4 -; VI-NEXT: v_div_scale_f32 v1, s[6:7], v0, v0, s2 -; VI-NEXT: v_div_scale_f32 v2, vcc, s2, v0, s2 -; VI-NEXT: v_rcp_f32_e32 v3, v1 +; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s2|, |v0| +; VI-NEXT: ; implicit-def: $vgpr0 +; VI-NEXT: s_cbranch_vccz .LBB11_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: s_and_b32 s6, s2, 0x80000000 +; VI-NEXT: v_mov_b32_e32 v1, s4 +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s2|, |v1| +; VI-NEXT: v_mov_b32_e32 v1, s6 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; VI-NEXT: s_mov_b32 s6, 0 +; VI-NEXT: .LBB11_2: ; %Flow53 +; VI-NEXT: s_xor_b32 s6, s6, 1 +; VI-NEXT: s_cmp_lg_u32 s6, 0 +; VI-NEXT: s_cbranch_scc1 .LBB11_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f32_e64 v1, |s4| +; VI-NEXT: v_ldexp_f32 v1, v1, 1 +; VI-NEXT: v_div_scale_f32 v3, s[6:7], v1, v1, 1.0 +; VI-NEXT: v_frexp_mant_f32_e64 v0, |s2| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s2| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s4| +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5 +; VI-NEXT: v_ldexp_f32 v4, v0, 12 +; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0 +; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; VI-NEXT: v_rcp_f32_e32 v8, v3 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 -; VI-NEXT: v_fma_f32 v3, v4, v3, v3 -; VI-NEXT: v_mul_f32_e32 v4, v2, v3 -; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 -; VI-NEXT: v_fma_f32 v4, v5, v3, v4 -; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 +; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; VI-NEXT: v_fma_f32 v8, v9, v8, v8 +; VI-NEXT: v_mul_f32_e32 v9, v7, v8 +; VI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; VI-NEXT: v_fma_f32 v9, v10, v8, v9 +; VI-NEXT: v_fma_f32 v3, -v3, v9, v7 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 -; VI-NEXT: v_div_fixup_f32 v1, v1, v0, s2 -; VI-NEXT: v_trunc_f32_e32 v1, v1 -; VI-NEXT: v_fma_f32 v0, -v1, v0, s2 +; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2 +; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB11_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v5 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6 +; VI-NEXT: .LBB11_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: v_mul_f32_e32 v4, v5, v3 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v6, v4, v1 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, -12, v2 +; VI-NEXT: v_ldexp_f32 v4, v4, 12 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2 +; VI-NEXT: s_cbranch_vccnz .LBB11_5 +; VI-NEXT: s_branch .LBB11_7 +; VI-NEXT: .LBB11_6: +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: .LBB11_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2 +; VI-NEXT: v_ldexp_f32 v2, v5, v2 +; VI-NEXT: v_mul_f32_e32 v3, v2, v3 +; VI-NEXT: v_rndne_f32_e32 v3, v3 +; VI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; VI-NEXT: v_add_f32_e32 v1, v2, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; VI-NEXT: v_ldexp_f32 v0, v1, v0 +; VI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; VI-NEXT: s_and_b32 s6, s2, 0x80000000 +; VI-NEXT: v_or_b32_e32 v0, s6, v0 +; VI-NEXT: .LBB11_8: ; %Flow54 ; VI-NEXT: v_mov_b32_e32 v1, s5 -; VI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, s3 -; VI-NEXT: v_div_scale_f32 v3, vcc, s3, v1, s3 -; VI-NEXT: v_rcp_f32_e32 v4, v2 +; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s3|, |v1| +; VI-NEXT: s_mov_b32 s6, 1 +; VI-NEXT: ; implicit-def: $vgpr1 +; VI-NEXT: s_cbranch_vccz .LBB11_10 +; VI-NEXT: ; %bb.9: ; %frem.else16 +; VI-NEXT: s_and_b32 s6, s3, 0x80000000 +; VI-NEXT: v_mov_b32_e32 v2, s5 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s3|, |v2| +; VI-NEXT: v_mov_b32_e32 v2, s6 +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; VI-NEXT: s_mov_b32 s6, 0 +; VI-NEXT: .LBB11_10: ; %Flow49 +; VI-NEXT: s_xor_b32 s6, s6, 1 +; VI-NEXT: s_cmp_lg_u32 s6, 0 +; VI-NEXT: s_cbranch_scc1 .LBB11_16 +; VI-NEXT: ; %bb.11: ; %frem.compute15 +; VI-NEXT: v_frexp_mant_f32_e64 v2, |s5| +; VI-NEXT: v_ldexp_f32 v2, v2, 1 +; VI-NEXT: v_div_scale_f32 v4, s[6:7], v2, v2, 1.0 +; VI-NEXT: v_frexp_mant_f32_e64 v1, |s3| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s3| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s5| +; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6 +; VI-NEXT: v_ldexp_f32 v5, v1, 12 +; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; VI-NEXT: v_rcp_f32_e32 v9, v4 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; VI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 -; VI-NEXT: v_fma_f32 v4, v5, v4, v4 -; VI-NEXT: v_mul_f32_e32 v5, v3, v4 -; VI-NEXT: v_fma_f32 v6, -v2, v5, v3 -; VI-NEXT: v_fma_f32 v5, v6, v4, v5 -; VI-NEXT: v_fma_f32 v2, -v2, v5, v3 +; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; VI-NEXT: v_fma_f32 v9, v10, v9, v9 +; VI-NEXT: v_mul_f32_e32 v10, v8, v9 +; VI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; VI-NEXT: v_fma_f32 v10, v11, v9, v10 +; VI-NEXT: v_fma_f32 v4, -v4, v10, v8 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; VI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 -; VI-NEXT: v_div_fixup_f32 v2, v2, v1, s3 -; VI-NEXT: v_trunc_f32_e32 v2, v2 -; VI-NEXT: v_fma_f32 v1, -v2, v1, s3 +; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3 +; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB11_14 +; VI-NEXT: ; %bb.12: ; %frem.loop_body23.preheader +; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v6 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7 +; VI-NEXT: .LBB11_13: ; %frem.loop_body23 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: v_mul_f32_e32 v5, v6, v4 +; VI-NEXT: v_rndne_f32_e32 v5, v5 +; VI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; VI-NEXT: v_add_f32_e32 v7, v5, v2 +; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, -12, v3 +; VI-NEXT: v_ldexp_f32 v5, v5, 12 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3 +; VI-NEXT: s_cbranch_vccnz .LBB11_13 +; VI-NEXT: s_branch .LBB11_15 +; VI-NEXT: .LBB11_14: +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: .LBB11_15: ; %frem.loop_exit24 +; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3 +; VI-NEXT: v_ldexp_f32 v3, v6, v3 +; VI-NEXT: v_mul_f32_e32 v4, v3, v4 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; VI-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; VI-NEXT: v_ldexp_f32 v1, v2, v1 +; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; VI-NEXT: s_and_b32 s6, s3, 0x80000000 +; VI-NEXT: v_or_b32_e32 v1, s6, v1 +; VI-NEXT: .LBB11_16: ; %Flow50 +; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s4, 0 +; VI-NEXT: v_mov_b32_e32 v2, 0x7fc00000 +; VI-NEXT: v_mov_b32_e32 v3, 0x7f800000 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s2|, v3 +; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s5, 0 +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s3|, v3 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v2, s0 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] @@ -892,73 +2495,327 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; CI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10 +; CI-NEXT: s_mov_b32 s2, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v0, s8 -; CI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s4 -; CI-NEXT: v_div_scale_f32 v2, vcc, s4, v0, s4 -; CI-NEXT: v_rcp_f32_e32 v3, v1 +; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s4|, |v0| +; CI-NEXT: ; implicit-def: $vgpr0 +; CI-NEXT: s_cbranch_vccz .LBB12_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: s_and_b32 s2, s4, 0x80000000 +; CI-NEXT: v_mov_b32_e32 v1, s8 +; CI-NEXT: v_mov_b32_e32 v0, s4 +; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s4|, |v1| +; CI-NEXT: v_mov_b32_e32 v1, s2 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: .LBB12_2: ; %Flow127 +; CI-NEXT: s_xor_b32 s2, s2, 1 +; CI-NEXT: s_cmp_lg_u32 s2, 0 +; CI-NEXT: s_cbranch_scc1 .LBB12_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f32_e64 v1, |s8| +; CI-NEXT: v_ldexp_f32_e64 v1, v1, 1 +; CI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0 +; CI-NEXT: v_frexp_mant_f32_e64 v0, |s4| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s4| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s8| +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v5 +; CI-NEXT: v_ldexp_f32_e64 v4, v0, 12 +; CI-NEXT: v_add_i32_e32 v0, vcc, -1, v6 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v0 +; CI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; CI-NEXT: v_rcp_f32_e32 v8, v3 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 -; CI-NEXT: v_fma_f32 v3, v4, v3, v3 -; CI-NEXT: v_mul_f32_e32 v4, v2, v3 -; CI-NEXT: v_fma_f32 v5, -v1, v4, v2 -; CI-NEXT: v_fma_f32 v4, v5, v3, v4 -; CI-NEXT: v_fma_f32 v1, -v1, v4, v2 +; CI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; CI-NEXT: v_fma_f32 v8, v9, v8, v8 +; CI-NEXT: v_mul_f32_e32 v9, v7, v8 +; CI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; CI-NEXT: v_fma_f32 v9, v10, v8, v9 +; CI-NEXT: v_fma_f32 v3, -v3, v9, v7 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 -; CI-NEXT: v_div_fixup_f32 v1, v1, v0, s4 -; CI-NEXT: v_trunc_f32_e32 v1, v1 -; CI-NEXT: v_fma_f32 v0, -v1, v0, s4 +; CI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2 +; CI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB12_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v2, vcc, 12, v5 +; CI-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CI-NEXT: .LBB12_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: v_mul_f32_e32 v4, v5, v3 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v6, v4, v1 +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; CI-NEXT: v_add_i32_e32 v2, vcc, -12, v2 +; CI-NEXT: v_ldexp_f32_e64 v4, v4, 12 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2 +; CI-NEXT: s_cbranch_vccnz .LBB12_5 +; CI-NEXT: s_branch .LBB12_7 +; CI-NEXT: .LBB12_6: +; CI-NEXT: v_mov_b32_e32 v5, v4 +; CI-NEXT: .LBB12_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v2, vcc, -11, v2 +; CI-NEXT: v_ldexp_f32_e32 v2, v5, v2 +; CI-NEXT: v_mul_f32_e32 v3, v2, v3 +; CI-NEXT: v_rndne_f32_e32 v3, v3 +; CI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; CI-NEXT: v_add_f32_e32 v1, v2, v1 +; CI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; CI-NEXT: v_ldexp_f32_e32 v0, v1, v0 +; CI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; CI-NEXT: s_and_b32 s2, s4, 0x80000000 +; CI-NEXT: v_or_b32_e32 v0, s2, v0 +; CI-NEXT: .LBB12_8: ; %Flow128 ; CI-NEXT: v_mov_b32_e32 v1, s9 -; CI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, s5 -; CI-NEXT: v_div_scale_f32 v3, vcc, s5, v1, s5 -; CI-NEXT: v_rcp_f32_e32 v4, v2 +; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s5|, |v1| +; CI-NEXT: s_mov_b32 s2, 1 +; CI-NEXT: ; implicit-def: $vgpr1 +; CI-NEXT: s_cbranch_vccz .LBB12_10 +; CI-NEXT: ; %bb.9: ; %frem.else16 +; CI-NEXT: s_and_b32 s2, s5, 0x80000000 +; CI-NEXT: v_mov_b32_e32 v2, s9 +; CI-NEXT: v_mov_b32_e32 v1, s5 +; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s5|, |v2| +; CI-NEXT: v_mov_b32_e32 v2, s2 +; CI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: .LBB12_10: ; %Flow123 +; CI-NEXT: s_xor_b32 s2, s2, 1 +; CI-NEXT: s_cmp_lg_u32 s2, 0 +; CI-NEXT: s_cbranch_scc1 .LBB12_16 +; CI-NEXT: ; %bb.11: ; %frem.compute15 +; CI-NEXT: v_frexp_mant_f32_e64 v2, |s9| +; CI-NEXT: v_ldexp_f32_e64 v2, v2, 1 +; CI-NEXT: v_div_scale_f32 v4, s[2:3], v2, v2, 1.0 +; CI-NEXT: v_frexp_mant_f32_e64 v1, |s5| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s5| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s9| +; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v6 +; CI-NEXT: v_ldexp_f32_e64 v5, v1, 12 +; CI-NEXT: v_add_i32_e32 v1, vcc, -1, v7 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v1 +; CI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; CI-NEXT: v_rcp_f32_e32 v9, v4 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 -; CI-NEXT: v_fma_f32 v4, v5, v4, v4 -; CI-NEXT: v_mul_f32_e32 v5, v3, v4 -; CI-NEXT: v_fma_f32 v6, -v2, v5, v3 -; CI-NEXT: v_fma_f32 v5, v6, v4, v5 -; CI-NEXT: v_fma_f32 v2, -v2, v5, v3 +; CI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; CI-NEXT: v_fma_f32 v9, v10, v9, v9 +; CI-NEXT: v_mul_f32_e32 v10, v8, v9 +; CI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; CI-NEXT: v_fma_f32 v10, v11, v9, v10 +; CI-NEXT: v_fma_f32 v4, -v4, v10, v8 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 -; CI-NEXT: v_div_fixup_f32 v2, v2, v1, s5 -; CI-NEXT: v_trunc_f32_e32 v2, v2 -; CI-NEXT: v_fma_f32 v1, -v2, v1, s5 +; CI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3 +; CI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB12_14 +; CI-NEXT: ; %bb.12: ; %frem.loop_body23.preheader +; CI-NEXT: v_add_i32_e32 v3, vcc, 12, v6 +; CI-NEXT: v_sub_i32_e32 v3, vcc, v3, v7 +; CI-NEXT: .LBB12_13: ; %frem.loop_body23 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: v_mul_f32_e32 v5, v6, v4 +; CI-NEXT: v_rndne_f32_e32 v5, v5 +; CI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; CI-NEXT: v_add_f32_e32 v7, v5, v2 +; CI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; CI-NEXT: v_add_i32_e32 v3, vcc, -12, v3 +; CI-NEXT: v_ldexp_f32_e64 v5, v5, 12 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3 +; CI-NEXT: s_cbranch_vccnz .LBB12_13 +; CI-NEXT: s_branch .LBB12_15 +; CI-NEXT: .LBB12_14: +; CI-NEXT: v_mov_b32_e32 v6, v5 +; CI-NEXT: .LBB12_15: ; %frem.loop_exit24 +; CI-NEXT: v_add_i32_e32 v3, vcc, -11, v3 +; CI-NEXT: v_ldexp_f32_e32 v3, v6, v3 +; CI-NEXT: v_mul_f32_e32 v4, v3, v4 +; CI-NEXT: v_rndne_f32_e32 v4, v4 +; CI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; CI-NEXT: v_add_f32_e32 v2, v3, v2 +; CI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; CI-NEXT: v_ldexp_f32_e32 v1, v2, v1 +; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; CI-NEXT: s_and_b32 s2, s5, 0x80000000 +; CI-NEXT: v_or_b32_e32 v1, s2, v1 +; CI-NEXT: .LBB12_16: ; %Flow124 ; CI-NEXT: v_mov_b32_e32 v2, s10 -; CI-NEXT: v_div_scale_f32 v3, s[2:3], v2, v2, s6 -; CI-NEXT: v_div_scale_f32 v4, vcc, s6, v2, s6 -; CI-NEXT: v_rcp_f32_e32 v5, v3 +; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s6|, |v2| +; CI-NEXT: s_mov_b32 s2, 1 +; CI-NEXT: ; implicit-def: $vgpr2 +; CI-NEXT: s_cbranch_vccz .LBB12_18 +; CI-NEXT: ; %bb.17: ; %frem.else47 +; CI-NEXT: s_and_b32 s2, s6, 0x80000000 +; CI-NEXT: v_mov_b32_e32 v3, s10 +; CI-NEXT: v_mov_b32_e32 v2, s6 +; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s6|, |v3| +; CI-NEXT: v_mov_b32_e32 v3, s2 +; CI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: .LBB12_18: ; %Flow119 +; CI-NEXT: s_xor_b32 s2, s2, 1 +; CI-NEXT: s_cmp_lg_u32 s2, 0 +; CI-NEXT: s_cbranch_scc1 .LBB12_24 +; CI-NEXT: ; %bb.19: ; %frem.compute46 +; CI-NEXT: v_frexp_mant_f32_e64 v3, |s10| +; CI-NEXT: v_ldexp_f32_e64 v3, v3, 1 +; CI-NEXT: v_div_scale_f32 v5, s[2:3], v3, v3, 1.0 +; CI-NEXT: v_frexp_mant_f32_e64 v2, |s6| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s6| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s10| +; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v7 +; CI-NEXT: v_ldexp_f32_e64 v6, v2, 12 +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v8 +; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v2 +; CI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0 +; CI-NEXT: v_rcp_f32_e32 v10, v5 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v6, -v3, v5, 1.0 -; CI-NEXT: v_fma_f32 v5, v6, v5, v5 -; CI-NEXT: v_mul_f32_e32 v6, v4, v5 -; CI-NEXT: v_fma_f32 v7, -v3, v6, v4 -; CI-NEXT: v_fma_f32 v6, v7, v5, v6 -; CI-NEXT: v_fma_f32 v3, -v3, v6, v4 +; CI-NEXT: v_fma_f32 v11, -v5, v10, 1.0 +; CI-NEXT: v_fma_f32 v10, v11, v10, v10 +; CI-NEXT: v_mul_f32_e32 v11, v9, v10 +; CI-NEXT: v_fma_f32 v12, -v5, v11, v9 +; CI-NEXT: v_fma_f32 v11, v12, v10, v11 +; CI-NEXT: v_fma_f32 v5, -v5, v11, v9 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v3, v3, v5, v6 -; CI-NEXT: v_div_fixup_f32 v3, v3, v2, s6 -; CI-NEXT: v_trunc_f32_e32 v3, v3 -; CI-NEXT: v_fma_f32 v2, -v3, v2, s6 +; CI-NEXT: v_div_fmas_f32 v5, v5, v10, v11 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v4 +; CI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB12_22 +; CI-NEXT: ; %bb.20: ; %frem.loop_body54.preheader +; CI-NEXT: v_add_i32_e32 v4, vcc, 12, v7 +; CI-NEXT: v_sub_i32_e32 v4, vcc, v4, v8 +; CI-NEXT: .LBB12_21: ; %frem.loop_body54 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v7, v6 +; CI-NEXT: v_mul_f32_e32 v6, v7, v5 +; CI-NEXT: v_rndne_f32_e32 v6, v6 +; CI-NEXT: v_fma_f32 v6, -v6, v3, v7 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6 +; CI-NEXT: v_add_f32_e32 v8, v6, v3 +; CI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc +; CI-NEXT: v_add_i32_e32 v4, vcc, -12, v4 +; CI-NEXT: v_ldexp_f32_e64 v6, v6, 12 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4 +; CI-NEXT: s_cbranch_vccnz .LBB12_21 +; CI-NEXT: s_branch .LBB12_23 +; CI-NEXT: .LBB12_22: +; CI-NEXT: v_mov_b32_e32 v7, v6 +; CI-NEXT: .LBB12_23: ; %frem.loop_exit55 +; CI-NEXT: v_add_i32_e32 v4, vcc, -11, v4 +; CI-NEXT: v_ldexp_f32_e32 v4, v7, v4 +; CI-NEXT: v_mul_f32_e32 v5, v4, v5 +; CI-NEXT: v_rndne_f32_e32 v5, v5 +; CI-NEXT: v_fma_f32 v4, -v5, v3, v4 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; CI-NEXT: v_add_f32_e32 v3, v4, v3 +; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; CI-NEXT: v_ldexp_f32_e32 v2, v3, v2 +; CI-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; CI-NEXT: s_and_b32 s2, s6, 0x80000000 +; CI-NEXT: v_or_b32_e32 v2, s2, v2 +; CI-NEXT: .LBB12_24: ; %Flow120 ; CI-NEXT: v_mov_b32_e32 v3, s11 -; CI-NEXT: v_div_scale_f32 v4, s[2:3], v3, v3, s7 -; CI-NEXT: v_div_scale_f32 v5, vcc, s7, v3, s7 -; CI-NEXT: v_rcp_f32_e32 v6, v4 +; CI-NEXT: v_cmp_ngt_f32_e64 vcc, |s7|, |v3| +; CI-NEXT: s_mov_b32 s2, 1 +; CI-NEXT: ; implicit-def: $vgpr3 +; CI-NEXT: s_cbranch_vccz .LBB12_26 +; CI-NEXT: ; %bb.25: ; %frem.else78 +; CI-NEXT: s_and_b32 s2, s7, 0x80000000 +; CI-NEXT: v_mov_b32_e32 v4, s11 +; CI-NEXT: v_mov_b32_e32 v3, s7 +; CI-NEXT: v_cmp_eq_f32_e64 vcc, |s7|, |v4| +; CI-NEXT: v_mov_b32_e32 v4, s2 +; CI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: .LBB12_26: ; %Flow115 +; CI-NEXT: s_xor_b32 s2, s2, 1 +; CI-NEXT: s_cmp_lg_u32 s2, 0 +; CI-NEXT: s_cbranch_scc1 .LBB12_32 +; CI-NEXT: ; %bb.27: ; %frem.compute77 +; CI-NEXT: v_frexp_mant_f32_e64 v4, |s11| +; CI-NEXT: v_ldexp_f32_e64 v4, v4, 1 +; CI-NEXT: v_div_scale_f32 v6, s[2:3], v4, v4, 1.0 +; CI-NEXT: v_frexp_mant_f32_e64 v3, |s7| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s7| +; CI-NEXT: v_frexp_exp_i32_f32_e64 v9, |s11| +; CI-NEXT: v_add_i32_e32 v5, vcc, -1, v8 +; CI-NEXT: v_ldexp_f32_e64 v7, v3, 12 +; CI-NEXT: v_add_i32_e32 v3, vcc, -1, v9 +; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v3 +; CI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0 +; CI-NEXT: v_rcp_f32_e32 v11, v6 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; CI-NEXT: v_fma_f32 v7, -v4, v6, 1.0 -; CI-NEXT: v_fma_f32 v6, v7, v6, v6 -; CI-NEXT: v_mul_f32_e32 v7, v5, v6 -; CI-NEXT: v_fma_f32 v8, -v4, v7, v5 -; CI-NEXT: v_fma_f32 v7, v8, v6, v7 -; CI-NEXT: v_fma_f32 v4, -v4, v7, v5 +; CI-NEXT: v_fma_f32 v12, -v6, v11, 1.0 +; CI-NEXT: v_fma_f32 v11, v12, v11, v11 +; CI-NEXT: v_mul_f32_e32 v12, v10, v11 +; CI-NEXT: v_fma_f32 v13, -v6, v12, v10 +; CI-NEXT: v_fma_f32 v12, v13, v11, v12 +; CI-NEXT: v_fma_f32 v6, -v6, v12, v10 ; CI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; CI-NEXT: v_div_fmas_f32 v4, v4, v6, v7 +; CI-NEXT: v_div_fmas_f32 v6, v6, v11, v12 +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v5 +; CI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB12_30 +; CI-NEXT: ; %bb.28: ; %frem.loop_body85.preheader +; CI-NEXT: v_add_i32_e32 v5, vcc, 12, v8 +; CI-NEXT: v_sub_i32_e32 v5, vcc, v5, v9 +; CI-NEXT: .LBB12_29: ; %frem.loop_body85 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v8, v7 +; CI-NEXT: v_mul_f32_e32 v7, v8, v6 +; CI-NEXT: v_rndne_f32_e32 v7, v7 +; CI-NEXT: v_fma_f32 v7, -v7, v4, v8 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7 +; CI-NEXT: v_add_f32_e32 v9, v7, v4 +; CI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc +; CI-NEXT: v_add_i32_e32 v5, vcc, -12, v5 +; CI-NEXT: v_ldexp_f32_e64 v7, v7, 12 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v5 +; CI-NEXT: s_cbranch_vccnz .LBB12_29 +; CI-NEXT: s_branch .LBB12_31 +; CI-NEXT: .LBB12_30: +; CI-NEXT: v_mov_b32_e32 v8, v7 +; CI-NEXT: .LBB12_31: ; %frem.loop_exit86 +; CI-NEXT: v_add_i32_e32 v5, vcc, -11, v5 +; CI-NEXT: v_ldexp_f32_e32 v5, v8, v5 +; CI-NEXT: v_mul_f32_e32 v6, v5, v6 +; CI-NEXT: v_rndne_f32_e32 v6, v6 +; CI-NEXT: v_fma_f32 v5, -v6, v4, v5 +; CI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; CI-NEXT: v_add_f32_e32 v4, v5, v4 +; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; CI-NEXT: v_ldexp_f32_e32 v3, v4, v3 +; CI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3 +; CI-NEXT: s_and_b32 s2, s7, 0x80000000 +; CI-NEXT: v_or_b32_e32 v3, s2, v3 +; CI-NEXT: .LBB12_32: ; %Flow116 +; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s8, 0 +; CI-NEXT: v_mov_b32_e32 v4, 0x7fc00000 +; CI-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; CI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s4|, v5 +; CI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s9, 0 +; CI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s5|, v5 +; CI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s10, 0 +; CI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s6|, v5 +; CI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; CI-NEXT: v_cmp_nlg_f32_e64 vcc, s11, 0 +; CI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; CI-NEXT: v_cmp_nge_f32_e64 vcc, |s7|, v5 +; CI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_div_fixup_f32 v4, v4, v3, s7 -; CI-NEXT: v_trunc_f32_e32 v4, v4 -; CI-NEXT: v_fma_f32 v3, -v4, v3, s7 ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CI-NEXT: s_endpgm ; @@ -969,71 +2826,325 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x40 +; VI-NEXT: s_mov_b32 s2, 1 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v0, s8 -; VI-NEXT: v_div_scale_f32 v1, s[2:3], v0, v0, s4 -; VI-NEXT: v_div_scale_f32 v2, vcc, s4, v0, s4 -; VI-NEXT: v_rcp_f32_e32 v3, v1 +; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s4|, |v0| +; VI-NEXT: ; implicit-def: $vgpr0 +; VI-NEXT: s_cbranch_vccz .LBB12_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: s_and_b32 s2, s4, 0x80000000 +; VI-NEXT: v_mov_b32_e32 v1, s8 +; VI-NEXT: v_mov_b32_e32 v0, s4 +; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s4|, |v1| +; VI-NEXT: v_mov_b32_e32 v1, s2 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB12_2: ; %Flow127 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB12_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f32_e64 v1, |s8| +; VI-NEXT: v_ldexp_f32 v1, v1, 1 +; VI-NEXT: v_div_scale_f32 v3, s[2:3], v1, v1, 1.0 +; VI-NEXT: v_frexp_mant_f32_e64 v0, |s4| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v5, |s4| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s8| +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v5 +; VI-NEXT: v_ldexp_f32 v4, v0, 12 +; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v6 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v0 +; VI-NEXT: v_div_scale_f32 v7, vcc, 1.0, v1, 1.0 +; VI-NEXT: v_rcp_f32_e32 v8, v3 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0 -; VI-NEXT: v_fma_f32 v3, v4, v3, v3 -; VI-NEXT: v_mul_f32_e32 v4, v2, v3 -; VI-NEXT: v_fma_f32 v5, -v1, v4, v2 -; VI-NEXT: v_fma_f32 v4, v5, v3, v4 -; VI-NEXT: v_fma_f32 v1, -v1, v4, v2 +; VI-NEXT: v_fma_f32 v9, -v3, v8, 1.0 +; VI-NEXT: v_fma_f32 v8, v9, v8, v8 +; VI-NEXT: v_mul_f32_e32 v9, v7, v8 +; VI-NEXT: v_fma_f32 v10, -v3, v9, v7 +; VI-NEXT: v_fma_f32 v9, v10, v8, v9 +; VI-NEXT: v_fma_f32 v3, -v3, v9, v7 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4 -; VI-NEXT: v_div_fixup_f32 v1, v1, v0, s4 -; VI-NEXT: v_trunc_f32_e32 v1, v1 -; VI-NEXT: v_fma_f32 v0, -v1, v0, s4 +; VI-NEXT: v_div_fmas_f32 v3, v3, v8, v9 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v2 +; VI-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB12_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v5 +; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v6 +; VI-NEXT: .LBB12_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: v_mul_f32_e32 v4, v5, v3 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v4, -v4, v1, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v6, v4, v1 +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; VI-NEXT: v_add_u32_e32 v2, vcc, -12, v2 +; VI-NEXT: v_ldexp_f32 v4, v4, 12 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v2 +; VI-NEXT: s_cbranch_vccnz .LBB12_5 +; VI-NEXT: s_branch .LBB12_7 +; VI-NEXT: .LBB12_6: +; VI-NEXT: v_mov_b32_e32 v5, v4 +; VI-NEXT: .LBB12_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v2, vcc, -11, v2 +; VI-NEXT: v_ldexp_f32 v2, v5, v2 +; VI-NEXT: v_mul_f32_e32 v3, v2, v3 +; VI-NEXT: v_rndne_f32_e32 v3, v3 +; VI-NEXT: v_fma_f32 v2, -v3, v1, v2 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2 +; VI-NEXT: v_add_f32_e32 v1, v2, v1 +; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; VI-NEXT: v_ldexp_f32 v0, v1, v0 +; VI-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; VI-NEXT: s_and_b32 s2, s4, 0x80000000 +; VI-NEXT: v_or_b32_e32 v0, s2, v0 +; VI-NEXT: .LBB12_8: ; %Flow128 ; VI-NEXT: v_mov_b32_e32 v1, s9 -; VI-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, s5 -; VI-NEXT: v_div_scale_f32 v3, vcc, s5, v1, s5 -; VI-NEXT: v_rcp_f32_e32 v4, v2 +; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s5|, |v1| +; VI-NEXT: s_mov_b32 s2, 1 +; VI-NEXT: ; implicit-def: $vgpr1 +; VI-NEXT: s_cbranch_vccz .LBB12_10 +; VI-NEXT: ; %bb.9: ; %frem.else16 +; VI-NEXT: s_and_b32 s2, s5, 0x80000000 +; VI-NEXT: v_mov_b32_e32 v2, s9 +; VI-NEXT: v_mov_b32_e32 v1, s5 +; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s5|, |v2| +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB12_10: ; %Flow123 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB12_16 +; VI-NEXT: ; %bb.11: ; %frem.compute15 +; VI-NEXT: v_frexp_mant_f32_e64 v2, |s9| +; VI-NEXT: v_ldexp_f32 v2, v2, 1 +; VI-NEXT: v_div_scale_f32 v4, s[2:3], v2, v2, 1.0 +; VI-NEXT: v_frexp_mant_f32_e64 v1, |s5| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v6, |s5| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s9| +; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v6 +; VI-NEXT: v_ldexp_f32 v5, v1, 12 +; VI-NEXT: v_add_u32_e32 v1, vcc, -1, v7 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v1 +; VI-NEXT: v_div_scale_f32 v8, vcc, 1.0, v2, 1.0 +; VI-NEXT: v_rcp_f32_e32 v9, v4 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; VI-NEXT: v_fma_f32 v5, -v2, v4, 1.0 -; VI-NEXT: v_fma_f32 v4, v5, v4, v4 -; VI-NEXT: v_mul_f32_e32 v5, v3, v4 -; VI-NEXT: v_fma_f32 v6, -v2, v5, v3 -; VI-NEXT: v_fma_f32 v5, v6, v4, v5 -; VI-NEXT: v_fma_f32 v2, -v2, v5, v3 +; VI-NEXT: v_fma_f32 v10, -v4, v9, 1.0 +; VI-NEXT: v_fma_f32 v9, v10, v9, v9 +; VI-NEXT: v_mul_f32_e32 v10, v8, v9 +; VI-NEXT: v_fma_f32 v11, -v4, v10, v8 +; VI-NEXT: v_fma_f32 v10, v11, v9, v10 +; VI-NEXT: v_fma_f32 v4, -v4, v10, v8 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; VI-NEXT: v_div_fmas_f32 v2, v2, v4, v5 -; VI-NEXT: v_div_fixup_f32 v2, v2, v1, s5 -; VI-NEXT: v_trunc_f32_e32 v2, v2 -; VI-NEXT: v_fma_f32 v1, -v2, v1, s5 +; VI-NEXT: v_div_fmas_f32 v4, v4, v9, v10 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v3 +; VI-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB12_14 +; VI-NEXT: ; %bb.12: ; %frem.loop_body23.preheader +; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v6 +; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v7 +; VI-NEXT: .LBB12_13: ; %frem.loop_body23 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: v_mul_f32_e32 v5, v6, v4 +; VI-NEXT: v_rndne_f32_e32 v5, v5 +; VI-NEXT: v_fma_f32 v5, -v5, v2, v6 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; VI-NEXT: v_add_f32_e32 v7, v5, v2 +; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; VI-NEXT: v_add_u32_e32 v3, vcc, -12, v3 +; VI-NEXT: v_ldexp_f32 v5, v5, 12 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v3 +; VI-NEXT: s_cbranch_vccnz .LBB12_13 +; VI-NEXT: s_branch .LBB12_15 +; VI-NEXT: .LBB12_14: +; VI-NEXT: v_mov_b32_e32 v6, v5 +; VI-NEXT: .LBB12_15: ; %frem.loop_exit24 +; VI-NEXT: v_add_u32_e32 v3, vcc, -11, v3 +; VI-NEXT: v_ldexp_f32 v3, v6, v3 +; VI-NEXT: v_mul_f32_e32 v4, v3, v4 +; VI-NEXT: v_rndne_f32_e32 v4, v4 +; VI-NEXT: v_fma_f32 v3, -v4, v2, v3 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3 +; VI-NEXT: v_add_f32_e32 v2, v3, v2 +; VI-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc +; VI-NEXT: v_ldexp_f32 v1, v2, v1 +; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; VI-NEXT: s_and_b32 s2, s5, 0x80000000 +; VI-NEXT: v_or_b32_e32 v1, s2, v1 +; VI-NEXT: .LBB12_16: ; %Flow124 ; VI-NEXT: v_mov_b32_e32 v2, s10 -; VI-NEXT: v_div_scale_f32 v3, s[2:3], v2, v2, s6 -; VI-NEXT: v_div_scale_f32 v4, vcc, s6, v2, s6 -; VI-NEXT: v_rcp_f32_e32 v5, v3 +; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s6|, |v2| +; VI-NEXT: s_mov_b32 s2, 1 +; VI-NEXT: ; implicit-def: $vgpr2 +; VI-NEXT: s_cbranch_vccz .LBB12_18 +; VI-NEXT: ; %bb.17: ; %frem.else47 +; VI-NEXT: s_and_b32 s2, s6, 0x80000000 +; VI-NEXT: v_mov_b32_e32 v3, s10 +; VI-NEXT: v_mov_b32_e32 v2, s6 +; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s6|, |v3| +; VI-NEXT: v_mov_b32_e32 v3, s2 +; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB12_18: ; %Flow119 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB12_24 +; VI-NEXT: ; %bb.19: ; %frem.compute46 +; VI-NEXT: v_frexp_mant_f32_e64 v3, |s10| +; VI-NEXT: v_ldexp_f32 v3, v3, 1 +; VI-NEXT: v_div_scale_f32 v5, s[2:3], v3, v3, 1.0 +; VI-NEXT: v_frexp_mant_f32_e64 v2, |s6| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v7, |s6| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s10| +; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v7 +; VI-NEXT: v_ldexp_f32 v6, v2, 12 +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v8 +; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v2 +; VI-NEXT: v_div_scale_f32 v9, vcc, 1.0, v3, 1.0 +; VI-NEXT: v_rcp_f32_e32 v10, v5 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; VI-NEXT: v_fma_f32 v6, -v3, v5, 1.0 -; VI-NEXT: v_fma_f32 v5, v6, v5, v5 -; VI-NEXT: v_mul_f32_e32 v6, v4, v5 -; VI-NEXT: v_fma_f32 v7, -v3, v6, v4 -; VI-NEXT: v_fma_f32 v6, v7, v5, v6 -; VI-NEXT: v_fma_f32 v3, -v3, v6, v4 +; VI-NEXT: v_fma_f32 v11, -v5, v10, 1.0 +; VI-NEXT: v_fma_f32 v10, v11, v10, v10 +; VI-NEXT: v_mul_f32_e32 v11, v9, v10 +; VI-NEXT: v_fma_f32 v12, -v5, v11, v9 +; VI-NEXT: v_fma_f32 v11, v12, v10, v11 +; VI-NEXT: v_fma_f32 v5, -v5, v11, v9 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; VI-NEXT: v_div_fmas_f32 v3, v3, v5, v6 -; VI-NEXT: v_div_fixup_f32 v3, v3, v2, s6 -; VI-NEXT: v_trunc_f32_e32 v3, v3 -; VI-NEXT: v_fma_f32 v2, -v3, v2, s6 +; VI-NEXT: v_div_fmas_f32 v5, v5, v10, v11 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v4 +; VI-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB12_22 +; VI-NEXT: ; %bb.20: ; %frem.loop_body54.preheader +; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v7 +; VI-NEXT: v_sub_u32_e32 v4, vcc, v4, v8 +; VI-NEXT: .LBB12_21: ; %frem.loop_body54 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: v_mul_f32_e32 v6, v7, v5 +; VI-NEXT: v_rndne_f32_e32 v6, v6 +; VI-NEXT: v_fma_f32 v6, -v6, v3, v7 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v6 +; VI-NEXT: v_add_f32_e32 v8, v6, v3 +; VI-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc +; VI-NEXT: v_add_u32_e32 v4, vcc, -12, v4 +; VI-NEXT: v_ldexp_f32 v6, v6, 12 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v4 +; VI-NEXT: s_cbranch_vccnz .LBB12_21 +; VI-NEXT: s_branch .LBB12_23 +; VI-NEXT: .LBB12_22: +; VI-NEXT: v_mov_b32_e32 v7, v6 +; VI-NEXT: .LBB12_23: ; %frem.loop_exit55 +; VI-NEXT: v_add_u32_e32 v4, vcc, -11, v4 +; VI-NEXT: v_ldexp_f32 v4, v7, v4 +; VI-NEXT: v_mul_f32_e32 v5, v4, v5 +; VI-NEXT: v_rndne_f32_e32 v5, v5 +; VI-NEXT: v_fma_f32 v4, -v5, v3, v4 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v4 +; VI-NEXT: v_add_f32_e32 v3, v4, v3 +; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; VI-NEXT: v_ldexp_f32 v2, v3, v2 +; VI-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; VI-NEXT: s_and_b32 s2, s6, 0x80000000 +; VI-NEXT: v_or_b32_e32 v2, s2, v2 +; VI-NEXT: .LBB12_24: ; %Flow120 ; VI-NEXT: v_mov_b32_e32 v3, s11 -; VI-NEXT: v_div_scale_f32 v4, s[2:3], v3, v3, s7 -; VI-NEXT: v_div_scale_f32 v5, vcc, s7, v3, s7 -; VI-NEXT: v_rcp_f32_e32 v6, v4 +; VI-NEXT: v_cmp_ngt_f32_e64 vcc, |s7|, |v3| +; VI-NEXT: s_mov_b32 s2, 1 +; VI-NEXT: ; implicit-def: $vgpr3 +; VI-NEXT: s_cbranch_vccz .LBB12_26 +; VI-NEXT: ; %bb.25: ; %frem.else78 +; VI-NEXT: s_and_b32 s2, s7, 0x80000000 +; VI-NEXT: v_mov_b32_e32 v4, s11 +; VI-NEXT: v_mov_b32_e32 v3, s7 +; VI-NEXT: v_cmp_eq_f32_e64 vcc, |s7|, |v4| +; VI-NEXT: v_mov_b32_e32 v4, s2 +; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB12_26: ; %Flow115 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB12_32 +; VI-NEXT: ; %bb.27: ; %frem.compute77 +; VI-NEXT: v_frexp_mant_f32_e64 v4, |s11| +; VI-NEXT: v_ldexp_f32 v4, v4, 1 +; VI-NEXT: v_div_scale_f32 v6, s[2:3], v4, v4, 1.0 +; VI-NEXT: v_frexp_mant_f32_e64 v3, |s7| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v8, |s7| +; VI-NEXT: v_frexp_exp_i32_f32_e64 v9, |s11| +; VI-NEXT: v_add_u32_e32 v5, vcc, -1, v8 +; VI-NEXT: v_ldexp_f32 v7, v3, 12 +; VI-NEXT: v_add_u32_e32 v3, vcc, -1, v9 +; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v3 +; VI-NEXT: v_div_scale_f32 v10, vcc, 1.0, v4, 1.0 +; VI-NEXT: v_rcp_f32_e32 v11, v6 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3 -; VI-NEXT: v_fma_f32 v7, -v4, v6, 1.0 -; VI-NEXT: v_fma_f32 v6, v7, v6, v6 -; VI-NEXT: v_mul_f32_e32 v7, v5, v6 -; VI-NEXT: v_fma_f32 v8, -v4, v7, v5 -; VI-NEXT: v_fma_f32 v7, v8, v6, v7 -; VI-NEXT: v_fma_f32 v4, -v4, v7, v5 +; VI-NEXT: v_fma_f32 v12, -v6, v11, 1.0 +; VI-NEXT: v_fma_f32 v11, v12, v11, v11 +; VI-NEXT: v_mul_f32_e32 v12, v10, v11 +; VI-NEXT: v_fma_f32 v13, -v6, v12, v10 +; VI-NEXT: v_fma_f32 v12, v13, v11, v12 +; VI-NEXT: v_fma_f32 v6, -v6, v12, v10 ; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0 -; VI-NEXT: v_div_fmas_f32 v4, v4, v6, v7 -; VI-NEXT: v_div_fixup_f32 v4, v4, v3, s7 -; VI-NEXT: v_trunc_f32_e32 v4, v4 -; VI-NEXT: v_fma_f32 v3, -v4, v3, s7 +; VI-NEXT: v_div_fmas_f32 v6, v6, v11, v12 +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 12, v5 +; VI-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB12_30 +; VI-NEXT: ; %bb.28: ; %frem.loop_body85.preheader +; VI-NEXT: v_add_u32_e32 v5, vcc, 12, v8 +; VI-NEXT: v_sub_u32_e32 v5, vcc, v5, v9 +; VI-NEXT: .LBB12_29: ; %frem.loop_body85 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: v_mul_f32_e32 v7, v8, v6 +; VI-NEXT: v_rndne_f32_e32 v7, v7 +; VI-NEXT: v_fma_f32 v7, -v7, v4, v8 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v7 +; VI-NEXT: v_add_f32_e32 v9, v7, v4 +; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, -12, v5 +; VI-NEXT: v_ldexp_f32 v7, v7, 12 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 12, v5 +; VI-NEXT: s_cbranch_vccnz .LBB12_29 +; VI-NEXT: s_branch .LBB12_31 +; VI-NEXT: .LBB12_30: +; VI-NEXT: v_mov_b32_e32 v8, v7 +; VI-NEXT: .LBB12_31: ; %frem.loop_exit86 +; VI-NEXT: v_add_u32_e32 v5, vcc, -11, v5 +; VI-NEXT: v_ldexp_f32 v5, v8, v5 +; VI-NEXT: v_mul_f32_e32 v6, v5, v6 +; VI-NEXT: v_rndne_f32_e32 v6, v6 +; VI-NEXT: v_fma_f32 v5, -v6, v4, v5 +; VI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v5 +; VI-NEXT: v_add_f32_e32 v4, v5, v4 +; VI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc +; VI-NEXT: v_ldexp_f32 v3, v4, v3 +; VI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3 +; VI-NEXT: s_and_b32 s2, s7, 0x80000000 +; VI-NEXT: v_or_b32_e32 v3, s2, v3 +; VI-NEXT: .LBB12_32: ; %Flow116 +; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s8, 0 +; VI-NEXT: v_mov_b32_e32 v4, 0x7fc00000 +; VI-NEXT: v_mov_b32_e32 v5, 0x7f800000 +; VI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s4|, v5 +; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc +; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s9, 0 +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s5|, v5 +; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc +; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s10, 0 +; VI-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s6|, v5 +; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; VI-NEXT: v_cmp_nlg_f32_e64 vcc, s11, 0 +; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc +; VI-NEXT: v_cmp_nge_f32_e64 vcc, |s7|, v5 +; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc ; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v4, s0 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] @@ -1054,39 +3165,198 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; CI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10 +; CI-NEXT: s_mov_b32 s2, 1 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v0, s8 ; CI-NEXT: v_mov_b32_e32 v1, s9 -; CI-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[4:5] -; CI-NEXT: v_div_scale_f64 v[8:9], vcc, s[4:5], v[0:1], s[4:5] -; CI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] -; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 -; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] -; CI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 -; CI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] -; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] -; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] -; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] -; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[4:5] -; CI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] -; CI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[4:5] +; CI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[4:5]|, |v[0:1]| +; CI-NEXT: ; implicit-def: $vgpr0_vgpr1 +; CI-NEXT: s_cbranch_vccz .LBB13_2 +; CI-NEXT: ; %bb.1: ; %frem.else +; CI-NEXT: v_mov_b32_e32 v0, s8 +; CI-NEXT: v_mov_b32_e32 v1, s9 +; CI-NEXT: v_cmp_eq_f64_e64 vcc, |s[4:5]|, |v[0:1]| +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: s_brev_b32 s3, 1 +; CI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] +; CI-NEXT: v_mov_b32_e32 v0, s2 +; CI-NEXT: v_mov_b32_e32 v1, s3 +; CI-NEXT: v_mov_b32_e32 v2, s4 +; CI-NEXT: v_mov_b32_e32 v3, s5 +; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: .LBB13_2: ; %Flow53 +; CI-NEXT: s_xor_b32 s2, s2, 1 +; CI-NEXT: s_cmp_lg_u32 s2, 0 +; CI-NEXT: s_cbranch_scc1 .LBB13_8 +; CI-NEXT: ; %bb.3: ; %frem.compute +; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| +; CI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[4:5]| +; CI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[8:9]| +; CI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26 +; CI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[8:9]| +; CI-NEXT: v_add_i32_e32 v2, vcc, -1, v6 +; CI-NEXT: v_add_i32_e32 v8, vcc, -1, v7 +; CI-NEXT: v_sub_i32_e32 v9, vcc, v2, v8 +; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 +; CI-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], 1.0 +; CI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0 +; CI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3] +; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; CI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; CI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; CI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11] +; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15] +; CI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13] +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9 +; CI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB13_6 +; CI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; CI-NEXT: v_add_i32_e32 v6, vcc, 26, v6 +; CI-NEXT: v_sub_i32_e32 v9, vcc, v6, v7 +; CI-NEXT: .LBB13_5: ; %frem.loop_body +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v7, v5 +; CI-NEXT: v_mov_b32_e32 v6, v4 +; CI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3] +; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] +; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7] +; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] +; CI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1] +; CI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc +; CI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc +; CI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26 +; CI-NEXT: v_add_i32_e32 v9, vcc, 0xffffffe6, v9 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9 +; CI-NEXT: s_cbranch_vccnz .LBB13_5 +; CI-NEXT: s_branch .LBB13_7 +; CI-NEXT: .LBB13_6: +; CI-NEXT: v_mov_b32_e32 v7, v5 +; CI-NEXT: v_mov_b32_e32 v6, v4 +; CI-NEXT: .LBB13_7: ; %frem.loop_exit +; CI-NEXT: v_add_i32_e32 v4, vcc, 0xffffffe7, v9 +; CI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4 +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: s_brev_b32 s3, 1 +; CI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] +; CI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] +; CI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] +; CI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] +; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] +; CI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] +; CI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; CI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; CI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8 +; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; CI-NEXT: v_or_b32_e32 v0, s2, v0 +; CI-NEXT: v_or_b32_e32 v1, s3, v1 +; CI-NEXT: .LBB13_8: ; %Flow54 +; CI-NEXT: v_mov_b32_e32 v2, s10 +; CI-NEXT: v_mov_b32_e32 v3, s11 +; CI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[6:7]|, |v[2:3]| +; CI-NEXT: s_mov_b32 s2, 1 +; CI-NEXT: ; implicit-def: $vgpr2_vgpr3 +; CI-NEXT: s_cbranch_vccz .LBB13_10 +; CI-NEXT: ; %bb.9: ; %frem.else16 ; CI-NEXT: v_mov_b32_e32 v2, s10 ; CI-NEXT: v_mov_b32_e32 v3, s11 -; CI-NEXT: v_div_scale_f64 v[4:5], s[2:3], v[2:3], v[2:3], s[6:7] -; CI-NEXT: v_div_scale_f64 v[10:11], vcc, s[6:7], v[2:3], s[6:7] +; CI-NEXT: v_cmp_eq_f64_e64 vcc, |s[6:7]|, |v[2:3]| +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: s_brev_b32 s3, 1 +; CI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3] +; CI-NEXT: v_mov_b32_e32 v2, s2 +; CI-NEXT: v_mov_b32_e32 v3, s3 +; CI-NEXT: v_mov_b32_e32 v4, s6 +; CI-NEXT: v_mov_b32_e32 v5, s7 +; CI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: .LBB13_10: ; %Flow49 +; CI-NEXT: s_xor_b32 s2, s2, 1 +; CI-NEXT: s_cmp_lg_u32 s2, 0 +; CI-NEXT: s_cbranch_scc1 .LBB13_16 +; CI-NEXT: ; %bb.11: ; %frem.compute15 +; CI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[6:7]| +; CI-NEXT: v_frexp_exp_i32_f64_e64 v8, |s[6:7]| +; CI-NEXT: v_frexp_exp_i32_f64_e64 v9, |s[10:11]| +; CI-NEXT: v_ldexp_f64 v[6:7], v[2:3], 26 +; CI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[10:11]| +; CI-NEXT: v_add_i32_e32 v4, vcc, -1, v8 +; CI-NEXT: v_add_i32_e32 v10, vcc, -1, v9 +; CI-NEXT: v_sub_i32_e32 v11, vcc, v4, v10 +; CI-NEXT: v_ldexp_f64 v[2:3], v[2:3], 1 +; CI-NEXT: v_div_scale_f64 v[4:5], s[2:3], v[2:3], v[2:3], 1.0 +; CI-NEXT: v_div_scale_f64 v[16:17], vcc, 1.0, v[2:3], 1.0 +; CI-NEXT: v_rcp_f64_e32 v[12:13], v[4:5] +; CI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0 +; CI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] +; CI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0 +; CI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] +; CI-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13] +; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[16:17] +; CI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[14:15] +; CI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v11 +; CI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0 +; CI-NEXT: s_cbranch_vccnz .LBB13_14 +; CI-NEXT: ; %bb.12: ; %frem.loop_body23.preheader +; CI-NEXT: v_add_i32_e32 v8, vcc, 26, v8 +; CI-NEXT: v_sub_i32_e32 v11, vcc, v8, v9 +; CI-NEXT: .LBB13_13: ; %frem.loop_body23 +; CI-NEXT: ; =>This Inner Loop Header: Depth=1 +; CI-NEXT: v_mov_b32_e32 v9, v7 +; CI-NEXT: v_mov_b32_e32 v8, v6 +; CI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] +; CI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7] +; CI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9] +; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7] +; CI-NEXT: v_add_f64 v[12:13], v[6:7], v[2:3] +; CI-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc +; CI-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc +; CI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26 +; CI-NEXT: v_add_i32_e32 v11, vcc, 0xffffffe6, v11 +; CI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v11 +; CI-NEXT: s_cbranch_vccnz .LBB13_13 +; CI-NEXT: s_branch .LBB13_15 +; CI-NEXT: .LBB13_14: +; CI-NEXT: v_mov_b32_e32 v9, v7 +; CI-NEXT: v_mov_b32_e32 v8, v6 +; CI-NEXT: .LBB13_15: ; %frem.loop_exit24 +; CI-NEXT: v_add_i32_e32 v6, vcc, 0xffffffe7, v11 +; CI-NEXT: v_ldexp_f64 v[6:7], v[8:9], v6 +; CI-NEXT: s_mov_b32 s2, 0 +; CI-NEXT: s_brev_b32 s3, 1 +; CI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3] +; CI-NEXT: v_mul_f64 v[4:5], v[6:7], v[4:5] +; CI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] +; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7] +; CI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] +; CI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3] +; CI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; CI-NEXT: v_ldexp_f64 v[2:3], v[2:3], v10 +; CI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3 +; CI-NEXT: v_or_b32_e32 v2, s2, v2 +; CI-NEXT: v_or_b32_e32 v3, s3, v3 +; CI-NEXT: .LBB13_16: ; %Flow50 +; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[8:9], 0 +; CI-NEXT: v_mov_b32_e32 v4, 0 +; CI-NEXT: v_mov_b32_e32 v6, 0x7ff80000 +; CI-NEXT: v_mov_b32_e32 v5, 0x7ff00000 ; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s3, 0xf000 -; CI-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] -; CI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 -; CI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] -; CI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 -; CI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] -; CI-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] -; CI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] -; CI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] -; CI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], s[6:7] -; CI-NEXT: v_trunc_f64_e32 v[4:5], v[4:5] -; CI-NEXT: v_fma_f64 v[2:3], -v[4:5], v[2:3], s[6:7] +; CI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc +; CI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc +; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[4:5]|, v[4:5] +; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; CI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[10:11], 0 +; CI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc +; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[6:7]|, v[4:5] +; CI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; CI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CI-NEXT: s_endpgm ; @@ -1097,39 +3367,198 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 ; VI-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x40 +; VI-NEXT: s_mov_b32 s2, 1 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v0, s8 ; VI-NEXT: v_mov_b32_e32 v1, s9 -; VI-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], s[4:5] -; VI-NEXT: v_div_scale_f64 v[8:9], vcc, s[4:5], v[0:1], s[4:5] -; VI-NEXT: v_rcp_f64_e32 v[4:5], v[2:3] -; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 -; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] -; VI-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0 -; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5] -; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] -; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9] -; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7] -; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], s[4:5] -; VI-NEXT: v_trunc_f64_e32 v[2:3], v[2:3] -; VI-NEXT: v_fma_f64 v[0:1], -v[2:3], v[0:1], s[4:5] +; VI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[4:5]|, |v[0:1]| +; VI-NEXT: ; implicit-def: $vgpr0_vgpr1 +; VI-NEXT: s_cbranch_vccz .LBB13_2 +; VI-NEXT: ; %bb.1: ; %frem.else +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: v_cmp_eq_f64_e64 vcc, |s[4:5]|, |v[0:1]| +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: s_brev_b32 s3, 1 +; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] +; VI-NEXT: v_mov_b32_e32 v0, s2 +; VI-NEXT: v_mov_b32_e32 v1, s3 +; VI-NEXT: v_mov_b32_e32 v2, s4 +; VI-NEXT: v_mov_b32_e32 v3, s5 +; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB13_2: ; %Flow53 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB13_8 +; VI-NEXT: ; %bb.3: ; %frem.compute +; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[4:5]| +; VI-NEXT: v_frexp_exp_i32_f64_e64 v6, |s[4:5]| +; VI-NEXT: v_frexp_exp_i32_f64_e64 v7, |s[8:9]| +; VI-NEXT: v_ldexp_f64 v[4:5], v[0:1], 26 +; VI-NEXT: v_frexp_mant_f64_e64 v[0:1], |s[8:9]| +; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v6 +; VI-NEXT: v_add_u32_e32 v8, vcc, -1, v7 +; VI-NEXT: v_sub_u32_e32 v9, vcc, v2, v8 +; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], 1 +; VI-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], 1.0 +; VI-NEXT: v_div_scale_f64 v[14:15], vcc, 1.0, v[0:1], 1.0 +; VI-NEXT: v_rcp_f64_e32 v[10:11], v[2:3] +; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; VI-NEXT: v_fma_f64 v[12:13], -v[2:3], v[10:11], 1.0 +; VI-NEXT: v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11] +; VI-NEXT: v_mul_f64 v[12:13], v[14:15], v[10:11] +; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[12:13], v[14:15] +; VI-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[10:11], v[12:13] +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v9 +; VI-NEXT: v_div_fixup_f64 v[2:3], v[2:3], v[0:1], 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB13_6 +; VI-NEXT: ; %bb.4: ; %frem.loop_body.preheader +; VI-NEXT: v_add_u32_e32 v6, vcc, 26, v6 +; VI-NEXT: v_sub_u32_e32 v9, vcc, v6, v7 +; VI-NEXT: .LBB13_5: ; %frem.loop_body +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v7, v5 +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: v_mul_f64 v[4:5], v[6:7], v[2:3] +; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] +; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[0:1], v[6:7] +; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] +; VI-NEXT: v_add_f64 v[10:11], v[4:5], v[0:1] +; VI-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc +; VI-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc +; VI-NEXT: v_ldexp_f64 v[4:5], v[4:5], 26 +; VI-NEXT: v_add_u32_e32 v9, vcc, 0xffffffe6, v9 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v9 +; VI-NEXT: s_cbranch_vccnz .LBB13_5 +; VI-NEXT: s_branch .LBB13_7 +; VI-NEXT: .LBB13_6: +; VI-NEXT: v_mov_b32_e32 v7, v5 +; VI-NEXT: v_mov_b32_e32 v6, v4 +; VI-NEXT: .LBB13_7: ; %frem.loop_exit +; VI-NEXT: v_add_u32_e32 v4, vcc, 0xffffffe7, v9 +; VI-NEXT: v_ldexp_f64 v[4:5], v[6:7], v4 +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: s_brev_b32 s3, 1 +; VI-NEXT: s_and_b64 s[2:3], s[4:5], s[2:3] +; VI-NEXT: v_mul_f64 v[2:3], v[4:5], v[2:3] +; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3] +; VI-NEXT: v_fma_f64 v[2:3], -v[2:3], v[0:1], v[4:5] +; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[2:3] +; VI-NEXT: v_add_f64 v[0:1], v[2:3], v[0:1] +; VI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; VI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8 +; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 +; VI-NEXT: v_or_b32_e32 v0, s2, v0 +; VI-NEXT: v_or_b32_e32 v1, s3, v1 +; VI-NEXT: .LBB13_8: ; %Flow54 +; VI-NEXT: v_mov_b32_e32 v2, s10 +; VI-NEXT: v_mov_b32_e32 v3, s11 +; VI-NEXT: v_cmp_ngt_f64_e64 vcc, |s[6:7]|, |v[2:3]| +; VI-NEXT: s_mov_b32 s2, 1 +; VI-NEXT: ; implicit-def: $vgpr2_vgpr3 +; VI-NEXT: s_cbranch_vccz .LBB13_10 +; VI-NEXT: ; %bb.9: ; %frem.else16 ; VI-NEXT: v_mov_b32_e32 v2, s10 ; VI-NEXT: v_mov_b32_e32 v3, s11 -; VI-NEXT: v_div_scale_f64 v[4:5], s[2:3], v[2:3], v[2:3], s[6:7] -; VI-NEXT: v_div_scale_f64 v[10:11], vcc, s[6:7], v[2:3], s[6:7] -; VI-NEXT: v_rcp_f64_e32 v[6:7], v[4:5] -; VI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 -; VI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] -; VI-NEXT: v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0 -; VI-NEXT: v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7] -; VI-NEXT: v_mul_f64 v[8:9], v[10:11], v[6:7] -; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11] -; VI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9] -; VI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], s[6:7] -; VI-NEXT: v_trunc_f64_e32 v[4:5], v[4:5] -; VI-NEXT: v_fma_f64 v[2:3], -v[4:5], v[2:3], s[6:7] +; VI-NEXT: v_cmp_eq_f64_e64 vcc, |s[6:7]|, |v[2:3]| +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: s_brev_b32 s3, 1 +; VI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3] +; VI-NEXT: v_mov_b32_e32 v2, s2 +; VI-NEXT: v_mov_b32_e32 v3, s3 +; VI-NEXT: v_mov_b32_e32 v4, s6 +; VI-NEXT: v_mov_b32_e32 v5, s7 +; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: .LBB13_10: ; %Flow49 +; VI-NEXT: s_xor_b32 s2, s2, 1 +; VI-NEXT: s_cmp_lg_u32 s2, 0 +; VI-NEXT: s_cbranch_scc1 .LBB13_16 +; VI-NEXT: ; %bb.11: ; %frem.compute15 +; VI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[6:7]| +; VI-NEXT: v_frexp_exp_i32_f64_e64 v8, |s[6:7]| +; VI-NEXT: v_frexp_exp_i32_f64_e64 v9, |s[10:11]| +; VI-NEXT: v_ldexp_f64 v[6:7], v[2:3], 26 +; VI-NEXT: v_frexp_mant_f64_e64 v[2:3], |s[10:11]| +; VI-NEXT: v_add_u32_e32 v4, vcc, -1, v8 +; VI-NEXT: v_add_u32_e32 v10, vcc, -1, v9 +; VI-NEXT: v_sub_u32_e32 v11, vcc, v4, v10 +; VI-NEXT: v_ldexp_f64 v[2:3], v[2:3], 1 +; VI-NEXT: v_div_scale_f64 v[4:5], s[2:3], v[2:3], v[2:3], 1.0 +; VI-NEXT: v_div_scale_f64 v[16:17], vcc, 1.0, v[2:3], 1.0 +; VI-NEXT: v_rcp_f64_e32 v[12:13], v[4:5] +; VI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0 +; VI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] +; VI-NEXT: v_fma_f64 v[14:15], -v[4:5], v[12:13], 1.0 +; VI-NEXT: v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13] +; VI-NEXT: v_mul_f64 v[14:15], v[16:17], v[12:13] +; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[14:15], v[16:17] +; VI-NEXT: v_div_fmas_f64 v[4:5], v[4:5], v[12:13], v[14:15] +; VI-NEXT: v_cmp_ge_i32_e32 vcc, 26, v11 +; VI-NEXT: v_div_fixup_f64 v[4:5], v[4:5], v[2:3], 1.0 +; VI-NEXT: s_cbranch_vccnz .LBB13_14 +; VI-NEXT: ; %bb.12: ; %frem.loop_body23.preheader +; VI-NEXT: v_add_u32_e32 v8, vcc, 26, v8 +; VI-NEXT: v_sub_u32_e32 v11, vcc, v8, v9 +; VI-NEXT: .LBB13_13: ; %frem.loop_body23 +; VI-NEXT: ; =>This Inner Loop Header: Depth=1 +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v8, v6 +; VI-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5] +; VI-NEXT: v_rndne_f64_e32 v[6:7], v[6:7] +; VI-NEXT: v_fma_f64 v[6:7], -v[6:7], v[2:3], v[8:9] +; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[6:7] +; VI-NEXT: v_add_f64 v[12:13], v[6:7], v[2:3] +; VI-NEXT: v_cndmask_b32_e32 v6, v6, v12, vcc +; VI-NEXT: v_cndmask_b32_e32 v7, v7, v13, vcc +; VI-NEXT: v_ldexp_f64 v[6:7], v[6:7], 26 +; VI-NEXT: v_add_u32_e32 v11, vcc, 0xffffffe6, v11 +; VI-NEXT: v_cmp_lt_i32_e32 vcc, 26, v11 +; VI-NEXT: s_cbranch_vccnz .LBB13_13 +; VI-NEXT: s_branch .LBB13_15 +; VI-NEXT: .LBB13_14: +; VI-NEXT: v_mov_b32_e32 v9, v7 +; VI-NEXT: v_mov_b32_e32 v8, v6 +; VI-NEXT: .LBB13_15: ; %frem.loop_exit24 +; VI-NEXT: v_add_u32_e32 v6, vcc, 0xffffffe7, v11 +; VI-NEXT: v_ldexp_f64 v[6:7], v[8:9], v6 +; VI-NEXT: s_mov_b32 s2, 0 +; VI-NEXT: s_brev_b32 s3, 1 +; VI-NEXT: s_and_b64 s[2:3], s[6:7], s[2:3] +; VI-NEXT: v_mul_f64 v[4:5], v[6:7], v[4:5] +; VI-NEXT: v_rndne_f64_e32 v[4:5], v[4:5] +; VI-NEXT: v_fma_f64 v[4:5], -v[4:5], v[2:3], v[6:7] +; VI-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[4:5] +; VI-NEXT: v_add_f64 v[2:3], v[4:5], v[2:3] +; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; VI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; VI-NEXT: v_ldexp_f64 v[2:3], v[2:3], v10 +; VI-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3 +; VI-NEXT: v_or_b32_e32 v2, s2, v2 +; VI-NEXT: v_or_b32_e32 v3, s3, v3 +; VI-NEXT: .LBB13_16: ; %Flow50 +; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[8:9], 0 +; VI-NEXT: v_mov_b32_e32 v4, 0 +; VI-NEXT: v_mov_b32_e32 v6, 0x7ff80000 +; VI-NEXT: v_mov_b32_e32 v5, 0x7ff00000 +; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc +; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[4:5]|, v[4:5] +; VI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; VI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[10:11], 0 +; VI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc +; VI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc +; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[6:7]|, v[4:5] ; VI-NEXT: v_mov_b32_e32 v5, s1 ; VI-NEXT: v_mov_b32_e32 v4, s0 +; VI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc +; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: s_endpgm %gep2 = getelementptr <2 x double>, ptr addrspace(1) %in2, i32 4 |