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-rw-r--r--llvm/test/CodeGen/AArch64/arm64-vcvt.ll748
1 files changed, 397 insertions, 351 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-vcvt.ll b/llvm/test/CodeGen/AArch64/arm64-vcvt.ll
index be21776e26f8..60fcb643fb9f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vcvt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vcvt.ll
@@ -1,43 +1,48 @@
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-eabi -pass-remarks-missed=gisel-* \
-; RUN: -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | \
-; RUN: FileCheck %s --check-prefixes=FALLBACK,CHECK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for fcvtas_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtau_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtms_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtmu_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtps_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtpu_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtns_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fcvtnu_1d
-; FALLBACK-NOT: remark{{.*}}fcvtas_2s
define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtas_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtas.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtas_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
-; FALLBACK-NOT: remark{{.*}}fcvtas_4s
define <4 x i32> @fcvtas_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtas_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtas.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtas_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
-; FALLBACK-NOT: remark{{.*}}fcvtas_2d
define <2 x i64> @fcvtas_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtas_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtas.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtas_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtas_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtas_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtas d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtas_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtas d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -48,37 +53,37 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtau_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtau_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtau.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtau_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtau_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtau_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtau.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtau_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtau_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtau_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtau.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtau_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtau_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtau_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtau d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtau_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtau d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -89,37 +94,37 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtms_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtms_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtms.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtms_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtms_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtms_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtms.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtms_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtms_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtms_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtms.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtms_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtms_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtms_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtms d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtms_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtms d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -130,37 +135,37 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtmu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtmu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtmu.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtmu_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtmu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtmu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtmu.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtmu_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtmu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtmu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtmu.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtmu_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtmu_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtmu_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtmu d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtmu_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtmu d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -171,37 +176,37 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtps_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtps_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtps.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtps_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtps_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtps_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtps.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtps_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtps_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtps_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtps.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtps_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtps_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtps_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtps d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtps_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtps d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -212,37 +217,37 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtpu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtpu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtpu.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtpu_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtpu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtpu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtpu.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtpu_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtpu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtpu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtpu.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtpu_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtpu_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtpu_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtpu d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtpu_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtpu d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -253,37 +258,37 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtns_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtns_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtns.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtns_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtns_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtns_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtns.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtns_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtns_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtns_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtns.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtns_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtns_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtns_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtns d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtns_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtns d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -294,37 +299,37 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtnu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtnu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtnu.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtnu_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtnu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtnu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtnu.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtnu_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtnu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtnu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtnu.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtnu_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtnu_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtnu_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtnu d0, d0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtnu_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtnu d0, d0
+; CHECK-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -335,75 +340,81 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtzs_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzs_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzs_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = fptosi <2 x float> %A to <2 x i32>
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtzs_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzs_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzs_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = fptosi <4 x float> %A to <4 x i32>
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtzs_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzs_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzs_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = fptosi <2 x double> %A to <2 x i64>
ret <2 x i64> %tmp3
}
; FIXME: Generate "fcvtzs d0, d0"?
define <1 x i64> @fcvtzs_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzs_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs x8, d0
-;CHECK-NEXT: mov d0, x8
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzs_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs x8, d0
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%tmp3 = fptosi <1 x double> %A to <1 x i64>
ret <1 x i64> %tmp3
}
define <2 x i32> @fcvtzs_2s_intrinsic(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzs_2s_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzs_2s_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtzs_4s_intrinsic(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzs_4s_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzs_4s_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtzs_2d_intrinsic(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzs_2d_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzs_2d_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtzs_1d_intrinsic(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzs_1d_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs{{.*}}, d0
-;CHECK: ret
+; CHECK-SD-LABEL: fcvtzs_1d_intrinsic:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcvtzs d0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fcvtzs_1d_intrinsic:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtzs x8, d0
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -414,75 +425,81 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x i32> @fcvtzu_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzu_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzu_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = fptoui <2 x float> %A to <2 x i32>
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtzu_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzu_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzu_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = fptoui <4 x float> %A to <4 x i32>
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtzu_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzu_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzu_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = fptoui <2 x double> %A to <2 x i64>
ret <2 x i64> %tmp3
}
; FIXME: Generate "fcvtzu d0, d0"?
define <1 x i64> @fcvtzu_1d(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzu_1d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu x8, d0
-;CHECK-NEXT: mov d0, x8
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzu_1d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu x8, d0
+; CHECK-NEXT: fmov d0, x8
+; CHECK-NEXT: ret
%tmp3 = fptoui <1 x double> %A to <1 x i64>
ret <1 x i64> %tmp3
}
define <2 x i32> @fcvtzu_2s_intrinsic(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzu_2s_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzu_2s_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float> %A)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtzu_4s_intrinsic(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzu_4s_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzu_4s_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float> %A)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtzu_2d_intrinsic(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzu_2d_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzu_2d_intrinsic:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double> %A)
ret <2 x i64> %tmp3
}
define <1 x i64> @fcvtzu_1d_intrinsic(<1 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzu_1d_intrinsic:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu{{.*}}, d0
-;CHECK: ret
+; CHECK-SD-LABEL: fcvtzu_1d_intrinsic:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcvtzu d0, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fcvtzu_1d_intrinsic:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtzu x8, d0
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
%tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> %A)
ret <1 x i64> %tmp3
}
@@ -493,28 +510,28 @@ declare <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double>) nounwind r
declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double>) nounwind readnone
define <2 x float> @frinta_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frinta_2s:
-;CHECK-NOT: ld1
-;CHECK: frinta.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frinta_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frinta.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.round.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
}
define <4 x float> @frinta_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frinta_4s:
-;CHECK-NOT: ld1
-;CHECK: frinta.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frinta_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frinta.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.round.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
}
define <2 x double> @frinta_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frinta_2d:
-;CHECK-NOT: ld1
-;CHECK: frinta.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frinta_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frinta.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.round.v2f64(<2 x double> %A)
ret <2 x double> %tmp3
}
@@ -524,28 +541,28 @@ declare <4 x float> @llvm.round.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.round.v2f64(<2 x double>) nounwind readnone
define <2 x float> @frinti_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frinti_2s:
-;CHECK-NOT: ld1
-;CHECK: frinti.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frinti_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frinti.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
}
define <4 x float> @frinti_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frinti_4s:
-;CHECK-NOT: ld1
-;CHECK: frinti.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frinti_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frinti.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
}
define <2 x double> @frinti_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frinti_2d:
-;CHECK-NOT: ld1
-;CHECK: frinti.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frinti_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frinti.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %A)
ret <2 x double> %tmp3
}
@@ -555,28 +572,28 @@ declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) nounwind readnone
define <2 x float> @frintm_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintm_2s:
-;CHECK-NOT: ld1
-;CHECK: frintm.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintm_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintm.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
}
define <4 x float> @frintm_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintm_4s:
-;CHECK-NOT: ld1
-;CHECK: frintm.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintm_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintm.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
}
define <2 x double> @frintm_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintm_2d:
-;CHECK-NOT: ld1
-;CHECK: frintm.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintm_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintm.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.floor.v2f64(<2 x double> %A)
ret <2 x double> %tmp3
}
@@ -586,28 +603,28 @@ declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone
define <2 x float> @frintn_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintn_2s:
-;CHECK-NOT: ld1
-;CHECK: frintn.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintn_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintn.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
}
define <4 x float> @frintn_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintn_4s:
-;CHECK-NOT: ld1
-;CHECK: frintn.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintn_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintn.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
}
define <2 x double> @frintn_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintn_2d:
-;CHECK-NOT: ld1
-;CHECK: frintn.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintn_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintn.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %A)
ret <2 x double> %tmp3
}
@@ -616,32 +633,29 @@ declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) nounwind readnone
declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) nounwind readnone
-; FALLBACK-NOT: remark{{.*}}frintp_2s
define <2 x float> @frintp_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintp_2s:
-;CHECK-NOT: ld1
-;CHECK: frintp.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintp_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintp.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.ceil.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
}
-; FALLBACK-NOT: remark{{.*}}frintp_4s
define <4 x float> @frintp_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintp_4s:
-;CHECK-NOT: ld1
-;CHECK: frintp.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintp_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintp.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
}
-; FALLBACK-NOT: remark{{.*}}frintp_2d
define <2 x double> @frintp_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintp_2d:
-;CHECK-NOT: ld1
-;CHECK: frintp.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintp_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintp.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %A)
ret <2 x double> %tmp3
}
@@ -651,28 +665,28 @@ declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
define <2 x float> @frintx_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintx_2s:
-;CHECK-NOT: ld1
-;CHECK: frintx.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintx_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintx.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.rint.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
}
define <4 x float> @frintx_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintx_4s:
-;CHECK-NOT: ld1
-;CHECK: frintx.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintx_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintx.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.rint.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
}
define <2 x double> @frintx_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintx_2d:
-;CHECK-NOT: ld1
-;CHECK: frintx.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintx_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintx.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.rint.v2f64(<2 x double> %A)
ret <2 x double> %tmp3
}
@@ -682,28 +696,28 @@ declare <4 x float> @llvm.rint.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.rint.v2f64(<2 x double>) nounwind readnone
define <2 x float> @frintz_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: frintz_2s:
-;CHECK-NOT: ld1
-;CHECK: frintz.2s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintz_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintz.2s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %A)
ret <2 x float> %tmp3
}
define <4 x float> @frintz_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: frintz_4s:
-;CHECK-NOT: ld1
-;CHECK: frintz.4s v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintz_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintz.4s v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %A)
ret <4 x float> %tmp3
}
define <2 x double> @frintz_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: frintz_2d:
-;CHECK-NOT: ld1
-;CHECK: frintz.2d v0, v0
-;CHECK-NEXT: ret
+; CHECK-LABEL: frintz_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: frintz.2d v0, v0
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %A)
ret <2 x double> %tmp3
}
@@ -713,19 +727,20 @@ declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone
declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone
define <2 x float> @fcvtxn_2s(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtxn_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtxn v0.2s, v0.2d
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtxn_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtxn v0.2s, v0.2d
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
ret <2 x float> %tmp3
}
define <4 x float> @fcvtxn_4s(<2 x float> %ret, <2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtxn_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtxn2 v0.4s, v1.2d
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtxn_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: fcvtxn2 v0.4s, v1.2d
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
%res = shufflevector <2 x float> %ret, <2 x float> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %res
@@ -734,28 +749,28 @@ define <4 x float> @fcvtxn_4s(<2 x float> %ret, <2 x double> %A) nounwind {
declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
define <2 x i32> @fcvtzsc_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzsc_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzsc_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.2s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %A, i32 1)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtzsc_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzsc_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.4s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzsc_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.4s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %A, i32 1)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtzsc_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzsc_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzs.2d v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzsc_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs.2d v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double> %A, i32 1)
ret <2 x i64> %tmp3
}
@@ -765,28 +780,28 @@ declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) no
declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32) nounwind readnone
define <2 x i32> @fcvtzuc_2s(<2 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzuc_2s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzuc_2s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.2s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %A, i32 1)
ret <2 x i32> %tmp3
}
define <4 x i32> @fcvtzuc_4s(<4 x float> %A) nounwind {
-;CHECK-LABEL: fcvtzuc_4s:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.4s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzuc_4s:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.4s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %A, i32 1)
ret <4 x i32> %tmp3
}
define <2 x i64> @fcvtzuc_2d(<2 x double> %A) nounwind {
-;CHECK-LABEL: fcvtzuc_2d:
-;CHECK-NOT: ld1
-;CHECK: fcvtzu.2d v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: fcvtzuc_2d:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu.2d v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double> %A, i32 1)
ret <2 x i64> %tmp3
}
@@ -796,28 +811,28 @@ declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) no
declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32) nounwind readnone
define <2 x float> @scvtf_2sc(<2 x i32> %A) nounwind {
-;CHECK-LABEL: scvtf_2sc:
-;CHECK-NOT: ld1
-;CHECK: scvtf.2s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: scvtf_2sc:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf.2s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %A, i32 1)
ret <2 x float> %tmp3
}
define <4 x float> @scvtf_4sc(<4 x i32> %A) nounwind {
-;CHECK-LABEL: scvtf_4sc:
-;CHECK-NOT: ld1
-;CHECK: scvtf.4s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: scvtf_4sc:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf.4s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %A, i32 1)
ret <4 x float> %tmp3
}
define <2 x double> @scvtf_2dc(<2 x i64> %A) nounwind {
-;CHECK-LABEL: scvtf_2dc:
-;CHECK-NOT: ld1
-;CHECK: scvtf.2d v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: scvtf_2dc:
+; CHECK: // %bb.0:
+; CHECK-NEXT: scvtf.2d v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %A, i32 1)
ret <2 x double> %tmp3
}
@@ -827,46 +842,77 @@ declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) no
declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
define <2 x float> @ucvtf_2sc(<2 x i32> %A) nounwind {
-;CHECK-LABEL: ucvtf_2sc:
-;CHECK-NOT: ld1
-;CHECK: ucvtf.2s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: ucvtf_2sc:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf.2s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %A, i32 1)
ret <2 x float> %tmp3
}
define <4 x float> @ucvtf_4sc(<4 x i32> %A) nounwind {
-;CHECK-LABEL: ucvtf_4sc:
-;CHECK-NOT: ld1
-;CHECK: ucvtf.4s v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: ucvtf_4sc:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf.4s v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %A, i32 1)
ret <4 x float> %tmp3
}
define <2 x double> @ucvtf_2dc(<2 x i64> %A) nounwind {
-;CHECK-LABEL: ucvtf_2dc:
-;CHECK-NOT: ld1
-;CHECK: ucvtf.2d v0, v0, #1
-;CHECK-NEXT: ret
+; CHECK-LABEL: ucvtf_2dc:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ucvtf.2d v0, v0, #1
+; CHECK-NEXT: ret
%tmp3 = call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %A, i32 1)
ret <2 x double> %tmp3
}
-
-;CHECK-LABEL: autogen_SD28458:
-;CHECK: fcvt
-;CHECK: ret
define void @autogen_SD28458(<8 x double> %val.f64, ptr %addr.f32) {
+; CHECK-SD-LABEL: autogen_SD28458:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: fcvtn v2.2s, v2.2d
+; CHECK-SD-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-SD-NEXT: fcvtn2 v2.4s, v3.2d
+; CHECK-SD-NEXT: fcvtn2 v0.4s, v1.2d
+; CHECK-SD-NEXT: stp q0, q2, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: autogen_SD28458:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fcvtn v0.2s, v0.2d
+; CHECK-GI-NEXT: fcvtn v2.2s, v2.2d
+; CHECK-GI-NEXT: fcvtn2 v0.4s, v1.2d
+; CHECK-GI-NEXT: fcvtn2 v2.4s, v3.2d
+; CHECK-GI-NEXT: stp q0, q2, [x0]
+; CHECK-GI-NEXT: ret
%Tr53 = fptrunc <8 x double> %val.f64 to <8 x float>
store <8 x float> %Tr53, ptr %addr.f32
ret void
}
-;CHECK-LABEL: autogen_SD19225:
-;CHECK: fcvt
-;CHECK: ret
define void @autogen_SD19225(ptr %addr.f64, ptr %addr.f32) {
+; CHECK-SD-LABEL: autogen_SD19225:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldp q1, q0, [x1]
+; CHECK-SD-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: fcvtl2 v3.2d, v1.4s
+; CHECK-SD-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-SD-NEXT: stp q0, q2, [x0, #32]
+; CHECK-SD-NEXT: stp q1, q3, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: autogen_SD19225:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldp q0, q1, [x1]
+; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: fcvtl v3.2d, v1.2s
+; CHECK-GI-NEXT: fcvtl2 v1.2d, v1.4s
+; CHECK-GI-NEXT: stp q2, q0, [x0]
+; CHECK-GI-NEXT: stp q3, q1, [x0, #32]
+; CHECK-GI-NEXT: ret
%A = load <8 x float>, ptr %addr.f32
%Tr53 = fpext <8 x float> %A to <8 x double>
store <8 x double> %Tr53, ptr %addr.f64
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:52:51 +0000