diff options
Diffstat (limited to 'llvm/lib/TargetParser/TargetParser.cpp')
| -rw-r--r-- | llvm/lib/TargetParser/TargetParser.cpp | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/llvm/lib/TargetParser/TargetParser.cpp b/llvm/lib/TargetParser/TargetParser.cpp index 7c54901dae47..49442c30eb44 100644 --- a/llvm/lib/TargetParser/TargetParser.cpp +++ b/llvm/lib/TargetParser/TargetParser.cpp @@ -18,6 +18,53 @@ using namespace llvm; using namespace AMDGPU; +/// Find KV in array using binary search. +static const BasicSubtargetSubTypeKV * +find(StringRef S, ArrayRef<BasicSubtargetSubTypeKV> A) { + // Binary search the array + auto F = llvm::lower_bound(A, S); + // If not found then return NULL + if (F == A.end() || StringRef(F->Key) != S) + return nullptr; + // Return the found array item + return F; +} + +/// For each feature that is (transitively) implied by this feature, set it. +static void setImpliedBits(FeatureBitset &Bits, const FeatureBitset &Implies, + ArrayRef<BasicSubtargetFeatureKV> FeatureTable) { + // OR the Implies bits in outside the loop. This allows the Implies for CPUs + // which might imply features not in FeatureTable to use this. + Bits |= Implies; + for (const auto &FE : FeatureTable) + if (Implies.test(FE.Value)) + setImpliedBits(Bits, FE.Implies.getAsBitset(), FeatureTable); +} + +std::optional<llvm::StringMap<bool>> llvm::getCPUDefaultTargetFeatures( + StringRef CPU, ArrayRef<BasicSubtargetSubTypeKV> ProcDesc, + ArrayRef<BasicSubtargetFeatureKV> ProcFeatures) { + if (CPU.empty()) + return std::nullopt; + + const BasicSubtargetSubTypeKV *CPUEntry = ::find(CPU, ProcDesc); + if (!CPUEntry) + return std::nullopt; + + // Set the features implied by this CPU feature if there is a match. + FeatureBitset Bits; + llvm::StringMap<bool> DefaultFeatures; + setImpliedBits(Bits, CPUEntry->Implies.getAsBitset(), ProcFeatures); + + [[maybe_unused]] unsigned BitSize = Bits.size(); + for (const BasicSubtargetFeatureKV &FE : ProcFeatures) { + assert(FE.Value < BitSize && "Target Feature is out of range"); + if (Bits[FE.Value]) + DefaultFeatures[FE.Key] = true; + } + return DefaultFeatures; +} + namespace { struct GPUInfo { @@ -127,6 +174,7 @@ constexpr GPUInfo AMDGCNGPUs[] = { {{"gfx1153"}, {"gfx1153"}, GK_GFX1153, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1200"}, {"gfx1200"}, GK_GFX1200, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, {{"gfx1201"}, {"gfx1201"}, GK_GFX1201, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_WGP}, + {{"gfx1250"}, {"gfx1250"}, GK_GFX1250, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32}, {{"gfx9-generic"}, {"gfx9-generic"}, GK_GFX9_GENERIC, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_XNACK}, {{"gfx10-1-generic"}, {"gfx10-1-generic"}, GK_GFX10_1_GENERIC, FEATURE_FAST_FMA_F32|FEATURE_FAST_DENORMAL_F32|FEATURE_WAVE32|FEATURE_XNACK|FEATURE_WGP}, @@ -281,6 +329,7 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) { case GK_GFX1153: return {11, 5, 3}; case GK_GFX1200: return {12, 0, 0}; case GK_GFX1201: return {12, 0, 1}; + case GK_GFX1250: return {12, 5, 0}; // Generic targets return the lowest common denominator // within their family. That is, the ISA that is the most @@ -378,6 +427,33 @@ void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple &T, } else if (T.isAMDGCN()) { AMDGPU::GPUKind Kind = parseArchAMDGCN(GPU); switch (Kind) { + case GK_GFX1250: + Features["ci-insts"] = true; + Features["dot7-insts"] = true; + Features["dot8-insts"] = true; + Features["dl-insts"] = true; + Features["16-bit-insts"] = true; + Features["dpp"] = true; + Features["gfx8-insts"] = true; + Features["gfx9-insts"] = true; + Features["gfx10-insts"] = true; + Features["gfx10-3-insts"] = true; + Features["gfx11-insts"] = true; + Features["gfx12-insts"] = true; + Features["gfx1250-insts"] = true; + Features["bitop3-insts"] = true; + Features["prng-inst"] = true; + Features["fp8-conversion-insts"] = true; + Features["permlane16-swap"] = true; + Features["ashr-pk-insts"] = true; + Features["atomic-buffer-pk-add-bf16-inst"] = true; + Features["atomic-fadd-rtn-insts"] = true; + Features["atomic-buffer-global-pk-add-f16-insts"] = true; + Features["atomic-flat-pk-add-16-insts"] = true; + Features["atomic-global-pk-add-bf16-inst"] = true; + Features["atomic-ds-pk-add-16-insts"] = true; + Features["setprio-inc-wg-inst"] = true; + break; case GK_GFX1201: case GK_GFX1200: case GK_GFX12_GENERIC: @@ -631,6 +707,7 @@ static bool isWave32Capable(StringRef GPU, const Triple &T) { // XXX - What does the member GPU mean if device name string passed here? if (T.isAMDGCN()) { switch (parseArchAMDGCN(GPU)) { + case GK_GFX1250: case GK_GFX1201: case GK_GFX1200: case GK_GFX1153: |