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-rw-r--r--llvm/lib/Target/SystemZ/SystemZInstrFormats.td60
1 files changed, 1 insertions, 59 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index d0a549518cc4..82415f412509 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -2646,28 +2646,24 @@ class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
: InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
mnemonic#"\t$R1, $RI2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
: InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
mnemonic#"\t$R1, $RI2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
: InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
@@ -2675,7 +2671,6 @@ class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
(ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
@@ -2683,14 +2678,12 @@ class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
(ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$R1, $XBD2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
: InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
mnemonic#"\t$R1, $R3, $RI2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
@@ -2698,7 +2691,6 @@ class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
(ins cls:$R1src, cls:$R3, brtarget16:$RI2),
mnemonic#"\t$R1, $R3, $RI2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
@@ -2706,7 +2698,6 @@ class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
(ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
@@ -2715,7 +2706,6 @@ class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
(ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
@@ -3116,7 +3106,6 @@ class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
: InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
mnemonic#"\t$R1", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let R2 = 0;
}
@@ -3125,7 +3114,6 @@ class UnaryMemRRFc<string mnemonic, bits<16> opcode,
: InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let M3 = 0;
}
@@ -3163,7 +3151,6 @@ class CondUnaryRSY<string mnemonic, bits<16> opcode,
(z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
cond4:$valid, cond4:$M3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
let CCMaskLast = 1;
@@ -3184,7 +3171,6 @@ class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
let mayLoad = 1;
let AccessBytes = bytes;
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
// Like CondUnaryRSY, but with a fixed CC mask.
@@ -3194,7 +3180,6 @@ class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
: InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2),
mnemonic#V.suffix#"\t$R1, $BD2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
let isAsmParserOnly = V.alternate;
@@ -3439,7 +3424,6 @@ class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
: InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src, $R2 = $R2src";
- let DisableEncoding = "$R1src, $R2src";
}
class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
@@ -3447,7 +3431,6 @@ class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
: InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R2 = $R2src";
- let DisableEncoding = "$R2src";
}
class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
@@ -3455,7 +3438,6 @@ class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
: InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src, $R2 = $R2src";
- let DisableEncoding = "$R1src, $R2src";
}
class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
@@ -3463,7 +3445,6 @@ class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
: InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src, $R2 = $R2src";
- let DisableEncoding = "$R1src, $R2src";
let M3 = 0;
}
@@ -3475,7 +3456,6 @@ class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
let OpKey = mnemonic#cls1;
let OpType = "reg";
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
@@ -3486,7 +3466,6 @@ class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpKey = mnemonic#cls1;
let OpType = "reg";
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
@@ -3565,7 +3544,6 @@ class BinaryMemRRFc<string mnemonic, bits<16> opcode,
: InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
mnemonic#"\t$R1, $R2, $M3", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
@@ -3594,7 +3572,6 @@ class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
[(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
cond4:$valid, cond4:$M3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let CCMaskLast = 1;
let NumOpsKey = !subst("loc", "sel", mnemonic);
let NumOpsValue = "2";
@@ -3610,7 +3587,6 @@ class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
(ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
mnemonic#"\t$R1, $R2, $M3", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
// Like CondBinaryRRF, but with a fixed CC mask.
@@ -3619,7 +3595,6 @@ class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
: InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
mnemonic#V.suffix#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
let M3 = V.ccmask;
@@ -3678,7 +3653,6 @@ class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
mnemonic#"\t$R1, $I2",
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
@@ -3707,7 +3681,6 @@ class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
[(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
cond4:$valid, cond4:$M3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let CCMaskLast = 1;
}
@@ -3719,7 +3692,6 @@ class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
(ins cls:$R1src, imm:$I2, imm32zx4:$M3),
mnemonic#"\t$R1, $I2, $M3", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
// Like CondBinaryRIE, but with a fixed CC mask.
@@ -3728,7 +3700,6 @@ class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
: InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
mnemonic#V.suffix#"\t$R1, $I2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let isAsmParserOnly = V.alternate;
let AsmVariantName = V.asmvariant;
let M3 = V.ccmask;
@@ -3747,7 +3718,6 @@ class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
mnemonic#"\t$R1, $I2",
[(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
@@ -3758,7 +3728,6 @@ class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
[(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
let R3 = 0;
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
@@ -3794,7 +3763,6 @@ class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -3809,7 +3777,6 @@ class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
let M3 = 0;
@@ -3838,7 +3805,6 @@ class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -4500,7 +4466,6 @@ class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode,
(ins cls1:$R1src, cls2:$R2src, cls3:$R3),
mnemonic#"\t$R1, $R2, $R3", []> {
let Constraints = "$R1 = $R1src, $R2 = $R2src";
- let DisableEncoding = "$R1src, $R2src";
let M4 = 0;
}
@@ -4520,7 +4485,6 @@ class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
(ins cls1:$R1src, cls2:$R2src, cls3:$R3src),
mnemonic#"\t$R1, $R3, $R2", []> {
let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
- let DisableEncoding = "$R1src, $R2src, $R3src";
let M4 = 0;
}
@@ -4544,7 +4508,6 @@ class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
(ins cls1:$R1src, cls2:$R2src, imm:$M3),
mnemonic#"\t$R1, $R2, $M3", []> {
let Constraints = "$R1 = $R1src, $R2 = $R2src";
- let DisableEncoding = "$R1src, $R2src";
}
multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
@@ -4574,7 +4537,6 @@ class TernaryRRFb<string mnemonic, bits<16> opcode,
(ins cls1:$R1src, cls2:$R2, imm32zx4:$M4),
mnemonic#"\t$R1, $R3, $R2, $M4", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
@@ -4591,7 +4553,6 @@ class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpKey = mnemonic#cls;
let OpType = "reg";
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
@@ -4601,7 +4562,6 @@ class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
mnemonic#"\t$R1, $M3, $BD2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -4613,7 +4573,6 @@ class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
mnemonic#"\t$R1, $M3, $BD2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -4646,7 +4605,6 @@ class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
(ins cls1:$R1src, cls2:$R3src, (shift12only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src, $R3 = $R3src";
- let DisableEncoding = "$R1src, $R3src";
}
class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
@@ -4655,7 +4613,6 @@ class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
(ins cls1:$R1src, cls2:$R3src, (shift20only $B2, $D2):$BD2),
mnemonic#"\t$R1, $R3, $BD2", []> {
let Constraints = "$R1 = $R1src, $R3 = $R3src";
- let DisableEncoding = "$R1src, $R3src";
}
class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
@@ -4669,7 +4626,6 @@ class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -4681,7 +4637,6 @@ class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
[(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
imm:$I2, index:$M3))]> {
let Constraints = "$V1 = $V1src";
- let DisableEncoding = "$V1src";
}
class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
@@ -4893,7 +4848,6 @@ class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
cls:$R3,
shift12only:$BD2))]> {
let Constraints = "$V1 = $V1src";
- let DisableEncoding = "$V1src";
let M4 = type;
}
@@ -4913,7 +4867,6 @@ class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
imm32zx4:$M4),
mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
let Constraints = "$V1 = $V1src";
- let DisableEncoding = "$V1src";
}
class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
@@ -4922,7 +4875,6 @@ class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
(ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
mnemonic#"\t$V1, $VBD2, $M3", []> {
let Constraints = "$V1 = $V1src";
- let DisableEncoding = "$V1src";
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -4936,7 +4888,6 @@ class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
bdxaddr12only:$XBD2,
index:$M3))]> {
let Constraints = "$V1 = $V1src";
- let DisableEncoding = "$V1src";
let mayLoad = 1;
let AccessBytes = bytes;
}
@@ -4951,7 +4902,6 @@ class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operato
(tr2.vt tr2.op:$V3),
imm32zx8_timm:$I4))]> {
let Constraints = "$V1 = $V1src";
- let DisableEncoding = "$V1src";
let M5 = type;
}
@@ -4961,7 +4911,6 @@ class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
imm32zx8:$I4, imm32zx4:$M5),
mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
let Constraints = "$V1 = $V1src";
- let DisableEncoding = "$V1src";
}
class QuaternaryVRIf<string mnemonic, bits<16> opcode>
@@ -5087,7 +5036,6 @@ class CmpSwapRRE<string mnemonic, bits<16> opcode,
: InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
mnemonic#"\t$R1, $R2", []> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let mayStore = 1;
}
@@ -5099,7 +5047,6 @@ class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let mayStore = 1;
}
@@ -5111,7 +5058,6 @@ class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
mnemonic#"\t$R1, $R3, $BD2",
[(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let mayStore = 1;
}
@@ -5128,7 +5074,7 @@ multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
multiclass RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0> {
- let Constraints = "$R1 = $R1src", DisableEncoding = "$R1src" in {
+ let Constraints = "$R1 = $R1src" in {
def "" : InstRIEf<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
imm32zx8:$I5),
@@ -5328,7 +5274,6 @@ class CondBinaryRRFPseudo<string mnemonic, RegisterOperand cls1,
[(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
cond4:$valid, cond4:$M3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let CCMaskLast = 1;
let NumOpsKey = !subst("loc", "sel", mnemonic);
let NumOpsValue = "2";
@@ -5359,7 +5304,6 @@ class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm>
[(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
cond4:$valid, cond4:$M3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let CCMaskLast = 1;
}
@@ -5374,7 +5318,6 @@ class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator,
(z_select_ccmask (operator mode:$BD2), cls:$R1src,
cond4:$valid, cond4:$R3))]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
let mayLoad = 1;
let AccessBytes = bytes;
let CCMaskLast = 1;
@@ -5414,7 +5357,6 @@ class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
imm32zx8:$I5),
[]> {
let Constraints = "$R1 = $R1src";
- let DisableEncoding = "$R1src";
}
// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:52:45 +0000