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Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td98
1 files changed, 43 insertions, 55 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index c2f91ce8e6b9..c12cf8511312 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -58,6 +58,10 @@ def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3>
]>;
+def SDT_PPCVecShiftQuad : SDTypeProfile<1, 2, [
+ SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>
+]>;
+
def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
]>;
@@ -157,6 +161,8 @@ def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
+def PPCvsrq: SDNode<"PPCISD::VSRQ", SDT_PPCVecShiftQuad, []>;
+
def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID",
SDTFPUnaryOp, [SDNPHasChain]>;
def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU",
@@ -665,9 +671,6 @@ class isRecordForm { bit RC = 1; }
class RegConstraint<string C> {
string Constraints = C;
}
-class NoEncode<string E> {
- string DisableEncoding = E;
-}
// Define PowerPC specific addressing mode.
@@ -1989,29 +1992,24 @@ def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D,
def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lhau $RST, $addr", IIC_LdStLHAU,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lhzu $RST, $addr", IIC_LdStLoadUpd,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lwzu $RST, $addr", IIC_LdStLoadUpd,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
let Predicates = [HasFPU] in {
def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lfsu $RST, $addr", IIC_LdStLFDU,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lfdu $RST, $addr", IIC_LdStLFDU,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
}
@@ -2019,39 +2017,33 @@ def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D,
def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lbzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lhaux $RST, $addr", IIC_LdStLHAUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lhzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lwzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
let Predicates = [HasFPU] in {
def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lfsux $RST, $addr", IIC_LdStLFDUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lfdux $RST, $addr", IIC_LdStLFDUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
}
}
}
@@ -2132,20 +2124,20 @@ def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst),
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
"stbu $RST, $dst", IIC_LdStSTU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
"sthu $RST, $dst", IIC_LdStSTU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
"stwu $RST, $dst", IIC_LdStSTU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
let Predicates = [HasFPU] in {
def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst),
"stfsu $RST, $dst", IIC_LdStSTFDU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst),
"stfdu $RST, $dst", IIC_LdStSTFDU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
}
}
@@ -2207,32 +2199,27 @@ def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$RST, (memrr $RA, $RB):$addr),
"stbux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$RST, (memrr $RA, $RB):$addr),
"sthux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$RST, (memrr $RA, $RB):$addr),
"stwux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
let Predicates = [HasFPU] in {
def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res),
(ins f4rc:$RST, (memrr $RA, $RB):$addr),
"stfsux $RST, $addr", IIC_LdStSTFDU, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res),
(ins f8rc:$RST, (memrr $RA, $RB):$addr),
"stfdux $RST, $addr", IIC_LdStSTFDU, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
}
}
@@ -3099,7 +3086,7 @@ defm RLWIMI : MForm_2r<20, (outs gprc:$RA),
(ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB,
u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",
IIC_IntRotate, []>, PPC970_DGroup_Cracked,
- RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">;
+ RegConstraint<"$RAi = $RA">;
}
let BaseName = "rlwinm" in {
def RLWINM : MForm_2<21,
@@ -3235,9 +3222,10 @@ def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
// This uses two output registers, the first as the real output, the second as a
-// temporary register, used internally in code generation.
+// temporary register, used internally in code generation. A "bl" also clobbers LR.
+let Defs = [LR] in
def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
- []>, NoEncode<"$rT">;
+ []>;
def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
"#LDgotTprelL32",
@@ -4287,7 +4275,7 @@ def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
bits<1> E;
let Inst{16} = E;
- let Inst{21-30} = 163;
+ let Inst{21...30} = 163;
}
def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB),
@@ -4967,44 +4955,44 @@ defm : BranchSimpleMnemonic1<"dzf", "", 2>;
multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
def : InstAlias<"b"#name#pm#" $cc, $dst",
- (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
+ (BCC (pred bibo, crrc:$cc), condbrtarget:$dst)>;
def : InstAlias<"b"#name#pm#" $dst",
- (BCC bibo, CR0, condbrtarget:$dst)>;
+ (BCC (pred bibo, CR0), condbrtarget:$dst)>;
def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
- (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
+ (BCCA (pred bibo, crrc:$cc), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"a"#pm#" $dst",
- (BCCA bibo, CR0, abscondbrtarget:$dst)>;
+ (BCCA (pred bibo, CR0), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lr"#pm#" $cc",
- (BCCLR bibo, crrc:$cc)>;
+ (BCCLR (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"lr"#pm,
- (BCCLR bibo, CR0)>;
+ (BCCLR (pred bibo, CR0))>;
def : InstAlias<"b"#name#"ctr"#pm#" $cc",
- (BCCCTR bibo, crrc:$cc)>;
+ (BCCCTR (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"ctr"#pm,
- (BCCCTR bibo, CR0)>;
+ (BCCCTR (pred bibo, CR0))>;
def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
- (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
+ (BCCL (pred bibo, crrc:$cc), condbrtarget:$dst)>;
def : InstAlias<"b"#name#"l"#pm#" $dst",
- (BCCL bibo, CR0, condbrtarget:$dst)>;
+ (BCCL (pred bibo, CR0), condbrtarget:$dst)>;
def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
- (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
+ (BCCLA (pred bibo, crrc:$cc), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"la"#pm#" $dst",
- (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
+ (BCCLA (pred bibo, CR0), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lrl"#pm#" $cc",
- (BCCLRL bibo, crrc:$cc)>;
+ (BCCLRL (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"lrl"#pm,
- (BCCLRL bibo, CR0)>;
+ (BCCLRL (pred bibo, CR0))>;
def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
- (BCCCTRL bibo, crrc:$cc)>;
+ (BCCCTRL (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"ctrl"#pm,
- (BCCCTRL bibo, CR0)>;
+ (BCCCTRL (pred bibo, CR0))>;
}
multiclass BranchExtendedMnemonic<string name, int bibo> {
defm : BranchExtendedMnemonicPM<name, "", bibo>;
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-31 14:52:17 +0000