1 files changed, 17 insertions, 4 deletions
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 77b8cbe5793c..4a1977ba1a00 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -19,6 +19,7 @@
 ///
 //===----------------------------------------------------------------------===//
 
+#include "AArch64ExpandImm.h"
 #include "AArch64GlobalISelUtils.h"
 #include "AArch64PerfectShuffle.h"
 #include "AArch64Subtarget.h"
@@ -563,7 +564,8 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
   auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS, MRI);
   if (!ValAndVReg)
     return std::nullopt;
-  uint64_t C = ValAndVReg->Value.getZExtValue();
+  uint64_t OriginalC = ValAndVReg->Value.getZExtValue();
+  uint64_t C = OriginalC;
   if (isLegalArithImmed(C))
     return std::nullopt;
 
@@ -633,9 +635,20 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
   // predicate if it is.
   if (Size == 32)
     C = static_cast<uint32_t>(C);
-  if (!isLegalArithImmed(C))
-    return std::nullopt;
-  return {{C, P}};
+  if (isLegalArithImmed(C))
+    return {{C, P}};
+
+  auto IsMaterializableInSingleInstruction = [=](uint64_t Imm) {
+    SmallVector<AArch64_IMM::ImmInsnModel> Insn;
+    AArch64_IMM::expandMOVImm(Imm, 32, Insn);
+    return Insn.size() == 1;
+  };
+
+  if (!IsMaterializableInSingleInstruction(OriginalC) &&
+      IsMaterializableInSingleInstruction(C))
+    return {{C, P}};
+
+  return std::nullopt;
 }
 
 /// Determine whether or not it is possible to update the RHS and predicate of