summaryrefslogtreecommitdiff
path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp22
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index aa7f88553951..7aa293af963e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3480,6 +3480,17 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
}
break;
+ case ISD::VECTOR_COMPRESS: {
+ SDValue Vec = Op.getOperand(0);
+ SDValue PassThru = Op.getOperand(2);
+ Known = computeKnownBits(PassThru, DemandedElts, Depth + 1);
+ // If we don't know any bits, early out.
+ if (Known.isUnknown())
+ break;
+ Known2 = computeKnownBits(Vec, Depth + 1);
+ Known = Known.intersectWith(Known2);
+ break;
+ }
case ISD::VECTOR_SHUFFLE: {
assert(!Op.getValueType().isScalableVector());
// Collect the known bits that are shared by every vector element referenced
@@ -4789,6 +4800,17 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
}
return Tmp;
+ case ISD::VECTOR_COMPRESS: {
+ SDValue Vec = Op.getOperand(0);
+ SDValue PassThru = Op.getOperand(2);
+ Tmp = ComputeNumSignBits(PassThru, DemandedElts, Depth + 1);
+ if (Tmp == 1)
+ return 1;
+ Tmp2 = ComputeNumSignBits(Vec, Depth + 1);
+ Tmp = std::min(Tmp, Tmp2);
+ return Tmp;
+ }
+
case ISD::VECTOR_SHUFFLE: {
// Collect the minimum number of sign bits that are shared by every vector
// element referenced by the shuffle.