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| author | Peter Collingbourne <peter@pcc.me.uk> | 2025-07-18 13:26:00 -0700 |
|---|---|---|
| committer | Peter Collingbourne <peter@pcc.me.uk> | 2025-07-18 13:26:00 -0700 |
| commit | 9bf3524731070cadc6175707314f3b6ca37190d5 (patch) | |
| tree | 86dcab7604336b01ae938fe81062c29ff69efba8 /mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp | |
| parent | 3a84c15cc13b6daf8e812592898ab6c7f19091a9 (diff) | |
| parent | 4f43f0606c3d7e1ce6d069583b5e59f036e112ce (diff) | |
Created using spr 1.3.6-beta.1
Diffstat (limited to 'mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp')
| -rw-r--r-- | mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp b/mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp index 03c5c2239ed7..0df91a243d07 100644 --- a/mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp +++ b/mlir/lib/Conversion/SCFToControlFlow/SCFToControlFlow.cpp @@ -630,14 +630,16 @@ DoWhileLowering::matchAndRewrite(WhileOp whileOp, // Loop around the "before" region based on condition. rewriter.setInsertionPointToEnd(before); auto condOp = cast<ConditionOp>(before->getTerminator()); - rewriter.replaceOpWithNewOp<cf::CondBranchOp>(condOp, condOp.getCondition(), - before, condOp.getArgs(), - continuation, ValueRange()); + rewriter.create<cf::CondBranchOp>(condOp.getLoc(), condOp.getCondition(), + before, condOp.getArgs(), continuation, + ValueRange()); // Replace the op with values "yielded" from the "before" region, which are // visible by dominance. rewriter.replaceOp(whileOp, condOp.getArgs()); + // Erase the condition op. + rewriter.eraseOp(condOp); return success(); } |
