diff options
| author | Mingming Liu <mingmingl@google.com> | 2025-09-10 15:25:31 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-10 15:25:31 -0700 |
| commit | 1417dafa1db9cb1b2b09438aa9f53ea5ab6e36e2 (patch) | |
| tree | 57f4b1f313c8cf74eed8819870f39c36ea263c68 /llvm/test/TableGen | |
| parent | 898b813bc8a6d0276bf0f4769f5f2f64b34e632d (diff) | |
| parent | b8cefcb601ddaa18482555c4ff363c01a270c2fe (diff) | |
Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format
Diffstat (limited to 'llvm/test/TableGen')
29 files changed, 680 insertions, 312 deletions
diff --git a/llvm/test/TableGen/AsmPredicateCombining.td b/llvm/test/TableGen/AsmPredicateCombining.td index f7c0ae7c7111..c8081a428d7b 100644 --- a/llvm/test/TableGen/AsmPredicateCombining.td +++ b/llvm/test/TableGen/AsmPredicateCombining.td @@ -1,4 +1,4 @@ -// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \ +// RUN: llvm-tblgen -gen-disassembler -ignore-non-decodable-operands -I %p/../../include %s | \ // RUN: FileCheck --check-prefix=DISASS %s // RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \ // RUN: FileCheck --check-prefix=MATCHER %s diff --git a/llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td b/llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td new file mode 100644 index 000000000000..c656616a6245 --- /dev/null +++ b/llvm/test/TableGen/DecoderEmitterBitwidthSpecialization.td @@ -0,0 +1,189 @@ +// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s --check-prefix=CHECK-DEFAULT +// RUN: llvm-tblgen -gen-disassembler -specialize-decoders-per-bitwidth -I %p/../../include %s | FileCheck %s --check-prefix=CHECK-SPECIALIZE-NO-TABLE +// RUN: llvm-tblgen -gen-disassembler -specialize-decoders-per-bitwidth -use-fn-table-in-decode-to-mcinst -I %p/../../include %s | FileCheck %s --check-prefix=CHECK-SPECIALIZE-TABLE + + +include "llvm/Target/Target.td" + +def archInstrInfo : InstrInfo { } + +def arch : Target { + let InstructionSet = archInstrInfo; +} + +let Namespace = "arch" in { + def R0 : Register<"r0">; + def R1 : Register<"r1">; + def R2 : Register<"r2">; + def R3 : Register<"r3">; +} +def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3)>; + +// Bit 0 of the encoding determines the size (8 or 16 bits). +// Bits {3..1} define the number of operands encoded. +class Instruction8Bit<int NumOps> : Instruction { + let Size = 1; + let OutOperandList = (outs); + field bits<8> Inst; + let Inst{0} = 0; + let Inst{3-1} = NumOps; +} + +class Instruction16Bit<int NumOps> : Instruction { + let Size = 2; + let OutOperandList = (outs); + field bits<16> Inst; + let Inst{0} = 1; + let Inst{3-1} = NumOps; +} + +// Define instructions to generate 4 cases in decodeToMCInst. +// Each register operand needs 2 bits to encode. + +// An instruction with no inputs. +def Inst0 : Instruction8Bit<0> { + let Inst{7-4} = 0; + let InOperandList = (ins); + let AsmString = "Inst0"; +} + +// An instruction with a single input. +def Inst1 : Instruction8Bit<1> { + bits<2> r0; + let Inst{5-4} = r0; + let Inst{7-6} = 0; + let InOperandList = (ins Regs:$r0); + let AsmString = "Inst1"; +} + +// An instruction with two inputs. +def Inst2 : Instruction16Bit<2> { + bits<2> r0; + bits<2> r1; + let Inst{5-4} = r0; + let Inst{7-6} = r1; + let Inst{15-8} = 0; + let InOperandList = (ins Regs:$r0, Regs:$r1); + let AsmString = "Inst2"; +} + +// An instruction with three inputs. . +def Inst3 : Instruction16Bit<3> { + bits<2> r0; + bits<2> r1; + bits<2> r2; + let Inst{5-4} = r0; + let Inst{7-6} = r1; + let Inst{9-8} = r2; + let Inst{15-10} = 0; + let InOperandList = (ins Regs:$r0, Regs:$r1, Regs:$r2); + let AsmString = "Inst3"; +} + +// ----------------------------------------------------------------------------- +// In the default case, we emit a single decodeToMCinst function and DecodeIdx +// is shared across all bitwidths. + +// CHECK-DEFAULT-LABEL: DecoderTable8[25] +// CHECK-DEFAULT: DecodeIdx: 0 +// CHECK-DEFAULT: DecodeIdx: 1 +// CHECK-DEFAULT: }; + +// CHECK-DEFAULT-LABEL: DecoderTable16[25] +// CHECK-DEFAULT: DecodeIdx: 2 +// CHECK-DEFAULT: DecodeIdx: 3 +// CHECK-DEFAULT: }; + +// CHECK-DEFAULT-LABEL: template <typename InsnType> +// CHECK-DEFAULT-NEXT: static DecodeStatus decodeToMCInst +// CHECK-DEFAULT: case 0 +// CHECK-DEFAULT: case 1 +// CHECK-DEFAULT: case 2 +// CHECK-DEFAULT: case 3 + +// ----------------------------------------------------------------------------- +// When we specialize per bitwidth, we emit 2 decodeToMCInst functions and +// DecodeIdx is assigned per bit width. + +// CHECK-SPECIALIZE-NO-TABLE-LABEL: DecoderTable8[26] +// CHECK-SPECIALIZE-NO-TABLE: /* 0 */ 8, // Bitwidth 8 +// CHECK-SPECIALIZE-NO-TABLE: DecodeIdx: 0 +// CHECK-SPECIALIZE-NO-TABLE: DecodeIdx: 1 +// CHECK-SPECIALIZE-NO-TABLE: }; + +// CHECK-SPECIALIZE-NO-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-NO-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 8, DecodeStatus> +// CHECK-SPECIALIZE-NO-TABLE-NEXT: decodeToMCInst +// CHECK-SPECIALIZE-NO-TABLE: case 0 +// CHECK-SPECIALIZE-NO-TABLE: case 1 + +// CHECK-SPECIALIZE-NO-TABLE-LABEL: DecoderTable16[26] +// CHECK-SPECIALIZE-NO-TABLE: /* 0 */ 16, // Bitwidth 16 +// CHECK-SPECIALIZE-NO-TABLE: DecodeIdx: 0 +// CHECK-SPECIALIZE-NO-TABLE: DecodeIdx: 1 +// CHECK-SPECIALIZE-NO-TABLE: }; + +// CHECK-SPECIALIZE-NO-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-NO-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 16, DecodeStatus> +// CHECK-SPECIALIZE-NO-TABLE-NEXT: decodeToMCInst +// CHECK-SPECIALIZE-NO-TABLE: case 0 +// CHECK-SPECIALIZE-NO-TABLE: case 1 + +// CHECK-SPECIALIZE-NO-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-NO-TABLE-NEXT: decodeInstruction +// CHECK-SPECIALIZE-NO-TABLE: uint32_t BitWidth = decodeULEB128AndIncUnsafe(Ptr); +// CHECK-SPECIALIZE-NO-TABLE-NEXT: assert(InsnBitWidth<InsnType> == BitWidth && + +// ----------------------------------------------------------------------------- +// Per bitwidth specialization with function table. + +// 8 bit deccoder table, functions, and function table. +// CHECK-SPECIALIZE-TABLE-LABEL: DecoderTable8[26] +// CHECK-SPECIALIZE-TABLE: /* 0 */ 8, // Bitwidth 8 +// CHECK-SPECIALIZE-TABLE: DecodeIdx: 0 +// CHECK-SPECIALIZE-TABLE: DecodeIdx: 1 +// CHECK-SPECIALIZE-TABLE: }; + +// CHECK-SPECIALIZE-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 8, DecodeStatus> +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_8bit_0 + +// CHECK-SPECIALIZE-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 8, DecodeStatus> +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_8bit_1 + +// CHECK-SPECIALIZE-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 8, DecodeStatus> +// CHECK-SPECIALIZE-TABLE-NEXT: decodeToMCInst +// CHECK-SPECIALIZE-TABLE-LABEL: static constexpr DecodeFnTy decodeFnTable[] = { +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_8bit_0, +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_8bit_1, +// CHECK-SPECIALIZE-TABLE-NEXT: }; + +// 16 bit deccoder table, functions, and function table. +// CHECK-SPECIALIZE-TABLE-LABEL: DecoderTable16[26] +// CHECK-SPECIALIZE-TABLE: /* 0 */ 16, // Bitwidth 16 +// CHECK-SPECIALIZE-TABLE: DecodeIdx: 0 +// CHECK-SPECIALIZE-TABLE: DecodeIdx: 1 +// CHECK-SPECIALIZE-TABLE: }; + +// CHECK-SPECIALIZE-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 16, DecodeStatus> +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_16bit_0 + +// CHECK-SPECIALIZE-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 16, DecodeStatus> +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_16bit_1 + +// CHECK-SPECIALIZE-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-TABLE-NEXT: static std::enable_if_t<InsnBitWidth<InsnType> == 16, DecodeStatus> +// CHECK-SPECIALIZE-TABLE-NEXT: decodeToMCInst +// CHECK-SPECIALIZE-TABLE-LABEL: static constexpr DecodeFnTy decodeFnTable[] = { +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_16bit_0, +// CHECK-SPECIALIZE-TABLE-NEXT: decodeFn_16bit_1, +// CHECK-SPECIALIZE-TABLE-NEXT: }; + +// CHECK-SPECIALIZE-TABLE-LABEL: template <typename InsnType> +// CHECK-SPECIALIZE-TABLE-NEXT: decodeInstruction +// CHECK-SPECIALIZE-TABLE: uint32_t BitWidth = decodeULEB128AndIncUnsafe(Ptr); +// CHECK-SPECIALIZE-TABLE-NEXT: assert(InsnBitWidth<InsnType> == BitWidth && diff --git a/llvm/test/TableGen/DecoderEmitterFnTable.td b/llvm/test/TableGen/DecoderEmitterFnTable.td index 7bed18c19a51..8929e6da716e 100644 --- a/llvm/test/TableGen/DecoderEmitterFnTable.td +++ b/llvm/test/TableGen/DecoderEmitterFnTable.td @@ -71,14 +71,14 @@ def Inst3 : TestInstruction { let AsmString = "Inst3"; } -// CHECK-LABEL: DecodeStatus decodeFn0(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) -// CHECK-LABEL: DecodeStatus decodeFn1(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) -// CHECK-LABEL: DecodeStatus decodeFn2(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) -// CHECK-LABEL: DecodeStatus decodeFn3(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) +// CHECK-LABEL: DecodeStatus decodeFn_0(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) +// CHECK-LABEL: DecodeStatus decodeFn_1(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) +// CHECK-LABEL: DecodeStatus decodeFn_2(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) +// CHECK-LABEL: DecodeStatus decodeFn_3(DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) // CHECK-LABEL: decodeToMCInst(unsigned Idx, DecodeStatus S, InsnType insn, MCInst &MI, uint64_t Address, const MCDisassembler *Decoder, bool &DecodeComplete) // CHECK: static constexpr DecodeFnTy decodeFnTable[] -// CHECK-NEXT: decodeFn0, -// CHECK-NEXT: decodeFn1, -// CHECK-NEXT: decodeFn2, -// CHECK-NEXT: decodeFn3, +// CHECK-NEXT: decodeFn_0, +// CHECK-NEXT: decodeFn_1, +// CHECK-NEXT: decodeFn_2, +// CHECK-NEXT: decodeFn_3, // CHECK: return decodeFnTable[Idx](S, insn, MI, Address, Decoder, DecodeComplete) diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td b/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td index d7263b69dd8f..ef15b6b9a900 100644 --- a/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td +++ b/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td @@ -12,39 +12,56 @@ def Reg : Register<"reg">; def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>; -def complex_nodec : Operand<i32> { +def complex_nodec1 : Operand<i32> { + let MIOperandInfo = (ops Regs); +} + +def complex_nodec2 : Operand<i32> { let MIOperandInfo = (ops Regs, Regs); } -def complex_withdec : Operand<i32> { +def complex_withdec1 : Operand<i32> { + let MIOperandInfo = (ops Regs); + let DecoderMethod = "DecodeComplex"; +} + +def complex_withdec2 : Operand<i32> { let MIOperandInfo = (ops Regs, Regs); let DecoderMethod = "DecodeComplex"; } class ArchInstr : Instruction { - let Size = 1; - bits<8> Inst; + let Size = 2; + bits<16> Inst; } // This definition is broken in both directions: // 1. Uses a complex operand without a decoder, and without named sub-ops. // 2. Uses a complex operand with named sub-ops, but with a decoder as well. -// CHECK: error: DecoderEmitter: operand "r1c" uses MIOperandInfo with multiple ops, but doesn't have a custom decoder! +// CHECK: error: DecoderEmitter: operand "r1c" has non-empty MIOperandInfo, but doesn't have a custom decoder! // CHECK: note: Dumping record for previous error: -// CHECK: error: DecoderEmitter: operand "r1ab" has type "complex_withdec" with a custom DecoderMethod, but also named sub-operands. +// CHECK: error: DecoderEmitter: operand "r2b" has non-empty MIOperandInfo, but doesn't have a custom decoder! +// CHECK: note: Dumping record for previous error: +// CHECK: error: DecoderEmitter: operand "r1" has type "complex_withdec2" with a custom DecoderMethod, but also named sub-operands. +// CHECK: error: DecoderEmitter: operand "r2" has type "complex_withdec1" with a custom DecoderMethod, but also named sub-operands. def foo1 : ArchInstr { bits<2> r1a; bits<2> r1b; bits<2> r1c; + bits<2> r2a; + bits<2> r2b; let Inst{1-0} = r1a; let Inst{3-2} = r1b; let Inst{5-4} = r1c; - let Inst{7-6} = 0b00; + let Inst{7-6} = r2a; + let Inst{9-8} = r2b; + let Inst{11-10} = 0b00; - let OutOperandList = (outs complex_nodec:$r1c); - let InOperandList = (ins (complex_withdec $r1a, $r1b):$r1ab); + let OutOperandList = (outs complex_nodec2:$r1c, complex_nodec1:$r2b); + let InOperandList = (ins (complex_withdec2 $r1a, $r1b):$r1, + (complex_withdec1 $r2a):$r2); } // This definition has no errors. @@ -52,12 +69,17 @@ def foo2 : ArchInstr { bits<2> r2a; bits<2> r2b; bits<2> r2c; + bits<2> r1a; + bits<2> r1b; let Inst{1-0} = r2a; let Inst{3-2} = r2b; let Inst{5-4} = r2c; - let Inst{7-6} = 0b01; + let Inst{7-6} = r1a; + let Inst{9-8} = r1b; + let Inst{11-10} = 0b01; - let OutOperandList = (outs complex_withdec:$r2c); - let InOperandList = (ins (complex_nodec $r2a, $r2b):$r2ab); + let OutOperandList = (outs complex_withdec2:$r2c, complex_withdec1:$r1b); + let InOperandList = (ins (complex_nodec2 $r2a, $r2b):$r2, + (complex_nodec1 $r1a):$r1); } diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td b/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td index 192cb3c3f585..ec7e35e1ecac 100644 --- a/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td +++ b/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td @@ -30,24 +30,28 @@ class I<dag out_ops, dag in_ops> : Instruction { let OutOperandList = out_ops; } -// CHECK: /* 0 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ... -// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21 -// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 6, 6, 0, 4, 0, // Skip to: 17 -// CHECK-NEXT: /* 13 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP -// CHECK-NEXT: /* 17 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1, -// CHECK-NEXT: /* 21 */ MCD::OPC_FilterValue, 1, 14, 0, // Skip to: 39 -// CHECK-NEXT: /* 25 */ MCD::OPC_CheckField, 6, 6, 0, 4, 0, // Skip to: 35 -// CHECK-NEXT: /* 31 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP -// CHECK-NEXT: /* 35 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1, -// CHECK-NEXT: /* 39 */ MCD::OPC_FilterValue, 2, 14, 0, // Skip to: 57 -// CHECK-NEXT: /* 43 */ MCD::OPC_CheckField, 6, 6, 0, 4, 0, // Skip to: 53 -// CHECK-NEXT: /* 49 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP -// CHECK-NEXT: /* 53 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1, -// CHECK-NEXT: /* 57 */ MCD::OPC_FilterValueOrFail, 3, -// CHECK-NEXT: /* 59 */ MCD::OPC_CheckField, 6, 6, 0, 4, 0, // Skip to: 69 -// CHECK-NEXT: /* 65 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP -// CHECK-NEXT: /* 69 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1, -// CHECK-NEXT: /* 73 */ MCD::OPC_Fail, +// CHECK: /* 0 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ... +// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 0, 15, 0, // Skip to: 22 +// CHECK-NEXT: /* 7 */ MCD::OPC_Scope, 8, 0, // Skip to: 18 +// CHECK-NEXT: /* 10 */ MCD::OPC_CheckField, 6, 6, 0, +// CHECK-NEXT: /* 14 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0 +// CHECK-NEXT: /* 18 */ MCD::OPC_TryDecode, 187, 2, 1, +// CHECK-NEXT: /* 22 */ MCD::OPC_FilterValueOrSkip, 1, 15, 0, // Skip to: 41 +// CHECK-NEXT: /* 26 */ MCD::OPC_Scope, 8, 0, // Skip to: 37 +// CHECK-NEXT: /* 29 */ MCD::OPC_CheckField, 6, 6, 0, +// CHECK-NEXT: /* 33 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0 +// CHECK-NEXT: /* 37 */ MCD::OPC_TryDecode, 188, 2, 1, +// CHECK-NEXT: /* 41 */ MCD::OPC_FilterValueOrSkip, 2, 15, 0, // Skip to: 60 +// CHECK-NEXT: /* 45 */ MCD::OPC_Scope, 8, 0, // Skip to: 56 +// CHECK-NEXT: /* 48 */ MCD::OPC_CheckField, 6, 6, 0, +// CHECK-NEXT: /* 52 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0 +// CHECK-NEXT: /* 56 */ MCD::OPC_TryDecode, 189, 2, 1, +// CHECK-NEXT: /* 60 */ MCD::OPC_FilterValue, 3, +// CHECK-NEXT: /* 62 */ MCD::OPC_Scope, 8, 0, // Skip to: 73 +// CHECK-NEXT: /* 65 */ MCD::OPC_CheckField, 6, 6, 0, +// CHECK-NEXT: /* 69 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0 +// CHECK-NEXT: /* 73 */ MCD::OPC_TryDecode, 190, 2, 1, + class SHIFT<bits<2> opc> : I<(outs), (ins ShAmtOp:$shamt)>, EncSHIFT<opc>; def SHIFT0 : SHIFT<0>; diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td b/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td index e525b4e7219d..28762bfa1ec2 100644 --- a/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td +++ b/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td @@ -11,15 +11,14 @@ class I : Instruction { // Check that a 64-bit filter with all bits set does not confuse DecoderEmitter. // -// CHECK-LABEL: static const uint8_t DecoderTable128[35] = { -// CHECK-NEXT: MCD::OPC_ExtractField, 0, 64, -// CHECK-NEXT: MCD::OPC_FilterValue, 1, 8, 0, -// CHECK-NEXT: MCD::OPC_CheckFieldOrFail, 127, 1, 1, -// CHECK-NEXT: MCD::OPC_Decode, 187, 2, 0, -// CHECK-NEXT: MCD::OPC_FilterValueOrFail, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1, -// CHECK-NEXT: MCD::OPC_CheckFieldOrFail, 127, 1, 0, -// CHECK-NEXT: MCD::OPC_Decode, 186, 2, 0, -// CHECK-NEXT: MCD::OPC_Fail, +// CHECK-LABEL: static const uint8_t DecoderTable128[34] = { +// CHECK-NEXT: /* 0 */ MCD::OPC_ExtractField, 0, 64, // Inst{63-0} ... +// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 1, 8, 0, // Skip to: 15 +// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 127, 1, 1, +// CHECK-NEXT: /* 11 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I2, DecodeIdx: 0 +// CHECK-NEXT: /* 15 */ MCD::OPC_FilterValue, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1, +// CHECK-NEXT: /* 26 */ MCD::OPC_CheckField, 127, 1, 0, +// CHECK-NEXT: /* 30 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I1, DecodeIdx: 0 // CHECK-NEXT: }; def I1 : I { diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td b/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td index 853a68d22d1d..e3666ebbf942 100644 --- a/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td +++ b/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td @@ -9,27 +9,63 @@ def MyTarget : Target { let InstructionSet = MyTargetISA; } def R0 : Register<"r0"> { let Namespace = "MyTarget"; } def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>; +def X0 : Register<"x0"> { let Namespace = "MyTarget"; } +def GPR64 : RegisterClass<"MyTarget", [i64], 64, (add X0)>; + class I<dag OOps, dag IOps, list<dag> Pat> : Instruction { let Namespace = "MyTarget"; let OutOperandList = OOps; let InOperandList = IOps; let Pattern = Pat; + let Size = 4; bits<32> Inst; bits<32> SoftFail; } +// Assume there is a 2 bit encoding for the dst and src register. def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> { - let Size = 4; - let Inst{31...0} = 0; + bits<2> dst; + bits<2> src1; + let Inst{31...4} = 0; + let Inst{1...0} = dst; + let Inst{3...2} = src1; } + def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> { - let Size = 4; - let Inst{31...0} = 0; + bits<2> dst; + bits<2> src1; + let Inst{31...4} = 0; + let Inst{1...0} = dst; + let Inst{3...2} = src1; +} + +def C : I<(outs GPR64:$dst), (ins GPR64:$src1), []> { + bits<2> dst; + bits<2> src1; + let Inst{31...4} = 1; + let Inst{1...0} = dst; + let Inst{3...2} = src1; } +def D : I<(outs GPR64:$dst), (ins GPR64:$src1), []> { + bits<2> dst; + bits<2> src1; + let Inst{31...4} = 1; + let Inst{1...0} = dst; + let Inst{3...2} = src1; +} + +// CHECK: Decoding Conflict: +// CHECK: ................................ +// CHECK: 0000000000000000000000000000.... +// CHECK: 0000000000000000000000000000____ A +// CHECK: 0000000000000000000000000000____ B + // CHECK: Decoding Conflict: // CHECK: ................................ -// CHECK: 00000000000000000000000000000000 -// CHECK: 00000000000000000000000000000000 A -// CHECK: 00000000000000000000000000000000 B +// CHECK: 0000000000000000000000000001.... +// CHECK: 0000000000000000000000000001____ C +// CHECK: 0000000000000000000000000001____ D + +// CHECK: Decoding conflict encountered diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-1.td b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-1.td new file mode 100644 index 000000000000..7090eaf20a9a --- /dev/null +++ b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-1.td @@ -0,0 +1,28 @@ +// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 \ +// RUN: | FileCheck %s --implicit-check-not=error: + +include "llvm/Target/Target.td" + +def R0 : Register<"r0">; +def RC : RegisterClass<"MyTarget", [i32], 32, (add R0)>; + +// Used to crash. +// CHECK: error: In instruction 'I', operand #0 has 1 sub-arg names, but no sub-operands + +def I : Instruction { + let Size = 1; + bits<8> Inst; + bits<1> r; + + let Inst{0} = 0; + let Inst{1} = r; + + let OutOperandList = (outs); + let InOperandList = (ins (RC $r):$op); +} + +def II : InstrInfo; + +def MyTarget : Target { + let InstructionSet = II; +} diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-2.td b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-2.td new file mode 100644 index 000000000000..65cc0e20350c --- /dev/null +++ b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-2.td @@ -0,0 +1,27 @@ +// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 \ +// RUN: | FileCheck %s --implicit-check-not=error: + +include "llvm/Target/Target.td" + +def CustomOp : Operand<i32>; + +// Used to crash. +// CHECK: error: In instruction 'I', operand #0 has 1 sub-arg names, expected 0 + +def I : Instruction { + let Size = 1; + bits<8> Inst; + bits<1> i; + + let Inst{0} = 0; + let Inst{1} = i; + + let OutOperandList = (outs); + let InOperandList = (ins (CustomOp $i):$op); +} + +def II : InstrInfo; + +def MyTarget : Target { + let InstructionSet = II; +} diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td b/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td index eda714eef104..8afcf786f9c7 100644 --- a/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td +++ b/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td @@ -18,18 +18,19 @@ class I : Instruction { // 00000001 ________ I16_1 // 00000010 ________ I16_2 -// CHECK: MCD::OPC_ExtractField, 0, 1, // Inst{0} ... -// CHECK-NEXT: MCD::OPC_FilterValue, 0, 4, 0, // Skip to: 11 -// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_0, DecodeIdx: 0 -// CHECK-NEXT: MCD::OPC_FilterValue, 1, 4, 0, // Skip to: 19 -// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_1, DecodeIdx: 0 -// CHECK-NEXT: MCD::OPC_ExtractField, 8, 8, // Inst{15-8} ... -// CHECK-NEXT: MCD::OPC_FilterValue, 0, 4, 0, // Skip to: 30 -// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_0, DecodeIdx: 1 -// CHECK-NEXT: MCD::OPC_FilterValue, 1, 4, 0, // Skip to: 38 -// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_1, DecodeIdx: 1 -// CHECK-NEXT: MCD::OPC_FilterValueOrFail, 2, -// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_2, DecodeIdx: 1 +// CHECK: /* 0 */ MCD::OPC_Scope, 17, 0, // Skip to: 20 +// CHECK-NEXT: /* 3 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ... +// CHECK-NEXT: /* 6 */ MCD::OPC_FilterValueOrSkip, 0, 4, 0, // Skip to: 14 +// CHECK-NEXT: /* 10 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_0, DecodeIdx: 0 +// CHECK-NEXT: /* 14 */ MCD::OPC_FilterValue, 1, +// CHECK-NEXT: /* 16 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_1, DecodeIdx: 0 +// CHECK-NEXT: /* 20 */ MCD::OPC_ExtractField, 8, 8, // Inst{15-8} ... +// CHECK-NEXT: /* 23 */ MCD::OPC_FilterValueOrSkip, 0, 4, 0, // Skip to: 31 +// CHECK-NEXT: /* 27 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_0, DecodeIdx: 1 +// CHECK-NEXT: /* 31 */ MCD::OPC_FilterValueOrSkip, 1, 4, 0, // Skip to: 39 +// CHECK-NEXT: /* 35 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_1, DecodeIdx: 1 +// CHECK-NEXT: /* 39 */ MCD::OPC_FilterValue, 2, +// CHECK-NEXT: /* 41 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_2, DecodeIdx: 1 def I8_0 : I { dag Inst = (descend (operand "$op", 7), 0b0); } def I8_1 : I { dag Inst = (descend (operand "$op", 7), 0b1); } diff --git a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td index 04f6872da4c4..56d62ca07088 100644 --- a/llvm/test/TableGen/GlobalISelEmitter/HwModes.td +++ b/llvm/test/TableGen/GlobalISelEmitter/HwModes.td @@ -13,8 +13,8 @@ class MyTargetGenericInstruction : GenericInstruction { //def Has32 : Predicate<"Subtarget->has32()">; def Has64 : Predicate<"Subtarget->has64()">; -//def Mode32 : HwMode<"+a", [Has32]>; -def Mode64 : HwMode<"+b", [Has64]>; +//def Mode32 : HwMode<[Has32]>; +def Mode64 : HwMode<[Has64]>; def ModeVT : ValueTypeByHwMode<[DefaultMode, Mode64], [i32, i64]>; diff --git a/llvm/test/TableGen/HwModeBitSet.td b/llvm/test/TableGen/HwModeBitSet.td index b2de6e8e012c..869b09b3c631 100644 --- a/llvm/test/TableGen/HwModeBitSet.td +++ b/llvm/test/TableGen/HwModeBitSet.td @@ -11,9 +11,17 @@ def TestTarget : Target { let InstructionSet = TestTargetInstrInfo; } -def TestMode : HwMode<"+feat", []>; -def TestMode1 : HwMode<"+feat1", []>; -def TestMode2 : HwMode<"+feat2", []>; +def Feat1 : SubtargetFeature<"feat1", "HasFeat1", "true", "enable feature 1">; +def Feat2 : SubtargetFeature<"feat2", "HasFeat2", "true", "enable feature 2">; + +def HasFeat1 : Predicate<"Subtarget->hasFeat1()">, + AssemblerPredicate<(all_of Feat1)>; +def HasFeat2 : Predicate<"Subtarget->hasFeat2()">, + AssemblerPredicate<(all_of Feat2)>; + +def TestMode : HwMode<[HasFeat1]>; +def TestMode1 : HwMode<[HasFeat2]>; +def TestMode2 : HwMode<[HasFeat1, HasFeat2]>; class MyReg<string n> : Register<n> { @@ -120,13 +128,26 @@ def foo : Instruction { let AsmString = "foo $factor"; } +// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenMCSubtargetInfo::getHwModeSet() const { +// CHECK-SUBTARGET{LITERAL}:[[maybe_unused]] const FeatureBitset &FB = getFeatureBits(); +// CHECK-SUBTARGET-NEXT: // Collect HwModes and store them as a bit set. +// CHECK-SUBTARGET-NEXT: unsigned Modes = 0; +// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat1]) Modes |= (1 << 0); +// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat2]) Modes |= (1 << 1); +// CHECK-SUBTARGET-NEXT: if (FB[TestTarget::Feat1] && FB[TestTarget::Feat2]) Modes |= (1 << 2); +// CHECK-SUBTARGET-NEXT: return Modes; +// CHECK-SUBTARGET-NEXT: } + // CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwModeSet() const { -// CHECK-SUBTARGET: unsigned Modes = 0; -// CHECK-SUBTARGET: if (checkFeatures("+feat")) Modes |= (1 << 0); -// CHECK-SUBTARGET: if (checkFeatures("+feat1")) Modes |= (1 << 1); -// CHECK-SUBTARGET: if (checkFeatures("+feat2")) Modes |= (1 << 2); -// CHECK-SUBTARGET: return Modes; -// CHECK-SUBTARGET: } +// CHECK-SUBTARGET{LITERAL}:[[maybe_unused]] const auto *Subtarget = +// CHECK-SUBTARGET-NEXT: static_cast<const TestTargetSubtarget *>(this); +// CHECK-SUBTARGET-NEXT: // Collect HwModes and store them as a bit set. +// CHECK-SUBTARGET-NEXT: unsigned Modes = 0; +// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat1())) Modes |= (1 << 0); +// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat2())) Modes |= (1 << 1); +// CHECK-SUBTARGET-NEXT: if ((Subtarget->hasFeat1()) && (Subtarget->hasFeat2())) Modes |= (1 << 2); +// CHECK-SUBTARGET-NEXT: return Modes; +// CHECK-SUBTARGET-NEXT: } // CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwMode(enum HwModeType type) const { // CHECK-SUBTARGET: unsigned Modes = getHwModeSet(); // CHECK-SUBTARGET: if (!Modes) @@ -159,4 +180,3 @@ def foo : Instruction { // CHECK-SUBTARGET: llvm_unreachable("unexpected HwModeType"); // CHECK-SUBTARGET: return 0; // should not get here // CHECK-SUBTARGET: } - diff --git a/llvm/test/TableGen/HwModeEncodeAPInt.td b/llvm/test/TableGen/HwModeEncodeAPInt.td index 43ca5edd952a..82d99940aa0f 100644 --- a/llvm/test/TableGen/HwModeEncodeAPInt.td +++ b/llvm/test/TableGen/HwModeEncodeAPInt.td @@ -17,9 +17,9 @@ def Myi32 : Operand<i32> { def HasA : Predicate<"Subtarget->hasA()">; def HasB : Predicate<"Subtarget->hasB()">; -def ModeA : HwMode<"+a", [HasA]>; // Mode 1 -def ModeB : HwMode<"+b", [HasB]>; // Mode 2 -def ModeC : HwMode<"+c", []>; // Mode 3 +def ModeA : HwMode<[HasA]>; // Mode 1 +def ModeB : HwMode<[HasB]>; // Mode 2 +def ModeC : HwMode<[]>; // Mode 3 def fooTypeEncDefault : InstructionEncoding { @@ -114,32 +114,38 @@ def unrelated: Instruction { // For 'baz' we only assigned ModeB for it, so it will be presented // as '0' in the tables of ModeA, ModeC and Default Mode. // ENCODER-LABEL: static const uint64_t InstBits[] = { -// ENCODER: UINT64_C(2), UINT64_C(0), // bar -// ENCODER: UINT64_C(0), UINT64_C(0), // baz -// ENCODER: UINT64_C(8), UINT64_C(0), // foo -// ENCODER: UINT64_C(2), UINT64_C(0), // unrelated +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // bar +// ENCODER-NEXT: UINT64_C(0), UINT64_C(0), // baz +// ENCODER-NEXT: UINT64_C(8), UINT64_C(0), // foo +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // unrelated +// ENCODER-NEXT: }; // ENCODER-LABEL: static const uint64_t InstBits_ModeA[] = { -// ENCODER: UINT64_C(2), UINT64_C(0), // bar -// ENCODER: UINT64_C(0), UINT64_C(0), // baz -// ENCODER: UINT64_C(12), UINT64_C(0), // foo -// ENCODER: UINT64_C(2), UINT64_C(0), // unrelated +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // bar +// ENCODER-NEXT: UINT64_C(0), UINT64_C(0), // baz +// ENCODER-NEXT: UINT64_C(12), UINT64_C(0), // foo +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // unrelated +// ENCODER-NEXT: }; // ENCODER-LABEL: static const uint64_t InstBits_ModeB[] = { -// ENCODER: UINT64_C(2), UINT64_C(0), // bar -// ENCODER: UINT64_C(12), UINT64_C(0), // baz -// ENCODER: UINT64_C(0), UINT64_C(211106232532992), // foo -// ENCODER: UINT64_C(2), UINT64_C(0), // unrelated +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // bar +// ENCODER-NEXT: UINT64_C(12), UINT64_C(0), // baz +// ENCODER-NEXT: UINT64_C(0), UINT64_C(211106232532992), // foo +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // unrelated +// ENCODER-NEXT: }; // ENCODER-LABEL: static const uint64_t InstBits_ModeC[] = { -// ENCODER: UINT64_C(2), UINT64_C(0), // bar -// ENCODER: UINT64_C(0), UINT64_C(0), // baz -// ENCODER: UINT64_C(12582915), UINT64_C(0), // foo -// ENCODER: UINT64_C(2), UINT64_C(0), // unrelated - +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // bar +// ENCODER-NEXT: UINT64_C(0), UINT64_C(0), // baz +// ENCODER-NEXT: UINT64_C(12582915), UINT64_C(0), // foo +// ENCODER-NEXT: UINT64_C(2), UINT64_C(0), // unrelated +// ENCODER-NEXT: }; // ENCODER: const uint64_t *InstBitsByHw; +// ENCODER: constexpr unsigned FirstSupportedOpcode // ENCODER: const unsigned opcode = MI.getOpcode(); +// ENCODER: if (opcode < FirstSupportedOpcode) +// ENCODER: unsigned TableIndex = opcode - FirstSupportedOpcode // ENCODER: if (Scratch.getBitWidth() != 128) // ENCODER: Scratch = Scratch.zext(128); -// ENCODER: Inst = APInt(128, ArrayRef(InstBits + opcode * 2, 2)); +// ENCODER: Inst = APInt(128, ArrayRef(InstBits + TableIndex * 2, 2)); // ENCODER: APInt &Value = Inst; // ENCODER: APInt &op = Scratch; // ENCODER: switch (opcode) { @@ -155,7 +161,7 @@ def unrelated: Instruction { // ENCODER: case 2: InstBitsByHw = InstBits_ModeB; break; // ENCODER: case 3: InstBitsByHw = InstBits_ModeC; break; // ENCODER: }; -// ENCODER: Inst = APInt(128, ArrayRef(InstBitsByHw + opcode * 2, 2)); +// ENCODER: Inst = APInt(128, ArrayRef(InstBitsByHw + TableIndex * 2, 2)); // ENCODER: Value = Inst; // ENCODER: switch (HwMode) { // ENCODER: default: llvm_unreachable("Unhandled HwMode"); @@ -189,7 +195,7 @@ def unrelated: Instruction { // ENCODER: default: llvm_unreachable("Unknown hardware mode!"); break; // ENCODER: case 2: InstBitsByHw = InstBits_ModeB; break; // ENCODER: }; -// ENCODER: Inst = APInt(128, ArrayRef(InstBitsByHw + opcode * 2, 2)); +// ENCODER: Inst = APInt(128, ArrayRef(InstBitsByHw + TableIndex * 2, 2)); // ENCODER: Value = Inst; // ENCODER: switch (HwMode) { // ENCODER: default: llvm_unreachable("Unhandled HwMode"); diff --git a/llvm/test/TableGen/HwModeEncodeDecode.td b/llvm/test/TableGen/HwModeEncodeDecode.td index 991054f8a279..6df5fd46297b 100644 --- a/llvm/test/TableGen/HwModeEncodeDecode.td +++ b/llvm/test/TableGen/HwModeEncodeDecode.td @@ -16,8 +16,8 @@ def Myi32 : Operand<i32> { def HasA : Predicate<"Subtarget->hasA()">; def HasB : Predicate<"Subtarget->hasB()">; -def ModeA : HwMode<"+a", [HasA]>; -def ModeB : HwMode<"+b", [HasB]>; +def ModeA : HwMode<[HasA]>; +def ModeB : HwMode<[HasB]>; def fooTypeEncA : InstructionEncoding { @@ -70,10 +70,10 @@ def baz : Instruction { } } -// DECODER-LABEL: DecoderTable_ModeA32[22] = +// DECODER-LABEL: DecoderTable_ModeA32 // DECODER-DAG: Opcode: fooTypeEncA:foo // DECODER-DAG: Opcode: bar -// DECODER-LABEL: DecoderTable_ModeB32[30] = +// DECODER-LABEL: DecoderTable_ModeB32 // DECODER-DAG: Opcode: fooTypeEncB:foo // DECODER-DAG: Opcode: fooTypeEncA:baz // DECODER-DAG: Opcode: bar diff --git a/llvm/test/TableGen/HwModeEncodeDecode2.td b/llvm/test/TableGen/HwModeEncodeDecode2.td index a62d723837c8..6431a9bd69a5 100644 --- a/llvm/test/TableGen/HwModeEncodeDecode2.td +++ b/llvm/test/TableGen/HwModeEncodeDecode2.td @@ -20,8 +20,8 @@ def Myi32 : Operand<i32> { def HasA : Predicate<"Subtarget->hasA()">; def HasB : Predicate<"Subtarget->hasB()">; -def ModeA : HwMode<"+a", [HasA]>; -def ModeB : HwMode<"+b", [HasB]>; +def ModeA : HwMode<[HasA]>; +def ModeB : HwMode<[HasB]>; def fooTypeEncA : InstructionEncoding { @@ -93,26 +93,26 @@ let OutOperandList = (outs) in { } } -// DECODER-LABEL: DecoderTable_ModeA32[22] = +// DECODER-LABEL: DecoderTable_ModeA32 // DECODER-DAG: Opcode: fooTypeEncA:foo // DECODER-DAG: Opcode: bar -// DECODER-LABEL: DecoderTable_ModeB32[30] = +// DECODER-LABEL: DecoderTable_ModeB32 // DECODER-DAG: Opcode: fooTypeEncB:foo // DECODER-DAG: Opcode: fooTypeEncA:baz // DECODER-DAG: Opcode: bar -// DECODER-LABEL: DecoderTableAlt_ModeA32[9] = +// DECODER-LABEL: DecoderTableAlt_ModeA32 // DECODER-DAG: Opcode: unrelated -// DECODER-LABEL: DecoderTableAlt_ModeB32[9] = +// DECODER-LABEL: DecoderTableAlt_ModeB32 // DECODER-DAG: Opcode: unrelated -// DECODER-SUPPRESS-LABEL: DecoderTable32[9] = +// DECODER-SUPPRESS-LABEL: DecoderTable32 // DECODER-SUPPRESS-DAG: Opcode: bar -// DECODER-SUPPRESS-LABEL: DecoderTable_ModeA32[9] = +// DECODER-SUPPRESS-LABEL: DecoderTable_ModeA32 // DECODER-SUPPRESS-DAG: Opcode: fooTypeEncA:foo // DECODER-SUPPRESS-NOT: Opcode: bar -// DECODER-SUPPRESS-LABEL: DecoderTable_ModeB32[22] = +// DECODER-SUPPRESS-LABEL: DecoderTable_ModeB32 // DECODER-SUPPRESS-DAG: Opcode: fooTypeEncB:foo // DECODER-SUPPRESS-DAG: Opcode: fooTypeEncA:baz // DECODER-SUPPRESS-NOT: Opcode: bar -// DECODER-SUPPRESS-LABEL: DecoderTableAlt32[9] = +// DECODER-SUPPRESS-LABEL: DecoderTableAlt32 // DECODER-SUPPRESS-DAG: Opcode: unrelated diff --git a/llvm/test/TableGen/HwModeEncodeDecode3.td b/llvm/test/TableGen/HwModeEncodeDecode3.td index a7366949f401..6a7d080491c2 100644 --- a/llvm/test/TableGen/HwModeEncodeDecode3.td +++ b/llvm/test/TableGen/HwModeEncodeDecode3.td @@ -22,9 +22,9 @@ def Myi32 : Operand<i32> { def HasA : Predicate<"Subtarget->hasA()">; def HasB : Predicate<"Subtarget->hasB()">; -def ModeA : HwMode<"+a", [HasA]>; // Mode 1 -def ModeB : HwMode<"+b", [HasB]>; // Mode 2 -def ModeC : HwMode<"+c", []>; // Mode 3 +def ModeA : HwMode<[HasA]>; // Mode 1 +def ModeB : HwMode<[HasB]>; // Mode 2 +def ModeC : HwMode<[]>; // Mode 3 def fooTypeEncDefault : InstructionEncoding { @@ -116,47 +116,47 @@ def unrelated: Instruction { // significant duplication of DecoderTables. The four tables ‘DecoderTableAlt32’, // ‘DecoderTableAlt_ModeA32’, ‘DecoderTableAlt_ModeB32’ and 'DecoderTable_ModeC32' are // exact duplicates and could effectively be merged into one. -// DECODER-LABEL: DecoderTable32[9] = +// DECODER-LABEL: DecoderTable32 // DECODER-DAG: Opcode: bar -// DECODER-LABEL: DecoderTable64[9] = -// DECODER-DAG: Opcode: fooTypeEncDefault:foo -// DECODER-LABEL: DecoderTable_ModeA32[22] = +// DECODER-LABEL: DecoderTable_ModeA32 // DECODER-DAG: Opcode: fooTypeEncA:foo // DECODER-DAG: Opcode: bar -// DECODER-LABEL: DecoderTable_ModeB32[30] = +// DECODER-LABEL: DecoderTable_ModeB32 // DECODER-DAG: Opcode: fooTypeEncB:foo // DECODER-DAG: Opcode: fooTypeEncA:baz // DECODER-DAG: Opcode: bar -// DECODER-LABEL: DecoderTable_ModeC32[22] = +// DECODER-LABEL: DecoderTable_ModeC32 // DECODER-DAG: Opcode: fooTypeEncC:foo // DECODER-DAG: Opcode: bar -// DECODER-LABEL: DecoderTableAlt32[9] = +// DECODER-LABEL: DecoderTableAlt32 // DECODER-DAG: Opcode: unrelated -// DECODER-LABEL: DecoderTableAlt_ModeA32[9] = +// DECODER-LABEL: DecoderTableAlt_ModeA32 // DECODER-DAG: Opcode: unrelated -// DECODER-LABEL: DecoderTableAlt_ModeB32[9] = +// DECODER-LABEL: DecoderTableAlt_ModeB32 // DECODER-DAG: Opcode: unrelated -// DECODER-LABEL: DecoderTableAlt_ModeC32[9] = +// DECODER-LABEL: DecoderTableAlt_ModeC32 // DECODER-DAG: Opcode: unrelated +// DECODER-LABEL: DecoderTable64 +// DECODER-DAG: Opcode: fooTypeEncDefault:foo // Under the 'O1' optimization level, unnecessary duplicate tables will be eliminated, // reducing the four ‘Alt’ tables down to just one. -// DECODER-SUPPRESS-O1-LABEL: DecoderTable32[9] = +// DECODER-SUPPRESS-O1-LABEL: DecoderTable32 // DECODER-SUPPRESS-O1-DAG: Opcode: bar -// DECODER-SUPPRESS-O1-LABEL: DecoderTable64[9] = -// DECODER-SUPPRESS-O1-DAG: Opcode: fooTypeEncDefault:foo -// DECODER-SUPPRESS-O1-LABEL: DecoderTable_ModeA32[22] = +// DECODER-SUPPRESS-O1-LABEL: DecoderTable_ModeA32 // DECODER-SUPPRESS-O1-DAG: Opcode: fooTypeEncA:foo // DECODER-SUPPRESS-O1-DAG: Opcode: bar -// DECODER-SUPPRESS-O1-LABEL: DecoderTable_ModeB32[30] = +// DECODER-SUPPRESS-O1-LABEL: DecoderTable_ModeB32 // DECODER-SUPPRESS-O1-DAG: Opcode: fooTypeEncB:foo // DECODER-SUPPRESS-O1-DAG: Opcode: fooTypeEncA:baz // DECODER-SUPPRESS-O1-DAG: Opcode: bar -// DECODER-SUPPRESS-O1-LABEL: DecoderTable_ModeC32[22] = +// DECODER-SUPPRESS-O1-LABEL: DecoderTable_ModeC32 // DECODER-SUPPRESS-O1-DAG: Opcode: fooTypeEncC:foo // DECODER-SUPPRESS-O1-DAG: Opcode: bar -// DECODER-SUPPRESS-O1-LABEL: DecoderTableAlt32[9] = +// DECODER-SUPPRESS-O1-LABEL: DecoderTableAlt32 // DECODER-SUPPRESS-O1-DAG: Opcode: unrelated +// DECODER-SUPPRESS-O1-LABEL: DecoderTable64 +// DECODER-SUPPRESS-O1-DAG: Opcode: fooTypeEncDefault:foo // Under the 'O2' optimization condition, instructions possessing the 'EncodingByHwMode' // attribute will be extracted from their original DecoderNamespace and placed into their @@ -164,23 +164,23 @@ def unrelated: Instruction { // attribute but are within the same DecoderNamespace will be stored in the 'Default' table. This // approach will significantly reduce instruction redundancy, but it necessitates users to thoroughly // consider the interplay between HwMode and DecoderNamespace for their instructions. -// DECODER-SUPPRESS-O2-LABEL: DecoderTable32[9] = +// DECODER-SUPPRESS-O2-LABEL: DecoderTable32 // DECODER-SUPPRESS-O2-DAG: Opcode: bar -// DECODER-SUPPRESS-O2-LABEL: DecoderTable64[9] = -// DECODER-SUPPRESS-O2-NOT: Opcode: bar -// DECODER-SUPPRESS-O2-DAG: Opcode: fooTypeEncDefault:foo -// DECODER-SUPPRESS-O2-LABEL: DecoderTable_ModeA32[9] = +// DECODER-SUPPRESS-O2-LABEL: DecoderTable_ModeA32 // DECODER-SUPPRESS-O2-DAG: Opcode: fooTypeEncA:foo // DECODER-SUPPRESS-O2-NOT: Opcode: bar -// DECODER-SUPPRESS-O2-LABEL: DecoderTable_ModeB32[22] = +// DECODER-SUPPRESS-O2-LABEL: DecoderTable_ModeB32 // DECODER-SUPPRESS-O2-DAG: Opcode: fooTypeEncB:foo // DECODER-SUPPRESS-O2-DAG: Opcode: fooTypeEncA:baz // DECODER-SUPPRESS-O2-NOT: Opcode: bar -// DECODER-SUPPRESS-O2-LABEL: DecoderTable_ModeC32[13] = +// DECODER-SUPPRESS-O2-LABEL: DecoderTable_ModeC32 // DECODER-SUPPRESS-O2-DAG: Opcode: fooTypeEncC:foo // DECODER-SUPPRESS-O2-NOT: Opcode: bar -// DECODER-SUPPRESS-O2-LABEL: DecoderTableAlt32[9] = +// DECODER-SUPPRESS-O2-LABEL: DecoderTableAlt32 // DECODER-SUPPRESS-O2-DAG: Opcode: unrelated +// DECODER-SUPPRESS-O2-LABEL: DecoderTable64 +// DECODER-SUPPRESS-O2-NOT: Opcode: bar +// DECODER-SUPPRESS-O2-DAG: Opcode: fooTypeEncDefault:foo // For 'bar' and 'unrelated', we didn't assign any HwModes for them, // they should keep the same in the following four tables. @@ -189,25 +189,29 @@ def unrelated: Instruction { // For 'baz' we only assigned ModeB for it, so it will be presented // as '0' in the tables of ModeA, ModeC and Default Mode. // ENCODER-LABEL: static const uint64_t InstBits[] = { -// ENCODER: UINT64_C(2), // bar -// ENCODER: UINT64_C(0), // baz -// ENCODER: UINT64_C(8), // foo -// ENCODER: UINT64_C(2), // unrelated +// ENCODER-NEXT: UINT64_C(2), // bar +// ENCODER-NEXT: UINT64_C(0), // baz +// ENCODER-NEXT: UINT64_C(8), // foo +// ENCODER-NEXT: UINT64_C(2), // unrelated +// ENCODER-NEXT: }; // ENCODER-LABEL: static const uint64_t InstBits_ModeA[] = { -// ENCODER: UINT64_C(2), // bar -// ENCODER: UINT64_C(0), // baz -// ENCODER: UINT64_C(12), // foo -// ENCODER: UINT64_C(2), // unrelated +// ENCODER-NEXT: UINT64_C(2), // bar +// ENCODER-NEXT: UINT64_C(0), // baz +// ENCODER-NEXT: UINT64_C(12), // foo +// ENCODER-NEXT: UINT64_C(2), // unrelated +// ENCODER-NEXT: }; // ENCODER-LABEL: static const uint64_t InstBits_ModeB[] = { -// ENCODER: UINT64_C(2), // bar -// ENCODER: UINT64_C(12), // baz -// ENCODER: UINT64_C(3), // foo -// ENCODER: UINT64_C(2), // unrelated +// ENCODER-NEXT: UINT64_C(2), // bar +// ENCODER-NEXT: UINT64_C(12), // baz +// ENCODER-NEXT: UINT64_C(3), // foo +// ENCODER-NEXT: UINT64_C(2), // unrelated +// ENCODER-NEXT: }; // ENCODER-LABEL: static const uint64_t InstBits_ModeC[] = { -// ENCODER: UINT64_C(2), // bar -// ENCODER: UINT64_C(0), // baz -// ENCODER: UINT64_C(12582915), // foo -// ENCODER: UINT64_C(2), // unrelated +// ENCODER-NEXT: UINT64_C(2), // bar +// ENCODER-NEXT: UINT64_C(0), // baz +// ENCODER-NEXT: UINT64_C(12582915), // foo +// ENCODER-NEXT: UINT64_C(2), // unrelated +// ENCODER-NEXT: }; // ENCODER-LABEL: case ::bar: // ENCODER-LABEL: case ::unrelated: @@ -221,7 +225,7 @@ def unrelated: Instruction { // ENCODER: case 2: InstBitsByHw = InstBits_ModeB; break; // ENCODER: case 3: InstBitsByHw = InstBits_ModeC; break; // ENCODER: }; -// ENCODER: Value = InstBitsByHw[opcode]; +// ENCODER: Value = InstBitsByHw[TableIndex]; // ENCODER: switch (HwMode) { // ENCODER: default: llvm_unreachable("Unhandled HwMode"); // ENCODER: case 0: { @@ -256,7 +260,7 @@ def unrelated: Instruction { // ENCODER: default: llvm_unreachable("Unknown hardware mode!"); break; // ENCODER: case 2: InstBitsByHw = InstBits_ModeB; break; // ENCODER: }; -// ENCODER: Value = InstBitsByHw[opcode]; +// ENCODER: Value = InstBitsByHw[TableIndex]; // ENCODER: switch (HwMode) { // ENCODER: default: llvm_unreachable("Unhandled HwMode"); // ENCODER: case 2: { diff --git a/llvm/test/TableGen/HwModeSelect.td b/llvm/test/TableGen/HwModeSelect.td index 0bac59a92304..dc58e7c02a4e 100644 --- a/llvm/test/TableGen/HwModeSelect.td +++ b/llvm/test/TableGen/HwModeSelect.td @@ -21,8 +21,8 @@ def TestClass : RegisterClass<"TestTarget", [i32], 32, (add TestReg)>; def HasFeat1 : Predicate<"Subtarget->hasFeat1()">; def HasFeat2 : Predicate<"Subtarget->hasFeat2()">; -def TestMode1 : HwMode<"+feat1", [HasFeat1]>; -def TestMode2 : HwMode<"+feat2", [HasFeat2]>; +def TestMode1 : HwMode<[HasFeat1]>; +def TestMode2 : HwMode<[HasFeat2]>; // CHECK: error: assertion failed: The Objects and Modes lists must be the same length // CHECK: [[FILE]]:[[@LINE+1]]:5: error: assertion failed in this record diff --git a/llvm/test/TableGen/HwModeSubRegs.td b/llvm/test/TableGen/HwModeSubRegs.td index 2bf7a917979d..31a569fcdaad 100644 --- a/llvm/test/TableGen/HwModeSubRegs.td +++ b/llvm/test/TableGen/HwModeSubRegs.td @@ -3,7 +3,7 @@ include "llvm/Target/Target.td" def HasFeat : Predicate<"Subtarget->hasFeat()">; -def TestMode : HwMode<"+feat1", [HasFeat]>; +def TestMode : HwMode<[HasFeat]>; class MyReg<string n> : Register<n> { diff --git a/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td b/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td index 7d1e830c912a..c224cd60412a 100644 --- a/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td +++ b/llvm/test/TableGen/RuntimeLibcallEmitter-calling-conv.td @@ -49,12 +49,12 @@ def MSP430LibraryWithCondCC : SystemRuntimeLibrary<isMSP430, // CHECK-NEXT: } // CHECK-EMPTY: // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::MALLOC, RTLIB::malloc}, // malloc +// CHECK-NEXT: {RTLIB::MALLOC, RTLIB::impl_malloc}, // malloc // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::SDIVREM_I8, RTLIB::__divmodqi4}, // __divmodqi4 -// CHECK-NEXT: {RTLIB::UDIVREM_I16, RTLIB::__udivmodhi4}, // __udivmodhi4 +// CHECK-NEXT: {RTLIB::SDIVREM_I8, RTLIB::impl___divmodqi4}, // __divmodqi4 +// CHECK-NEXT: {RTLIB::UDIVREM_I16, RTLIB::impl___udivmodhi4}, // __udivmodhi4 // CHECK-NEXT: }, CallingConv::AVR_BUILTIN); // CHECK-EMPTY: // CHECK-NEXT: return; @@ -62,12 +62,12 @@ def MSP430LibraryWithCondCC : SystemRuntimeLibrary<isMSP430, // CHECK-EMPTY: // CHECK-NEXT: if (TT.getArch() == Triple::avr) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::MALLOC, RTLIB::malloc}, // malloc +// CHECK-NEXT: {RTLIB::MALLOC, RTLIB::impl_malloc}, // malloc // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::SDIVREM_I8, RTLIB::__divmodqi4}, // __divmodqi4 -// CHECK-NEXT: {RTLIB::UDIVREM_I16, RTLIB::__udivmodhi4}, // __udivmodhi4 +// CHECK-NEXT: {RTLIB::SDIVREM_I8, RTLIB::impl___divmodqi4}, // __divmodqi4 +// CHECK-NEXT: {RTLIB::UDIVREM_I16, RTLIB::impl___udivmodhi4}, // __udivmodhi4 // CHECK-NEXT: }, CallingConv::AVR_BUILTIN); // CHECK-EMPTY: // CHECK-NEXT: return; @@ -75,19 +75,19 @@ def MSP430LibraryWithCondCC : SystemRuntimeLibrary<isMSP430, // CHECK-EMPTY: // CHECK-NEXT: if (TT.getArch() == Triple::msp430) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::MALLOC, RTLIB::malloc}, // malloc +// CHECK-NEXT: {RTLIB::MALLOC, RTLIB::impl_malloc}, // malloc // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: if ( isFoo() ) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::SDIVREM_I8, RTLIB::__divmodqi4}, // __divmodqi4 +// CHECK-NEXT: {RTLIB::SDIVREM_I8, RTLIB::impl___divmodqi4}, // __divmodqi4 // CHECK-NEXT: }, CallingConv::AVR_BUILTIN); // CHECK-EMPTY: // CHECK-NEXT: } // CHECK-EMPTY: // CHECK-NEXT: if ( isBar() ) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::UDIVREM_I16, RTLIB::__udivmodhi4}, // __udivmodhi4 +// CHECK-NEXT: {RTLIB::UDIVREM_I16, RTLIB::impl___udivmodhi4}, // __udivmodhi4 // CHECK-NEXT: }, CallingConv::MSP430_BUILTIN); // CHECK-EMPTY: // CHECK-NEXT: } diff --git a/llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td b/llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td index 2608faf2f75f..8169f5691cf0 100644 --- a/llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td +++ b/llvm/test/TableGen/RuntimeLibcallEmitter-conflict-warning.td @@ -26,7 +26,7 @@ def dup1 : RuntimeLibcallImpl<ANOTHER_DUP>; // CHECK: if (isTargetArchA()) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::SOME_FUNC, RTLIB::func_b}, // func_b +// CHECK-NEXT: {RTLIB::SOME_FUNC, RTLIB::impl_func_b}, // func_b // CHECK-NEXT: }); // ERR: :[[@LINE+1]]:5: warning: conflicting implementations for libcall SOME_FUNC: func_b, func_a @@ -36,8 +36,8 @@ def TheSystemLibraryA : SystemRuntimeLibrary<isTargetArchA, // CHECK: if (isTargetArchB()) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::OTHER_FUNC, RTLIB::other_func}, // other_func -// CHECK-NEXT: {RTLIB::SOME_FUNC, RTLIB::func_a}, // func_a +// CHECK-NEXT: {RTLIB::OTHER_FUNC, RTLIB::impl_other_func}, // other_func +// CHECK-NEXT: {RTLIB::SOME_FUNC, RTLIB::impl_func_a}, // func_a // CHECK-NEXT: }); // ERR: :[[@LINE+1]]:5: warning: conflicting implementations for libcall SOME_FUNC: func_a, func_b @@ -47,9 +47,9 @@ def TheSystemLibraryB : SystemRuntimeLibrary<isTargetArchB, // CHECK: if (isTargetArchC()) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::ANOTHER_DUP, RTLIB::dup1}, // dup1 -// CHECK-NEXT: {RTLIB::OTHER_FUNC, RTLIB::other_func}, // other_func -// CHECK-NEXT: {RTLIB::SOME_FUNC, RTLIB::func_a}, // func_a +// CHECK-NEXT: {RTLIB::ANOTHER_DUP, RTLIB::impl_dup1}, // dup1 +// CHECK-NEXT: {RTLIB::OTHER_FUNC, RTLIB::impl_other_func}, // other_func +// CHECK-NEXT: {RTLIB::SOME_FUNC, RTLIB::impl_func_a}, // func_a // CHECK-NEXT: }); // ERR: :[[@LINE+3]]:5: warning: conflicting implementations for libcall ANOTHER_DUP: dup1, dup0 diff --git a/llvm/test/TableGen/RuntimeLibcallEmitter.td b/llvm/test/TableGen/RuntimeLibcallEmitter.td index dbb5c5e7199d..78705e25dc5d 100644 --- a/llvm/test/TableGen/RuntimeLibcallEmitter.td +++ b/llvm/test/TableGen/RuntimeLibcallEmitter.td @@ -89,16 +89,16 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-EMPTY: // CHECK-NEXT:enum LibcallImpl : unsigned short { // CHECK-NEXT: Unsupported = 0, -// CHECK-NEXT: ___memcpy = 1, // ___memcpy -// CHECK-NEXT: ___memset = 2, // ___memset -// CHECK-NEXT: __ashlsi3 = 3, // __ashlsi3 -// CHECK-NEXT: __lshrdi3 = 4, // __lshrdi3 +// CHECK-NEXT: impl____memcpy = 1, // ___memcpy +// CHECK-NEXT: impl____memset = 2, // ___memset +// CHECK-NEXT: impl___ashlsi3 = 3, // __ashlsi3 +// CHECK-NEXT: impl___lshrdi3 = 4, // __lshrdi3 // CHECK-NEXT: bzero = 5, // bzero // CHECK-NEXT: calloc = 6, // calloc // CHECK-NEXT: sqrtl_f128 = 7, // sqrtl // CHECK-NEXT: sqrtl_f80 = 8, // sqrtl -// CHECK-NEXT: NumLibcallImpls = 9 // CHECK-NEXT: }; +// CHECK-NEXT: constexpr size_t NumLibcallImpls = 9; // CHECK-NEXT: } // End namespace RTLIB // CHECK-NEXT: } // End namespace llvm // CHECK-NEXT: #endif @@ -152,14 +152,14 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-EMPTY: // CHECK-NEXT: const RTLIB::Libcall llvm::RTLIB::RuntimeLibcallsInfo::ImplToLibcall[RTLIB::NumLibcallImpls] = { // CHECK-NEXT: RTLIB::UNKNOWN_LIBCALL, // RTLIB::Unsupported -// CHECK-NEXT: RTLIB::MEMCPY, // RTLIB::___memcpy -// CHECK-NEXT: RTLIB::MEMSET, // RTLIB::___memset -// CHECK-NEXT: RTLIB::SHL_I32, // RTLIB::__ashlsi3 -// CHECK-NEXT: RTLIB::SRL_I64, // RTLIB::__lshrdi3 -// CHECK-NEXT: RTLIB::BZERO, // RTLIB::bzero -// CHECK-NEXT: RTLIB::CALLOC, // RTLIB::calloc -// CHECK-NEXT: RTLIB::SQRT_F128, // RTLIB::sqrtl_f128 -// CHECK-NEXT: RTLIB::SQRT_F80, // RTLIB::sqrtl_f80 +// CHECK-NEXT: RTLIB::MEMCPY, // RTLIB::impl____memcpy +// CHECK-NEXT: RTLIB::MEMSET, // RTLIB::impl____memset +// CHECK-NEXT: RTLIB::SHL_I32, // RTLIB::impl___ashlsi3 +// CHECK-NEXT: RTLIB::SRL_I64, // RTLIB::impl___lshrdi3 +// CHECK-NEXT: RTLIB::BZERO, // RTLIB::impl_bzero +// CHECK-NEXT: RTLIB::CALLOC, // RTLIB::impl_calloc +// CHECK-NEXT: RTLIB::SQRT_F128, // RTLIB::impl_sqrtl_f128 +// CHECK-NEXT: RTLIB::SQRT_F80, // RTLIB::impl_sqrtl_f80 // CHECK-NEXT: }; // CHECK: #ifdef GET_LOOKUP_LIBCALL_IMPL_NAME_BODY @@ -176,9 +176,9 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK: iota_range<RTLIB::LibcallImpl> RTLIB::RuntimeLibcallsInfo::lookupLibcallImplNameImpl(StringRef Name) { // CHECK: static constexpr uint16_t HashTableNameToEnum[16] = { -// CHECK: 2, // 0x000000705301b8, ___memset +// CHECK: 2, // CHECK: 0, -// CHECK: 6, // 0x0000001417a2af, calloc +// CHECK: 6, // CHECK: 0, // CHECK: }; @@ -207,22 +207,22 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-EMPTY: // CHECK-NEXT: if (TT.getArch() == Triple::blah) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::BZERO, RTLIB::bzero}, // bzero -// CHECK-NEXT: {RTLIB::CALLOC, RTLIB::calloc}, // calloc -// CHECK-NEXT: {RTLIB::SQRT_F128, RTLIB::sqrtl_f128}, // sqrtl +// CHECK-NEXT: {RTLIB::BZERO, RTLIB::impl_bzero}, // bzero +// CHECK-NEXT: {RTLIB::CALLOC, RTLIB::impl_calloc}, // calloc +// CHECK-NEXT: {RTLIB::SQRT_F128, RTLIB::impl_sqrtl_f128}, // sqrtl // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: if (TT.hasCompilerRT()) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::SHL_I32, RTLIB::__ashlsi3}, // __ashlsi3 -// CHECK-NEXT: {RTLIB::SRL_I64, RTLIB::__lshrdi3}, // __lshrdi3 +// CHECK-NEXT: {RTLIB::SHL_I32, RTLIB::impl___ashlsi3}, // __ashlsi3 +// CHECK-NEXT: {RTLIB::SRL_I64, RTLIB::impl___lshrdi3}, // __lshrdi3 // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: } // CHECK-EMPTY: // CHECK-NEXT: if (TT.getOS() == Triple::bar) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::MEMSET, RTLIB::___memset}, // ___memset +// CHECK-NEXT: {RTLIB::MEMSET, RTLIB::impl____memset}, // ___memset // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: } @@ -232,9 +232,9 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-EMPTY: // CHECK-NEXT: if (TT.getArch() == Triple::buzz) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::SHL_I32, RTLIB::__ashlsi3}, // __ashlsi3 -// CHECK-NEXT: {RTLIB::SQRT_F80, RTLIB::sqrtl_f80}, // sqrtl -// CHECK-NEXT: {RTLIB::SRL_I64, RTLIB::__lshrdi3}, // __lshrdi3 +// CHECK-NEXT: {RTLIB::SHL_I32, RTLIB::impl___ashlsi3}, // __ashlsi3 +// CHECK-NEXT: {RTLIB::SQRT_F80, RTLIB::impl_sqrtl_f80}, // sqrtl +// CHECK-NEXT: {RTLIB::SRL_I64, RTLIB::impl___lshrdi3}, // __lshrdi3 // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: return; @@ -242,13 +242,13 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-EMPTY: // CHECK-NEXT: if (TT.getArch() == Triple::foo) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::BZERO, RTLIB::bzero}, // bzero -// CHECK-NEXT: {RTLIB::SQRT_F128, RTLIB::sqrtl_f128}, // sqrtl +// CHECK-NEXT: {RTLIB::BZERO, RTLIB::impl_bzero}, // bzero +// CHECK-NEXT: {RTLIB::SQRT_F128, RTLIB::impl_sqrtl_f128}, // sqrtl // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: if (TT.getOS() == Triple::bar) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::MEMSET, RTLIB::___memset}, // ___memset +// CHECK-NEXT: {RTLIB::MEMSET, RTLIB::impl____memset}, // ___memset // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: } @@ -258,10 +258,10 @@ def BlahLibrary : SystemRuntimeLibrary<isBlahArch, (add calloc, LibraryWithCondi // CHECK-EMPTY: // CHECK-NEXT: if (TT.getArch() == Triple::simple) { // CHECK-NEXT: setLibcallsImpl({ -// CHECK-NEXT: {RTLIB::CALLOC, RTLIB::calloc}, // calloc -// CHECK-NEXT: {RTLIB::SHL_I32, RTLIB::__ashlsi3}, // __ashlsi3 -// CHECK-NEXT: {RTLIB::SQRT_F80, RTLIB::sqrtl_f80}, // sqrtl -// CHECK-NEXT: {RTLIB::SRL_I64, RTLIB::__lshrdi3}, // __lshrdi3 +// CHECK-NEXT: {RTLIB::CALLOC, RTLIB::impl_calloc}, // calloc +// CHECK-NEXT: {RTLIB::SHL_I32, RTLIB::impl___ashlsi3}, // __ashlsi3 +// CHECK-NEXT: {RTLIB::SQRT_F80, RTLIB::impl_sqrtl_f80}, // sqrtl +// CHECK-NEXT: {RTLIB::SRL_I64, RTLIB::impl___lshrdi3}, // __lshrdi3 // CHECK-NEXT: }); // CHECK-EMPTY: // CHECK-NEXT: return; diff --git a/llvm/test/TableGen/VarLenDecoder.td b/llvm/test/TableGen/VarLenDecoder.td index 06ff62294a19..7eda1e6e4743 100644 --- a/llvm/test/TableGen/VarLenDecoder.td +++ b/llvm/test/TableGen/VarLenDecoder.td @@ -47,24 +47,25 @@ def FOO32 : MyVarInst<MemOp32> { ); } +// Instruction length table +// CHECK: InstrLenTable +// CHECK: 27, +// CHECK-NEXT: 43, +// CHECK-NEXT: }; + // CHECK-SMALL: /* 0 */ MCD::OPC_ExtractField, 3, 5, // Inst{7-3} ... -// CHECK-SMALL-NEXT: /* 3 */ MCD::OPC_FilterValue, 8, 4, 0, // Skip to: 11 +// CHECK-SMALL-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 8, 4, 0, // Skip to: 11 // CHECK-SMALL-NEXT: /* 7 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 0, // Opcode: FOO16 -// CHECK-SMALL-NEXT: /* 11 */ MCD::OPC_FilterValueOrFail, 9, +// CHECK-SMALL-NEXT: /* 11 */ MCD::OPC_FilterValue, 9, // CHECK-SMALL-NEXT: /* 13 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: FOO32 -// CHECK-SMALL-NEXT: /* 17 */ MCD::OPC_Fail, +// CHECK-SMALL-NEXT: }; // CHECK-LARGE: /* 0 */ MCD::OPC_ExtractField, 3, 5, // Inst{7-3} ... -// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValue, 8, 4, 0, 0, // Skip to: 12 +// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 8, 4, 0, 0, // Skip to: 12 // CHECK-LARGE-NEXT: /* 8 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 0, // Opcode: FOO16 -// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_FilterValueOrFail, 9, +// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_FilterValue, 9, // CHECK-LARGE-NEXT: /* 14 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: FOO32 -// CHECK-LARGE-NEXT: /* 18 */ MCD::OPC_Fail, - -// Instruction length table -// CHECK: 27, -// CHECK-NEXT: 43, -// CHECK-NEXT: }; +// CHECK-LARGE-NEXT: }; // CHECK: case 0: // CHECK-NEXT: tmp = fieldFromInstruction(insn, 8, 3); @@ -88,8 +89,7 @@ def FOO32 : MyVarInst<MemOp32> { // CHECK-LABEL: case MCD::OPC_ExtractField: { // CHECK: makeUp(insn, Start + Len); -// CHECK-LABEL: case MCD::OPC_CheckField: -// CHECK-NEXT: case MCD::OPC_CheckFieldOrFail: { +// CHECK-LABEL: case MCD::OPC_CheckField: { // CHECK: makeUp(insn, Start + Len); // CHECK-LABEL: case MCD::OPC_Decode: { diff --git a/llvm/test/TableGen/VarLenEncoderHwModes.td b/llvm/test/TableGen/VarLenEncoderHwModes.td index e0da0c9b93df..bbae024bfd87 100644 --- a/llvm/test/TableGen/VarLenEncoderHwModes.td +++ b/llvm/test/TableGen/VarLenEncoderHwModes.td @@ -19,8 +19,8 @@ def GR64 : RegisterOperand<RegClass>; def HasA : Predicate<"Subtarget->hasA()">; def HasB : Predicate<"Subtarget->hasB()">; -def ModeA : HwMode<"+a", [HasA]>; -def ModeB : HwMode<"+b", [HasB]>; +def ModeA : HwMode<[HasA]>; +def ModeB : HwMode<[HasB]>; def fooTypeEncA : InstructionEncoding { dag Inst = (descend diff --git a/llvm/test/TableGen/def-multiple-operands.td b/llvm/test/TableGen/def-multiple-operands.td index b747c5890750..5d215056920e 100644 --- a/llvm/test/TableGen/def-multiple-operands.td +++ b/llvm/test/TableGen/def-multiple-operands.td @@ -24,7 +24,7 @@ def Reg3Opnd : Operand<OtherVT> { // CHECK: archInstrTable {{.* = \{}} // CHECK: {{\{}} // CHECK: {{\{}} [[ID:[0-9]+]], 4, 3, 13, {{.+\}, \/\/}} -// CHECK-SAME: Inst #[[ID]] = InstA +// CHECK-SAME: InstA def InstA : Instruction { let Namespace = "MyNS"; let Size = 13; diff --git a/llvm/test/TableGen/get-named-operand-idx.td b/llvm/test/TableGen/get-named-operand-idx.td index ab23edd54c72..e6f6331cd9c4 100644 --- a/llvm/test/TableGen/get-named-operand-idx.td +++ b/llvm/test/TableGen/get-named-operand-idx.td @@ -48,34 +48,70 @@ def InstD : InstBase { let UseNamedOperandTable = 0; } -// CHECK: #ifdef GET_INSTRINFO_OPERAND_ENUM -// CHECK: #undef GET_INSTRINFO_OPERAND_ENUM -// CHECK: namespace llvm::MyNamespace { -// CHECK: enum class OpName { -// CHECK: a = 0, -// CHECK: b = 1, -// CHECK: c = 2, -// CHECK: d = 3, -// CHECK: x = 4, -// CHECK: NUM_OPERAND_NAMES = 5, -// CHECK: }; // enum class OpName -// CHECK: } // end namespace llvm::MyNamespace -// CHECK: #endif //GET_INSTRINFO_OPERAND_ENUM +// CHECK-LABEL: #ifdef GET_INSTRINFO_OPERAND_ENUM +// CHECK-NEXT: #undef GET_INSTRINFO_OPERAND_ENUM +// CHECK-NEXT: namespace llvm::MyNamespace { +// CHECK-NEXT: enum class OpName : uint8_t { +// CHECK-NEXT: a = 0, +// CHECK-NEXT: b = 1, +// CHECK-NEXT: c = 2, +// CHECK-NEXT: d = 3, +// CHECK-NEXT: x = 4, +// CHECK-NEXT: NUM_OPERAND_NAMES = 5, +// CHECK-NEXT: }; // enum class OpName +// CHECK-EMPTY: +// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name); +// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx); +// CHECK-NEXT: } // end namespace llvm::MyNamespace +// CHECK-NEXT: #endif //GET_INSTRINFO_OPERAND_ENUM -// CHECK: #ifdef GET_INSTRINFO_NAMED_OPS -// CHECK: #undef GET_INSTRINFO_NAMED_OPS -// CHECK: namespace llvm::MyNamespace { -// CHECK: LLVM_READONLY -// CHECK: int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) { -// CHECK: assert(Name != OpName::NUM_OPERAND_NAMES); -// CHECK: static constexpr int8_t OperandMap[][5] = { -// CHECK: {0, 1, 2, -1, -1, }, -// CHECK: {-1, -1, -1, 0, 1, }, -// CHECK: }; -// CHECK: static constexpr uint8_t InstructionIndex[] = { -// CHECK: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -// CHECK: }; -// CHECK: return OperandMap[InstructionIndex[Opcode]][(unsigned)Name]; -// CHECK: } -// CHECK: } // end namespace llvm::MyNamespace -// CHECK: #endif //GET_INSTRINFO_NAMED_OPS +// CHECK-LABEL: #ifdef GET_INSTRINFO_NAMED_OPS +// CHECK-NEXT: #undef GET_INSTRINFO_NAMED_OPS +// CHECK-NEXT: namespace llvm::MyNamespace { +// CHECK-NEXT: LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint16_t Opcode) { +// CHECK-NEXT: static constexpr uint8_t InstructionIndex[] = { +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 2, 0, +// CHECK-NEXT: }; +// CHECK-NEXT: return InstructionIndex[Opcode]; +// CHECK-NEXT: } +// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) { +// CHECK-NEXT: assert(Name != OpName::NUM_OPERAND_NAMES); +// CHECK-NEXT: static constexpr int8_t OperandMap[][5] = { +// CHECK-NEXT: {-1, -1, -1, -1, -1, }, +// CHECK-NEXT: {0, 1, 2, -1, -1, }, +// CHECK-NEXT: {-1, -1, -1, 0, 1, }, +// CHECK-NEXT: }; +// CHECK-NEXT: unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode); +// CHECK-NEXT: return OperandMap[InstrIdx][(unsigned)Name]; +// CHECK-NEXT: } +// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) { +// CHECK-NEXT: assert(Idx >= 0 && Idx < 3); +// CHECK-NEXT: static constexpr OpName OperandMap[][3] = { +// CHECK-NEXT: {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, }, +// CHECK-NEXT: {OpName::a, OpName::b, OpName::c, }, +// CHECK-NEXT: {OpName::d, OpName::x, OpName::NUM_OPERAND_NAMES, }, +// CHECK-NEXT: }; +// CHECK-NEXT: unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode); +// CHECK-NEXT: return OperandMap[InstrIdx][(unsigned)Idx]; +// CHECK-NEXT: } +// CHECK-NEXT: } // end namespace llvm::MyNamespace +// CHECK-NEXT: #endif //GET_INSTRINFO_NAMED_OPS diff --git a/llvm/test/TableGen/trydecode-emission.td b/llvm/test/TableGen/trydecode-emission.td index c3178dd71cf4..d1cf4bf54183 100644 --- a/llvm/test/TableGen/trydecode-emission.td +++ b/llvm/test/TableGen/trydecode-emission.td @@ -34,12 +34,12 @@ def InstB : TestInstruction { let hasCompleteDecoder = 0; } -// CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ... -// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-NEXT: /* 5 */ MCD::OPC_CheckField, 2, 2, 0, 6, 0, // Skip to: 17 -// CHECK-NEXT: /* 11 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 17 -// CHECK-NEXT: /* 17 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: {{[0-9]+}} -// CHECK-NEXT: /* 21 */ MCD::OPC_Fail, +// CHECK: /* 0 */ MCD::OPC_CheckField, 4, 4, 0, +// CHECK-NEXT: /* 4 */ MCD::OPC_Scope, 8, 0, // Skip to: 15 +// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, +// CHECK-NEXT: /* 11 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-NEXT: /* 15 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: 1 +// CHECK-NEXT: }; // CHECK: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } @@ -47,12 +47,12 @@ def InstB : TestInstruction { // CHECK-NEXT: NumToSkip |= (*Ptr++) << 8; // CHECK-NEXT: return NumToSkip; -// CHECK-LARGE: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ... -// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-LARGE-NEXT: /* 5 */ MCD::OPC_CheckField, 2, 2, 0, 7, 0, 0, // Skip to: 19 -// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 19 -// CHECK-LARGE-NEXT: /* 19 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: {{[0-9]+}} -// CHECK-LARGE-NEXT: /* 23 */ MCD::OPC_Fail, +// CHECK-LARGE: /* 0 */ MCD::OPC_CheckField, 4, 4, 0, +// CHECK-LARGE-NEXT: /* 4 */ MCD::OPC_Scope, 8, 0, 0, // Skip to: 16 +// CHECK-LARGE-NEXT: /* 8 */ MCD::OPC_CheckField, 2, 2, 0, +// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-LARGE-NEXT: /* 16 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: 1 +// CHECK-LARGE-NEXT: }; // CHECK-LARGE: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } diff --git a/llvm/test/TableGen/trydecode-emission2.td b/llvm/test/TableGen/trydecode-emission2.td index 4c8a95eff5dd..d7a87eb4b869 100644 --- a/llvm/test/TableGen/trydecode-emission2.td +++ b/llvm/test/TableGen/trydecode-emission2.td @@ -31,28 +31,25 @@ def InstB : TestInstruction { let hasCompleteDecoder = 0; } -// CHECK: /* 0 */ MCD::OPC_ExtractField, 2, 1, // Inst{2} ... -// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-NEXT: /* 5 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ... -// CHECK-NEXT: /* 8 */ MCD::OPC_FilterValueOrFail, 0 -// CHECK-NEXT: /* 10 */ MCD::OPC_CheckField, 0, 2, 3, 6, 0, // Skip to: 22 -// CHECK-NEXT: /* 16 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 22 -// CHECK-NEXT: /* 22 */ MCD::OPC_CheckFieldOrFail, 3, 2, 0, -// CHECK-NEXT: /* 26 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, {{[0-9]+}}, 1, -// CHECK-NEXT: /* 30 */ MCD::OPC_Fail, +// CHECK: /* 0 */ MCD::OPC_CheckField, 2, 1, 0, +// CHECK-NEXT: /* 4 */ MCD::OPC_CheckField, 5, 3, 0, +// CHECK-NEXT: /* 8 */ MCD::OPC_Scope, 8, 0, // Skip to: 19 +// CHECK-NEXT: /* 11 */ MCD::OPC_CheckField, 0, 2, 3, +// CHECK-NEXT: /* 15 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-NEXT: /* 19 */ MCD::OPC_CheckField, 3, 2, 0, +// CHECK-NEXT: /* 23 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 1, // CHECK: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } // CHECK: if (!Check(S, DecodeInstA(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } -// CHECK-LARGE: /* 0 */ MCD::OPC_ExtractField, 2, 1, // Inst{2} ... -// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-LARGE-NEXT: /* 5 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ... -// CHECK-LARGE-NEXT: /* 8 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-LARGE-NEXT: /* 10 */ MCD::OPC_CheckField, 0, 2, 3, 7, 0, 0, // Skip to: 24 -// CHECK-LARGE-NEXT: /* 17 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 24 -// CHECK-LARGE-NEXT: /* 24 */ MCD::OPC_CheckFieldOrFail, 3, 2, 0, -// CHECK-LARGE-NEXT: /* 28 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, {{[0-9]+}}, 1, -// CHECK-LARGE-NEXT: /* 32 */ MCD::OPC_Fail, +// CHECK-LARGE: /* 0 */ MCD::OPC_CheckField, 2, 1, 0, +// CHECK-LARGE-NEXT: /* 4 */ MCD::OPC_CheckField, 5, 3, 0, +// CHECK-LARGE-NEXT: /* 8 */ MCD::OPC_Scope, 8, 0, 0, // Skip to: 20 +// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_CheckField, 0, 2, 3, +// CHECK-LARGE-NEXT: /* 16 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-LARGE-NEXT: /* 20 */ MCD::OPC_CheckField, 3, 2, 0, +// CHECK-LARGE-NEXT: /* 24 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 1, +// CHECK-LARGE-NEXT: }; // CHECK-LARGE: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } // CHECK-LARGE: if (!Check(S, DecodeInstA(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } diff --git a/llvm/test/TableGen/trydecode-emission3.td b/llvm/test/TableGen/trydecode-emission3.td index f262bfab77c3..b7d1b8ddc1b6 100644 --- a/llvm/test/TableGen/trydecode-emission3.td +++ b/llvm/test/TableGen/trydecode-emission3.td @@ -35,20 +35,20 @@ def InstB : TestInstruction { let AsmString = "InstB"; } -// CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ... -// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-NEXT: /* 5 */ MCD::OPC_CheckField, 2, 2, 0, 6, 0, // Skip to: 17 -// CHECK-NEXT: /* 11 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 17 -// CHECK-NEXT: /* 17 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA -// CHECK-NEXT: /* 21 */ MCD::OPC_Fail, +// CHECK: /* 0 */ MCD::OPC_CheckField, 4, 4, 0, +// CHECK-NEXT: /* 4 */ MCD::OPC_Scope, 8, 0, // Skip to: 15 +// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, +// CHECK-NEXT: /* 11 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-NEXT: /* 15 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: 1 +// CHECK-NEXT: }; // CHECK: if (!Check(S, DecodeInstBOp(MI, tmp, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } -// CHECK-LARGE: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ... -// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-LARGE-NEXT: /* 5 */ MCD::OPC_CheckField, 2, 2, 0, 7, 0, 0, // Skip to: 19 -// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 19 -// CHECK-LARGE-NEXT: /* 19 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: {{[0-9]+}} -// CHECK-LARGE-NEXT: /* 23 */ MCD::OPC_Fail, +// CHECK-LARGE: /* 0 */ MCD::OPC_CheckField, 4, 4, 0, +// CHECK-LARGE-NEXT: /* 4 */ MCD::OPC_Scope, 8, 0, 0, // Skip to: 16 +// CHECK-LARGE-NEXT: /* 8 */ MCD::OPC_CheckField, 2, 2, 0, +// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-LARGE-NEXT: /* 16 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: 1 +// CHECK-LARGE-NEXT: }; // CHECK-LARGE: if (!Check(S, DecodeInstBOp(MI, tmp, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } diff --git a/llvm/test/TableGen/trydecode-emission4.td b/llvm/test/TableGen/trydecode-emission4.td index 2c63229c053a..439bd9d4ff36 100644 --- a/llvm/test/TableGen/trydecode-emission4.td +++ b/llvm/test/TableGen/trydecode-emission4.td @@ -33,22 +33,21 @@ def InstB : TestInstruction { let hasCompleteDecoder = 0; } -// CHECK: /* 0 */ MCD::OPC_ExtractField, 250, 3, 4, // Inst{509-506} ... -// CHECK-NEXT: /* 4 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-NEXT: /* 6 */ MCD::OPC_CheckField, 248, 3, 2, 0, 6, 0, // Skip to: 19 -// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 19 -// CHECK-NEXT: /* 19 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: {{[0-9]+}} -// CHECK-NEXT: /* 23 */ MCD::OPC_Fail, +// CHECK: /* 0 */ MCD::OPC_CheckField, 250, 3, 4, 0, +// CHECK-NEXT: /* 5 */ MCD::OPC_Scope, 9, 0, // Skip to: 17 +// CHECK-NEXT: /* 8 */ MCD::OPC_CheckField, 248, 3, 2, 0, +// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-NEXT: /* 17 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: 1 +// CHECK-NEXT: }; // CHECK: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } -// CHECK-LARGE: /* 0 */ MCD::OPC_ExtractField, 250, 3, 4, // Inst{509-506} ... -// CHECK-LARGE-NEXT: /* 4 */ MCD::OPC_FilterValueOrFail, 0, -// CHECK-LARGE-NEXT: /* 6 */ MCD::OPC_CheckField, 248, 3, 2, 0, 7, 0, 0, // Skip to: 21 -// CHECK-LARGE-NEXT: /* 14 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, 0, 0, 0, // Opcode: InstB, DecodeIdx: {{[0-9]+}}, Skip to: 21 -// CHECK-LARGE-NEXT: /* 21 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: {{[0-9]+}} -// CHECK-LARGE-NEXT: /* 25 */ MCD::OPC_Fail, +// CHECK-LARGE: /* 0 */ MCD::OPC_CheckField, 250, 3, 4, 0, +// CHECK-LARGE-NEXT: /* 5 */ MCD::OPC_Scope, 9, 0, 0, // Skip to: 18 +// CHECK-LARGE-NEXT: /* 9 */ MCD::OPC_CheckField, 248, 3, 2, 0, +// CHECK-LARGE-NEXT: /* 14 */ MCD::OPC_TryDecode, {{[0-9]+}}, {{[0-9]+}}, 0, +// CHECK-LARGE-NEXT: /* 18 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: InstA, DecodeIdx: 1 +// CHECK-LARGE-NEXT: }; // CHECK-LARGE: if (!Check(S, DecodeInstB(MI, insn, Address, Decoder))) { DecodeComplete = false; return MCDisassembler::Fail; } - |