Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format

7 files changed, 175 insertions, 58 deletions

diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td b/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td
index d7263b69dd8f..ef15b6b9a900 100644
--- a/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/MultiOps.td
@@ -12,39 +12,56 @@ def Reg : Register<"reg">;
 
 def Regs : RegisterClass<"foo", [i32], 0, (add Reg)>;
 
-def complex_nodec : Operand<i32> {
+def complex_nodec1 : Operand<i32> {
+  let MIOperandInfo = (ops Regs);
+}
+
+def complex_nodec2 : Operand<i32> {
   let MIOperandInfo = (ops Regs, Regs);
 }
 
-def complex_withdec : Operand<i32> {
+def complex_withdec1 : Operand<i32> {
+  let MIOperandInfo = (ops Regs);
+  let DecoderMethod = "DecodeComplex";
+}
+
+def complex_withdec2 : Operand<i32> {
   let MIOperandInfo = (ops Regs, Regs);
   let DecoderMethod = "DecodeComplex";
 }
 
 class ArchInstr : Instruction {
-  let Size = 1;
-  bits<8> Inst;
+  let Size = 2;
+  bits<16> Inst;
 }
 
 // This definition is broken in both directions:
 // 1. Uses a complex operand without a decoder, and without named sub-ops.
 // 2. Uses a complex operand with named sub-ops, but with a decoder as well.
 
-// CHECK: error: DecoderEmitter: operand "r1c" uses MIOperandInfo with multiple ops, but doesn't have a custom decoder!
+// CHECK: error: DecoderEmitter: operand "r1c" has non-empty MIOperandInfo, but doesn't have a custom decoder!
 // CHECK: note: Dumping record for previous error:
-// CHECK: error: DecoderEmitter: operand "r1ab" has type "complex_withdec" with a custom DecoderMethod, but also named sub-operands.
+// CHECK: error: DecoderEmitter: operand "r2b" has non-empty MIOperandInfo, but doesn't have a custom decoder!
+// CHECK: note: Dumping record for previous error:
+// CHECK: error: DecoderEmitter: operand "r1" has type "complex_withdec2" with a custom DecoderMethod, but also named sub-operands.
+// CHECK: error: DecoderEmitter: operand "r2" has type "complex_withdec1" with a custom DecoderMethod, but also named sub-operands.
 def foo1 : ArchInstr {
   bits<2> r1a;
   bits<2> r1b;
   bits<2> r1c;
+  bits<2> r2a;
+  bits<2> r2b;
 
   let Inst{1-0} = r1a;
   let Inst{3-2} = r1b;
   let Inst{5-4} = r1c;
-  let Inst{7-6} = 0b00;
+  let Inst{7-6} = r2a;
+  let Inst{9-8} = r2b;
+  let Inst{11-10} = 0b00;
 
-  let OutOperandList = (outs complex_nodec:$r1c);
-  let InOperandList = (ins (complex_withdec $r1a, $r1b):$r1ab);
+  let OutOperandList = (outs complex_nodec2:$r1c, complex_nodec1:$r2b);
+  let InOperandList = (ins (complex_withdec2 $r1a, $r1b):$r1,
+                           (complex_withdec1 $r2a):$r2);
 }
 
 // This definition has no errors.
@@ -52,12 +69,17 @@ def foo2 : ArchInstr {
   bits<2> r2a;
   bits<2> r2b;
   bits<2> r2c;
+  bits<2> r1a;
+  bits<2> r1b;
 
   let Inst{1-0} = r2a;
   let Inst{3-2} = r2b;
   let Inst{5-4} = r2c;
-  let Inst{7-6} = 0b01;
+  let Inst{7-6} = r1a;
+  let Inst{9-8} = r1b;
+  let Inst{11-10} = 0b01;
 
-  let OutOperandList = (outs complex_withdec:$r2c);
-  let InOperandList = (ins (complex_nodec $r2a, $r2b):$r2ab);
+  let OutOperandList = (outs complex_withdec2:$r2c, complex_withdec1:$r1b);
+  let InOperandList = (ins (complex_nodec2 $r2a, $r2b):$r2,
+                           (complex_nodec1 $r1a):$r1);
 }
diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td b/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td
index 192cb3c3f585..ec7e35e1ecac 100644
--- a/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td
@@ -30,24 +30,28 @@ class I<dag out_ops, dag in_ops> : Instruction {
   let OutOperandList = out_ops;
 }
 
-// CHECK:      /* 0 */  MCD::OPC_ExtractField, 12, 4,                // Inst{15-12} ...
-// CHECK-NEXT: /* 3 */  MCD::OPC_FilterValue, 0, 14, 0,              // Skip to: 21
-// CHECK-NEXT: /* 7 */  MCD::OPC_CheckField, 6, 6, 0, 4, 0,          // Skip to: 17
-// CHECK-NEXT: /* 13 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0,           // Opcode: {{.*}}:NOP
-// CHECK-NEXT: /* 17 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1,
-// CHECK-NEXT: /* 21 */ MCD::OPC_FilterValue, 1, 14, 0,              // Skip to: 39
-// CHECK-NEXT: /* 25 */ MCD::OPC_CheckField, 6, 6, 0, 4, 0,          // Skip to: 35
-// CHECK-NEXT: /* 31 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0,           // Opcode: {{.*}}:NOP
-// CHECK-NEXT: /* 35 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1,
-// CHECK-NEXT: /* 39 */ MCD::OPC_FilterValue, 2, 14, 0,              // Skip to: 57
-// CHECK-NEXT: /* 43 */ MCD::OPC_CheckField, 6, 6, 0, 4, 0,          // Skip to: 53
-// CHECK-NEXT: /* 49 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0,           // Opcode: {{.*}}:NOP
-// CHECK-NEXT: /* 53 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1,
-// CHECK-NEXT: /* 57 */ MCD::OPC_FilterValueOrFail, 3,
-// CHECK-NEXT: /* 59 */ MCD::OPC_CheckField, 6, 6, 0, 4, 0,          // Skip to: 69
-// CHECK-NEXT: /* 65 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0,           // Opcode: {{.*}}:NOP
-// CHECK-NEXT: /* 69 */ MCD::OPC_TryDecodeOrFail, {{[0-9]+}}, 2, 1,
-// CHECK-NEXT: /* 73 */ MCD::OPC_Fail,
+// CHECK:      /* 0 */  MCD::OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+// CHECK-NEXT: /* 3 */  MCD::OPC_FilterValueOrSkip, 0, 15, 0, // Skip to: 22
+// CHECK-NEXT: /* 7 */  MCD::OPC_Scope, 8, 0, // Skip to: 18
+// CHECK-NEXT: /* 10 */ MCD::OPC_CheckField, 6, 6, 0,
+// CHECK-NEXT: /* 14 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
+// CHECK-NEXT: /* 18 */ MCD::OPC_TryDecode, 187, 2, 1,
+// CHECK-NEXT: /* 22 */ MCD::OPC_FilterValueOrSkip, 1, 15, 0, // Skip to: 41
+// CHECK-NEXT: /* 26 */ MCD::OPC_Scope, 8, 0, // Skip to: 37
+// CHECK-NEXT: /* 29 */ MCD::OPC_CheckField, 6, 6, 0,
+// CHECK-NEXT: /* 33 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
+// CHECK-NEXT: /* 37 */ MCD::OPC_TryDecode, 188, 2, 1,
+// CHECK-NEXT: /* 41 */ MCD::OPC_FilterValueOrSkip, 2, 15, 0, // Skip to: 60
+// CHECK-NEXT: /* 45 */ MCD::OPC_Scope, 8, 0, // Skip to: 56
+// CHECK-NEXT: /* 48 */ MCD::OPC_CheckField, 6, 6, 0,
+// CHECK-NEXT: /* 52 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
+// CHECK-NEXT: /* 56 */ MCD::OPC_TryDecode, 189, 2, 1,
+// CHECK-NEXT: /* 60 */ MCD::OPC_FilterValue, 3,
+// CHECK-NEXT: /* 62 */ MCD::OPC_Scope, 8, 0, // Skip to: 73
+// CHECK-NEXT: /* 65 */ MCD::OPC_CheckField, 6, 6, 0,
+// CHECK-NEXT: /* 69 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
+// CHECK-NEXT: /* 73 */ MCD::OPC_TryDecode, 190, 2, 1,
+
 
 class SHIFT<bits<2> opc> : I<(outs), (ins ShAmtOp:$shamt)>, EncSHIFT<opc>;
 def SHIFT0 : SHIFT<0>;
diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td b/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td
index e525b4e7219d..28762bfa1ec2 100644
--- a/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td
@@ -11,15 +11,14 @@ class I : Instruction {
 
 // Check that a 64-bit filter with all bits set does not confuse DecoderEmitter.
 //
-// CHECK-LABEL: static const uint8_t DecoderTable128[35] = {
-// CHECK-NEXT:    MCD::OPC_ExtractField, 0, 64,
-// CHECK-NEXT:    MCD::OPC_FilterValue, 1, 8, 0,
-// CHECK-NEXT:    MCD::OPC_CheckFieldOrFail, 127, 1, 1,
-// CHECK-NEXT:    MCD::OPC_Decode, 187, 2, 0,
-// CHECK-NEXT:    MCD::OPC_FilterValueOrFail, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1,
-// CHECK-NEXT:    MCD::OPC_CheckFieldOrFail, 127, 1, 0,
-// CHECK-NEXT:    MCD::OPC_Decode, 186, 2, 0,
-// CHECK-NEXT:    MCD::OPC_Fail,
+// CHECK-LABEL: static const uint8_t DecoderTable128[34] = {
+// CHECK-NEXT:  /* 0 */  MCD::OPC_ExtractField, 0, 64,  // Inst{63-0} ...
+// CHECK-NEXT:  /* 3 */  MCD::OPC_FilterValueOrSkip, 1, 8, 0, // Skip to: 15
+// CHECK-NEXT:  /* 7 */  MCD::OPC_CheckField, 127, 1, 1,
+// CHECK-NEXT:  /* 11 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I2, DecodeIdx: 0
+// CHECK-NEXT:  /* 15 */ MCD::OPC_FilterValue, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1,
+// CHECK-NEXT:  /* 26 */ MCD::OPC_CheckField, 127, 1, 0,
+// CHECK-NEXT:  /* 30 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I1, DecodeIdx: 0
 // CHECK-NEXT:  };
 
 def I1 : I {
diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td b/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
index 853a68d22d1d..e3666ebbf942 100644
--- a/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
@@ -9,27 +9,63 @@ def MyTarget : Target { let InstructionSet = MyTargetISA; }
 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
 
+def X0 : Register<"x0"> { let Namespace = "MyTarget"; }
+def GPR64 : RegisterClass<"MyTarget", [i64], 64, (add X0)>;
+
 class I<dag OOps, dag IOps, list<dag> Pat>
   : Instruction {
   let Namespace = "MyTarget";
   let OutOperandList = OOps;
   let InOperandList = IOps;
   let Pattern = Pat;
+  let Size = 4;
   bits<32> Inst;
   bits<32> SoftFail;
 }
 
+// Assume there is a 2 bit encoding for the dst and src register.
 def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
-  let Size = 4;
-  let Inst{31...0} = 0;
+  bits<2> dst;
+  bits<2> src1;
+  let Inst{31...4} = 0;
+  let Inst{1...0} = dst;
+  let Inst{3...2} = src1;
 }
+
 def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
-  let Size = 4;
-  let Inst{31...0} = 0;
+  bits<2> dst;
+  bits<2> src1;
+  let Inst{31...4} = 0;
+  let Inst{1...0} = dst;
+  let Inst{3...2} = src1;
+}
+
+def C : I<(outs GPR64:$dst), (ins GPR64:$src1), []> {
+  bits<2> dst;
+  bits<2> src1;
+  let Inst{31...4} = 1;
+  let Inst{1...0} = dst;
+  let Inst{3...2} = src1;
 }
 
+def D : I<(outs GPR64:$dst), (ins GPR64:$src1), []> {
+  bits<2> dst;
+  bits<2> src1;
+  let Inst{31...4} = 1;
+  let Inst{1...0} = dst;
+  let Inst{3...2} = src1;
+}
+
+// CHECK: Decoding Conflict:
+// CHECK:     ................................
+// CHECK:     0000000000000000000000000000....
+// CHECK:     0000000000000000000000000000____  A
+// CHECK:     0000000000000000000000000000____  B
+
 // CHECK: Decoding Conflict:
 // CHECK:     ................................
-// CHECK:     00000000000000000000000000000000
-// CHECK:     00000000000000000000000000000000  A
-// CHECK:     00000000000000000000000000000000  B
+// CHECK:     0000000000000000000000000001....
+// CHECK:     0000000000000000000000000001____  C
+// CHECK:     0000000000000000000000000001____  D
+
+// CHECK: Decoding conflict encountered
diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-1.td b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-1.td
new file mode 100644
index 000000000000..7090eaf20a9a
--- /dev/null
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-1.td
@@ -0,0 +1,28 @@
+// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 \
+// RUN:   | FileCheck %s --implicit-check-not=error:
+
+include "llvm/Target/Target.td"
+
+def R0 : Register<"r0">;
+def RC : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
+
+// Used to crash.
+// CHECK: error: In instruction 'I', operand #0 has 1 sub-arg names, but no sub-operands
+
+def I : Instruction {
+  let Size = 1;
+  bits<8> Inst;
+  bits<1> r;
+
+  let Inst{0} = 0;
+  let Inst{1} = r;
+
+  let OutOperandList = (outs);
+  let InOperandList = (ins (RC $r):$op);
+}
+
+def II : InstrInfo;
+
+def MyTarget : Target {
+  let InstructionSet = II;
+}
diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-2.td b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-2.td
new file mode 100644
index 000000000000..65cc0e20350c
--- /dev/null
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/sub-arg-dag-error-2.td
@@ -0,0 +1,27 @@
+// RUN: not llvm-tblgen -gen-disassembler -I %p/../../../include %s 2>&1 \
+// RUN:   | FileCheck %s --implicit-check-not=error:
+
+include "llvm/Target/Target.td"
+
+def CustomOp : Operand<i32>;
+
+// Used to crash.
+// CHECK: error: In instruction 'I', operand #0 has 1 sub-arg names, expected 0
+
+def I : Instruction {
+  let Size = 1;
+  bits<8> Inst;
+  bits<1> i;
+
+  let Inst{0} = 0;
+  let Inst{1} = i;
+
+  let OutOperandList = (outs);
+  let InOperandList = (ins (CustomOp $i):$op);
+}
+
+def II : InstrInfo;
+
+def MyTarget : Target {
+  let InstructionSet = II;
+}
diff --git a/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td b/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td
index eda714eef104..8afcf786f9c7 100644
--- a/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td
+++ b/llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td
@@ -18,18 +18,19 @@ class I : Instruction {
 // 00000001 ________  I16_1
 // 00000010 ________  I16_2
 
-// CHECK:      MCD::OPC_ExtractField, 0, 1,       // Inst{0} ...
-// CHECK-NEXT: MCD::OPC_FilterValue, 0, 4, 0,     // Skip to: 11
-// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_0, DecodeIdx: 0
-// CHECK-NEXT: MCD::OPC_FilterValue, 1, 4, 0,     // Skip to: 19
-// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_1, DecodeIdx: 0
-// CHECK-NEXT: MCD::OPC_ExtractField, 8, 8,       // Inst{15-8} ...
-// CHECK-NEXT: MCD::OPC_FilterValue, 0, 4, 0,     // Skip to: 30
-// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_0, DecodeIdx: 1
-// CHECK-NEXT: MCD::OPC_FilterValue, 1, 4, 0,     // Skip to: 38
-// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_1, DecodeIdx: 1
-// CHECK-NEXT: MCD::OPC_FilterValueOrFail, 2,
-// CHECK-NEXT: MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_2, DecodeIdx: 1
+// CHECK:      /* 0 */  MCD::OPC_Scope, 17, 0,               // Skip to: 20
+// CHECK-NEXT: /* 3 */  MCD::OPC_ExtractField, 0, 1,         // Inst{0} ...
+// CHECK-NEXT: /* 6 */  MCD::OPC_FilterValueOrSkip, 0, 4, 0, // Skip to: 14
+// CHECK-NEXT: /* 10 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0,   // Opcode: I8_0, DecodeIdx: 0
+// CHECK-NEXT: /* 14 */ MCD::OPC_FilterValue, 1,
+// CHECK-NEXT: /* 16 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0,   // Opcode: I8_1, DecodeIdx: 0
+// CHECK-NEXT: /* 20 */ MCD::OPC_ExtractField, 8, 8,         // Inst{15-8} ...
+// CHECK-NEXT: /* 23 */ MCD::OPC_FilterValueOrSkip, 0, 4, 0, // Skip to: 31
+// CHECK-NEXT: /* 27 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1,   // Opcode: I16_0, DecodeIdx: 1
+// CHECK-NEXT: /* 31 */ MCD::OPC_FilterValueOrSkip, 1, 4, 0, // Skip to: 39
+// CHECK-NEXT: /* 35 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1,   // Opcode: I16_1, DecodeIdx: 1
+// CHECK-NEXT: /* 39 */ MCD::OPC_FilterValue, 2,
+// CHECK-NEXT: /* 41 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1,   // Opcode: I16_2, DecodeIdx: 1
 
 def I8_0  : I { dag Inst = (descend (operand "$op", 7), 0b0); }
 def I8_1  : I { dag Inst = (descend (operand "$op", 7), 0b1); }