diff options
| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-10 19:25:56 +0900 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2025-01-10 19:25:56 +0900 |
| commit | 63f5dc16d6bfca0512fb034052b41d13c3751e20 (patch) | |
| tree | e70266be1fda941e0974e71e3d2c1cf080081311 /llvm/test/CodeGen | |
| parent | 9e5734688ed3d5f6b3fb76a26b3d90a736d60781 (diff) | |
| parent | 397ac44f623f891d8f05d6673a95984ac0a26671 (diff) | |
Merge branch 'main' into users/chapuni/cov/single/unifyusers/chapuni/cov/single/unify
Diffstat (limited to 'llvm/test/CodeGen')
190 files changed, 6724 insertions, 5338 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll index 1aa28f5c2733..9a1203f18243 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll @@ -156,11 +156,10 @@ define i32 @fptosi_bf(bfloat %a) nounwind ssp { ; CHECK-LABEL: fptosi_bf: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: fmov s1, s0 -; CHECK-NEXT: // implicit-def: $s0 +; CHECK-NEXT: // implicit-def: $d0 ; CHECK-NEXT: fmov s0, s1 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret entry: @@ -173,11 +172,10 @@ define i32 @fptoui_sbf(bfloat %a) nounwind ssp { ; CHECK-LABEL: fptoui_sbf: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: fmov s1, s0 -; CHECK-NEXT: // implicit-def: $s0 +; CHECK-NEXT: // implicit-def: $d0 ; CHECK-NEXT: fmov s0, s1 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: fcvtzu w0, s0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll index ed9c1b037d0c..fb40dfcbe101 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll @@ -182,17 +182,14 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fadd s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -202,36 +199,34 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fadd s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2: @@ -281,17 +276,14 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fadd s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -301,36 +293,34 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fadd s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4: diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll index 888b795876f7..818dcf3a0b48 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll @@ -184,17 +184,14 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fmaxnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -204,36 +201,34 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fmaxnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2: @@ -283,17 +278,14 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fmaxnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -303,36 +295,34 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fmaxnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4: @@ -653,31 +643,23 @@ define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; NOLSE-LABEL: test_atomicrmw_fmax_v2bf16_seq_cst_align4: ; NOLSE: // %bb.0: ; NOLSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NOLSE-NEXT: mov h1, v0.h[1] -; NOLSE-NEXT: fmov w10, s0 +; NOLSE-NEXT: dup v1.4h, v0.h[1] ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fmov w9, s1 -; NOLSE-NEXT: fmov s1, w10 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s0, w9 +; NOLSE-NEXT: shll v0.4s, v0.4h, #16 +; NOLSE-NEXT: shll v1.4s, v1.4h, #16 ; NOLSE-NEXT: .LBB7_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxr w9, [x0] ; NOLSE-NEXT: fmov s2, w9 -; NOLSE-NEXT: mov h3, v2.h[1] -; NOLSE-NEXT: fmov w11, s2 -; NOLSE-NEXT: lsl w11, w11, #16 -; NOLSE-NEXT: fmov w10, s3 -; NOLSE-NEXT: fmov s3, w11 -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fmaxnm s3, s3, s1 -; NOLSE-NEXT: fmov s2, w10 +; NOLSE-NEXT: dup v3.4h, v2.h[1] +; NOLSE-NEXT: shll v2.4s, v2.4h, #16 ; NOLSE-NEXT: fmaxnm s2, s2, s0 -; NOLSE-NEXT: fmov w11, s3 +; NOLSE-NEXT: shll v3.4s, v3.4h, #16 +; NOLSE-NEXT: fmaxnm s3, s3, s1 +; NOLSE-NEXT: fmov w11, s2 ; NOLSE-NEXT: ubfx w13, w11, #16, #1 ; NOLSE-NEXT: add w11, w11, w8 -; NOLSE-NEXT: fmov w10, s2 +; NOLSE-NEXT: fmov w10, s3 ; NOLSE-NEXT: add w11, w13, w11 ; NOLSE-NEXT: lsr w11, w11, #16 ; NOLSE-NEXT: ubfx w12, w10, #16, #1 @@ -697,25 +679,17 @@ define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; LSE-LABEL: test_atomicrmw_fmax_v2bf16_seq_cst_align4: ; LSE: // %bb.0: ; LSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; LSE-NEXT: mov h1, v0.h[1] -; LSE-NEXT: fmov w10, s0 +; LSE-NEXT: dup v1.4h, v0.h[1] +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr s0, [x0] -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s1 -; LSE-NEXT: fmov s2, w10 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 +; LSE-NEXT: shll v1.4s, v1.4h, #16 ; LSE-NEXT: .LBB7_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: mov h3, v0.h[1] -; LSE-NEXT: fmov w10, s0 -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s3 -; LSE-NEXT: fmov s4, w10 -; LSE-NEXT: lsl w9, w9, #16 +; LSE-NEXT: dup v3.4h, v0.h[1] +; LSE-NEXT: shll v4.4s, v0.4h, #16 ; LSE-NEXT: fmaxnm s4, s4, s2 -; LSE-NEXT: fmov s3, w9 +; LSE-NEXT: shll v3.4s, v3.4h, #16 ; LSE-NEXT: fmaxnm s3, s3, s1 ; LSE-NEXT: fmov w10, s4 ; LSE-NEXT: ubfx w12, w10, #16, #1 diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll index a3665c6e4286..b969241e8bf9 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll @@ -184,17 +184,14 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fminnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -204,36 +201,34 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fminnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2: @@ -283,17 +278,14 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fminnm s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -303,36 +295,34 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fminnm s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4: @@ -653,31 +643,23 @@ define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; NOLSE-LABEL: test_atomicrmw_fmin_v2bf16_seq_cst_align4: ; NOLSE: // %bb.0: ; NOLSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; NOLSE-NEXT: mov h1, v0.h[1] -; NOLSE-NEXT: fmov w10, s0 +; NOLSE-NEXT: dup v1.4h, v0.h[1] ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fmov w9, s1 -; NOLSE-NEXT: fmov s1, w10 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s0, w9 +; NOLSE-NEXT: shll v0.4s, v0.4h, #16 +; NOLSE-NEXT: shll v1.4s, v1.4h, #16 ; NOLSE-NEXT: .LBB7_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxr w9, [x0] ; NOLSE-NEXT: fmov s2, w9 -; NOLSE-NEXT: mov h3, v2.h[1] -; NOLSE-NEXT: fmov w11, s2 -; NOLSE-NEXT: lsl w11, w11, #16 -; NOLSE-NEXT: fmov w10, s3 -; NOLSE-NEXT: fmov s3, w11 -; NOLSE-NEXT: lsl w10, w10, #16 -; NOLSE-NEXT: fminnm s3, s3, s1 -; NOLSE-NEXT: fmov s2, w10 +; NOLSE-NEXT: dup v3.4h, v2.h[1] +; NOLSE-NEXT: shll v2.4s, v2.4h, #16 ; NOLSE-NEXT: fminnm s2, s2, s0 -; NOLSE-NEXT: fmov w11, s3 +; NOLSE-NEXT: shll v3.4s, v3.4h, #16 +; NOLSE-NEXT: fminnm s3, s3, s1 +; NOLSE-NEXT: fmov w11, s2 ; NOLSE-NEXT: ubfx w13, w11, #16, #1 ; NOLSE-NEXT: add w11, w11, w8 -; NOLSE-NEXT: fmov w10, s2 +; NOLSE-NEXT: fmov w10, s3 ; NOLSE-NEXT: add w11, w13, w11 ; NOLSE-NEXT: lsr w11, w11, #16 ; NOLSE-NEXT: ubfx w12, w10, #16, #1 @@ -697,25 +679,17 @@ define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_seq_cst_align4(ptr %ptr, <2 x bf ; LSE-LABEL: test_atomicrmw_fmin_v2bf16_seq_cst_align4: ; LSE: // %bb.0: ; LSE-NEXT: // kill: def $d0 killed $d0 def $q0 -; LSE-NEXT: mov h1, v0.h[1] -; LSE-NEXT: fmov w10, s0 +; LSE-NEXT: dup v1.4h, v0.h[1] +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr s0, [x0] -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s1 -; LSE-NEXT: fmov s2, w10 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 +; LSE-NEXT: shll v1.4s, v1.4h, #16 ; LSE-NEXT: .LBB7_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: mov h3, v0.h[1] -; LSE-NEXT: fmov w10, s0 -; LSE-NEXT: lsl w10, w10, #16 -; LSE-NEXT: fmov w9, s3 -; LSE-NEXT: fmov s4, w10 -; LSE-NEXT: lsl w9, w9, #16 +; LSE-NEXT: dup v3.4h, v0.h[1] +; LSE-NEXT: shll v4.4s, v0.4h, #16 ; LSE-NEXT: fminnm s4, s4, s2 -; LSE-NEXT: fmov s3, w9 +; LSE-NEXT: shll v3.4s, v3.4h, #16 ; LSE-NEXT: fminnm s3, s3, s1 ; LSE-NEXT: fmov w10, s4 ; LSE-NEXT: ubfx w12, w10, #16, #1 diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll index 7725ce0e7318..e603337e7a56 100644 --- a/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll @@ -182,17 +182,14 @@ define half @test_atomicrmw_fsub_f16_seq_cst_align4(ptr %ptr, half %value) #0 { define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fsub s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -202,36 +199,34 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB2_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB2_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fsub s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB2_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2: @@ -281,17 +276,14 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value) define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align4(ptr %ptr, bfloat %value) #0 { ; NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4: ; NOLSE: // %bb.0: -; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; NOLSE-NEXT: shll v1.4s, v0.4h, #16 ; NOLSE-NEXT: mov w8, #32767 // =0x7fff -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s1, w9 ; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start ; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1 ; NOLSE-NEXT: ldaxrh w9, [x0] ; NOLSE-NEXT: fmov s0, w9 -; NOLSE-NEXT: lsl w9, w9, #16 -; NOLSE-NEXT: fmov s2, w9 +; NOLSE-NEXT: shll v2.4s, v0.4h, #16 ; NOLSE-NEXT: fsub s2, s2, s1 ; NOLSE-NEXT: fmov w9, s2 ; NOLSE-NEXT: ubfx w10, w9, #16, #1 @@ -301,36 +293,34 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align4(ptr %ptr, bfloat %value) ; NOLSE-NEXT: stlxrh w10, w9, [x0] ; NOLSE-NEXT: cbnz w10, .LBB3_1 ; NOLSE-NEXT: // %bb.2: // %atomicrmw.end -; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; NOLSE-NEXT: ret ; ; LSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4: ; LSE: // %bb.0: -; LSE-NEXT: // kill: def $h0 killed $h0 def $s0 -; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: // kill: def $h0 killed $h0 def $d0 +; LSE-NEXT: shll v1.4s, v0.4h, #16 ; LSE-NEXT: mov w8, #32767 // =0x7fff ; LSE-NEXT: ldr h0, [x0] -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s1, w9 ; LSE-NEXT: .LBB3_1: // %atomicrmw.start ; LSE-NEXT: // =>This Inner Loop Header: Depth=1 -; LSE-NEXT: fmov w9, s0 -; LSE-NEXT: lsl w9, w9, #16 -; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: shll v2.4s, v0.4h, #16 ; LSE-NEXT: fsub s2, s2, s1 ; LSE-NEXT: fmov w9, s2 ; LSE-NEXT: ubfx w10, w9, #16, #1 ; LSE-NEXT: add w9, w9, w8 ; LSE-NEXT: add w9, w10, w9 -; LSE-NEXT: fmov w10, s0 ; LSE-NEXT: lsr w9, w9, #16 -; LSE-NEXT: mov w11, w10 -; LSE-NEXT: casalh w11, w9, [x0] +; LSE-NEXT: fmov s2, w9 +; LSE-NEXT: fmov w9, s0 +; LSE-NEXT: fmov w10, s2 +; LSE-NEXT: mov w11, w9 +; LSE-NEXT: casalh w11, w10, [x0] ; LSE-NEXT: fmov s0, w11 -; LSE-NEXT: cmp w11, w10, uxth +; LSE-NEXT: cmp w11, w9, uxth ; LSE-NEXT: b.ne .LBB3_1 ; LSE-NEXT: // %bb.2: // %atomicrmw.end -; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0 +; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0 ; LSE-NEXT: ret ; ; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4: diff --git a/llvm/test/CodeGen/AArch64/bf16-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-instructions.ll index 33997614598c..bc06453e9c01 100644 --- a/llvm/test/CodeGen/AArch64/bf16-instructions.ll +++ b/llvm/test/CodeGen/AArch64/bf16-instructions.ll @@ -5,16 +5,12 @@ define bfloat @test_fadd(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fadd: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fadd s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -26,15 +22,11 @@ define bfloat @test_fadd(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fadd: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fadd s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fadd bfloat %a, %b @@ -44,16 +36,12 @@ define bfloat @test_fadd(bfloat %a, bfloat %b) #0 { define bfloat @test_fsub(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fsub: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fsub s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fsub s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -65,15 +53,11 @@ define bfloat @test_fsub(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fsub: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fsub s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fsub s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fsub bfloat %a, %b @@ -83,16 +67,12 @@ define bfloat @test_fsub(bfloat %a, bfloat %b) #0 { define bfloat @test_fmul(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fmul: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fmul s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmul s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -104,15 +84,11 @@ define bfloat @test_fmul(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fmul: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmul s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmul s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fmul bfloat %a, %b @@ -122,27 +98,21 @@ define bfloat @test_fmul(bfloat %a, bfloat %b) #0 { define bfloat @test_fmadd(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-CVT-LABEL: test_fmadd: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w10, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmul s0, s1, s0 +; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmul s0, s0, s1 +; CHECK-CVT-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 ; CHECK-CVT-NEXT: add w8, w8, w10 ; CHECK-CVT-NEXT: add w8, w9, w8 -; CHECK-CVT-NEXT: fmov w9, s2 ; CHECK-CVT-NEXT: lsr w8, w8, #16 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 ; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 @@ -155,23 +125,15 @@ define bfloat @test_fmadd(bfloat %a, bfloat %b, bfloat %c) #0 { ; ; CHECK-BF16-LABEL: test_fmadd: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmov w9, s2 -; CHECK-BF16-NEXT: fmul s0, s1, s0 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmul s0, s0, s1 +; CHECK-BF16-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-BF16-NEXT: bfcvt h0, s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -183,16 +145,12 @@ define bfloat @test_fmadd(bfloat %a, bfloat %b, bfloat %c) #0 { define bfloat @test_fdiv(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_fdiv: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fdiv s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fdiv s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -204,15 +162,11 @@ define bfloat @test_fdiv(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_fdiv: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fdiv s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fdiv s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = fdiv bfloat %a, %b @@ -223,14 +177,12 @@ define bfloat @test_frem(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_frem: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-CVT-NEXT: bl fmodf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -246,14 +198,12 @@ define bfloat @test_frem(bfloat %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_frem: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-BF16-NEXT: bl fmodf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -334,17 +284,13 @@ define bfloat @test_select(bfloat %a, bfloat %b, i1 zeroext %c) #0 { define bfloat @test_select_cc(bfloat %a, bfloat %b, bfloat %c, bfloat %d) #0 { ; CHECK-LABEL: test_select_cc: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h3 killed $h3 def $s3 -; CHECK-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: // kill: def $h3 killed $h3 def $d3 +; CHECK-NEXT: // kill: def $h2 killed $h2 def $d2 ; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 ; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: fcmp s2, s3 ; CHECK-NEXT: fcsel s0, s0, s1, ne ; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0 ; CHECK-NEXT: ret @@ -356,15 +302,11 @@ define bfloat @test_select_cc(bfloat %a, bfloat %b, bfloat %c, bfloat %d) #0 { define float @test_select_cc_f32_f16(float %a, float %b, bfloat %c, bfloat %d) #0 { ; CHECK-LABEL: test_select_cc_f32_f16: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h3 killed $h3 def $s3 -; CHECK-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s2 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: // kill: def $h3 killed $h3 def $d3 +; CHECK-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: fcmp s2, s3 ; CHECK-NEXT: fcsel s0, s0, s1, ne ; CHECK-NEXT: ret %cc = fcmp une bfloat %c, %d @@ -389,15 +331,11 @@ define bfloat @test_select_cc_f16_f32(bfloat %a, bfloat %b, float %c, float %d) define i1 @test_fcmp_une(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_une: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, ne ; CHECK-NEXT: ret %r = fcmp une bfloat %a, %b @@ -407,15 +345,11 @@ define i1 @test_fcmp_une(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ueq(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ueq: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w8, eq ; CHECK-NEXT: csinc w0, w8, wzr, vc ; CHECK-NEXT: ret @@ -426,15 +360,11 @@ define i1 @test_fcmp_ueq(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ugt(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ugt: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, hi ; CHECK-NEXT: ret %r = fcmp ugt bfloat %a, %b @@ -444,15 +374,11 @@ define i1 @test_fcmp_ugt(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_uge(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_uge: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, pl ; CHECK-NEXT: ret %r = fcmp uge bfloat %a, %b @@ -462,15 +388,11 @@ define i1 @test_fcmp_uge(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ult(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ult: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, lt ; CHECK-NEXT: ret %r = fcmp ult bfloat %a, %b @@ -480,15 +402,11 @@ define i1 @test_fcmp_ult(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ule(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ule: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, le ; CHECK-NEXT: ret %r = fcmp ule bfloat %a, %b @@ -498,15 +416,11 @@ define i1 @test_fcmp_ule(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_uno(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_uno: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, vs ; CHECK-NEXT: ret %r = fcmp uno bfloat %a, %b @@ -516,15 +430,11 @@ define i1 @test_fcmp_uno(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_one(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_one: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w8, mi ; CHECK-NEXT: csinc w0, w8, wzr, le ; CHECK-NEXT: ret @@ -535,15 +445,11 @@ define i1 @test_fcmp_one(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_oeq(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_oeq: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, eq ; CHECK-NEXT: ret %r = fcmp oeq bfloat %a, %b @@ -553,15 +459,11 @@ define i1 @test_fcmp_oeq(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ogt(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ogt: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, gt ; CHECK-NEXT: ret %r = fcmp ogt bfloat %a, %b @@ -571,15 +473,11 @@ define i1 @test_fcmp_ogt(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_oge(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_oge: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, ge ; CHECK-NEXT: ret %r = fcmp oge bfloat %a, %b @@ -589,15 +487,11 @@ define i1 @test_fcmp_oge(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_olt(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_olt: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, mi ; CHECK-NEXT: ret %r = fcmp olt bfloat %a, %b @@ -607,15 +501,11 @@ define i1 @test_fcmp_olt(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ole(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ole: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, ls ; CHECK-NEXT: ret %r = fcmp ole bfloat %a, %b @@ -625,15 +515,11 @@ define i1 @test_fcmp_ole(bfloat %a, bfloat %b) #0 { define i1 @test_fcmp_ord(bfloat %a, bfloat %b) #0 { ; CHECK-LABEL: test_fcmp_ord: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: cset w0, vc ; CHECK-NEXT: ret %r = fcmp ord bfloat %a, %b @@ -643,13 +529,11 @@ define i1 @test_fcmp_ord(bfloat %a, bfloat %b) #0 { define void @test_fccmp(bfloat %in, ptr %out) { ; CHECK-LABEL: test_fccmp: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: movi v1.2s, #69, lsl #24 -; CHECK-NEXT: movi v3.2s, #72, lsl #24 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s2, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v2.4s, v0.4h, #16 ; CHECK-NEXT: adrp x8, .LCPI29_0 +; CHECK-NEXT: movi v3.2s, #72, lsl #24 ; CHECK-NEXT: fcmp s2, s1 ; CHECK-NEXT: ldr h1, [x8, :lo12:.LCPI29_0] ; CHECK-NEXT: fccmp s2, s3, #4, mi @@ -667,15 +551,11 @@ define void @test_fccmp(bfloat %in, ptr %out) { define void @test_br_cc(bfloat %a, bfloat %b, ptr %p1, ptr %p2) #0 { ; CHECK-LABEL: test_br_cc: ; CHECK: // %bb.0: // %common.ret -; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: csel x8, x0, x1, pl ; CHECK-NEXT: str wzr, [x8] ; CHECK-NEXT: ret @@ -725,10 +605,8 @@ declare i1 @test_dummy(ptr %p1) #0 define i32 @test_fptosi_i32(bfloat %a) #0 { ; CHECK-LABEL: test_fptosi_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret %r = fptosi bfloat %a to i32 @@ -738,10 +616,8 @@ define i32 @test_fptosi_i32(bfloat %a) #0 { define i64 @test_fptosi_i64(bfloat %a) #0 { ; CHECK-LABEL: test_fptosi_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs x0, s0 ; CHECK-NEXT: ret %r = fptosi bfloat %a to i64 @@ -751,10 +627,8 @@ define i64 @test_fptosi_i64(bfloat %a) #0 { define i32 @test_fptoui_i32(bfloat %a) #0 { ; CHECK-LABEL: test_fptoui_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu w0, s0 ; CHECK-NEXT: ret %r = fptoui bfloat %a to i32 @@ -764,10 +638,8 @@ define i32 @test_fptoui_i32(bfloat %a) #0 { define i64 @test_fptoui_i64(bfloat %a) #0 { ; CHECK-LABEL: test_fptoui_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu x0, s0 ; CHECK-NEXT: ret %r = fptoui bfloat %a to i64 @@ -927,7 +799,8 @@ define bfloat @test_uitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: ucvtf d1, w0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fcvtxn s1, d1 ; CHECK-CVT-NEXT: fmov w9, s1 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -935,12 +808,7 @@ define bfloat @test_uitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT-NEXT: add w9, w10, w9 ; CHECK-CVT-NEXT: lsr w9, w9, #16 ; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmov w9, s0 -; CHECK-CVT-NEXT: fmov w10, s1 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s1, w10 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -954,15 +822,11 @@ define bfloat @test_uitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_uitofp_i32_fadd: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: ucvtf d1, w0 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fcvtxn s1, d1 -; CHECK-BF16-NEXT: fmov s0, w8 ; CHECK-BF16-NEXT: bfcvt h1, s1 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -976,7 +840,8 @@ define bfloat @test_sitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: scvtf d1, w0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fcvtxn s1, d1 ; CHECK-CVT-NEXT: fmov w9, s1 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -984,12 +849,7 @@ define bfloat @test_sitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-CVT-NEXT: add w9, w10, w9 ; CHECK-CVT-NEXT: lsr w9, w9, #16 ; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmov w9, s0 -; CHECK-CVT-NEXT: fmov w10, s1 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s1, w10 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -1003,15 +863,11 @@ define bfloat @test_sitofp_i32_fadd(i32 %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_sitofp_i32_fadd: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: scvtf d1, w0 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fcvtxn s1, d1 -; CHECK-BF16-NEXT: fmov s0, w8 ; CHECK-BF16-NEXT: bfcvt h1, s1 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -1070,10 +926,9 @@ define bfloat @test_fptrunc_double(double %a) #0 { define float @test_fpext_float(bfloat %a) #0 { ; CHECK-LABEL: test_fpext_float: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: ret %r = fpext bfloat %a to float ret float %r @@ -1082,10 +937,8 @@ define float @test_fpext_float(bfloat %a) #0 { define double @test_fpext_double(bfloat %a) #0 { ; CHECK-LABEL: test_fpext_double: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvt d0, s0 ; CHECK-NEXT: ret %r = fpext bfloat %a to double @@ -1148,11 +1001,9 @@ declare bfloat @llvm.fmuladd.f16(bfloat %a, bfloat %b, bfloat %c) #0 define bfloat @test_sqrt(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_sqrt: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fsqrt s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -1165,10 +1016,8 @@ define bfloat @test_sqrt(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_sqrt: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fsqrt s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -1180,10 +1029,9 @@ define bfloat @test_powi(bfloat %a, i32 %b) #0 { ; CHECK-CVT-LABEL: test_powi: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl __powisf2 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1199,10 +1047,9 @@ define bfloat @test_powi(bfloat %a, i32 %b) #0 { ; CHECK-BF16-LABEL: test_powi: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl __powisf2 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1216,10 +1063,9 @@ define bfloat @test_sin(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_sin: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl sinf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1235,10 +1081,9 @@ define bfloat @test_sin(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_sin: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl sinf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1251,10 +1096,9 @@ define bfloat @test_cos(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_cos: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl cosf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1270,10 +1114,9 @@ define bfloat @test_cos(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_cos: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl cosf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1286,10 +1129,9 @@ define bfloat @test_tan(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_tan: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl tanf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1305,10 +1147,9 @@ define bfloat @test_tan(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_tan: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl tanf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1321,10 +1162,9 @@ define bfloat @test_acos(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_acos: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl acosf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1340,10 +1180,9 @@ define bfloat @test_acos(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_acos: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl acosf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1356,10 +1195,9 @@ define bfloat @test_asin(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_asin: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl asinf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1375,10 +1213,9 @@ define bfloat @test_asin(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_asin: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl asinf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1391,10 +1228,9 @@ define bfloat @test_atan(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_atan: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl atanf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1410,10 +1246,9 @@ define bfloat @test_atan(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_atan: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl atanf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1426,14 +1261,12 @@ define bfloat @test_atan2(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_atan2: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-CVT-NEXT: bl atan2f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1449,14 +1282,12 @@ define bfloat @test_atan2(bfloat %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_atan2: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-BF16-NEXT: bl atan2f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1469,10 +1300,9 @@ define bfloat @test_cosh(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_cosh: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl coshf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1488,10 +1318,9 @@ define bfloat @test_cosh(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_cosh: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl coshf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1504,10 +1333,9 @@ define bfloat @test_sinh(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_sinh: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl sinhf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1523,10 +1351,9 @@ define bfloat @test_sinh(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_sinh: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl sinhf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1539,10 +1366,9 @@ define bfloat @test_tanh(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_tanh: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl tanhf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1558,10 +1384,9 @@ define bfloat @test_tanh(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_tanh: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl tanhf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1574,14 +1399,12 @@ define bfloat @test_pow(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_pow: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-CVT-NEXT: bl powf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1597,14 +1420,12 @@ define bfloat @test_pow(bfloat %a, bfloat %b) #0 { ; CHECK-BF16-LABEL: test_pow: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 +; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 killed $q1 ; CHECK-BF16-NEXT: bl powf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1617,10 +1438,9 @@ define bfloat @test_exp(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_exp: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl expf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1636,10 +1456,9 @@ define bfloat @test_exp(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_exp: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl expf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1652,10 +1471,9 @@ define bfloat @test_exp2(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_exp2: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl exp2f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1671,10 +1489,9 @@ define bfloat @test_exp2(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_exp2: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl exp2f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1687,10 +1504,9 @@ define bfloat @test_log(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_log: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl logf ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1706,10 +1522,9 @@ define bfloat @test_log(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_log: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl logf ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1722,10 +1537,9 @@ define bfloat @test_log10(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_log10: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl log10f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1741,10 +1555,9 @@ define bfloat @test_log10(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_log10: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl log10f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1757,10 +1570,9 @@ define bfloat @test_log2(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_log2: ; CHECK-CVT: // %bb.0: ; CHECK-CVT-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: bl log2f ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff @@ -1776,10 +1588,9 @@ define bfloat @test_log2(bfloat %a) #0 { ; CHECK-BF16-LABEL: test_log2: ; CHECK-BF16: // %bb.0: ; CHECK-BF16-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: bl log2f ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -1791,20 +1602,14 @@ define bfloat @test_log2(bfloat %a) #0 { define bfloat @test_fma(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-CVT-LABEL: test_fma: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s2 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmov s2, w10 +; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w10, #32767 // =0x7fff -; CHECK-CVT-NEXT: fmadd s0, s2, s1, s0 +; CHECK-CVT-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmadd s0, s0, s1, s2 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 ; CHECK-CVT-NEXT: add w8, w8, w10 @@ -1816,19 +1621,13 @@ define bfloat @test_fma(bfloat %a, bfloat %b, bfloat %c) #0 { ; ; CHECK-BF16-LABEL: test_fma: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s2 -; CHECK-BF16-NEXT: fmov w9, s1 -; CHECK-BF16-NEXT: fmov w10, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: lsl w10, w10, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmov s2, w10 -; CHECK-BF16-NEXT: fmadd s0, s2, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmadd s0, s0, s1, s2 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.fma.f16(bfloat %a, bfloat %b, bfloat %c) @@ -1851,16 +1650,12 @@ define bfloat @test_fabs(bfloat %a) #0 { define bfloat @test_minnum(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_minnum: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fminnm s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fminnm s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -1872,15 +1667,11 @@ define bfloat @test_minnum(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_minnum: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fminnm s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fminnm s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.minnum.f16(bfloat %a, bfloat %b) @@ -1890,16 +1681,12 @@ define bfloat @test_minnum(bfloat %a, bfloat %b) #0 { define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_maxnum: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s1 -; CHECK-CVT-NEXT: fmov w10, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: lsl w10, w10, #16 -; CHECK-CVT-NEXT: fmov s0, w9 -; CHECK-CVT-NEXT: fmov s1, w10 -; CHECK-CVT-NEXT: fmaxnm s0, s1, s0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmaxnm s0, s0, s1 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 ; CHECK-CVT-NEXT: add w8, w9, w8 @@ -1911,15 +1698,11 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_maxnum: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmaxnm s0, s1, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmaxnm s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.maxnum.f16(bfloat %a, bfloat %b) @@ -1929,16 +1712,12 @@ define bfloat @test_maxnum(bfloat %a, bfloat %b) #0 { define bfloat @test_copysign(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_copysign: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 ; CHECK-CVT-NEXT: fmov s0, w8 @@ -1947,16 +1726,12 @@ define bfloat @test_copysign(bfloat %a, bfloat %b) #0 { ; ; CHECK-BF16-LABEL: test_copysign: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.copysign.f16(bfloat %a, bfloat %b) @@ -1966,12 +1741,10 @@ define bfloat @test_copysign(bfloat %a, bfloat %b) #0 { define bfloat @test_copysign_f32(bfloat %a, float %b) #0 { ; CHECK-CVT-LABEL: test_copysign_f32: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 ; CHECK-CVT-NEXT: // kill: def $s1 killed $s1 def $q1 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 @@ -1981,12 +1754,10 @@ define bfloat @test_copysign_f32(bfloat %a, float %b) #0 { ; ; CHECK-BF16-LABEL: test_copysign_f32: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 ; CHECK-BF16-NEXT: // kill: def $s1 killed $s1 def $q1 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -1998,12 +1769,10 @@ define bfloat @test_copysign_f32(bfloat %a, float %b) #0 { define bfloat @test_copysign_f64(bfloat %a, double %b) #0 { ; CHECK-CVT-LABEL: test_copysign_f64: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: fcvt s1, d1 ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 @@ -2013,12 +1782,10 @@ define bfloat @test_copysign_f64(bfloat %a, double %b) #0 { ; ; CHECK-BF16-LABEL: test_copysign_f64: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-BF16-NEXT: fcvt s1, d1 ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2032,34 +1799,33 @@ define bfloat @test_copysign_f64(bfloat %a, double %b) #0 { define float @test_copysign_extended(bfloat %a, bfloat %b) #0 { ; CHECK-CVT-LABEL: test_copysign_extended: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-CVT-NEXT: movi v2.4s, #16 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: ushll v0.4s, v0.4h, #0 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-CVT-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-CVT-NEXT: bif v0.16b, v1.16b, v2.16b ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: lsr w8, w8, #16 -; CHECK-CVT-NEXT: lsl w8, w8, #16 ; CHECK-CVT-NEXT: fmov s0, w8 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-CVT-NEXT: ret ; ; CHECK-BF16-LABEL: test_copysign_extended: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: movi v2.4s, #16 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: ushll v0.4s, v0.4h, #0 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: ushl v0.4s, v0.4s, v2.4s ; CHECK-BF16-NEXT: mvni v2.4s, #128, lsl #24 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: bit v0.16b, v1.16b, v2.16b +; CHECK-BF16-NEXT: bif v0.16b, v1.16b, v2.16b +; CHECK-BF16-NEXT: bfcvt h0, s0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: // kill: def $s0 killed $s0 killed $q0 ; CHECK-BF16-NEXT: ret %r = call bfloat @llvm.copysign.f16(bfloat %a, bfloat %b) @@ -2070,11 +1836,9 @@ define float @test_copysign_extended(bfloat %a, bfloat %b) #0 { define bfloat @test_floor(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_floor: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintm s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2087,10 +1851,8 @@ define bfloat @test_floor(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_floor: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintm s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2101,11 +1863,9 @@ define bfloat @test_floor(bfloat %a) #0 { define bfloat @test_ceil(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_ceil: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintp s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2118,10 +1878,8 @@ define bfloat @test_ceil(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_ceil: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintp s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2132,11 +1890,9 @@ define bfloat @test_ceil(bfloat %a) #0 { define bfloat @test_trunc(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_trunc: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintz s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2149,10 +1905,8 @@ define bfloat @test_trunc(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_trunc: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintz s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2163,11 +1917,9 @@ define bfloat @test_trunc(bfloat %a) #0 { define bfloat @test_rint(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_rint: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintx s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2180,10 +1932,8 @@ define bfloat @test_rint(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_rint: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintx s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2194,11 +1944,9 @@ define bfloat @test_rint(bfloat %a) #0 { define bfloat @test_nearbyint(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_nearbyint: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frinti s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2211,10 +1959,8 @@ define bfloat @test_nearbyint(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_nearbyint: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frinti s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2225,11 +1971,9 @@ define bfloat @test_nearbyint(bfloat %a) #0 { define bfloat @test_round(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_round: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frinta s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2242,10 +1986,8 @@ define bfloat @test_round(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_round: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frinta s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2256,11 +1998,9 @@ define bfloat @test_round(bfloat %a) #0 { define bfloat @test_roundeven(bfloat %a) #0 { ; CHECK-CVT-LABEL: test_roundeven: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w8, #32767 // =0x7fff -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: frintn s0, s0 ; CHECK-CVT-NEXT: fmov w9, s0 ; CHECK-CVT-NEXT: ubfx w10, w9, #16, #1 @@ -2273,10 +2013,8 @@ define bfloat @test_roundeven(bfloat %a) #0 { ; ; CHECK-BF16-LABEL: test_roundeven: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: frintn s0, s0 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret @@ -2287,27 +2025,21 @@ define bfloat @test_roundeven(bfloat %a) #0 { define bfloat @test_fmuladd(bfloat %a, bfloat %b, bfloat %c) #0 { ; CHECK-CVT-LABEL: test_fmuladd: ; CHECK-CVT: // %bb.0: -; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-CVT-NEXT: fmov w8, s1 -; CHECK-CVT-NEXT: fmov w9, s0 +; CHECK-CVT-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-CVT-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-CVT-NEXT: mov w10, #32767 // =0x7fff -; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 -; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 -; CHECK-CVT-NEXT: fmul s0, s1, s0 +; CHECK-CVT-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-CVT-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-CVT-NEXT: fmul s0, s0, s1 +; CHECK-CVT-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 ; CHECK-CVT-NEXT: add w8, w8, w10 ; CHECK-CVT-NEXT: add w8, w9, w8 -; CHECK-CVT-NEXT: fmov w9, s2 ; CHECK-CVT-NEXT: lsr w8, w8, #16 -; CHECK-CVT-NEXT: lsl w8, w8, #16 -; CHECK-CVT-NEXT: lsl w9, w9, #16 ; CHECK-CVT-NEXT: fmov s0, w8 -; CHECK-CVT-NEXT: fmov s1, w9 +; CHECK-CVT-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-CVT-NEXT: fadd s0, s0, s1 ; CHECK-CVT-NEXT: fmov w8, s0 ; CHECK-CVT-NEXT: ubfx w9, w8, #16, #1 @@ -2320,23 +2052,15 @@ define bfloat @test_fmuladd(bfloat %a, bfloat %b, bfloat %c) #0 { ; ; CHECK-BF16-LABEL: test_fmuladd: ; CHECK-BF16: // %bb.0: -; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $s1 -; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-BF16-NEXT: fmov w8, s1 -; CHECK-BF16-NEXT: fmov w9, s0 -; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $s2 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s0, w8 -; CHECK-BF16-NEXT: fmov s1, w9 -; CHECK-BF16-NEXT: fmov w9, s2 -; CHECK-BF16-NEXT: fmul s0, s1, s0 -; CHECK-BF16-NEXT: lsl w9, w9, #16 -; CHECK-BF16-NEXT: fmov s1, w9 +; CHECK-BF16-NEXT: // kill: def $h1 killed $h1 def $d1 +; CHECK-BF16-NEXT: // kill: def $h0 killed $h0 def $d0 +; CHECK-BF16-NEXT: // kill: def $h2 killed $h2 def $d2 +; CHECK-BF16-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 +; CHECK-BF16-NEXT: fmul s0, s0, s1 +; CHECK-BF16-NEXT: shll v1.4s, v2.4h, #16 ; CHECK-BF16-NEXT: bfcvt h0, s0 -; CHECK-BF16-NEXT: fmov w8, s0 -; CHECK-BF16-NEXT: lsl w8, w8, #16 -; CHECK-BF16-NEXT: fmov s0, w8 +; CHECK-BF16-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-BF16-NEXT: fadd s0, s0, s1 ; CHECK-BF16-NEXT: bfcvt h0, s0 ; CHECK-BF16-NEXT: ret diff --git a/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll index c03e2e532132..a609e33be935 100644 --- a/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll +++ b/llvm/test/CodeGen/AArch64/bf16-v8-instructions.ll @@ -272,9 +272,8 @@ define <8 x bfloat> @d_to_h(<8 x double> %a) { define <8 x float> @h_to_s(<8 x bfloat> %a) { ; CHECK-LABEL: h_to_s: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: ret %1 = fpext <8 x bfloat> %a to <8 x float> ret <8 x float> %1 @@ -283,13 +282,12 @@ define <8 x float> @h_to_s(<8 x bfloat> %a) { define <8 x double> @h_to_d(<8 x bfloat> %a) { ; CHECK-LABEL: h_to_d: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: shll v2.4s, v0.4h, #16 -; CHECK-NEXT: fcvtl v0.2d, v2.2s -; CHECK-NEXT: shll v4.4s, v1.4h, #16 -; CHECK-NEXT: fcvtl2 v1.2d, v2.4s -; CHECK-NEXT: fcvtl2 v3.2d, v4.4s -; CHECK-NEXT: fcvtl v2.2d, v4.2s +; CHECK-NEXT: shll v1.4s, v0.4h, #16 +; CHECK-NEXT: shll2 v2.4s, v0.8h, #16 +; CHECK-NEXT: fcvtl v0.2d, v1.2s +; CHECK-NEXT: fcvtl2 v3.2d, v2.4s +; CHECK-NEXT: fcvtl2 v1.2d, v1.4s +; CHECK-NEXT: fcvtl v2.2d, v2.2s ; CHECK-NEXT: ret %1 = fpext <8 x bfloat> %a to <8 x double> ret <8 x double> %1 @@ -788,11 +786,10 @@ define void @test_insert_at_zero(bfloat %a, ptr %b) #0 { define <8 x i8> @fptosi_i8(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptosi_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzs v1.4s, v1.4s +; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: xtn v0.8b, v0.8h ; CHECK-NEXT: ret @@ -803,11 +800,10 @@ define <8 x i8> @fptosi_i8(<8 x bfloat> %a) #0 { define <8 x i16> @fptosi_i16(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptosi_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzs v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzs v1.4s, v1.4s +; CHECK-NEXT: fcvtzs v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: ret %1 = fptosi<8 x bfloat> %a to <8 x i16> @@ -817,11 +813,10 @@ define <8 x i16> @fptosi_i16(<8 x bfloat> %a) #0 { define <8 x i8> @fptoui_i8(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptoui_i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzu v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzu v1.4s, v1.4s +; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: xtn v0.8b, v0.8h ; CHECK-NEXT: ret @@ -832,11 +827,10 @@ define <8 x i8> @fptoui_i8(<8 x bfloat> %a) #0 { define <8 x i16> @fptoui_i16(<8 x bfloat> %a) #0 { ; CHECK-LABEL: fptoui_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: shll2 v1.4s, v0.8h, #16 ; CHECK-NEXT: shll v0.4s, v0.4h, #16 -; CHECK-NEXT: fcvtzu v0.4s, v0.4s -; CHECK-NEXT: shll v1.4s, v1.4h, #16 ; CHECK-NEXT: fcvtzu v1.4s, v1.4s +; CHECK-NEXT: fcvtzu v0.4s, v0.4s ; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h ; CHECK-NEXT: ret %1 = fptoui<8 x bfloat> %a to <8 x i16> @@ -846,90 +840,58 @@ define <8 x i16> @fptoui_i16(<8 x bfloat> %a) #0 { define <8 x i1> @test_fcmp_une(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_une: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, ne -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, ne -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, ne +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, ne -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, ne ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -941,96 +903,64 @@ define <8 x i1> @test_fcmp_une(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ueq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ueq: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: lsl w9, w11, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s7, w9 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: csetm w10, eq -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csinv w10, w10, wzr, vc -; CHECK-NEXT: fcmp s7, s6 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w11, s4 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h4, v0.h[4] -; CHECK-NEXT: mov h7, v1.h[5] +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 +; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: csinv w8, w8, wzr, vc +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] ; CHECK-NEXT: csetm w9, eq ; CHECK-NEXT: csinv w9, w9, wzr, vc -; CHECK-NEXT: fcmp s3, s2 -; CHECK-NEXT: mov h3, v1.h[4] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 ; CHECK-NEXT: fmov s2, w9 -; CHECK-NEXT: lsl w11, w11, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s5, w11 -; CHECK-NEXT: fmov s6, w8 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, eq -; CHECK-NEXT: mov v2.h[1], w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csinv w8, w8, wzr, vc -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov s6, w10 ; CHECK-NEXT: csetm w8, eq -; CHECK-NEXT: fmov w9, s7 -; CHECK-NEXT: fmov w10, s5 ; CHECK-NEXT: csinv w8, w8, wzr, vc -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: fmov s6, w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csinv w8, w8, wzr, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: lsl w8, w9, #16 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: csetm w10, eq -; CHECK-NEXT: csinv w10, w10, wzr, vc -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csinv w8, w8, wzr, vc -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: csinv w8, w8, wzr, vc +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: csinv w8, w8, wzr, vc @@ -1044,90 +974,58 @@ define <8 x i1> @test_fcmp_ueq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ugt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ugt: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, hi -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, hi -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, hi +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, hi -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, hi +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, hi ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1139,90 +1037,58 @@ define <8 x i1> @test_fcmp_ugt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_uge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_uge: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, pl -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, pl -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, pl +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, pl -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, pl +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, pl ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1234,90 +1100,58 @@ define <8 x i1> @test_fcmp_uge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ult(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ult: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, lt -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, lt -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, lt +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, lt -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, lt +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, lt ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1329,90 +1163,58 @@ define <8 x i1> @test_fcmp_ult(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ule(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ule: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, le -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, le -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, le +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, le -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, le +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, le ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1424,90 +1226,58 @@ define <8 x i1> @test_fcmp_ule(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_uno(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_uno: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, vs -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, vs -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, vs +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, vs -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, vs +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, vs ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1519,96 +1289,64 @@ define <8 x i1> @test_fcmp_uno(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_one(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_one: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: lsl w9, w11, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s7, w9 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: csetm w10, mi -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csinv w10, w10, wzr, le -; CHECK-NEXT: fcmp s7, s6 -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w11, s4 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h4, v0.h[4] -; CHECK-NEXT: mov h7, v1.h[5] +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 +; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: csinv w8, w8, wzr, le +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] ; CHECK-NEXT: csetm w9, mi ; CHECK-NEXT: csinv w9, w9, wzr, le -; CHECK-NEXT: fcmp s3, s2 -; CHECK-NEXT: mov h3, v1.h[4] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 ; CHECK-NEXT: fmov s2, w9 -; CHECK-NEXT: lsl w11, w11, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov s5, w11 -; CHECK-NEXT: fmov s6, w8 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, mi -; CHECK-NEXT: mov v2.h[1], w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csinv w8, w8, wzr, le -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov s6, w10 ; CHECK-NEXT: csetm w8, mi -; CHECK-NEXT: fmov w9, s7 -; CHECK-NEXT: fmov w10, s5 ; CHECK-NEXT: csinv w8, w8, wzr, le -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: fmov s6, w10 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: fmov w10, s4 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: csinv w8, w8, wzr, le +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: lsl w8, w9, #16 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: csetm w10, mi -; CHECK-NEXT: csinv w10, w10, wzr, le -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: csinv w8, w8, wzr, le -; CHECK-NEXT: fcmp s1, s0 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: csinv w8, w8, wzr, le +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: csinv w8, w8, wzr, le @@ -1622,90 +1360,58 @@ define <8 x i1> @test_fcmp_one(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_oeq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_oeq: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, eq -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, eq -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, eq +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, eq -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, eq +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, eq ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1717,90 +1423,58 @@ define <8 x i1> @test_fcmp_oeq(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ogt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ogt: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, gt -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, gt -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, gt +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, gt -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, gt +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, gt ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1812,90 +1486,58 @@ define <8 x i1> @test_fcmp_ogt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_oge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_oge: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, ge -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, ge -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, ge +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, ge -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, ge +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, ge ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -1907,90 +1549,58 @@ define <8 x i1> @test_fcmp_oge(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_olt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_olt: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, mi -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, mi -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, mi +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, mi -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, mi +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, mi ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -2002,90 +1612,58 @@ define <8 x i1> @test_fcmp_olt(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ole(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ole: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, ls -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, ls -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, ls +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, ls -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, ls +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, ls ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h @@ -2097,90 +1675,58 @@ define <8 x i1> @test_fcmp_ole(<8 x bfloat> %a, <8 x bfloat> %b) #0 { define <8 x i1> @test_fcmp_ord(<8 x bfloat> %a, <8 x bfloat> %b) #0 { ; CHECK-LABEL: test_fcmp_ord: ; CHECK: // %bb.0: -; CHECK-NEXT: mov h2, v1.h[1] -; CHECK-NEXT: mov h3, v0.h[1] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: fmov w9, s3 -; CHECK-NEXT: mov h2, v1.h[2] -; CHECK-NEXT: mov h3, v0.h[2] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov h3, v1.h[4] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s5, s4 -; CHECK-NEXT: fmov s5, w9 -; CHECK-NEXT: mov h4, v1.h[3] -; CHECK-NEXT: lsl w10, w10, #16 -; CHECK-NEXT: fmov s6, w8 -; CHECK-NEXT: fmov w8, s2 -; CHECK-NEXT: csetm w9, vc -; CHECK-NEXT: fmov s16, w10 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: mov h5, v0.h[3] -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: mov h6, v0.h[4] -; CHECK-NEXT: mov h4, v1.h[5] -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: dup v2.4h, v1.h[1] +; CHECK-NEXT: dup v3.4h, v0.h[1] +; CHECK-NEXT: dup v4.4h, v1.h[2] +; CHECK-NEXT: dup v5.4h, v0.h[2] +; CHECK-NEXT: dup v6.4h, v0.h[3] +; CHECK-NEXT: shll v2.4s, v2.4h, #16 +; CHECK-NEXT: shll v3.4s, v3.4h, #16 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v2.4s, v1.4h, #16 +; CHECK-NEXT: shll v3.4s, v0.4h, #16 ; CHECK-NEXT: csetm w8, vc -; CHECK-NEXT: fmov s2, w8 -; CHECK-NEXT: fmov w8, s5 -; CHECK-NEXT: mov h5, v0.h[5] -; CHECK-NEXT: fcmp s16, s7 -; CHECK-NEXT: mov v2.h[1], w9 -; CHECK-NEXT: lsl w9, w10, #16 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: fmov s3, w9 -; CHECK-NEXT: fmov w9, s6 -; CHECK-NEXT: fmov s7, w8 +; CHECK-NEXT: fcmp s3, s2 +; CHECK-NEXT: shll v3.4s, v4.4h, #16 +; CHECK-NEXT: shll v4.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.4h, v1.h[3] +; CHECK-NEXT: csetm w9, vc +; CHECK-NEXT: fmov s2, w9 +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[4] +; CHECK-NEXT: dup v6.8h, v0.h[4] +; CHECK-NEXT: mov v2.h[1], w8 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[5] +; CHECK-NEXT: dup v6.8h, v0.h[5] ; CHECK-NEXT: mov v2.h[2], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fmov w10, s4 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fcmp s7, s3 -; CHECK-NEXT: mov h3, v1.h[6] -; CHECK-NEXT: fmov s4, w8 -; CHECK-NEXT: mov h1, v1.h[7] -; CHECK-NEXT: fmov s6, w9 -; CHECK-NEXT: fmov w9, s5 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: dup v5.8h, v1.h[6] +; CHECK-NEXT: dup v6.8h, v0.h[6] +; CHECK-NEXT: dup v1.8h, v1.h[7] +; CHECK-NEXT: dup v0.8h, v0.h[7] ; CHECK-NEXT: mov v2.h[3], w8 -; CHECK-NEXT: lsl w8, w10, #16 -; CHECK-NEXT: fcmp s6, s4 -; CHECK-NEXT: mov h4, v0.h[6] -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s5, w8 -; CHECK-NEXT: mov h0, v0.h[7] -; CHECK-NEXT: fmov s6, w9 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: shll v3.4s, v5.4h, #16 +; CHECK-NEXT: shll v4.4s, v6.4h, #16 +; CHECK-NEXT: shll v1.4s, v1.4h, #16 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: mov v2.h[4], w8 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w9, s4 -; CHECK-NEXT: fcmp s6, s5 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: csetm w10, vc -; CHECK-NEXT: fmov s3, w8 -; CHECK-NEXT: fmov s4, w9 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: mov v2.h[5], w10 -; CHECK-NEXT: lsl w8, w8, #16 -; CHECK-NEXT: fcmp s4, s3 -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w8 -; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s4, s3 +; CHECK-NEXT: mov v2.h[5], w8 +; CHECK-NEXT: csetm w8, vc +; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: mov v2.h[6], w8 -; CHECK-NEXT: fcmp s1, s0 ; CHECK-NEXT: csetm w8, vc ; CHECK-NEXT: mov v2.h[7], w8 ; CHECK-NEXT: xtn v0.8b, v2.8h diff --git a/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll b/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll index 40684b0f3a25..e3263252875f 100644 --- a/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll +++ b/llvm/test/CodeGen/AArch64/cvt-fp-int-fp.ll @@ -76,11 +76,9 @@ entry: define bfloat @t7(bfloat %x) { ; CHECK-LABEL: t7: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w9, s0 ; CHECK-NEXT: scvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 @@ -101,11 +99,9 @@ entry: define bfloat @t8(bfloat %x) { ; CHECK-LABEL: t8: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu w9, s0 ; CHECK-NEXT: ucvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 @@ -198,11 +194,9 @@ entry: define bfloat @t7_strict(bfloat %x) #0 { ; CHECK-LABEL: t7_strict: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w9, s0 ; CHECK-NEXT: scvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 @@ -223,11 +217,9 @@ entry: define bfloat @t8_strict(bfloat %x) #0 { ; CHECK-LABEL: t8_strict: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzu w9, s0 ; CHECK-NEXT: ucvtf d0, w9 ; CHECK-NEXT: fcvtxn s0, d0 diff --git a/llvm/test/CodeGen/AArch64/hwasan-zero-ptr.ll b/llvm/test/CodeGen/AArch64/hwasan-zero-ptr.ll new file mode 100644 index 000000000000..dca39fe03fb1 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/hwasan-zero-ptr.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -filetype asm -o - %s | FileCheck %s + +; This shows that when dereferencing a null pointer, HWASan will call +; __hwasan_check_x4294967071_19_fixed_0_short_v2 +; (N.B. 4294967071 == 2**32 - 239 + 14 == 2**32 - X0 + XZR +; +; The source was generated from llvm/test/Instrumentation/HWAddressSanitizer/zero-ptr.ll. + +; ModuleID = '<stdin>' +source_filename = "<stdin>" +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android10000" + +$hwasan.module_ctor = comdat any + +@__start_hwasan_globals = external hidden constant [0 x i8] +@__stop_hwasan_globals = external hidden constant [0 x i8] +@hwasan.note = private constant { i32, i32, i32, [8 x i8], i32, i32 } { i32 8, i32 8, i32 3, [8 x i8] c"LLVM\00\00\00\00", i32 trunc (i64 sub (i64 ptrtoint (ptr @__start_hwasan_globals to i64), i64 ptrtoint (ptr @hwasan.note to i64)) to i32), i32 trunc (i64 sub (i64 ptrtoint (ptr @__stop_hwasan_globals to i64), i64 ptrtoint (ptr @hwasan.note to i64)) to i32) }, section ".note.hwasan.globals", comdat($hwasan.module_ctor), align 4 + +; Function Attrs: sanitize_hwaddress +define void @test_store_to_zeroptr() #0 { +; CHECK-LABEL: test_store_to_zeroptr: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -16 +; CHECK-NEXT: bl __hwasan_check_x4294967071_19_fixed_0_short_v2 +; CHECK-NEXT: mov x8, xzr +; CHECK-NEXT: mov w9, #42 // =0x2a +; CHECK-NEXT: str x9, [x8] +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +entry: + %.hwasan.shadow = call ptr asm "", "=r,0"(ptr null) + %b = inttoptr i64 0 to ptr + call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr %b, i32 19, i64 0) + store i64 42, ptr %b, align 8 + ret void +} + +; Function Attrs: nounwind +declare void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr, i32 immarg, i64 immarg) #1 + +attributes #0 = { sanitize_hwaddress } +attributes #1 = { nounwind } + +declare void @__hwasan_init() + +; Function Attrs: nounwind +define internal void @hwasan.module_ctor() #1 comdat { +; CHECK-LABEL: hwasan.module_ctor: +; CHECK: // %bb.0: +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: bl __hwasan_init +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret + call void @__hwasan_init() + ret void +} + +!llvm.module.flags = !{!1} + +!0 = !{ptr @hwasan.note} +!1 = !{i32 4, !"nosanitize_hwaddress", i32 1} diff --git a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir index b61fa4be0400..08fc47d9480c 100644 --- a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir +++ b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir @@ -1,5 +1,5 @@ +# RUN: llc -mtriple=aarch64 -o /dev/null -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking -debug-only=regalloc %s 2>&1 | FileCheck %s --check-prefix=CHECK-DBG # RUN: llc -mtriple=aarch64 -verify-machineinstrs -o - -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking %s | FileCheck %s --check-prefix=CHECK -# RUN: llc -mtriple=aarch64 -verify-machineinstrs -o /dev/null -run-pass=register-coalescer -aarch64-enable-subreg-liveness-tracking -debug-only=regalloc %s 2>&1 | FileCheck %s --check-prefix=CHECK-DBG # REQUIRES: asserts # CHECK-DBG: ********** REGISTER COALESCER ********** @@ -36,3 +36,94 @@ body: | RET_ReallyLR ... +# CHECK-DBG: ********** REGISTER COALESCER ********** +# CHECK-DBG: ********** Function: reproducer +# CHECK-DBG: ********** JOINING INTERVALS *********** +# CHECK-DBG: ********** INTERVALS ********** +# CHECK-DBG: %1 [32r,48B:2)[48B,320r:0)[320r,368B:1) 0@48B-phi 1@320r 2@32r +# CHECK-DBG-SAME: weight:0.000000e+00 +# CHECK-DBG: %3 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0@288r 1@240r 2@80r 3@304B-phi +# CHECK-DBG-SAME: L0000000000000080 [288r,304B:0)[304B,320r:3) 0@288r 1@x 2@x 3@304B-phi +# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0@288r 1@240r 2@80r 3@304B-phi +# CHECK-DBG-SAME: weight:0.000000e+00 +--- +name: reproducer +tracksRegLiveness: true +body: | + bb.0: + %0:gpr32 = MOVi32imm 1 + %1:gpr64 = IMPLICIT_DEF + + bb.1: + + bb.2: + %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + + bb.3: + $nzcv = IMPLICIT_DEF + %4:gpr64 = COPY killed %3 + Bcc 1, %bb.7, implicit killed $nzcv + + bb.4: + $nzcv = IMPLICIT_DEF + Bcc 1, %bb.6, implicit killed $nzcv + + bb.5: + %5:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + %4:gpr64 = COPY killed %5 + B %bb.7 + + bb.6: + %4:gpr64 = COPY $xzr + + bb.7: + %7:gpr64 = ADDXrs killed %1, killed %4, 1 + %1:gpr64 = COPY killed %7 + B %bb.1 + +... +# CHECK-DBG: ********** REGISTER COALESCER ********** +# CHECK-DBG: ********** Function: reproducer2 +# CHECK-DBG: ********** JOINING INTERVALS *********** +# CHECK-DBG: ********** INTERVALS ********** +# CHECK-DBG: %1 [32r,48B:2)[48B,304r:0)[304r,352B:1) 0@48B-phi 1@304r 2@32r +# CHECK-DBG-SAME: weight:0.000000e+00 +# CHECK-DBG: %3 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@80r 3@288B-phi +# CHECK-DBG-SAME: L0000000000000080 [224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@x 3@288B-phi +# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0@272r 1@224r 2@80r 3@288B-phi +# CHECK-DBG-SAME: weight:0.000000e+00 +--- +name: reproducer2 +tracksRegLiveness: true +body: | + bb.0: + %0:gpr32 = MOVi32imm 1 + %1:gpr64 = IMPLICIT_DEF + + bb.1: + + bb.2: + %3:gpr64all = SUBREG_TO_REG 0, %0, %subreg.sub_32 + + bb.3: + $nzcv = IMPLICIT_DEF + %4:gpr64 = COPY killed %3 + Bcc 1, %bb.7, implicit killed $nzcv + + bb.4: + $nzcv = IMPLICIT_DEF + Bcc 1, %bb.6, implicit killed $nzcv + + bb.5: + %4:gpr64 = IMPLICIT_DEF + B %bb.7 + + bb.6: + %4:gpr64 = COPY $xzr + + bb.7: + %5:gpr64 = ADDXrs killed %1, killed %4, 1 + %1:gpr64 = COPY killed %5 + B %bb.1 + +... diff --git a/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll b/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll index ec7548e1e654..b7fae2bff687 100644 --- a/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll +++ b/llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll @@ -7,19 +7,17 @@ define i32 @testmswbf(bfloat %a) { ; CHECK-LABEL: testmswbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintm s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret entry: @@ -31,19 +29,17 @@ entry: define i64 @testmsxbf(bfloat %a) { ; CHECK-LABEL: testmsxbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintm s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs x0, s0 ; CHECK-NEXT: ret entry: @@ -141,19 +137,17 @@ entry: define i32 @testpswbf(bfloat %a) { ; CHECK-LABEL: testpswbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintp s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs w0, s0 ; CHECK-NEXT: ret entry: @@ -165,19 +159,17 @@ entry: define i64 @testpsxbf(bfloat %a) { ; CHECK-LABEL: testpsxbf: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0 -; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0 ; CHECK-NEXT: mov w8, #32767 // =0x7fff -; CHECK-NEXT: lsl w9, w9, #16 -; CHECK-NEXT: fmov s0, w9 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: frintp s0, s0 ; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: ubfx w10, w9, #16, #1 ; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w10, w8 ; CHECK-NEXT: lsr w8, w8, #16 -; CHECK-NEXT: lsl w8, w8, #16 ; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: shll v0.4s, v0.4h, #16 ; CHECK-NEXT: fcvtzs x0, s0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/sme-intrinsics-state.ll b/llvm/test/CodeGen/AArch64/sme-intrinsics-state.ll new file mode 100644 index 000000000000..5037772a51ce --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme-intrinsics-state.ll @@ -0,0 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s + + +define i1 @streaming_mode_streaming_compatible() #0 { +; CHECK-LABEL: streaming_mode_streaming_compatible: +; CHECK: // %bb.0: +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: bl __arm_sme_state +; CHECK-NEXT: and w0, w0, #0x1 +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret + %mode = tail call noundef i1 @llvm.aarch64.sme.in.streaming.mode() + ret i1 %mode +} + + +attributes #0 = {nounwind memory(none) "aarch64_pstate_sm_compatible"} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll index b0f2aac9a42d..7cafa2f608a4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll @@ -3990,6 +3990,116 @@ bb: ret void } +define amdgpu_gs void @sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset(ptr addrspace(5) inreg %sgpr_base, i32 inreg %sidx, i32 %vidx) { +; GFX9-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX9: ; %bb.0: ; %bb +; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s5 +; GFX9-NEXT: v_add_u32_e32 v0, s3, v0 +; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 +; GFX9-NEXT: v_add3_u32 v0, s2, v0, -16 +; GFX9-NEXT: v_mov_b32_e32 v1, 15 +; GFX9-NEXT: scratch_store_dword v0, v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX10: ; %bb.0: ; %bb +; GFX10-NEXT: s_add_u32 s0, s0, s5 +; GFX10-NEXT: s_addc_u32 s1, s1, 0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 +; GFX10-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX10-NEXT: v_mov_b32_e32 v1, 15 +; GFX10-NEXT: v_add_nc_u32_e32 v0, s2, v0 +; GFX10-NEXT: scratch_store_dword v0, v1, off offset:-16 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX940-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX940: ; %bb.0: ; %bb +; GFX940-NEXT: v_add_u32_e32 v0, s1, v0 +; GFX940-NEXT: v_add3_u32 v0, s0, v0, -16 +; GFX940-NEXT: v_mov_b32_e32 v1, 15 +; GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1 +; GFX940-NEXT: s_waitcnt vmcnt(0) +; GFX940-NEXT: s_endpgm +; +; GFX11-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX11: ; %bb.0: ; %bb +; GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX12: ; %bb.0: ; %bb +; GFX12-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; GFX12-NEXT: scratch_store_b32 v0, v1, off offset:-16 scope:SCOPE_SYS +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm +; +; UNALIGNED_GFX9-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX9: ; %bb.0: ; %bb +; UNALIGNED_GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s5 +; UNALIGNED_GFX9-NEXT: v_add_u32_e32 v0, s3, v0 +; UNALIGNED_GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 +; UNALIGNED_GFX9-NEXT: v_add3_u32 v0, s2, v0, -16 +; UNALIGNED_GFX9-NEXT: v_mov_b32_e32 v1, 15 +; UNALIGNED_GFX9-NEXT: scratch_store_dword v0, v1, off +; UNALIGNED_GFX9-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX9-NEXT: s_endpgm +; +; UNALIGNED_GFX10-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX10: ; %bb.0: ; %bb +; UNALIGNED_GFX10-NEXT: s_add_u32 s0, s0, s5 +; UNALIGNED_GFX10-NEXT: s_addc_u32 s1, s1, 0 +; UNALIGNED_GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 +; UNALIGNED_GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 +; UNALIGNED_GFX10-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; UNALIGNED_GFX10-NEXT: v_mov_b32_e32 v1, 15 +; UNALIGNED_GFX10-NEXT: v_add_nc_u32_e32 v0, s2, v0 +; UNALIGNED_GFX10-NEXT: scratch_store_dword v0, v1, off offset:-16 +; UNALIGNED_GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX10-NEXT: s_endpgm +; +; UNALIGNED_GFX940-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX940: ; %bb.0: ; %bb +; UNALIGNED_GFX940-NEXT: v_add_u32_e32 v0, s1, v0 +; UNALIGNED_GFX940-NEXT: v_add3_u32 v0, s0, v0, -16 +; UNALIGNED_GFX940-NEXT: v_mov_b32_e32 v1, 15 +; UNALIGNED_GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1 +; UNALIGNED_GFX940-NEXT: s_waitcnt vmcnt(0) +; UNALIGNED_GFX940-NEXT: s_endpgm +; +; UNALIGNED_GFX11-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX11: ; %bb.0: ; %bb +; UNALIGNED_GFX11-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; UNALIGNED_GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; UNALIGNED_GFX11-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; UNALIGNED_GFX11-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; UNALIGNED_GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; UNALIGNED_GFX11-NEXT: s_endpgm +; +; UNALIGNED_GFX12-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; UNALIGNED_GFX12: ; %bb.0: ; %bb +; UNALIGNED_GFX12-NEXT: v_dual_mov_b32 v1, 15 :: v_dual_add_nc_u32 v0, s1, v0 +; UNALIGNED_GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; UNALIGNED_GFX12-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; UNALIGNED_GFX12-NEXT: scratch_store_b32 v0, v1, off offset:-16 scope:SCOPE_SYS +; UNALIGNED_GFX12-NEXT: s_wait_storecnt 0x0 +; UNALIGNED_GFX12-NEXT: s_endpgm +bb: + %add1 = add nsw i32 %sidx, %vidx + %add2 = add nsw i32 %add1, -16 + %gep = getelementptr inbounds [16 x i8], ptr addrspace(5) %sgpr_base, i32 0, i32 %add2 + store volatile i32 15, ptr addrspace(5) %gep, align 4 + ret void +} + define amdgpu_gs void @sgpr_base_negative_offset(ptr addrspace(1) %out, ptr addrspace(5) inreg %scevgep) { ; GFX9-LABEL: sgpr_base_negative_offset: ; GFX9: ; %bb.0: ; %entry diff --git a/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll b/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll new file mode 100644 index 000000000000..52259c4c2e6e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll @@ -0,0 +1,193 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s + +; Reduce a 64-bit add by a constant if we know the low 32-bits are all +; zero. + +; add i64:x, K if computeTrailingZeros(K) >= 32 +; => build_pair (add x.hi, K.hi), x.lo + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0x40000 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_1(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 4294967296 ; (1 << 32) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_2(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 2 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 8589934592 ; (1 << 33) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_3(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0x80000000 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_low_bits_known0_4(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0x40000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_1(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 4294967296 ; (1 << 32) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_2(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 2, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 8589934592 ; (1 << 33) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_3(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %add +} + +define i64 @v_add_i64_const_low_bits_known0_4(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %add +} + +define amdgpu_ps i64 @s_add_i64_const_high_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_add_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_u32 s0, s0, -1 +; GFX9-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-NEXT: ; return to shader part epilog + %add = add i64 %reg, 4294967295 ; (1 << 31) + ret i64 %add +} + +define i64 @v_add_i64_const_high_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_add_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, -1, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add i64 %reg, 4294967295 ; (1 << 31) + ret i64 %add +} + +define <2 x i64> @v_add_v2i64_splat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_add_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, 1, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %add +} + +define <2 x i64> @v_add_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_add_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, 2, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %add = add <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %add +} + +define amdgpu_ps <2 x i64> @s_add_v2i64_splat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_add_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: s_add_i32 s3, s3, 1 +; GFX9-NEXT: ; return to shader part epilog + %add = add <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %add +} + +define amdgpu_ps <2 x i64> @s_add_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_add_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: s_add_i32 s3, s3, 2 +; GFX9-NEXT: ; return to shader part epilog + %add = add <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %add +} + +; We could reduce this to use a 32-bit add if we use computeKnownBits +define i64 @v_add_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) { +; GFX9-LABEL: v_add_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %add = add i64 %reg, %in.high.bits + ret i64 %add +} + +; We could reduce this to use a 32-bit add if we use computeKnownBits +define amdgpu_ps i64 @s_add_i64_variable_high_bits_known0_0(i64 inreg %reg, i32 inreg %offset.hi32) { +; GFX9-LABEL: s_add_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_u32 s0, s0, 0 +; GFX9-NEXT: s_addc_u32 s1, s1, s2 +; GFX9-NEXT: ; return to shader part epilog + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %add = add i64 %reg, %in.high.bits + ret i64 %add +} diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll index 97d642b991f7..5415af02ef89 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll @@ -5249,6 +5249,114 @@ bb: ret void } +define amdgpu_gs void @sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset(ptr addrspace(5) inreg %sgpr_base, i32 inreg %sidx, i32 %vidx) { +; GFX9-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX9: ; %bb.0: ; %bb +; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s5 +; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 +; GFX9-NEXT: s_add_i32 s2, s2, s3 +; GFX9-NEXT: v_add_u32_e32 v0, s2, v0 +; GFX9-NEXT: v_add_u32_e32 v0, -16, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, 15 +; GFX9-NEXT: scratch_store_dword v0, v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX10-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX10: ; %bb.0: ; %bb +; GFX10-NEXT: s_add_u32 s0, s0, s5 +; GFX10-NEXT: s_addc_u32 s1, s1, 0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 +; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 +; GFX10-NEXT: v_add3_u32 v0, s2, s3, v0 +; GFX10-NEXT: v_mov_b32_e32 v1, 15 +; GFX10-NEXT: scratch_store_dword v0, v1, off offset:-16 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX11: ; %bb.0: ; %bb +; GFX11-NEXT: v_add3_u32 v0, s0, s1, v0 +; GFX11-NEXT: v_mov_b32_e32 v1, 15 +; GFX11-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX12: ; %bb.0: ; %bb +; GFX12-NEXT: v_mov_b32_e32 v1, 15 +; GFX12-NEXT: s_add_co_i32 s0, s0, s1 +; GFX12-NEXT: scratch_store_b32 v0, v1, s0 offset:-16 scope:SCOPE_SYS +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm +; +; GFX9-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX9-PAL: ; %bb.0: ; %bb +; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] +; GFX9-PAL-NEXT: s_mov_b32 s2, s8 +; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff +; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s5 +; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 +; GFX9-PAL-NEXT: s_add_i32 s0, s0, s1 +; GFX9-PAL-NEXT: v_add_u32_e32 v0, s0, v0 +; GFX9-PAL-NEXT: v_add_u32_e32 v0, -16, v0 +; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off +; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) +; GFX9-PAL-NEXT: s_endpgm +; +; GFX940-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX940: ; %bb.0: ; %bb +; GFX940-NEXT: s_add_i32 s0, s0, s1 +; GFX940-NEXT: v_add_u32_e32 v0, s0, v0 +; GFX940-NEXT: v_add_u32_e32 v0, -16, v0 +; GFX940-NEXT: v_mov_b32_e32 v1, 15 +; GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1 +; GFX940-NEXT: s_waitcnt vmcnt(0) +; GFX940-NEXT: s_endpgm +; +; GFX10-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX10-PAL: ; %bb.0: ; %bb +; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] +; GFX10-PAL-NEXT: s_mov_b32 s2, s8 +; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 +; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff +; GFX10-PAL-NEXT: s_add_u32 s2, s2, s5 +; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 +; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 +; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 +; GFX10-PAL-NEXT: v_add3_u32 v0, s0, s1, v0 +; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off offset:-16 +; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-PAL-NEXT: s_endpgm +; +; GFX11-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX11-PAL: ; %bb.0: ; %bb +; GFX11-PAL-NEXT: v_add3_u32 v0, s0, s1, v0 +; GFX11-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX11-PAL-NEXT: scratch_store_b32 v0, v1, off offset:-16 dlc +; GFX11-PAL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-PAL-NEXT: s_endpgm +; +; GFX12-PAL-LABEL: sgpr_base_plus_sgpr_plus_vgpr_plus_negative_imm_offset: +; GFX12-PAL: ; %bb.0: ; %bb +; GFX12-PAL-NEXT: v_mov_b32_e32 v1, 15 +; GFX12-PAL-NEXT: s_add_co_i32 s0, s0, s1 +; GFX12-PAL-NEXT: scratch_store_b32 v0, v1, s0 offset:-16 scope:SCOPE_SYS +; GFX12-PAL-NEXT: s_wait_storecnt 0x0 +; GFX12-PAL-NEXT: s_endpgm +bb: + %add1 = add nsw i32 %sidx, %vidx + %add2 = add nsw i32 %add1, -16 + %gep = getelementptr inbounds [16 x i8], ptr addrspace(5) %sgpr_base, i32 0, i32 %add2 + store volatile i32 15, ptr addrspace(5) %gep, align 4 + ret void +} + define amdgpu_gs void @sgpr_base_negative_offset(ptr addrspace(1) %out, ptr addrspace(5) inreg %scevgep) { ; GFX9-LABEL: sgpr_base_negative_offset: ; GFX9: ; %bb.0: ; %entry diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll index 157f91ccc6b1..b2f113f08a91 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll @@ -668,37 +668,32 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0xFFFFFFFF(ptr addrspace(1) define amdgpu_ps float @global_load_saddr_i8_offset_0x100000000(ptr addrspace(1) inreg %sbase) { ; GFX9-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 1, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-NEXT: s_add_i32 s3, s3, 1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1] -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_add_i32 s3, s3, 1 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s[0:1] -; GFX11-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_add_i32 s3, s3, 1 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX12-SDAG-NEXT: s_mov_b32 s1, 1 -; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] -; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 +; GFX12-SDAG-NEXT: s_add_co_i32 s3, s3, 1 +; GFX12-SDAG-NEXT: s_load_u8 s0, s[2:3], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-SDAG-NEXT: ; return to shader part epilog @@ -934,37 +929,32 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg0xFFFFFFFF(ptr addrspace( define amdgpu_ps float @global_load_saddr_i8_offset_neg0x100000000(ptr addrspace(1) inreg %sbase) { ; GFX9-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX9: ; %bb.0: -; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-NEXT: s_add_i32 s3, s3, -1 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; ; GFX10-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1] -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_add_i32 s3, s3, -1 +; GFX10-NEXT: global_load_ubyte v0, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; ; GFX11-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s[0:1] -; GFX11-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_add_i32 s3, s3, -1 +; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, 0 -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 -; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] -; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 +; GFX12-SDAG-NEXT: s_add_co_i32 s3, s3, -1 +; GFX12-SDAG-NEXT: s_load_u8 s0, s[2:3], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-SDAG-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll index 73f3d4c037ad..774a22fb907d 100644 --- a/llvm/test/CodeGen/AMDGPU/minmax.ll +++ b/llvm/test/CodeGen/AMDGPU/minmax.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG %s -; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11 %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12 %s +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12 %s define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-LABEL: test_minmax_i32: @@ -8,6 +10,16 @@ define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b) %sminmax = call i32 @llvm.smin.i32(i32 %smax, i32 %c) ret i32 %sminmax @@ -45,6 +57,16 @@ define i32 @test_minmax_commuted_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_commuted_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b) %sminmax = call i32 @llvm.smin.i32(i32 %c, i32 %smax) ret i32 %sminmax @@ -56,6 +78,16 @@ define i32 @test_maxmin_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b) %smaxmin = call i32 @llvm.smax.i32(i32 %smin, i32 %c) ret i32 %smaxmin @@ -67,6 +99,16 @@ define i32 @test_maxmin_commuted_i32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_i32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_commuted_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_i32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b) %smaxmin = call i32 @llvm.smax.i32(i32 %c, i32 %smin) ret i32 %smaxmin @@ -79,6 +121,17 @@ define void @test_smed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) { ; GFX11-NEXT: v_med3_i32 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_smed3_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_i32 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call i32 @llvm.smin.i32(i32 %x, i32 %y) %tmp1 = call i32 @llvm.smax.i32(i32 %x, i32 %y) %tmp2 = call i32 @llvm.smin.i32(i32 %tmp1, i32 %z) @@ -93,6 +146,16 @@ define i32 @test_minmax_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b) %uminmax = call i32 @llvm.umin.i32(i32 %umax, i32 %c) ret i32 %uminmax @@ -130,6 +193,16 @@ define i32 @test_minmax_commuted_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_maxmin_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_minmax_commuted_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_maxmin_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b) %uminmax = call i32 @llvm.umin.i32(i32 %c, i32 %umax) ret i32 %uminmax @@ -141,6 +214,16 @@ define i32 @test_maxmin_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b) %umaxmin = call i32 @llvm.umax.i32(i32 %umin, i32 %c) ret i32 %umaxmin @@ -152,6 +235,16 @@ define i32 @test_maxmin_commuted_u32(i32 %a, i32 %b, i32 %c) { ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: v_minmax_u32 v0, v0, v1, v2 ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_maxmin_commuted_u32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_minmax_u32 v0, v0, v1, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b) %umaxmin = call i32 @llvm.umax.i32(i32 %c, i32 %umin) ret i32 %umaxmin @@ -164,6 +257,17 @@ define void @test_umed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) { ; GFX11-NEXT: v_med3_u32 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_umed3_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_u32 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call i32 @llvm.umin.i32(i32 %x, i32 %y) %tmp1 = call i32 @llvm.umax.i32(i32 %x, i32 %y) %tmp2 = call i32 @llvm.umin.i32(i32 %tmp1, i32 %z) @@ -173,44 +277,88 @@ define void @test_umed3_i32(ptr addrspace(1) %arg, i32 %x, i32 %y, i32 %z) { } define float @test_minmax_f32_ieee_true(float %a, float %b, float %c) { -; SDAG-LABEL: test_minmax_f32_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; SDAG-NEXT: v_max_f32_e32 v2, v2, v2 -; SDAG-NEXT: v_maxmin_f32 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_minmax_f32_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] ; -; GISEL-LABEL: test_minmax_f32_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GISEL-NEXT: v_max_f32_e32 v2, v2, v2 -; GISEL-NEXT: v_maxmin_f32 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; GISEL-GFX11-LABEL: test_minmax_f32_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_minmax_f32_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_minmax_f32_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %max = call float @llvm.maxnum.f32(float %a, float %b) %minmax = call float @llvm.minnum.f32(float %max, float %c) ret float %minmax } define amdgpu_ps void @s_test_minmax_f32_ieee_false(float inreg %a, float inreg %b, float inreg %c, ptr addrspace(1) inreg %out) { -; SDAG-LABEL: s_test_minmax_f32_ieee_false: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; SDAG-NEXT: s_mov_b32 s5, s4 -; SDAG-NEXT: s_mov_b32 s4, s3 -; SDAG-NEXT: v_maxmin_f32 v0, s0, s1, v0 -; SDAG-NEXT: global_store_b32 v1, v0, s[4:5] -; SDAG-NEXT: s_endpgm +; SDAG-GFX11-LABEL: s_test_minmax_f32_ieee_false: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX11-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX11-NEXT: v_maxmin_f32 v0, s0, s1, v0 +; SDAG-GFX11-NEXT: global_store_b32 v1, v0, s[4:5] +; SDAG-GFX11-NEXT: s_endpgm ; -; GISEL-LABEL: s_test_minmax_f32_ieee_false: -; GISEL: ; %bb.0: -; GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; GISEL-NEXT: s_mov_b32 s6, s3 -; GISEL-NEXT: s_mov_b32 s7, s4 -; GISEL-NEXT: v_maxmin_f32 v0, s0, s1, v0 -; GISEL-NEXT: global_store_b32 v1, v0, s[6:7] -; GISEL-NEXT: s_endpgm +; GISEL-GFX11-LABEL: s_test_minmax_f32_ieee_false: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX11-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX11-NEXT: v_maxmin_f32 v0, s0, s1, v0 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[6:7] +; GISEL-GFX11-NEXT: s_endpgm +; +; SDAG-GFX12-LABEL: s_test_minmax_f32_ieee_false: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX12-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX12-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX12-NEXT: v_maxmin_num_f32 v0, s0, s1, v0 +; SDAG-GFX12-NEXT: global_store_b32 v1, v0, s[4:5] +; SDAG-GFX12-NEXT: s_endpgm +; +; GISEL-GFX12-LABEL: s_test_minmax_f32_ieee_false: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_max_num_f32 s0, s0, s1 +; GISEL-GFX12-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX12-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX12-NEXT: s_min_num_f32 s0, s0, s2 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX12-NEXT: global_store_b32 v1, v0, s[6:7] +; GISEL-GFX12-NEXT: s_endpgm %smax = call float @llvm.maxnum.f32(float %a, float %b) %sminmax = call float @llvm.minnum.f32(float %smax, float %c) store float %sminmax, ptr addrspace(1) %out @@ -222,27 +370,56 @@ define amdgpu_ps float @test_minmax_commuted_f32_ieee_false(float %a, float %b, ; GFX11: ; %bb.0: ; GFX11-NEXT: v_maxmin_f32 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_minmax_commuted_f32_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maxmin_num_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %max = call float @llvm.maxnum.f32(float %a, float %b) %minmax = call float @llvm.minnum.f32(float %c, float %max) ret float %minmax } define float @test_maxmin_f32_ieee_true(float %a, float %b, float %c) { -; SDAG-LABEL: test_maxmin_f32_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 -; SDAG-NEXT: v_max_f32_e32 v2, v2, v2 -; SDAG-NEXT: v_minmax_f32 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_maxmin_f32_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_dual_max_f32 v1, v1, v1 :: v_dual_max_f32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] ; -; GISEL-LABEL: test_maxmin_f32_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 -; GISEL-NEXT: v_max_f32_e32 v2, v2, v2 -; GISEL-NEXT: v_minmax_f32 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; GISEL-GFX11-LABEL: test_maxmin_f32_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_dual_max_f32 v0, v0, v0 :: v_dual_max_f32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f32_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_maxmin_f32_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_dual_max_num_f32 v1, v1, v1 :: v_dual_max_num_f32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_maxmin_f32_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_dual_max_num_f32 v0, v0, v0 :: v_dual_max_num_f32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f32_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %min = call float @llvm.minnum.f32(float %a, float %b) %maxmin = call float @llvm.maxnum.f32(float %min, float %c) ret float %maxmin @@ -253,6 +430,11 @@ define amdgpu_ps float @test_maxmin_commuted_f32_ieee_false(float %a, float %b, ; GFX11: ; %bb.0: ; GFX11-NEXT: v_minmax_f32 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_maxmin_commuted_f32_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_minmax_num_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %min = call float @llvm.minnum.f32(float %a, float %b) %maxmin = call float @llvm.maxnum.f32(float %c, float %min) ret float %maxmin @@ -265,6 +447,17 @@ define void @test_med3_f32(ptr addrspace(1) %arg, float %x, float %y, float %z) ; GFX11-NEXT: v_med3_f32 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b32 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_med3_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_num_f32 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b32 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call float @llvm.minnum.f32(float %x, float %y) %tmp1 = call float @llvm.maxnum.f32(float %x, float %y) %tmp2 = call float @llvm.minnum.f32(float %tmp1, float %z) @@ -278,29 +471,54 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) { ; GFX11: ; %bb.0: ; GFX11-NEXT: v_maxmin_f16 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_minmax_f16_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maxmin_num_f16 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %max = call half @llvm.maxnum.f16(half %a, half %b) %minmax = call half @llvm.minnum.f16(half %max, half %c) ret half %minmax } define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b, half inreg %c, ptr addrspace(1) inreg %out) { -; SDAG-LABEL: s_test_minmax_f16_ieee_false: -; SDAG: ; %bb.0: -; SDAG-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; SDAG-NEXT: s_mov_b32 s5, s4 -; SDAG-NEXT: s_mov_b32 s4, s3 -; SDAG-NEXT: v_maxmin_f16 v0, s0, s1, v0 -; SDAG-NEXT: global_store_b16 v1, v0, s[4:5] -; SDAG-NEXT: s_endpgm +; SDAG-GFX11-LABEL: s_test_minmax_f16_ieee_false: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX11-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX11-NEXT: v_maxmin_f16 v0, s0, s1, v0 +; SDAG-GFX11-NEXT: global_store_b16 v1, v0, s[4:5] +; SDAG-GFX11-NEXT: s_endpgm ; -; GISEL-LABEL: s_test_minmax_f16_ieee_false: -; GISEL: ; %bb.0: -; GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 -; GISEL-NEXT: s_mov_b32 s6, s3 -; GISEL-NEXT: s_mov_b32 s7, s4 -; GISEL-NEXT: v_maxmin_f16 v0, s0, s1, v0 -; GISEL-NEXT: global_store_b16 v1, v0, s[6:7] -; GISEL-NEXT: s_endpgm +; GISEL-GFX11-LABEL: s_test_minmax_f16_ieee_false: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX11-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX11-NEXT: v_maxmin_f16 v0, s0, s1, v0 +; GISEL-GFX11-NEXT: global_store_b16 v1, v0, s[6:7] +; GISEL-GFX11-NEXT: s_endpgm +; +; SDAG-GFX12-LABEL: s_test_minmax_f16_ieee_false: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0 +; SDAG-GFX12-NEXT: s_mov_b32 s5, s4 +; SDAG-GFX12-NEXT: s_mov_b32 s4, s3 +; SDAG-GFX12-NEXT: v_maxmin_num_f16 v0, s0, s1, v0 +; SDAG-GFX12-NEXT: global_store_b16 v1, v0, s[4:5] +; SDAG-GFX12-NEXT: s_endpgm +; +; GISEL-GFX12-LABEL: s_test_minmax_f16_ieee_false: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_max_num_f16 s0, s0, s1 +; GISEL-GFX12-NEXT: s_mov_b32 s6, s3 +; GISEL-GFX12-NEXT: s_mov_b32 s7, s4 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX12-NEXT: s_min_num_f16 s0, s0, s2 +; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX12-NEXT: global_store_b16 v1, v0, s[6:7] +; GISEL-GFX12-NEXT: s_endpgm %smax = call half @llvm.maxnum.f16(half %a, half %b) %sminmax = call half @llvm.minnum.f16(half %smax, half %c) store half %sminmax, ptr addrspace(1) %out @@ -308,23 +526,49 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b } define half @test_minmax_commuted_f16_ieee_true(half %a, half %b, half %c) { -; SDAG-LABEL: test_minmax_commuted_f16_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_max_f16_e32 v1, v1, v1 -; SDAG-NEXT: v_max_f16_e32 v0, v0, v0 -; SDAG-NEXT: v_max_f16_e32 v2, v2, v2 -; SDAG-NEXT: v_maxmin_f16 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GISEL-LABEL: test_minmax_commuted_f16_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_max_f16_e32 v0, v0, v0 -; GISEL-NEXT: v_max_f16_e32 v1, v1, v1 -; GISEL-NEXT: v_max_f16_e32 v2, v2, v2 -; GISEL-NEXT: v_maxmin_f16 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_minmax_commuted_f16_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; SDAG-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_maxmin_f16 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX11-LABEL: test_minmax_commuted_f16_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; GISEL-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_maxmin_f16 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_minmax_commuted_f16_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_maxmin_num_f16 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_minmax_commuted_f16_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_maxmin_num_f16 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %max = call half @llvm.maxnum.f16(half %a, half %b) %minmax = call half @llvm.minnum.f16(half %c, half %max) ret half %minmax @@ -335,29 +579,60 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) { ; GFX11: ; %bb.0: ; GFX11-NEXT: v_minmax_f16 v0, v0, v1, v2 ; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: test_maxmin_f16_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_minmax_num_f16 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog %min = call half @llvm.minnum.f16(half %a, half %b) %maxmin = call half @llvm.maxnum.f16(half %min, half %c) ret half %maxmin } define half @test_maxmin_commuted_f16_ieee_true(half %a, half %b, half %c) { -; SDAG-LABEL: test_maxmin_commuted_f16_ieee_true: -; SDAG: ; %bb.0: -; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; SDAG-NEXT: v_max_f16_e32 v1, v1, v1 -; SDAG-NEXT: v_max_f16_e32 v0, v0, v0 -; SDAG-NEXT: v_max_f16_e32 v2, v2, v2 -; SDAG-NEXT: v_minmax_f16 v0, v0, v1, v2 -; SDAG-NEXT: s_setpc_b64 s[30:31] -; -; GISEL-LABEL: test_maxmin_commuted_f16_ieee_true: -; GISEL: ; %bb.0: -; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GISEL-NEXT: v_max_f16_e32 v0, v0, v0 -; GISEL-NEXT: v_max_f16_e32 v1, v1, v1 -; GISEL-NEXT: v_max_f16_e32 v2, v2, v2 -; GISEL-NEXT: v_minmax_f16 v0, v0, v1, v2 -; GISEL-NEXT: s_setpc_b64 s[30:31] +; SDAG-GFX11-LABEL: test_maxmin_commuted_f16_ieee_true: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; SDAG-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; SDAG-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; SDAG-GFX11-NEXT: v_minmax_f16 v0, v0, v1, v2 +; SDAG-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX11-LABEL: test_maxmin_commuted_f16_ieee_true: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-GFX11-NEXT: v_max_f16_e32 v0, v0, v0 +; GISEL-GFX11-NEXT: v_max_f16_e32 v1, v1, v1 +; GISEL-GFX11-NEXT: v_max_f16_e32 v2, v2, v2 +; GISEL-GFX11-NEXT: v_minmax_f16 v0, v0, v1, v2 +; GISEL-GFX11-NEXT: s_setpc_b64 s[30:31] +; +; SDAG-GFX12-LABEL: test_maxmin_commuted_f16_ieee_true: +; SDAG-GFX12: ; %bb.0: +; SDAG-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; SDAG-GFX12-NEXT: s_wait_expcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_samplecnt 0x0 +; SDAG-GFX12-NEXT: s_wait_bvhcnt 0x0 +; SDAG-GFX12-NEXT: s_wait_kmcnt 0x0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; SDAG-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; SDAG-GFX12-NEXT: v_minmax_num_f16 v0, v0, v1, v2 +; SDAG-GFX12-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-GFX12-LABEL: test_maxmin_commuted_f16_ieee_true: +; GISEL-GFX12: ; %bb.0: +; GISEL-GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GISEL-GFX12-NEXT: s_wait_expcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_samplecnt 0x0 +; GISEL-GFX12-NEXT: s_wait_bvhcnt 0x0 +; GISEL-GFX12-NEXT: s_wait_kmcnt 0x0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v1, v1, v1 +; GISEL-GFX12-NEXT: v_max_num_f16_e32 v2, v2, v2 +; GISEL-GFX12-NEXT: v_minmax_num_f16 v0, v0, v1, v2 +; GISEL-GFX12-NEXT: s_setpc_b64 s[30:31] %min = call half @llvm.minnum.f16(half %a, half %b) %maxmin = call half @llvm.maxnum.f16(half %c, half %min) ret half %maxmin @@ -370,6 +645,17 @@ define void @test_med3_f16(ptr addrspace(1) %arg, half %x, half %y, half %z) #0 ; GFX11-NEXT: v_med3_f16 v2, v2, v3, v4 ; GFX11-NEXT: global_store_b16 v[0:1], v2, off ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_med3_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_med3_num_f16 v2, v2, v3, v4 +; GFX12-NEXT: global_store_b16 v[0:1], v2, off +; GFX12-NEXT: s_setpc_b64 s[30:31] %tmp0 = call half @llvm.minnum.f16(half %x, half %y) %tmp1 = call half @llvm.maxnum.f16(half %x, half %y) %tmp2 = call half @llvm.minnum.f16(half %tmp1, half %z) diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll new file mode 100644 index 000000000000..a9b8663a48de --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll @@ -0,0 +1,120 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 %s -o - | FileCheck %s --check-prefixes=GFX942 +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 %s -o - | FileCheck %s --check-prefixes=GFX908 + +define amdgpu_kernel void @matmul_kernel(i32 %a0, i32 %a1) { +; GFX942-LABEL: matmul_kernel: +; GFX942: ; %bb.0: ; %entry +; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; GFX942-NEXT: v_mov_b32_e32 v1, 0 +; GFX942-NEXT: s_mov_b32 s2, 0 +; GFX942-NEXT: v_accvgpr_write_b32 a0, v1 +; GFX942-NEXT: s_mov_b32 s3, 0 +; GFX942-NEXT: s_waitcnt lgkmcnt(0) +; GFX942-NEXT: s_cmp_lg_u32 s0, 0 +; GFX942-NEXT: s_cselect_b64 s[0:1], -1, 0 +; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX942-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0 +; GFX942-NEXT: s_branch .LBB0_2 +; GFX942-NEXT: .LBB0_1: ; %bb2 +; GFX942-NEXT: ; in Loop: Header=BB0_2 Depth=1 +; GFX942-NEXT: s_or_b32 s4, s3, 1 +; GFX942-NEXT: s_ashr_i32 s5, s3, 31 +; GFX942-NEXT: s_mov_b32 s3, s2 +; GFX942-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX942-NEXT: v_accvgpr_read_b32 v0, a0 +; GFX942-NEXT: v_mov_b32_e32 v2, v1 +; GFX942-NEXT: v_mov_b32_e32 v3, v1 +; GFX942-NEXT: v_accvgpr_write_b32 a0, v0 +; GFX942-NEXT: v_accvgpr_write_b32 a1, v1 +; GFX942-NEXT: v_accvgpr_write_b32 a2, v2 +; GFX942-NEXT: v_accvgpr_write_b32 a3, v3 +; GFX942-NEXT: s_and_b32 s3, s5, s4 +; GFX942-NEXT: s_nop 0 +; GFX942-NEXT: v_mfma_f32_16x16x16_f16 a[0:3], v[4:5], v[4:5], a[0:3] +; GFX942-NEXT: s_cbranch_execz .LBB0_4 +; GFX942-NEXT: .LBB0_2: ; %bb +; GFX942-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX942-NEXT: s_and_b64 vcc, exec, s[0:1] +; GFX942-NEXT: s_cbranch_vccz .LBB0_1 +; GFX942-NEXT: ; %bb.3: +; GFX942-NEXT: ; implicit-def: $sgpr3 +; GFX942-NEXT: .LBB0_4: ; %common.ret +; GFX942-NEXT: s_endpgm +; +; GFX908-LABEL: matmul_kernel: +; GFX908: ; %bb.0: ; %entry +; GFX908-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 +; GFX908-NEXT: v_mov_b32_e32 v1, 0 +; GFX908-NEXT: s_mov_b32 s2, 0 +; GFX908-NEXT: s_mov_b32 s3, 0 +; GFX908-NEXT: v_accvgpr_write_b32 a0, v1 +; GFX908-NEXT: s_waitcnt lgkmcnt(0) +; GFX908-NEXT: s_cmp_lg_u32 s0, 0 +; GFX908-NEXT: s_cselect_b64 s[0:1], -1, 0 +; GFX908-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1] +; GFX908-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v0 +; GFX908-NEXT: s_branch .LBB0_2 +; GFX908-NEXT: .LBB0_1: ; %bb2 +; GFX908-NEXT: ; in Loop: Header=BB0_2 Depth=1 +; GFX908-NEXT: s_or_b32 s4, s3, 1 +; GFX908-NEXT: s_ashr_i32 s5, s3, 31 +; GFX908-NEXT: s_mov_b32 s3, s2 +; GFX908-NEXT: s_nop 3 +; GFX908-NEXT: v_accvgpr_read_b32 v0, a0 +; GFX908-NEXT: v_mov_b32_e32 v5, s3 +; GFX908-NEXT: v_mov_b32_e32 v4, s2 +; GFX908-NEXT: v_mov_b32_e32 v2, v1 +; GFX908-NEXT: v_mov_b32_e32 v3, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a0, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a1, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a2, v2 +; GFX908-NEXT: v_accvgpr_write_b32 a3, v3 +; GFX908-NEXT: s_and_b32 s3, s5, s4 +; GFX908-NEXT: v_mfma_f32_16x16x16f16 a[0:3], v[4:5], v[4:5], a[0:3] +; GFX908-NEXT: s_cbranch_execz .LBB0_4 +; GFX908-NEXT: .LBB0_2: ; %bb +; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX908-NEXT: s_and_b64 vcc, exec, s[0:1] +; GFX908-NEXT: s_cbranch_vccz .LBB0_1 +; GFX908-NEXT: ; %bb.3: +; GFX908-NEXT: ; implicit-def: $sgpr3 +; GFX908-NEXT: .LBB0_4: ; %common.ret +; GFX908-NEXT: s_endpgm +entry: + br label %bb + +bb: + %i = phi { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } [ %i10, %bb2 ], [ zeroinitializer, %entry ] + %i1 = phi i32 [ %i5, %bb2 ], [ 0, %entry ] + %c0 = icmp ne i32 %a0, 0 + br i1 %c0, label %bb2, label %bb11 + +bb2: + %i3 = or i32 %i1, 1 + %i4 = icmp slt i32 %i1, 0 + %i5 = select i1 %i4, i32 %i3, i32 0 + %i6 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 123 + %i7 = insertelement <4 x float> zeroinitializer, float %i6, i32 0 + %i8 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i7, i32 0, i32 0, i32 0) + %i9 = extractelement <4 x float> %i8, i32 0 + %i10 = insertvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } zeroinitializer, float %i9, 123 + br label %bb + +bb11: + %c1 = icmp ne i32 %a1, 0 + br i1 %c1, label %bb12, label %common.ret + +common.ret: + ret void + +bb12: + %i13 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 0 + %i14 = insertelement <4 x float> zeroinitializer, float %i13, i32 0 + %i15 = insertelement <4 x float> %i14, float 0.000000e+00, i32 0 + %i16 = insertelement <4 x float> %i15, float 0.000000e+00, i32 0 + br label %common.ret +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half>, <4 x half>, <4 x float>, i32 immarg, i32 immarg, i32 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir new file mode 100644 index 000000000000..5c83170563e5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir @@ -0,0 +1,235 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE + +... +--- +name: test +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: test + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $sgpr4_sgpr5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; CHECK-NEXT: S_BITCMP1_B32 killed [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; CHECK-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc + ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B32_e32_]] + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec + ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_CNDMASK_B32_e64_]], 1, implicit $exec + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %24, %bb.3 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %11, %bb.3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]] + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[PHI]] + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 + ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[PHI1]], 1, implicit-def dead $scc + ; CHECK-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[PHI1]], 31, implicit-def dead $scc + ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 killed [[S_ASHR_I32_]], killed [[S_OR_B32_]], implicit-def dead $scc + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub3 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:areg_128_align2 = COPY [[REG_SEQUENCE]] + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY4]], [[COPY4]], killed [[COPY5]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_32 = PHI [[DEF]], %bb.1, [[S_AND_B32_]], %bb.2 + ; CHECK-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.1, [[V_MFMA_F32_16X16X16F16_e64_]].sub0, %bb.2 + ; CHECK-NEXT: [[PHI4:%[0-9]+]]:sreg_64_xexec = PHI [[S_MOV_B64_]], %bb.1, [[S_MOV_B64_1]], %bb.2 + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[PHI4]], implicit $exec + ; CHECK-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_CNDMASK_B32_e64_1]], 1, implicit $exec + ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc + ; CHECK-NEXT: S_BRANCH %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5: + ; CHECK-NEXT: S_ENDPGM 0 + ; + ; COALESCE-LABEL: name: test + ; COALESCE: bb.0: + ; COALESCE-NEXT: successors: %bb.1(0x80000000) + ; COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0 + ; COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc + ; COALESCE-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec + ; COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec + ; COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec + ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.1: + ; COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1 + ; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc + ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc + ; COALESCE-NEXT: S_BRANCH %bb.2 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.2: + ; COALESCE-NEXT: successors: %bb.3(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_MOV_B32_1]], 1, implicit-def dead $scc + ; COALESCE-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[S_MOV_B32_1]], 31, implicit-def dead $scc + ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_ASHR_I32_]], [[S_OR_B32_]], implicit-def dead $scc + ; COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]] + ; COALESCE-NEXT: [[COPY2:%[0-9]+]]:areg_128_align2 = COPY [[V_MOV_B32_e32_]] + ; COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.3: + ; COALESCE-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec + ; COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec + ; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc + ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc + ; COALESCE-NEXT: S_BRANCH %bb.4 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.4: + ; COALESCE-NEXT: successors: %bb.5(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.5: + ; COALESCE-NEXT: S_ENDPGM 0 + ; + ; GFX908-COALESCE-LABEL: name: test + ; GFX908-COALESCE: bb.0: + ; GFX908-COALESCE-NEXT: successors: %bb.1(0x80000000) + ; GFX908-COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; GFX908-COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; GFX908-COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0 + ; GFX908-COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc + ; GFX908-COALESCE-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec + ; GFX908-COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec + ; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.1: + ; GFX908-COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1 + ; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc + ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc + ; GFX908-COALESCE-NEXT: S_BRANCH %bb.2 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.2: + ; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_MOV_B32_1]], 1, implicit-def dead $scc + ; GFX908-COALESCE-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[S_MOV_B32_1]], 31, implicit-def dead $scc + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_ASHR_I32_]], [[S_OR_B32_]], implicit-def dead $scc + ; GFX908-COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub2:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; GFX908-COALESCE-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub3:vreg_128_align2 = COPY [[V_MOV_B32_e32_]].sub1 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]] + ; GFX908-COALESCE-NEXT: [[COPY2:%[0-9]+]]:areg_128_align2 = COPY [[V_MOV_B32_e32_]] + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.3: + ; GFX908-COALESCE-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec + ; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec + ; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc + ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc + ; GFX908-COALESCE-NEXT: S_BRANCH %bb.4 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.4: + ; GFX908-COALESCE-NEXT: successors: %bb.5(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.5: + ; GFX908-COALESCE-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1 + liveins: $sgpr4_sgpr5 + + %0:sgpr_64(p4) = COPY $sgpr4_sgpr5 + %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + S_BITCMP1_B32 killed %1, 0, implicit-def $scc + %2:sgpr_32 = S_MOV_B32 0 + %3:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc + %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %5:sreg_32 = IMPLICIT_DEF + %6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec + %7:sreg_64_xexec = V_CMP_NE_U32_e64 %6, 1, implicit $exec + + bb.1: + successors: %bb.2, %bb.3 + + %8:vgpr_32 = PHI %4, %bb.0, %9, %bb.3 + %10:sreg_32 = PHI %2, %bb.0, %11, %bb.3 + %12:agpr_32 = COPY %8 + %13:sreg_64 = S_MOV_B64 -1 + $vcc = S_AND_B64 $exec, %7, implicit-def $scc + S_CBRANCH_VCCNZ %bb.3, implicit $vcc + S_BRANCH %bb.2 + + bb.2: + successors: %bb.3 + + %14:sreg_32 = S_OR_B32 %10, 1, implicit-def dead $scc + %15:sreg_32 = S_ASHR_I32 %10, 31, implicit-def dead $scc + %16:sreg_32 = S_AND_B32 killed %15, killed %14, implicit-def dead $scc + %17:vreg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3 + %18:sreg_64 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1 + %19:vreg_64_align2 = COPY %18 + %20:areg_128_align2 = COPY %17 + %21:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %19, %19, killed %20, 0, 0, 0, implicit $mode, implicit $exec + %22:vgpr_32 = COPY %21.sub0 + %23:sreg_64 = S_MOV_B64 0 + + bb.3: + successors: %bb.4, %bb.1 + + %11:sreg_32 = PHI %5, %bb.1, %16, %bb.2 + %24:agpr_32 = PHI %12, %bb.1, %21.sub0, %bb.2 + %25:sreg_64_xexec = PHI %13, %bb.1, %23, %bb.2 + %9:vgpr_32 = COPY %24 + %26:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %25, implicit $exec + %27:sreg_64_xexec = V_CMP_NE_U32_e64 %26, 1, implicit $exec + $vcc = S_AND_B64 $exec, %27, implicit-def $scc + S_CBRANCH_VCCNZ %bb.1, implicit $vcc + S_BRANCH %bb.4 + + bb.4: + successors: %bb.5 + + bb.5: + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir new file mode 100644 index 000000000000..49c0aaf9fb39 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir @@ -0,0 +1,182 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE + +... +--- +name: test +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: test + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK-NEXT: liveins: $sgpr4_sgpr5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; CHECK-NEXT: S_BITCMP0_B32 killed [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.2, implicit $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 0 + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_3:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_4:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_3]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_4]], %subreg.sub3 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_1]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_1:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_2:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_3:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], killed [[V_MFMA_F32_16X16X16F16_e64_2]], 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_MFMA_F32_16X16X16F16_e64_3]].sub0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[V_ACCVGPR_WRITE_B32_e64_]], %bb.1, [[V_MFMA_F32_16X16X16F16_e64_3]].sub0, %bb.2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[PHI]] + ; CHECK-NEXT: [[V_CVT_F16_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_PACK_B32_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_PACK_B32_F16_e64 0, killed [[V_CVT_F16_F32_e64_]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_PACK_B32_F16_e64_]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1 + ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub1, [[S_MOV_B32_]], %subreg.sub2, [[S_MOV_B32_]], %subreg.sub3 + ; CHECK-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[REG_SEQUENCE2]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + ; CHECK-NEXT: S_ENDPGM 0 + ; + ; COALESCE-LABEL: name: test + ; COALESCE: bb.0: + ; COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0 + ; COALESCE-NEXT: S_BITCMP0_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.1: + ; COALESCE-NEXT: successors: %bb.3(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; COALESCE-NEXT: S_BRANCH %bb.3 + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.2: + ; COALESCE-NEXT: successors: %bb.3(0x80000000) + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]].sub0_sub1 + ; COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_1:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_2:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_2]], 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: {{ $}} + ; COALESCE-NEXT: bb.3: + ; COALESCE-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; COALESCE-NEXT: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY2]], implicit $mode, implicit $exec + ; COALESCE-NEXT: undef [[V_PACK_B32_F16_e64_:%[0-9]+]].sub0:vreg_64_align2 = nofpexcept V_PACK_B32_F16_e64 0, [[V_CVT_F16_F32_e32_]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; COALESCE-NEXT: [[V_PACK_B32_F16_e64_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; COALESCE-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[V_PACK_B32_F16_e64_]], [[S_MOV_B32_]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + ; COALESCE-NEXT: S_ENDPGM 0 + ; + ; GFX908-COALESCE-LABEL: name: test + ; GFX908-COALESCE: bb.0: + ; GFX908-COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; GFX908-COALESCE-NEXT: liveins: $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5 + ; GFX908-COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + ; GFX908-COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_128 = S_MOV_B32 0 + ; GFX908-COALESCE-NEXT: S_BITCMP0_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc + ; GFX908-COALESCE-NEXT: S_CBRANCH_SCC0 %bb.2, implicit killed $scc + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.1: + ; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; GFX908-COALESCE-NEXT: S_BRANCH %bb.3 + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.2: + ; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000) + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: undef [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub0:areg_128_align2 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub1:areg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_1]].sub0 + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub2:areg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_1]].sub0 + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]].sub3:areg_128_align2 = COPY [[V_ACCVGPR_WRITE_B32_e64_1]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[COPY1:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]].sub0_sub1 + ; GFX908-COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_ACCVGPR_WRITE_B32_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_1:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_MFMA_F32_16X16X16F16_e64_2:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_1]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY1]], [[COPY1]], [[V_MFMA_F32_16X16X16F16_e64_2]], 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: {{ $}} + ; GFX908-COALESCE-NEXT: bb.3: + ; GFX908-COALESCE-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[V_ACCVGPR_WRITE_B32_e64_]].sub0 + ; GFX908-COALESCE-NEXT: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_e32 [[COPY2]], implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: undef [[V_PACK_B32_F16_e64_:%[0-9]+]].sub0:vreg_64_align2 = nofpexcept V_PACK_B32_F16_e64 0, [[V_CVT_F16_F32_e32_]], 0, 0, 0, 0, implicit $mode, implicit $exec + ; GFX908-COALESCE-NEXT: [[V_PACK_B32_F16_e64_:%[0-9]+]].sub1:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub2:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub3:sgpr_128 = COPY [[S_MOV_B32_]].sub0 + ; GFX908-COALESCE-NEXT: BUFFER_STORE_DWORDX2_OFFSET_exact [[V_PACK_B32_F16_e64_]], [[S_MOV_B32_]], 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + ; GFX908-COALESCE-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.2, %bb.1 + liveins: $sgpr4_sgpr5 + + %0:sgpr_64(p4) = COPY $sgpr4_sgpr5 + %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4) + %2:sgpr_32 = S_MOV_B32 0 + S_BITCMP0_B32 killed %1, 0, implicit-def $scc + S_CBRANCH_SCC0 %bb.2, implicit $scc + + bb.1: + successors: %bb.3 + + %3:sgpr_32 = COPY %2 + %4:vgpr_32 = COPY %3, implicit $exec + S_BRANCH %bb.3 + + bb.2: + successors: %bb.3 + + %5:sgpr_32 = S_MOV_B32 0 + %6:vgpr_32 = COPY %5 + %7:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %8:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %9:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %10:agpr_32 = V_ACCVGPR_WRITE_B32_e64 %6, implicit $exec + %11:areg_128_align2 = REG_SEQUENCE %7, %subreg.sub0, %8, %subreg.sub1, %9, %subreg.sub2, %10, %subreg.sub3 + %12:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, %5, %subreg.sub1 + %13:vreg_64_align2 = COPY %12 + %14:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %11, 0, 0, 0, implicit $mode, implicit $exec + %15:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %14, 0, 0, 0, implicit $mode, implicit $exec + %16:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %15, 0, 0, 0, implicit $mode, implicit $exec + %17:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %13, %13, killed %16, 0, 0, 0, implicit $mode, implicit $exec + %18:vgpr_32 = COPY %17.sub0 + %19:vgpr_32 = COPY %18 + + bb.3: + %20:vgpr_32 = PHI %4, %bb.1, %19, %bb.2 + %21:vgpr_32 = nofpexcept V_CVT_F16_F32_e64 0, %20, 0, 0, implicit $mode, implicit $exec + %22:vgpr_32 = nofpexcept V_PACK_B32_F16_e64 0, killed %21, 0, %2, 0, 0, implicit $mode, implicit $exec + %23:vgpr_32 = V_MOV_B32_e32 0, implicit $exec + %24:vreg_64_align2 = REG_SEQUENCE %22, %subreg.sub0, killed %23, %subreg.sub1 + %25:sgpr_128 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1, %2, %subreg.sub2, %2, %subreg.sub3 + %26:vreg_64_align2 = COPY %24 + BUFFER_STORE_DWORDX2_OFFSET_exact killed %26, killed %25, %2, 0, 0, 0, implicit $exec :: (dereferenceable store (s64) into `ptr addrspace(8) null`, align 1, addrspace 8) + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll index 98d5f3097153..a2a0107a6f7d 100644 --- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll @@ -1372,20 +1372,19 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v1, v0 ; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc ; GFX8-NEXT: s_movk_i32 s0, 0xf000 -; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v3 -; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v4, vcc +; GFX8-NEXT: v_add_u32_e32 v7, vcc, s0, v3 +; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v4, vcc ; GFX8-NEXT: s_movk_i32 s0, 0xf800 -; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[3:4] -; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[5:6] +; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[3:4] +; GFX8-NEXT: flat_load_dwordx2 v[7:8], v[7:8] ; GFX8-NEXT: v_add_u32_e32 v9, vcc, s0, v3 ; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc ; GFX8-NEXT: flat_load_dwordx2 v[9:10], v[9:10] -; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0, v3 -; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 1, v4, vcc +; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v4 ; GFX8-NEXT: flat_load_dwordx2 v[3:4], v[3:4] ; GFX8-NEXT: s_waitcnt vmcnt(2) -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v5, v7 -; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v6, v8, vcc +; GFX8-NEXT: v_add_u32_e32 v0, vcc, v7, v5 +; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc ; GFX8-NEXT: s_waitcnt vmcnt(1) ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v9, v0 ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc @@ -1416,32 +1415,32 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 7, v0 -; GFX9-NEXT: v_and_b32_e32 v12, 0xffff8000, v1 +; GFX9-NEXT: v_and_b32_e32 v10, 0xffff8000, v1 ; GFX9-NEXT: v_mov_b32_e32 v1, s35 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s34, v12 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s34, v10 ; GFX9-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 1, v1, vcc -; GFX9-NEXT: global_load_dwordx2 v[2:3], v[0:1], off -; GFX9-NEXT: global_load_dwordx2 v[6:7], v[4:5], off offset:-4096 ; GFX9-NEXT: s_movk_i32 s0, 0xf000 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: global_load_dwordx2 v[8:9], v[4:5], off -; GFX9-NEXT: global_load_dwordx2 v[10:11], v[0:1], off offset:2048 +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc +; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off +; GFX9-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: global_load_dwordx2 v[8:9], v[2:3], off offset:2048 +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(2) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v3, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v7, vcc +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v8, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v3, vcc ; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v10, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v8, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v9, v1, vcc -; GFX9-NEXT: global_store_dwordx2 v12, v[0:1], s[34:35] +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-NEXT: global_store_dwordx2 v10, v[0:1], s[34:35] ; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: Offset64: @@ -1477,8 +1476,7 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off ; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off offset:-2048 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 1, v1, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v1 ; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[8:9], v[2:3], off ; GFX10-NEXT: global_load_dwordx2 v[10:11], v[0:1], off @@ -1517,25 +1515,25 @@ define amdgpu_kernel void @Offset64(ptr addrspace(1) %buffer) { ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, 0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 1, v1, vcc_lo -; GFX11-NEXT: global_load_b64 v[2:3], v[0:1], off -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0xfffff000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo ; GFX11-NEXT: s_clause 0x2 -; GFX11-NEXT: global_load_b64 v[6:7], v[4:5], off offset:-4096 -; GFX11-NEXT: global_load_b64 v[4:5], v[4:5], off -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:2048 +; GFX11-NEXT: global_load_b64 v[4:5], v[2:3], off +; GFX11-NEXT: global_load_b64 v[6:7], v[0:1], off +; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off offset:2048 +; GFX11-NEXT: v_add_nc_u32_e32 v1, 1, v1 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v6, v2 -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v7, v3, vcc_lo +; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, v6 +; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo +; GFX11-NEXT: s_waitcnt vmcnt(1) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo ; GFX11-NEXT: global_store_b64 v8, v[0:1], s[34:35] ; GFX11-NEXT: s_endpgm entry: @@ -2408,18 +2406,17 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX8-NEXT: v_mov_b32_e32 v3, 3 ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 -; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0 -; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v2, vcc +; GFX8-NEXT: v_add_u32_e32 v3, vcc, v1, v0 +; GFX8-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc ; GFX8-NEXT: s_movk_i32 s0, 0x800 -; GFX8-NEXT: v_add_u32_e32 v3, vcc, s0, v0 -; GFX8-NEXT: v_addc_u32_e32 v4, vcc, -1, v6, vcc -; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0, v0 -; GFX8-NEXT: v_addc_u32_e32 v6, vcc, -1, v6, vcc -; GFX8-NEXT: flat_load_dwordx2 v[3:4], v[3:4] +; GFX8-NEXT: v_add_u32_e32 v5, vcc, s0, v3 +; GFX8-NEXT: v_addc_u32_e32 v6, vcc, -1, v0, vcc +; GFX8-NEXT: v_add_u32_e32 v4, vcc, -1, v0 ; GFX8-NEXT: flat_load_dwordx2 v[5:6], v[5:6] +; GFX8-NEXT: flat_load_dwordx2 v[3:4], v[3:4] ; GFX8-NEXT: s_waitcnt vmcnt(0) -; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 -; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc +; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5 +; GFX8-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GFX8-NEXT: flat_store_dwordx2 v[1:2], v[3:4] ; GFX8-NEXT: s_endpgm ; @@ -2450,14 +2447,13 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX9-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v3, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v3, vcc -; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:-2048 -; GFX9-NEXT: global_load_dwordx2 v[6:7], v[2:3], off +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0x1000, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off offset:-2048 +; GFX9-NEXT: global_load_dwordx2 v[6:7], v[0:1], off ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v5, vcc @@ -2490,15 +2486,14 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 ; GFX10-NEXT: v_add_co_u32 v1, s0, s34, v8 ; GFX10-NEXT: v_add_co_ci_u32_e64 v2, s0, s35, 0, s0 -; GFX10-NEXT: v_add_co_u32 v3, vcc_lo, v1, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v3 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v4, vcc_lo -; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0, v3 -; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v4, vcc_lo +; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo +; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, 0x800, v0 +; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v1, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v1, -1, v1 ; GFX10-NEXT: s_clause 0x1 -; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off -; GFX10-NEXT: global_load_dwordx2 v[6:7], v[2:3], off +; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v6, v4 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v7, v5, vcc_lo @@ -2525,19 +2520,18 @@ define hidden amdgpu_kernel void @negativeoffset(ptr addrspace(1) nocapture %buf ; GFX11-NEXT: v_add_co_u32 v1, s0, s34, v4 ; GFX11-NEXT: v_add_co_ci_u32_e64 v2, null, s35, 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v3, vcc_lo, v1, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v1, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v3 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v5, vcc_lo -; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0, v3 -; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v5, vcc_lo +; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, 0x1000, v0 +; GFX11-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, -1, v1, vcc_lo +; GFX11-NEXT: v_add_nc_u32_e32 v1, -1, v1 ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:-2048 -; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off +; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off offset:-2048 +; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo +; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo ; GFX11-NEXT: global_store_b64 v4, v[0:1], s[34:35] ; GFX11-NEXT: s_endpgm entry: diff --git a/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir b/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir new file mode 100644 index 000000000000..3879f6dccf9d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir @@ -0,0 +1,85 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=register-coalescer -o - %s | FileCheck %s + +# This used to assert due to trying to rematerialize V_MOV_B64_PSEUDO +# at copy to $vgpr1. This would assert since this would clobber the +# live value in $vgpr0. + +--- +name: rematerialize_physreg_sub_def_already_live_at_def_assert +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_already_live_at_def_assert + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_MOV_B:%[0-9]+]]:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: $vgpr1 = COPY [[V_MOV_B]].sub1 + ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit killed $vgpr1 + %0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + %1:vgpr_32 = COPY %0.sub1 + $vgpr0 = V_MOV_B32_e32 0, implicit $exec + $vgpr1 = COPY %1 + SI_RETURN implicit $vgpr0, implicit killed $vgpr1 +... + +# Same as previous, except with an IMPLICIT_DEF +--- +name: rematerialize_physreg_sub_def_already_live_at_def_assert_implicit_def +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_already_live_at_def_assert_implicit_def + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec + ; CHECK-NEXT: $vgpr1 = COPY [[DEF]].sub1 + ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit killed $vgpr1 + %0:vreg_64 = IMPLICIT_DEF + %1:vgpr_32 = COPY %0.sub1 + $vgpr0 = V_MOV_B32_e32 0, implicit $exec + $vgpr1 = COPY %1 + SI_RETURN implicit $vgpr0, implicit killed $vgpr1 +... + +--- +name: rematerialize_physreg_sub_def_no_live_sub_def_0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_no_live_sub_def_0 + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $vgpr0_vgpr1 = V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1 + ; CHECK-NEXT: SI_RETURN implicit killed $vgpr1 + %0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + %1:vgpr_32 = COPY %0.sub1 + $vgpr1 = COPY %1 + SI_RETURN implicit killed $vgpr1 +... + +--- +name: rematerialize_physreg_sub_def_no_live_sub_def_1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: rematerialize_physreg_sub_def_no_live_sub_def_1 + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead $vgpr1_vgpr2 = V_MOV_B64_PSEUDO 1, implicit $exec, implicit-def $vgpr1 + ; CHECK-NEXT: SI_RETURN implicit killed $vgpr1 + %0:vreg_64 = V_MOV_B64_PSEUDO 1, implicit $exec + %1:vgpr_32 = COPY %0.sub0 + $vgpr1 = COPY %1 + SI_RETURN implicit killed $vgpr1 +... diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index 3e8768c98b5c..96dd6276f7e3 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -1065,100 +1065,37 @@ define amdgpu_kernel void @s_test_sdiv24_48(ptr addrspace(1) %out, i48 %x, i48 % ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv24_48: -; GCN-IR: ; %bb.0: ; %_udiv-special-cases -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb -; GCN-IR-NEXT: s_mov_b32 s15, 0 -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_sext_i32_i16 s1, s1 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 24 -; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 -; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 -; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 24 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[0:1], 16 -; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31 -; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[2:3], 16 -; GCN-IR-NEXT: s_mov_b32 s1, s0 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[2:3], 16 -; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 -; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1] -; GCN-IR-NEXT: s_mov_b32 s3, s2 -; GCN-IR-NEXT: s_sub_u32 s12, s6, s0 -; GCN-IR-NEXT: s_subb_u32 s13, s7, s0 -; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3] -; GCN-IR-NEXT: s_sub_u32 s6, s6, s2 -; GCN-IR-NEXT: s_subb_u32 s7, s7, s2 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[12:13], 0 -; GCN-IR-NEXT: s_flbit_i32_b64 s14, s[6:7] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] -; GCN-IR-NEXT: s_flbit_i32_b64 s20, s[12:13] -; GCN-IR-NEXT: s_sub_u32 s16, s14, s20 -; GCN-IR-NEXT: s_subb_u32 s17, 0, 0 -; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[18:19], s[16:17], 63 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[22:23], s[16:17], 63 -; GCN-IR-NEXT: s_or_b64 s[18:19], s[10:11], s[18:19] -; GCN-IR-NEXT: s_and_b64 s[10:11], s[18:19], exec -; GCN-IR-NEXT: s_cselect_b32 s11, 0, s13 -; GCN-IR-NEXT: s_cselect_b32 s10, 0, s12 -; GCN-IR-NEXT: s_or_b64 s[18:19], s[18:19], s[22:23] -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[18:19] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 -; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: s_add_u32 s18, s16, 1 -; GCN-IR-NEXT: s_addc_u32 s19, s17, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[18:19], 0 -; GCN-IR-NEXT: s_sub_i32 s16, 63, s16 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[12:13], s16 -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 -; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: s_lshr_b64 s[16:17], s[12:13], s18 -; GCN-IR-NEXT: s_add_u32 s18, s6, -1 -; GCN-IR-NEXT: s_addc_u32 s19, s7, -1 -; GCN-IR-NEXT: s_not_b64 s[8:9], s[14:15] -; GCN-IR-NEXT: s_add_u32 s12, s8, s20 -; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 -; GCN-IR-NEXT: s_mov_b64 s[14:15], 0 -; GCN-IR-NEXT: s_mov_b32 s9, 0 -; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while -; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: s_lshl_b64 s[16:17], s[16:17], 1 -; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[8:9] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[14:15], s[10:11] -; GCN-IR-NEXT: s_sub_u32 s8, s18, s16 -; GCN-IR-NEXT: s_subb_u32 s8, s19, s17 -; GCN-IR-NEXT: s_ashr_i32 s14, s8, 31 -; GCN-IR-NEXT: s_mov_b32 s15, s14 -; GCN-IR-NEXT: s_and_b32 s8, s14, 1 -; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7] -; GCN-IR-NEXT: s_sub_u32 s16, s16, s14 -; GCN-IR-NEXT: s_subb_u32 s17, s17, s15 -; GCN-IR-NEXT: s_add_u32 s12, s12, 1 -; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0 -; GCN-IR-NEXT: s_mov_b64 s[14:15], s[8:9] -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3 -; GCN-IR-NEXT: .LBB9_4: ; %Flow4 -; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[6:7] -; GCN-IR-NEXT: .LBB9_5: ; %udiv-end -; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] -; GCN-IR-NEXT: s_xor_b64 s[2:3], s[10:11], s[0:1] -; GCN-IR-NEXT: s_sub_u32 s0, s2, s0 -; GCN-IR-NEXT: s_subb_u32 s1, s3, s1 +; GCN-IR: ; %bb.0: +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4 -; GCN-IR-NEXT: s_waitcnt expcnt(0) -; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: s_sext_i32_i16 s1, s9 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 +; GCN-IR-NEXT: v_alignbit_b32 v0, s1, v0, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: s_sext_i32_i16 s0, s3 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s2 +; GCN-IR-NEXT: v_alignbit_b32 v2, s0, v2, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v4 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, v3 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: s_endpgm %1 = ashr i48 %x, 24 %2 = ashr i48 %y, 24 diff --git a/llvm/test/CodeGen/AMDGPU/smed3.ll b/llvm/test/CodeGen/AMDGPU/smed3.ll index e0d0ddce208c..ddf6297bc27a 100644 --- a/llvm/test/CodeGen/AMDGPU/smed3.ll +++ b/llvm/test/CodeGen/AMDGPU/smed3.ll @@ -1,6 +1,8 @@ ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-TRUE16 %s declare i32 @llvm.amdgcn.workitem.id.x() #0 @@ -98,6 +100,8 @@ declare i64 @llvm.smin.i64(i64, i64) ; VI: v_max_i16_e32 [[MAX:v[0-9]]], 12, {{v[0-9]}} ; VI: v_min_i16_e32 {{v[0-9]}}, 17, [[MAX]] ; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +; GFX11-TRUE16: v_med3_i16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, 12, 17 +; GFX11-FAKE16: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 define amdgpu_kernel void @v_test_smed3_r_i_i_i16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr i16, ptr addrspace(1) %aptr, i32 %tid @@ -686,6 +690,8 @@ bb: ; VI: v_max_i16 ; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_i16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_smed3_i16_pat_0(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -707,6 +713,8 @@ bb: ; GCN-LABEL: {{^}}v_test_smed3_i16_pat_1: ; GFX9: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_i16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_i16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_smed3_i16_pat_1(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index cb8f82db92bb..23364e860d15 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -1188,109 +1188,39 @@ define amdgpu_kernel void @s_test_srem24_48(ptr addrspace(1) %out, i48 %x, i48 % ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem24_48: -; GCN-IR: ; %bb.0: ; %_udiv-special-cases -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb -; GCN-IR-NEXT: s_mov_b32 s13, 0 +; GCN-IR: ; %bb.0: +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_sext_i32_i16 s1, s1 ; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 24 -; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 24 -; GCN-IR-NEXT: s_lshl_b64 s[0:1], s[0:1], 16 -; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], 16 -; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[0:1], 16 -; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31 -; GCN-IR-NEXT: s_mov_b32 s1, s0 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 16 -; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] -; GCN-IR-NEXT: s_sub_u32 s2, s2, s0 -; GCN-IR-NEXT: s_subb_u32 s3, s3, s0 -; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31 -; GCN-IR-NEXT: s_mov_b32 s11, s10 -; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[10:11] -; GCN-IR-NEXT: s_sub_u32 s6, s6, s10 -; GCN-IR-NEXT: s_subb_u32 s7, s7, s10 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0 -; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[6:7] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] -; GCN-IR-NEXT: s_flbit_i32_b64 s20, s[2:3] -; GCN-IR-NEXT: s_sub_u32 s14, s12, s20 -; GCN-IR-NEXT: s_subb_u32 s15, 0, 0 -; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[14:15], 63 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[14:15], 63 -; GCN-IR-NEXT: s_or_b64 s[16:17], s[10:11], s[16:17] -; GCN-IR-NEXT: s_and_b64 s[10:11], s[16:17], exec -; GCN-IR-NEXT: s_cselect_b32 s11, 0, s3 -; GCN-IR-NEXT: s_cselect_b32 s10, 0, s2 -; GCN-IR-NEXT: s_or_b64 s[16:17], s[16:17], s[18:19] -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[16:17] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_5 -; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: s_add_u32 s16, s14, 1 -; GCN-IR-NEXT: s_addc_u32 s17, s15, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[16:17], 0 -; GCN-IR-NEXT: s_sub_i32 s14, 63, s14 -; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11] -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[2:3], s14 -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_4 -; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s16 -; GCN-IR-NEXT: s_add_u32 s18, s6, -1 -; GCN-IR-NEXT: s_addc_u32 s19, s7, -1 -; GCN-IR-NEXT: s_not_b64 s[8:9], s[12:13] -; GCN-IR-NEXT: s_add_u32 s12, s8, s20 -; GCN-IR-NEXT: s_addc_u32 s13, s9, 0 -; GCN-IR-NEXT: s_mov_b64 s[16:17], 0 -; GCN-IR-NEXT: s_mov_b32 s9, 0 -; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while -; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: s_lshl_b64 s[14:15], s[14:15], 1 -; GCN-IR-NEXT: s_lshr_b32 s8, s11, 31 -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[8:9] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[16:17], s[10:11] -; GCN-IR-NEXT: s_sub_u32 s8, s18, s14 -; GCN-IR-NEXT: s_subb_u32 s8, s19, s15 -; GCN-IR-NEXT: s_ashr_i32 s16, s8, 31 -; GCN-IR-NEXT: s_mov_b32 s17, s16 -; GCN-IR-NEXT: s_and_b32 s8, s16, 1 -; GCN-IR-NEXT: s_and_b64 s[16:17], s[16:17], s[6:7] -; GCN-IR-NEXT: s_sub_u32 s14, s14, s16 -; GCN-IR-NEXT: s_subb_u32 s15, s15, s17 -; GCN-IR-NEXT: s_add_u32 s12, s12, 1 -; GCN-IR-NEXT: s_addc_u32 s13, s13, 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[20:21], s[12:13], 0 -; GCN-IR-NEXT: s_mov_b64 s[16:17], s[8:9] -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[20:21] -; GCN-IR-NEXT: s_cbranch_vccz .LBB9_3 -; GCN-IR-NEXT: .LBB9_4: ; %Flow4 -; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1 -; GCN-IR-NEXT: s_or_b64 s[10:11], s[8:9], s[10:11] -; GCN-IR-NEXT: .LBB9_5: ; %udiv-end -; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 -; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, v0 -; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x9 -; GCN-IR-NEXT: s_mul_i32 s4, s6, s11 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v0 -; GCN-IR-NEXT: s_mul_i32 s4, s7, s10 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v0 -; GCN-IR-NEXT: s_mul_i32 s4, s6, s10 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s4 -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, s2, v1 -; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v2, v0, vcc -; GCN-IR-NEXT: v_xor_b32_e32 v1, s0, v1 -; GCN-IR-NEXT: v_xor_b32_e32 v0, s1, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 -; GCN-IR-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1 -; GCN-IR-NEXT: s_mov_b32 s15, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s14, -1 -; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, v0, v2, vcc -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: buffer_store_short v0, off, s[12:15], 0 offset:4 -; GCN-IR-NEXT: buffer_store_dword v1, off, s[12:15], 0 +; GCN-IR-NEXT: s_sext_i32_i16 s5, s5 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 +; GCN-IR-NEXT: v_alignbit_b32 v0, s5, v0, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s2 +; GCN-IR-NEXT: v_alignbit_b32 v2, s3, v2, 24 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-IR-NEXT: v_xor_b32_e32 v5, v2, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 30, v5 +; GCN-IR-NEXT: v_or_b32_e32 v5, 1, v5 +; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-IR-NEXT: v_mad_f32 v3, -v4, v1, v3 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: s_endpgm %1 = ashr i48 %x, 24 %2 = ashr i48 %y, 24 diff --git a/llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll b/llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll new file mode 100644 index 000000000000..f52f1164f2ba --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll @@ -0,0 +1,193 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s + +; Reduce a 64-bit sub by a constant if we know the low 32-bits are all +; zero. + +; sub i64:x, K if computeTrailingZeros(K) >= 32 +; => build_pair (sub x.hi, K.hi), x.lo + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0xfffc0000 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_1(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 4294967296 ; (1 << 32) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_2(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -2 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 8589934592 ; (1 << 33) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_3(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 0x80000000 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_low_bits_known0_4(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, 1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0xfffc0000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 1125899906842624 ; (1 << 50) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_1(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 4294967296 ; (1 << 32) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_2(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -2, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 8589934592 ; (1 << 33) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_3(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_3: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, -9223372036854775808 ; (1 << 63) + ret i64 %sub +} + +define i64 @v_sub_i64_const_low_bits_known0_4(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_low_bits_known0_4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, 1, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, -4294967296 ; 0xffffffff00000000 + ret i64 %sub +} + +define amdgpu_ps i64 @s_sub_i64_const_high_bits_known0_0(i64 inreg %reg) { +; GFX9-LABEL: s_sub_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_u32 s0, s0, 1 +; GFX9-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub i64 %reg, 4294967295 ; (1 << 31) + ret i64 %sub +} + +define i64 @v_sub_i64_const_high_bits_known0_0(i64 %reg) { +; GFX9-LABEL: v_sub_i64_const_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub i64 %reg, 4294967295 ; (1 << 31) + ret i64 %sub +} + +define <2 x i64> @v_sub_v2i64_splat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_sub_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, -1, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %sub +} + +define <2 x i64> @v_sub_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> %reg) { +; GFX9-LABEL: v_sub_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v1, -1, v1 +; GFX9-NEXT: v_add_u32_e32 v3, -2, v3 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %sub +} + +define amdgpu_ps <2 x i64> @s_sub_v2i64_splat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_sub_v2i64_splat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: s_add_i32 s3, s3, -1 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 4294967296> ; (1 << 32) + ret <2 x i64> %sub +} + +define amdgpu_ps <2 x i64> @s_sub_v2i64_nonsplat_const_low_bits_known0_0(<2 x i64> inreg %reg) { +; GFX9-LABEL: s_sub_v2i64_nonsplat_const_low_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_add_i32 s1, s1, -1 +; GFX9-NEXT: s_add_i32 s3, s3, -2 +; GFX9-NEXT: ; return to shader part epilog + %sub = sub <2 x i64> %reg, <i64 4294967296, i64 8589934592> ; (1 << 32), (1 << 33) + ret <2 x i64> %sub +} + +; We could reduce this to use a 32-bit sub if we use computeKnownBits +define i64 @v_sub_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) { +; GFX9-LABEL: v_sub_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, 0, v0 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-NEXT: s_setpc_b64 s[30:31] + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %sub = sub i64 %reg, %in.high.bits + ret i64 %sub +} + +; We could reduce this to use a 32-bit sub if we use computeKnownBits +define amdgpu_ps i64 @s_sub_i64_variable_high_bits_known0_0(i64 inreg %reg, i32 inreg %offset.hi32) { +; GFX9-LABEL: s_sub_i64_variable_high_bits_known0_0: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_sub_u32 s0, s0, 0 +; GFX9-NEXT: s_subb_u32 s1, s1, s2 +; GFX9-NEXT: ; return to shader part epilog + %zext.offset.hi32 = zext i32 %offset.hi32 to i64 + %in.high.bits = shl i64 %zext.offset.hi32, 32 + %sub = sub i64 %reg, %in.high.bits + ret i64 %sub +} diff --git a/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir b/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir index 3135e3c60f5f..831570800d06 100644 --- a/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir +++ b/llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -stress-regalloc=4 -start-before=greedy,2 -stop-after=virtregrewriter,2 -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -stress-regalloc=4 -verify-regalloc -start-before=greedy,2 -stop-after=virtregrewriter,2 -o - %s | FileCheck %s # This testcase hit a situation where greedy would hit a use after # free during last chance recoloring. This case successfully allocates @@ -26,11 +26,12 @@ body: | ; CHECK-NEXT: renamable $vgpr5 = V_FMA_F32_e64 0, $vgpr7, 0, $vgpr7, 0, $vgpr2, 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: SI_SPILL_AV128_SAVE $vgpr6_vgpr7_vgpr8_vgpr9, %stack.2, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.2, align 4, addrspace 5) ; CHECK-NEXT: renamable $vgpr6 = V_FMA_F32_e64 0, killed $vgpr8, 0, $vgpr8, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: renamable $vgpr7 = IMPLICIT_DEF ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: successors: %bb.2(0x80000000) - ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3:0x00000000000000FF, $vgpr4_vgpr5_vgpr6_vgpr7:0x000000000000003F + ; CHECK-NEXT: liveins: $vgpr0_vgpr1_vgpr2_vgpr3:0x00000000000000FF, $vgpr4_vgpr5_vgpr6_vgpr7:0x00000000000000FF ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: SI_SPILL_AV128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3, %stack.1, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.1, align 4, addrspace 5) ; CHECK-NEXT: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5) @@ -40,7 +41,7 @@ body: | ; CHECK-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) ; CHECK-NEXT: renamable $vgpr0 = IMPLICIT_DEF ; CHECK-NEXT: renamable $vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5) - ; CHECK-NEXT: renamable $vgpr5 = nofpexcept V_DIV_FIXUP_F32_e64 0, killed $vgpr0, 0, undef $vgpr7, 0, killed $vgpr5, 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: renamable $vgpr5 = nofpexcept V_DIV_FIXUP_F32_e64 0, killed $vgpr0, 0, killed $vgpr7, 0, killed $vgpr5, 0, 0, implicit $mode, implicit $exec ; CHECK-NEXT: renamable $vgpr0 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) ; CHECK-NEXT: renamable $vgpr9 = COPY killed renamable $vgpr5 ; CHECK-NEXT: renamable $vgpr4_vgpr5_vgpr6_vgpr7 = SI_SPILL_V128_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.4, align 4, addrspace 5) @@ -73,6 +74,7 @@ body: | undef %4.sub0:vreg_128_align2 = V_FMA_F32_e64 0, %3.sub0, 0, %3.sub0, 0, %0.sub3, 0, 0, implicit $mode, implicit $exec %4.sub1:vreg_128_align2 = V_FMA_F32_e64 0, %3.sub1, 0, %3.sub1, 0, %0.sub2, 0, 0, implicit $mode, implicit $exec %4.sub2:vreg_128_align2 = V_FMA_F32_e64 0, %3.sub2, 0, %3.sub2, 0, %0.sub1, 0, 0, implicit $mode, implicit $exec + %4.sub3:vreg_128_align2 = IMPLICIT_DEF S_CBRANCH_EXECZ %bb.2, implicit $exec bb.1: diff --git a/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll b/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll new file mode 100644 index 000000000000..f0b3d334af67 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/swdev503538-move-to-valu-stack-srd-physreg.ll @@ -0,0 +1,23 @@ +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs=0 -O0 2> %t.err < %s | FileCheck %s +; RUN: FileCheck -check-prefix=ERR %s < %t.err + +; FIXME: This error will be fixed by supporting arbitrary divergent +; dynamic allocas by performing a wave umax of the size. + +; ERR: error: <unknown>:0:0: in function move_to_valu_assert_srd_is_physreg_swdev503538 i32 (ptr addrspace(1)): illegal VGPR to SGPR copy + +; CHECK: ; illegal copy v0 to s32 + +define i32 @move_to_valu_assert_srd_is_physreg_swdev503538(ptr addrspace(1) %ptr) { +entry: + %idx = load i32, ptr addrspace(1) %ptr, align 4 + %zero = extractelement <4 x i32> zeroinitializer, i32 %idx + %alloca = alloca [2048 x i8], i32 %zero, align 8, addrspace(5) + %ld = load i32, ptr addrspace(5) %alloca, align 8 + call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 2048, i1 false) + ret i32 %ld +} + +declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg) #0 + +attributes #0 = { nocallback nofree nounwind willreturn memory(argmem: write) } diff --git a/llvm/test/CodeGen/AMDGPU/umed3.ll b/llvm/test/CodeGen/AMDGPU/umed3.ll index 557d023c45f9..4726e81ceb8c 100644 --- a/llvm/test/CodeGen/AMDGPU/umed3.ll +++ b/llvm/test/CodeGen/AMDGPU/umed3.ll @@ -1,6 +1,8 @@ ; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-FAKE16 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11-TRUE16 %s declare i32 @llvm.amdgcn.workitem.id.x() #0 @@ -84,6 +86,8 @@ define amdgpu_kernel void @v_test_umed3_r_i_i_i64(ptr addrspace(1) %out, ptr add ; VI: v_max_u16_e32 [[MAX:v[0-9]]], 12, {{v[0-9]}} ; VI: v_min_u16_e32 {{v[0-9]}}, 17, [[MAX]] ; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +; GFX11-TRUE16: v_med3_u16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, 12, 17 +; GFX11-FAKE16: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 define amdgpu_kernel void @v_test_umed3_r_i_i_i16(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #1 { %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr i16, ptr addrspace(1) %aptr, i32 %tid @@ -707,6 +711,8 @@ bb: ; VI: v_max_u16 ; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_u16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_umed3_i16_pat_0(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: %tid = call i32 @llvm.amdgcn.workitem.id.x() @@ -728,6 +734,8 @@ bb: ; GCN-LABEL: {{^}}v_test_umed3_i16_pat_1: ; GFX9: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GFX11-TRUE16: v_med3_u16 v{{[0-9]+}}.l, v{{[0-9]+}}.l, v{{[0-9]+}}.h, v{{[0-9]+}}.l +; GFX11-FAKE16: v_med3_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} define amdgpu_kernel void @v_test_umed3_i16_pat_1(ptr addrspace(1) %arg, ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) #1 { bb: %tid = call i32 @llvm.amdgcn.workitem.id.x() diff --git a/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir new file mode 100644 index 000000000000..92c983e2bfd1 --- /dev/null +++ b/llvm/test/CodeGen/ARM/sink-store-pre-load-dependency.mir @@ -0,0 +1,41 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -o - %s -mtriple=armv7-- -run-pass=machine-sink | FileCheck %s + +name: sink-store-load-dep +tracksRegLiveness: true +stack: + - { id: 0, type: default, size: 8, alignment: 8 } +body: | + bb.0: + ; CHECK-LABEL: name: sink-store-load-dep + ; CHECK: bb.0: + ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 %stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32)) + ; CHECK-NEXT: [[MOVi:%[0-9]+]]:gpr = MOVi 55296, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[ADDri1:%[0-9]+]]:gpr = ADDri [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[LDRH:%[0-9]+]]:gpr = LDRH killed [[ADDri1:%[0-9]+]], $noreg, 0, 14 /* CC::al */, $noreg :: (load (s16)) + ; CHECK-NEXT: [[MOVi1:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: early-clobber %5:gpr = STRH_PRE [[MOVi:%[0-9]+]], [[LDRi12_:%[0-9]+]], [[MOVi1:%[0-9]+]], 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: [[SUBri:%.*]]:gpr = SUBri killed [[LDRi12_:%[0-9]+]], 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK: bb.2: + ; CHECK-NEXT: [[MOVi2:%[0-9]+]]:gpr = MOVi [[LDRH:%[0-9]+]], 14 /* CC::al */, $noreg, $noreg + %0:gpr = LDRi12 %stack.0, 0, 14, $noreg :: (load (s32)) + %1:gpr = MOVi 55296, 14, $noreg, $noreg + %2:gpr = ADDri %0:gpr, 0, 14, $noreg, $noreg + %3:gpr = LDRH killed %2:gpr, $noreg, 0, 14, $noreg :: (load (s16)) + %4:gpr = MOVi 0, 14, $noreg, $noreg + early-clobber %5:gpr = STRH_PRE %1:gpr, %0:gpr, %4:gpr, 0, 14, $noreg + %6:gpr = SUBri killed %0:gpr, 0, 14, $noreg, $noreg + CMPri %6:gpr, 0, 14, $noreg, implicit-def $cpsr + Bcc %bb.2, 3, $cpsr + B %bb.1 + + bb.1: + %8:gpr = MOVi 0, 14, $noreg, $noreg + $r0 = COPY %8:gpr + BX_RET 14, $noreg, implicit $r0 + + bb.2: + %9:gpr = MOVi %3:gpr, 14, $noreg, $noreg + $r0 = COPY %9:gpr + BX_RET 14, $noreg, implicit $r0 +... diff --git a/llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll b/llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll new file mode 100644 index 000000000000..501f15192d27 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/BufferLoad-sm61.ll @@ -0,0 +1,60 @@ +; RUN: opt -S -dxil-op-lower %s | FileCheck %s +; Before SM6.2 ByteAddressBuffer and StructuredBuffer lower to bufferLoad. + +target triple = "dxil-pc-shadermodel6.1-compute" + +; CHECK-LABEL: define void @loadf32_struct +define void @loadf32_struct(i32 %index) { + %buffer = call target("dx.RawBuffer", float, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 0) + %load = call {float, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_0_0_0t( + target("dx.RawBuffer", float, 0, 0, 0) %buffer, + i32 %index, + i32 0) + + ret void +} + +; CHECK-LABEL: define void @loadv4f32_byte +define void @loadv4f32_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle %{{.*}}, i32 %offset, i32 0) + %load = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_i8_0_0_0t( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, + i32 %offset, + i32 0) + + ret void +} + +; CHECK-LABEL: define void @loadnested +define void @loadnested(i32 %index) { + %buffer = call + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATAI32:%.*]] = call %dx.types.ResRet.i32 @dx.op.bufferLoad.i32(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 0) + %loadi32 = call {i32, i1} @llvm.dx.resource.load.rawbuffer.i32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 0) + + ; CHECK: [[DATAF32:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 4) + %loadf32 = call {<4 x float>, i1} @llvm.dx.resource.load.rawbuffer.v4f32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 4) + + ; CHECK: [[DATAF16:%.*]] = call %dx.types.ResRet.f16 @dx.op.bufferLoad.f16(i32 68, %dx.types.Handle %{{.*}}, i32 %index, i32 20) + %loadf16 = call {<3 x half>, i1} @llvm.dx.resource.load.rawbuffer.v3f16( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 20) + + ret void +} diff --git a/llvm/test/CodeGen/DirectX/BufferLoad.ll b/llvm/test/CodeGen/DirectX/BufferLoad.ll index 7f1291bf4a5c..86e2217a8e76 100644 --- a/llvm/test/CodeGen/DirectX/BufferLoad.ll +++ b/llvm/test/CodeGen/DirectX/BufferLoad.ll @@ -17,8 +17,9 @@ define void @loadv4f32() { ; CHECK-NOT: %dx.resource.casthandle ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load0 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 0) + %data0 = extractvalue {<4 x float>, i1} %load0, 0 ; The extract order depends on the users, so don't enforce that here. ; CHECK-DAG: [[VAL0_0:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 0 @@ -34,8 +35,9 @@ define void @loadv4f32() { call void @scalar_user(float %data0_2) ; CHECK: [[DATA4:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 4, i32 undef) - %data4 = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load4 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 4) + %data4 = extractvalue {<4 x float>, i1} %load4, 0 ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA4]], 0 ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA4]], 1 @@ -48,8 +50,9 @@ define void @loadv4f32() { call void @vector_user(<4 x float> %data4) ; CHECK: [[DATA12:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 12, i32 undef) - %data12 = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load12 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 12) + %data12 = extractvalue {<4 x float>, i1} %load12, 0 ; CHECK: [[DATA12_3:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA12]], 3 %data12_3 = extractelement <4 x float> %data12, i32 3 @@ -70,8 +73,9 @@ define void @index_dynamic(i32 %bufindex, i32 %elemindex) { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[LOAD:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 %bufindex, i32 undef) - %load = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 %bufindex) + %data = extractvalue {<4 x float>, i1} %load, 0 ; CHECK: [[ALLOCA:%.*]] = alloca [4 x float] ; CHECK: [[V0:%.*]] = extractvalue %dx.types.ResRet.f32 [[LOAD]], 0 @@ -89,10 +93,10 @@ define void @index_dynamic(i32 %bufindex, i32 %elemindex) { ; ; CHECK: [[PTR:%.*]] = getelementptr inbounds [4 x float], ptr [[ALLOCA]], i32 0, i32 %elemindex ; CHECK: [[X:%.*]] = load float, ptr [[PTR]] - %data = extractelement <4 x float> %load, i32 %elemindex + %x = extractelement <4 x float> %data, i32 %elemindex ; CHECK: call void @scalar_user(float [[X]]) - call void @scalar_user(float %data) + call void @scalar_user(float %x) ret void } @@ -105,8 +109,9 @@ define void @loadf32() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call float @llvm.dx.resource.load.typedbuffer( + %load0 = call {float, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", float, 0, 0, 0) %buffer, i32 0) + %data0 = extractvalue {float, i1} %load0, 0 ; CHECK: [[VAL0:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 0 ; CHECK: call void @scalar_user(float [[VAL0]]) @@ -123,7 +128,7 @@ define void @loadv2f32() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <2 x float> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<2 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <2 x float>, 0, 0, 0) %buffer, i32 0) ret void @@ -137,7 +142,7 @@ define void @loadv4f32_checkbit() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f32 @dx.op.bufferLoad.f32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call {<4 x float>, i1} @llvm.dx.resource.loadchecked.typedbuffer.f32( + %data0 = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer.f32( target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i32 0) ; CHECK: [[STATUS:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA0]], 4 @@ -158,7 +163,7 @@ define void @loadv4i32() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.i32 @dx.op.bufferLoad.i32(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x i32> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<4 x i32>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x i32>, 0, 0, 0) %buffer, i32 0) ret void @@ -172,7 +177,7 @@ define void @loadv4f16() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.f16 @dx.op.bufferLoad.f16(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x half> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<4 x half>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x half>, 0, 0, 0) %buffer, i32 0) ret void @@ -186,7 +191,7 @@ define void @loadv4i16() { i32 0, i32 0, i32 1, i32 0, i1 false) ; CHECK: [[DATA0:%.*]] = call %dx.types.ResRet.i16 @dx.op.bufferLoad.i16(i32 68, %dx.types.Handle [[HANDLE]], i32 0, i32 undef) - %data0 = call <4 x i16> @llvm.dx.resource.load.typedbuffer( + %data0 = call {<4 x i16>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x i16>, 0, 0, 0) %buffer, i32 0) ret void diff --git a/llvm/test/CodeGen/DirectX/HLSLControlFlowHint.ll b/llvm/test/CodeGen/DirectX/HLSLControlFlowHint.ll deleted file mode 100644 index fe66e481359b..000000000000 --- a/llvm/test/CodeGen/DirectX/HLSLControlFlowHint.ll +++ /dev/null @@ -1,98 +0,0 @@ -; RUN: opt -S -dxil-op-lower -dxil-translate-metadata -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s - -; This test make sure LLVM metadata is being translated into DXIL. - - -; CHECK: define i32 @test_branch(i32 %X) -; CHECK-NO: hlsl.controlflow.hint -; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_BRANCH:![0-9]+]] -define i32 @test_branch(i32 %X) { -entry: - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !0 - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} - - -; CHECK: define i32 @test_flatten(i32 %X) -; CHECK-NO: hlsl.controlflow.hint -; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_FLATTEN:![0-9]+]] -define i32 @test_flatten(i32 %X) { -entry: - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !1 - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} - - -; CHECK: define i32 @test_no_attr(i32 %X) -; CHECK-NO: hlsl.controlflow.hint -; CHECK-NO: !dx.controlflow.hints -define i32 @test_no_attr(i32 %X) { -entry: - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} -; CHECK-NO: hlsl.controlflow.hint -; CHECK: [[HINT_BRANCH]] = !{!"dx.controlflow.hints", i32 1} -; CHECK: [[HINT_FLATTEN]] = !{!"dx.controlflow.hints", i32 2} -!0 = !{!"hlsl.controlflow.hint", i32 1} -!1 = !{!"hlsl.controlflow.hint", i32 2} diff --git a/llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll b/llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll new file mode 100644 index 000000000000..b8a6649baf68 --- /dev/null +++ b/llvm/test/CodeGen/DirectX/RawBufferLoad-error64.ll @@ -0,0 +1,24 @@ +; We use llc for this test so that we don't abort after the first error. +; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s + +target triple = "dxil-pc-shadermodel6.2-compute" + +declare void @v4f64_user(<4 x double>) + +; Can't load 64 bit types directly until SM6.3 (byteaddressbuf.Load<int64_t4>) +; CHECK: error: +; CHECK-SAME: in function loadv4f64_byte +; CHECK-SAME: Cannot create RawBufferLoad operation: Invalid overload type +define void @loadv4f64_byte(i32 %offset) "hlsl.export" { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + %load = call {<4 x double>, i1} @llvm.dx.resource.load.rawbuffer.v4i64( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, i32 %offset, i32 0) + %data = extractvalue {<4 x double>, i1} %load, 0 + + call void @v4f64_user(<4 x double> %data) + + ret void +} diff --git a/llvm/test/CodeGen/DirectX/RawBufferLoad.ll b/llvm/test/CodeGen/DirectX/RawBufferLoad.ll new file mode 100644 index 000000000000..586b9c44e95d --- /dev/null +++ b/llvm/test/CodeGen/DirectX/RawBufferLoad.ll @@ -0,0 +1,232 @@ +; RUN: opt -S -dxil-op-lower %s | FileCheck %s + +target triple = "dxil-pc-shadermodel6.6-compute" + +declare void @f32_user(float) +declare void @v4f32_user(<4 x float>) +declare void @i32_user(i32) +declare void @v4i32_user(<4 x i32>) +declare void @v3f16_user(<3 x half>) +declare void @v4f64_user(<4 x double>) + +; CHECK-LABEL: define void @loadf32_struct +define void @loadf32_struct(i32 %index) { + %buffer = call target("dx.RawBuffer", float, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_f32_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 1, i32 4) + %load = call {float, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_f32_0_0_0t( + target("dx.RawBuffer", float, 0, 0, 0) %buffer, + i32 %index, + i32 0) + %data = extractvalue {float, i1} %load, 0 + + ; CHECK: [[VAL:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: call void @f32_user(float [[VAL]]) + call void @f32_user(float %data) + + ret void +} + +; CHECK-LABEL: define void @loadf32_byte +define void @loadf32_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %offset, i32 0, i8 1, i32 4) + %load = call {float, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_i8_0_0_0t( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, + i32 %offset, + i32 0) + %data = extractvalue {float, i1} %load, 0 + + ; CHECK: [[VAL:%.*]] = extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: call void @f32_user(float [[VAL]]) + call void @f32_user(float %data) + + ret void +} + +; CHECK-LABEL: define void @loadv4f32_struct +define void @loadv4f32_struct(i32 %index) { + %buffer = call target("dx.RawBuffer", <4 x float>, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4f32_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 15, i32 4) + %load = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_v4f32_0_0_0t( + target("dx.RawBuffer", <4 x float>, 0, 0, 0) %buffer, + i32 %index, + i32 0) + %data = extractvalue {<4 x float>, i1} %load, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %data) + + ret void +} + +; CHECK-LABEL: define void @loadv4f32_byte +define void @loadv4f32_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %offset, i32 0, i8 15, i32 4) + %load = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.f32.tdx.RawBuffer_i8_0_0_0t( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, + i32 %offset, + i32 0) + %data = extractvalue {<4 x float>, i1} %load, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATA]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %data) + + ret void +} + +; CHECK-LABEL: define void @loadelements +define void @loadelements(i32 %index) { + %buffer = call target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_sl_v4f32v4i32s_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATAF32:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 15, i32 4) + %loadf32 = call {<4 x float>, i1} + @llvm.dx.resource.load.rawbuffer.v4f32( + target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0, 0) %buffer, + i32 %index, + i32 0) + %dataf32 = extractvalue {<4 x float>, i1} %loadf32, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %dataf32) + + ; CHECK: [[DATAI32:%.*]] = call %dx.types.ResRet.i32 @dx.op.rawBufferLoad.i32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 1, i8 15, i32 4) + %loadi32 = call {<4 x i32>, i1} + @llvm.dx.resource.load.rawbuffer.v4i32( + target("dx.RawBuffer", {<4 x float>, <4 x i32>}, 0, 0, 0) %buffer, + i32 %index, + i32 1) + %datai32 = extractvalue {<4 x i32>, i1} %loadi32, 0 + + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 0 + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 1 + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 2 + ; CHECK: extractvalue %dx.types.ResRet.i32 [[DATAI32]], 3 + ; CHECK: insertelement <4 x i32> undef + ; CHECK: insertelement <4 x i32> + ; CHECK: insertelement <4 x i32> + ; CHECK: insertelement <4 x i32> + ; CHECK: call void @v4i32_user(<4 x i32> + call void @v4i32_user(<4 x i32> %datai32) + + ret void +} + +; CHECK-LABEL: define void @loadnested +define void @loadnested(i32 %index) { + %buffer = call + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) + @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATAI32:%.*]] = call %dx.types.ResRet.i32 @dx.op.rawBufferLoad.i32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 0, i8 1, i32 4) + %loadi32 = call {i32, i1} @llvm.dx.resource.load.rawbuffer.i32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 0) + %datai32 = extractvalue {i32, i1} %loadi32, 0 + + ; CHECK: [[VALI32:%.*]] = extractvalue %dx.types.ResRet.i32 [[DATAI32]], 0 + ; CHECK: call void @i32_user(i32 [[VALI32]]) + call void @i32_user(i32 %datai32) + + ; CHECK: [[DATAF32:%.*]] = call %dx.types.ResRet.f32 @dx.op.rawBufferLoad.f32(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 4, i8 15, i32 4) + %loadf32 = call {<4 x float>, i1} @llvm.dx.resource.load.rawbuffer.v4f32( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 4) + %dataf32 = extractvalue {<4 x float>, i1} %loadf32, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f32 [[DATAF32]], 3 + ; CHECK: insertelement <4 x float> undef + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: insertelement <4 x float> + ; CHECK: call void @v4f32_user(<4 x float> + call void @v4f32_user(<4 x float> %dataf32) + + ; CHECK: [[DATAF16:%.*]] = call %dx.types.ResRet.f16 @dx.op.rawBufferLoad.f16(i32 139, %dx.types.Handle %{{.*}}, i32 %index, i32 20, i8 7, i32 2) + %loadf16 = call {<3 x half>, i1} @llvm.dx.resource.load.rawbuffer.v3f16( + target("dx.RawBuffer", {i32, {<4 x float>, <3 x half>}}, 0, 0, 0) %buffer, + i32 %index, i32 20) + %dataf16 = extractvalue {<3 x half>, i1} %loadf16, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f16 [[DATAF16]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f16 [[DATAF16]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f16 [[DATAF16]], 2 + ; CHECK: insertelement <3 x half> undef + ; CHECK: insertelement <3 x half> + ; CHECK: insertelement <3 x half> + ; CHECK: call void @v3f16_user(<3 x half> + call void @v3f16_user(<3 x half> %dataf16) + + ret void +} + +; byteaddressbuf.Load<int64_t4> +; CHECK-LABEL: define void @loadv4f64_byte +define void @loadv4f64_byte(i32 %offset) { + %buffer = call target("dx.RawBuffer", i8, 0, 0, 0) + @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i8_0_0_0( + i32 0, i32 0, i32 1, i32 0, i1 false) + + ; CHECK: [[DATA:%.*]] = call %dx.types.ResRet.f64 @dx.op.rawBufferLoad.f64(i32 139, %dx.types.Handle %{{.*}}, i32 %offset, i32 0, i8 15, i32 8) + %load = call {<4 x double>, i1} @llvm.dx.resource.load.rawbuffer.v4i64( + target("dx.RawBuffer", i8, 0, 0, 0) %buffer, i32 %offset, i32 0) + %data = extractvalue {<4 x double>, i1} %load, 0 + + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 0 + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 1 + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 2 + ; CHECK: extractvalue %dx.types.ResRet.f64 [[DATA]], 3 + ; CHECK: insertelement <4 x double> undef + ; CHECK: insertelement <4 x double> + ; CHECK: insertelement <4 x double> + ; CHECK: insertelement <4 x double> + ; CHECK: call void @v4f64_user(<4 x double> + call void @v4f64_user(<4 x double> %data) + + ret void +} diff --git a/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll b/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll index 9b7e7fd04f60..8769e6ec66d8 100644 --- a/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll +++ b/llvm/test/CodeGen/DirectX/ResourceAccess/load_typedbuffer.ll @@ -15,17 +15,19 @@ define void @load_float4(i32 %index, i32 %elemindex) { %ptr = call ptr @llvm.dx.resource.getpointer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) %vec_data = load <4 x float>, ptr %ptr call void @use_float4(<4 x float> %vec_data) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 ; CHECK: extractelement <4 x float> %[[VALUE]], i32 1 %y_ptr = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 1 %y_data = load float, ptr %y_ptr call void @use_float(float %y_data) - ; CHECK: %[[VALUE:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VALUE:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 ; CHECK: extractelement <4 x float> %[[VALUE]], i32 %elemindex %dynamic = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 %elemindex %dyndata = load float, ptr %dynamic diff --git a/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll b/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll index 17606408cadf..0b7882ac722e 100644 --- a/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll +++ b/llvm/test/CodeGen/DirectX/ResourceAccess/store_typedbuffer.ll @@ -18,21 +18,24 @@ define void @store_float4(<4 x float> %data, i32 %index, i32 %elemindex) { ; Store just the .x component %scalar = extractelement <4 x float> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 0 + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[VEC]], float %scalar, i32 0 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) store float %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 1 + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[VEC]], float %scalar, i32 1 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 4 store float %scalar, ptr %y_ptr ; Store to one of the elements dynamically - ; CHECK: %[[LOAD:.*]] = call <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[LOAD]], float %scalar, i32 %elemindex + ; CHECK: %[[LOAD:.*]] = call { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x float>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x float> %[[VEC]], float %scalar, i32 %elemindex ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %buffer, i32 %index, <4 x float> %[[INSERT]]) %dynamic = getelementptr inbounds <4 x float>, ptr %ptr, i32 0, i32 %elemindex store float %scalar, ptr %dynamic @@ -56,14 +59,16 @@ define void @store_half4(<4 x half> %data, i32 %index) { ; Store just the .x component %scalar = extractelement <4 x half> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[LOAD]], half %scalar, i32 0 + ; CHECK: %[[LOAD:.*]] = call { <4 x half>, i1 } @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x half>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[VEC]], half %scalar, i32 0 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) store half %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <4 x half> @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[LOAD]], half %scalar, i32 1 + ; CHECK: %[[LOAD:.*]] = call { <4 x half>, i1 } @llvm.dx.resource.load.typedbuffer.v4f16.tdx.TypedBuffer_v4f16_1_0_0t(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <4 x half>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <4 x half> %[[VEC]], half %scalar, i32 1 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f16_1_0_0t.v4f16(target("dx.TypedBuffer", <4 x half>, 1, 0, 0) %buffer, i32 %index, <4 x half> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 2 store half %scalar, ptr %y_ptr @@ -87,14 +92,16 @@ define void @store_double2(<2 x double> %data, i32 %index) { ; Store just the .x component %scalar = extractelement <2 x double> %data, i32 0 - ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[LOAD]], double %scalar, i32 0 + ; CHECK: %[[LOAD:.*]] = call { <2 x double>, i1 } @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <2 x double>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[VEC]], double %scalar, i32 0 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) store double %scalar, ptr %ptr ; Store just the .y component - ; CHECK: %[[LOAD:.*]] = call <2 x double> @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) - ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[LOAD]], double %scalar, i32 1 + ; CHECK: %[[LOAD:.*]] = call { <2 x double>, i1 } @llvm.dx.resource.load.typedbuffer.v2f64.tdx.TypedBuffer_v2f64_1_0_0t(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index) + ; CHECK: %[[VEC:.*]] = extractvalue { <2 x double>, i1 } %[[LOAD]], 0 + ; CHECK: %[[INSERT:.*]] = insertelement <2 x double> %[[VEC]], double %scalar, i32 1 ; CHECK: call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v2f64_1_0_0t.v2f64(target("dx.TypedBuffer", <2 x double>, 1, 0, 0) %buffer, i32 %index, <2 x double> %[[INSERT]]) %y_ptr = getelementptr inbounds i8, ptr %ptr, i32 8 store double %scalar, ptr %y_ptr diff --git a/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll b/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll index c837b36a19e1..cd21adc11a9b 100644 --- a/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll +++ b/llvm/test/CodeGen/DirectX/ResourceGlobalElimination.ll @@ -29,18 +29,20 @@ entry: %0 = call i32 @llvm.dx.flattened.thread.id.in.group() ; CHECK-NOT: load {{.*}} ptr @In %1 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4 - ; CSE: call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t - %2 = call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %1, i32 %0) + ; CSE: call noundef { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t + %load = call noundef {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %1, i32 %0) + %2 = extractvalue {<4 x float>, i1} %load, 0 ; CHECK-NOT: load {{.*}} ptr @In %3 = load target("dx.TypedBuffer", <4 x float>, 1, 0, 0), ptr @In, align 4 - %4 = call noundef <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %3, i32 %0) + %load2 = call noundef {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %3, i32 %0) + %4 = extractvalue {<4 x float>, i1} %load2, 0 %add.i = fadd <4 x float> %2, %4 call void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %Out_h.i, i32 %0, <4 x float> %add.i) ; CHECK: ret void ret void } -; CSE-DAG: declare <4 x float> @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) [[ROAttr:#[0-9]+]] +; CSE-DAG: declare { <4 x float>, i1 } @llvm.dx.resource.load.typedbuffer.v4f32.tdx.TypedBuffer_v4f32_1_0_0t(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32) [[ROAttr:#[0-9]+]] ; CSE-DAG: declare void @llvm.dx.resource.store.typedbuffer.tdx.TypedBuffer_v4f32_1_0_0t.v4f32(target("dx.TypedBuffer", <4 x float>, 1, 0, 0), i32, <4 x float>) [[WOAttr:#[0-9]+]] attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="8,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll index 26223359dfdf..060d54f961c7 100644 --- a/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/typed-uav-load-additional-formats.ll @@ -17,8 +17,9 @@ target triple = "dxil-pc-shadermodel6.7-library" define <4 x float> @multicomponent() #0 { %res = call target("dx.TypedBuffer", <4 x float>, 1, 0, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) - %val = call <4 x float> @llvm.dx.resource.load.typedbuffer( + %load = call {<4 x float>, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", <4 x float>, 1, 0, 0) %res, i32 0) + %val = extractvalue {<4 x float>, i1} %load, 0 ret <4 x float> %val } @@ -26,8 +27,9 @@ define <4 x float> @multicomponent() #0 { define float @onecomponent() #0 { %res = call target("dx.TypedBuffer", float, 1, 0, 0) @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, i1 false) - %val = call float @llvm.dx.resource.load.typedbuffer( + %load = call {float, i1} @llvm.dx.resource.load.typedbuffer( target("dx.TypedBuffer", float, 1, 0, 0) %res, i32 0) + %val = extractvalue {float, i1} %load, 0 ret float %val } diff --git a/llvm/test/CodeGen/Hexagon/loopIdiom.ll b/llvm/test/CodeGen/Hexagon/loopIdiom.ll new file mode 100644 index 000000000000..9c3df674a493 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/loopIdiom.ll @@ -0,0 +1,75 @@ +; RUN: opt -debug -S -march=hexagon -O2 < %s | FileCheck %s +; REQUIRES: asserts +; CHECK: define dso_local void @complexMultAccum +target triple = "hexagon" + +; Function Attrs: noinline nounwind +define dso_local void @complexMultAccum(i32 noundef %n) #0 { +entry: + %n.addr = alloca i32, align 4 + %run_c_code = alloca i8, align 1 + %run_asm_code = alloca i8, align 1 + %iOutter = alloca i32, align 4 + %iOutter1 = alloca i32, align 4 + store i32 %n, ptr %n.addr, align 4 + store i8 1, ptr %run_c_code, align 1 + store i8 0, ptr %run_asm_code, align 1 + %0 = load i8, ptr %run_c_code, align 1 + %tobool = icmp ne i8 %0, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + store i32 0, ptr %iOutter, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %if.then + %1 = load i32, ptr %iOutter, align 4 + %cmp = icmp slt i32 %1, 2 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + br label %for.inc + +for.inc: ; preds = %for.body + %2 = load i32, ptr %iOutter, align 4 + %inc = add nsw i32 %2, 1 + store i32 %inc, ptr %iOutter, align 4 + br label %for.cond, !llvm.loop !3 + +for.end: ; preds = %for.cond + store i32 0, ptr %iOutter1, align 4 + br label %for.cond2 + +for.cond2: ; preds = %for.inc5, %for.end + %3 = load i32, ptr %iOutter1, align 4 + %cmp3 = icmp slt i32 %3, 2 + br i1 %cmp3, label %for.body4, label %for.end7 + +for.body4: ; preds = %for.cond2 + br label %for.inc5 + +for.inc5: ; preds = %for.body4 + %4 = load i32, ptr %iOutter1, align 4 + %inc6 = add nsw i32 %4, 1 + store i32 %inc6, ptr %iOutter1, align 4 + br label %for.cond2, !llvm.loop !5 + +for.end7: ; preds = %for.cond2 + br label %if.end + +if.end: ; preds = %for.end7, %entry + ret void +} + +attributes #0 = { noinline nounwind "approx-func-fp-math"="true" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv79" "target-features"="+v79,-long-calls" "unsafe-fp-math"="true" } + +!llvm.module.flags = !{!0, !1} +!llvm.ident = !{!2} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 7, !"frame-pointer", i32 2} +!2 = !{!"LLVM Clang"} +!3 = distinct !{!3, !4} +!4 = !{!"llvm.loop.mustprogress"} +!5 = distinct !{!5, !4} + diff --git a/llvm/test/CodeGen/NVPTX/b52037.ll b/llvm/test/CodeGen/NVPTX/b52037.ll index 5d1c390909f6..b6317dfb2859 100644 --- a/llvm/test/CodeGen/NVPTX/b52037.ll +++ b/llvm/test/CodeGen/NVPTX/b52037.ll @@ -39,7 +39,7 @@ declare %int3 @hoge(i32, i32, i32) local_unnamed_addr declare i64 @foo() local_unnamed_addr -define void @barney(ptr nocapture readonly %arg) local_unnamed_addr { +define ptx_kernel void @barney(ptr nocapture readonly %arg) local_unnamed_addr { bb: tail call void asm sideeffect "// KEEP", ""() #1 %tmp = alloca %struct.zot, align 16 @@ -210,9 +210,6 @@ bb14: ; preds = %bb49.i.lr.ph, %bb49 attributes #0 = { argmemonly mustprogress nofree nounwind willreturn } attributes #1 = { nounwind } -!nvvm.annotations = !{!0} - -!0 = !{ptr @barney, !"kernel", i32 1} !1 = !{!2, !11, i64 64} !2 = !{!"_ZTSN7cuneibs22neiblist_iterator_coreE", !3, i64 0, !3, i64 8, !6, i64 16, !8, i64 32, !9, i64 44, !10, i64 48, !11, i64 64, !9, i64 72, !4, i64 76, !9, i64 80} !3 = !{!"any pointer", !4, i64 0} diff --git a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll index 03cdeb9683ab..8be3a66b7f48 100644 --- a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll +++ b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll @@ -182,8 +182,8 @@ define <2 x bfloat> @test_fneg(<2 x bfloat> %a) #0 { ; CHECK-NEXT: .reg .b32 %r<3>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.u32 %r1, [test_fneg_param_0]; -; CHECK-NEXT: xor.b32 %r2, %r1, -2147450880; +; CHECK-NEXT: ld.param.b32 %r1, [test_fneg_param_0]; +; CHECK-NEXT: neg.bf16x2 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; %r = fneg <2 x bfloat> %a @@ -532,8 +532,8 @@ define <2 x bfloat> @test_fabs(<2 x bfloat> %a) #0 { ; CHECK-NEXT: .reg .b32 %r<3>; ; CHECK-EMPTY: ; CHECK-NEXT: // %bb.0: -; CHECK-NEXT: ld.param.u32 %r1, [test_fabs_param_0]; -; CHECK-NEXT: and.b32 %r2, %r1, 2147450879; +; CHECK-NEXT: ld.param.b32 %r1, [test_fabs_param_0]; +; CHECK-NEXT: abs.bf16x2 %r2, %r1; ; CHECK-NEXT: st.param.b32 [func_retval0], %r2; ; CHECK-NEXT: ret; %r = call <2 x bfloat> @llvm.fabs.f16(<2 x bfloat> %a) diff --git a/llvm/test/CodeGen/NVPTX/bug21465.ll b/llvm/test/CodeGen/NVPTX/bug21465.ll index 9b1f1049c648..76300e3cfdc5 100644 --- a/llvm/test/CodeGen/NVPTX/bug21465.ll +++ b/llvm/test/CodeGen/NVPTX/bug21465.ll @@ -8,7 +8,7 @@ target triple = "nvptx64-unknown-unknown" %struct.S = type { i32, i32 } ; Function Attrs: nounwind -define void @_Z11TakesStruct1SPi(ptr byval(%struct.S) nocapture readonly %input, ptr nocapture %output) #0 { +define ptx_kernel void @_Z11TakesStruct1SPi(ptr byval(%struct.S) nocapture readonly %input, ptr nocapture %output) #0 { entry: ; CHECK-LABEL: @_Z11TakesStruct1SPi ; PTX-LABEL: .visible .entry _Z11TakesStruct1SPi( @@ -23,7 +23,3 @@ entry: } attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - -!nvvm.annotations = !{!0} - -!0 = !{ptr @_Z11TakesStruct1SPi, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/bug22322.ll b/llvm/test/CodeGen/NVPTX/bug22322.ll index e3656fd16b21..ace31667184b 100644 --- a/llvm/test/CodeGen/NVPTX/bug22322.ll +++ b/llvm/test/CodeGen/NVPTX/bug22322.ll @@ -8,7 +8,7 @@ target triple = "nvptx64-nvidia-cuda" ; Function Attrs: nounwind ; CHECK-LABEL: some_kernel -define void @some_kernel(ptr nocapture %dst) #0 { +define ptx_kernel void @some_kernel(ptr nocapture %dst) #0 { _ZL11compute_vecRK6float3jb.exit: %ret_vec.sroa.8.i = alloca float, align 4 %0 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() @@ -55,8 +55,5 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "n attributes #1 = { nounwind readnone } attributes #2 = { nounwind } -!nvvm.annotations = !{!0} !llvm.ident = !{!1} - -!0 = !{ptr @some_kernel, !"kernel", i32 1} !1 = !{!"clang version 3.5.1 (tags/RELEASE_351/final)"} diff --git a/llvm/test/CodeGen/NVPTX/bug26185.ll b/llvm/test/CodeGen/NVPTX/bug26185.ll index 00c97fb381e0..193df7f86ca7 100644 --- a/llvm/test/CodeGen/NVPTX/bug26185.ll +++ b/llvm/test/CodeGen/NVPTX/bug26185.ll @@ -8,7 +8,7 @@ target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-unknown-unknown" ; CHECK-LABEL: ex_zext -define void @ex_zext(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_zext(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.u8 %val = load i8, ptr %data @@ -19,7 +19,7 @@ entry: } ; CHECK-LABEL: ex_sext -define void @ex_sext(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_sext(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.u8 %val = load i8, ptr %data @@ -30,7 +30,7 @@ entry: } ; CHECK-LABEL: ex_zext_v2 -define void @ex_zext_v2(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_zext_v2(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.v2.u8 %val = load <2 x i8>, ptr %data @@ -41,7 +41,7 @@ entry: } ; CHECK-LABEL: ex_sext_v2 -define void @ex_sext_v2(ptr noalias readonly %data, ptr %res) { +define ptx_kernel void @ex_sext_v2(ptr noalias readonly %data, ptr %res) { entry: ; CHECK: ld.global.nc.v2.u8 %val = load <2 x i8>, ptr %data @@ -51,8 +51,3 @@ entry: ret void } -!nvvm.annotations = !{!0,!1,!2,!3} -!0 = !{ptr @ex_zext, !"kernel", i32 1} -!1 = !{ptr @ex_sext, !"kernel", i32 1} -!2 = !{ptr @ex_zext_v2, !"kernel", i32 1} -!3 = !{ptr @ex_sext_v2, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll b/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll index 19f4ef8ec77b..1c9d271902fd 100644 --- a/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll +++ b/llvm/test/CodeGen/NVPTX/call-with-alloca-buffer.ll @@ -16,7 +16,7 @@ ; } ; CHECK: .visible .entry kernel_func -define void @kernel_func(ptr %a) { +define ptx_kernel void @kernel_func(ptr %a) { entry: %buf = alloca [16 x i8], align 4 @@ -56,7 +56,3 @@ entry: } declare void @callee(ptr, ptr) - -!nvvm.annotations = !{!0} - -!0 = !{ptr @kernel_func, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/cluster-dim.ll b/llvm/test/CodeGen/NVPTX/cluster-dim.ll index c9258addbe04..9275c895b224 100644 --- a/llvm/test/CodeGen/NVPTX/cluster-dim.ll +++ b/llvm/test/CodeGen/NVPTX/cluster-dim.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 | FileCheck -check-prefixes=CHECK90 %s ; RUN: %if ptxas-12.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 | %ptxas-verify -arch=sm_90 %} -define void @kernel_func_clusterxyz() { +define ptx_kernel void @kernel_func_clusterxyz() { ; CHECK80-LABEL: kernel_func_clusterxyz( ; CHECK80: { ; CHECK80-EMPTY: @@ -23,7 +23,6 @@ define void @kernel_func_clusterxyz() { } -!nvvm.annotations = !{!1, !2} +!nvvm.annotations = !{!1} -!1 = !{ptr @kernel_func_clusterxyz, !"kernel", i32 1} -!2 = !{ptr @kernel_func_clusterxyz, !"cluster_dim_x", i32 3, !"cluster_dim_y", i32 5, !"cluster_dim_z", i32 7} +!1 = !{ptr @kernel_func_clusterxyz, !"cluster_dim_x", i32 3, !"cluster_dim_y", i32 5, !"cluster_dim_z", i32 7} diff --git a/llvm/test/CodeGen/NVPTX/disjoint-or-addr.ll b/llvm/test/CodeGen/NVPTX/disjoint-or-addr.ll new file mode 100644 index 000000000000..1b1bb91d5c79 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/disjoint-or-addr.ll @@ -0,0 +1,25 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck %s +; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %} +target triple = "nvptx64-nvidia-cuda" + +@a = external global ptr align 16 + +define i32 @test_disjoint_or_addr(i16 %a) { +; CHECK-LABEL: test_disjoint_or_addr( +; CHECK: { +; CHECK-NEXT: .reg .b32 %r<2>; +; CHECK-NEXT: .reg .b64 %rd<3>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: mov.u64 %rd1, a; +; CHECK-NEXT: cvta.global.u64 %rd2, %rd1; +; CHECK-NEXT: ld.u32 %r1, [%rd2+8]; +; CHECK-NEXT: st.param.b32 [func_retval0], %r1; +; CHECK-NEXT: ret; + %a1 = ptrtoint ptr @a to i64 + %a2 = or disjoint i64 %a1, 8 + %a3 = inttoptr i64 %a2 to ptr + %v = load i32, ptr %a3 + ret i32 %v +} diff --git a/llvm/test/CodeGen/NVPTX/fabs-fneg-free.ll b/llvm/test/CodeGen/NVPTX/fabs-fneg-free.ll new file mode 100644 index 000000000000..9031f33939f2 --- /dev/null +++ b/llvm/test/CodeGen/NVPTX/fabs-fneg-free.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck %s +; RUN: %if ptxas %{ llc < %s -mtriple=nvptx64 -mcpu=sm_35 | %ptxas-verify %} +target triple = "nvptx64-nvidia-cuda" + +define float @fabs_free(i32 %in) { +; CHECK-LABEL: fabs_free( +; CHECK: { +; CHECK-NEXT: .reg .f32 %f<3>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.f32 %f1, [fabs_free_param_0]; +; CHECK-NEXT: abs.f32 %f2, %f1; +; CHECK-NEXT: st.param.f32 [func_retval0], %f2; +; CHECK-NEXT: ret; + %b = bitcast i32 %in to float + %f = call float @llvm.fabs.f32(float %b) + ret float %f +} + +define float @fneg_free(i32 %in) { +; CHECK-LABEL: fneg_free( +; CHECK: { +; CHECK-NEXT: .reg .f32 %f<3>; +; CHECK-EMPTY: +; CHECK-NEXT: // %bb.0: +; CHECK-NEXT: ld.param.f32 %f1, [fneg_free_param_0]; +; CHECK-NEXT: neg.f32 %f2, %f1; +; CHECK-NEXT: st.param.f32 [func_retval0], %f2; +; CHECK-NEXT: ret; + %b = bitcast i32 %in to float + %f = fneg float %b + ret float %f +} diff --git a/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll b/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll index 43e4dfca1456..2b6631154e38 100644 --- a/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll +++ b/llvm/test/CodeGen/NVPTX/generic-to-nvvm.ll @@ -12,7 +12,7 @@ target triple = "nvptx-nvidia-cuda" @myconst = internal constant i32 420, align 4 -define void @foo(ptr %a, ptr %b) { +define ptx_kernel void @foo(ptr %a, ptr %b) { ; Expect one load -- @myconst isn't loaded from, because we know its value ; statically. ; CHECK: ld.global.u32 @@ -24,7 +24,3 @@ define void @foo(ptr %a, ptr %b) { store i32 %ld2, ptr %b ret void } - - -!nvvm.annotations = !{!0} -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/i1-array-global.ll b/llvm/test/CodeGen/NVPTX/i1-array-global.ll index ff3848b6f8f7..20b376f94c0d 100644 --- a/llvm/test/CodeGen/NVPTX/i1-array-global.ll +++ b/llvm/test/CodeGen/NVPTX/i1-array-global.ll @@ -7,13 +7,9 @@ target triple = "nvptx-nvidia-cuda" @global_cst = private constant [6 x i1] [i1 true, i1 false, i1 true, i1 false, i1 true, i1 false] ; CHECK: .global .align 1 .b8 global_cst[6] = {1, 0, 1, 0, 1} -define void @kernel(i32 %i, ptr %out) { +define ptx_kernel void @kernel(i32 %i, ptr %out) { %5 = getelementptr inbounds i1, ptr @global_cst, i32 %i %6 = load i1, ptr %5, align 1 store i1 %6, ptr %out, align 1 ret void } - -!nvvm.annotations = !{!0} -!0 = !{ptr @kernel, !"kernel", i32 1} - diff --git a/llvm/test/CodeGen/NVPTX/i1-ext-load.ll b/llvm/test/CodeGen/NVPTX/i1-ext-load.ll index 83f8f80919f8..f5f1dd9fcf0e 100644 --- a/llvm/test/CodeGen/NVPTX/i1-ext-load.ll +++ b/llvm/test/CodeGen/NVPTX/i1-ext-load.ll @@ -5,7 +5,7 @@ target triple = "nvptx-nvidia-cuda" -define void @foo(ptr noalias readonly %ptr, ptr noalias %retval) { +define ptx_kernel void @foo(ptr noalias readonly %ptr, ptr noalias %retval) { ; CHECK-LABEL: foo( ; CHECK: .reg .b16 %rs<2>; ; CHECK: .reg .b32 %r<4>; @@ -28,7 +28,3 @@ define void @foo(ptr noalias readonly %ptr, ptr noalias %retval) { store i32 %and, ptr %retval ret void } - -!nvvm.annotations = !{!0} - -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/i1-global.ll b/llvm/test/CodeGen/NVPTX/i1-global.ll index 17af1fa29e6c..60d2ccd46419 100644 --- a/llvm/test/CodeGen/NVPTX/i1-global.ll +++ b/llvm/test/CodeGen/NVPTX/i1-global.ll @@ -8,13 +8,9 @@ target triple = "nvptx-nvidia-cuda" @mypred = addrspace(1) global i1 true, align 1 -define void @foo(i1 %p, ptr %out) { +define ptx_kernel void @foo(i1 %p, ptr %out) { %ld = load i1, ptr addrspace(1) @mypred %val = zext i1 %ld to i32 store i32 %val, ptr %out ret void } - - -!nvvm.annotations = !{!0} -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/i1-param.ll b/llvm/test/CodeGen/NVPTX/i1-param.ll index 3c74ee6aaa3b..14d417bca459 100644 --- a/llvm/test/CodeGen/NVPTX/i1-param.ll +++ b/llvm/test/CodeGen/NVPTX/i1-param.ll @@ -9,12 +9,8 @@ target triple = "nvptx-nvidia-cuda" ; CHECK: .entry foo ; CHECK: .param .u8 foo_param_0 ; CHECK: .param .u64 .ptr .align 1 foo_param_1 -define void @foo(i1 %p, ptr %out) { +define ptx_kernel void @foo(i1 %p, ptr %out) { %val = zext i1 %p to i32 store i32 %val, ptr %out ret void } - - -!nvvm.annotations = !{!0} -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/intr-range.ll b/llvm/test/CodeGen/NVPTX/intr-range.ll index 2f3e08a039f5..86776ab09efc 100644 --- a/llvm/test/CodeGen/NVPTX/intr-range.ll +++ b/llvm/test/CodeGen/NVPTX/intr-range.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-attributes --version 5 ; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -mcpu=sm_20 -passes=nvvm-intr-range | FileCheck %s -define i32 @test_maxntid() { -; CHECK-LABEL: define i32 @test_maxntid( +define ptx_kernel i32 @test_maxntid() { +; CHECK-LABEL: define ptx_kernel i32 @test_maxntid( ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 96) i32 @llvm.nvvm.read.ptx.sreg.tid.x() ; CHECK-NEXT: [[TMP3:%.*]] = call range(i32 0, 96) i32 @llvm.nvvm.read.ptx.sreg.tid.y() @@ -31,8 +31,8 @@ define i32 @test_maxntid() { ret i32 %11 } -define i32 @test_reqntid() { -; CHECK-LABEL: define i32 @test_reqntid( +define ptx_kernel i32 @test_reqntid() { +; CHECK-LABEL: define ptx_kernel i32 @test_reqntid( ; CHECK-SAME: ) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 20) i32 @llvm.nvvm.read.ptx.sreg.tid.x() ; CHECK-NEXT: [[TMP5:%.*]] = call range(i32 0, 20) i32 @llvm.nvvm.read.ptx.sreg.tid.y() @@ -64,8 +64,8 @@ define i32 @test_reqntid() { ;; A case like this could occur if a function with the sreg intrinsic was ;; inlined into a kernel where the tid metadata is present, ensure the range is ;; updated. -define i32 @test_inlined() { -; CHECK-LABEL: define i32 @test_inlined( +define ptx_kernel i32 @test_inlined() { +; CHECK-LABEL: define ptx_kernel i32 @test_inlined( ; CHECK-SAME: ) #[[ATTR0]] { ; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 4) i32 @llvm.nvvm.read.ptx.sreg.tid.x() ; CHECK-NEXT: ret i32 [[TMP1]] @@ -83,6 +83,6 @@ declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y() declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z() !nvvm.annotations = !{!0, !1, !2} -!0 = !{ptr @test_maxntid, !"kernel", i32 1, !"maxntidx", i32 32, !"maxntidz", i32 3} -!1 = !{ptr @test_reqntid, !"kernel", i32 1, !"reqntidx", i32 20} -!2 = !{ptr @test_inlined, !"kernel", i32 1, !"maxntidx", i32 4} +!0 = !{ptr @test_maxntid, !"maxntidx", i32 32, !"maxntidz", i32 3} +!1 = !{ptr @test_reqntid, !"reqntidx", i32 20} +!2 = !{ptr @test_inlined, !"maxntidx", i32 4} diff --git a/llvm/test/CodeGen/NVPTX/kernel-param-align.ll b/llvm/test/CodeGen/NVPTX/kernel-param-align.ll index 93d428d6fe6f..2889d2d89a85 100644 --- a/llvm/test/CodeGen/NVPTX/kernel-param-align.ll +++ b/llvm/test/CodeGen/NVPTX/kernel-param-align.ll @@ -10,7 +10,7 @@ ; CHECK: .param .u64 .ptr .shared .align 8 func_align_param_3 ; CHECK: .param .u64 .ptr .const .align 16 func_align_param_4 ; CHECK: .param .u64 .ptr .local .align 32 func_align_param_5 -define void @func_align(ptr nocapture readonly align 1 %input, +define ptx_kernel void @func_align(ptr nocapture readonly align 1 %input, ptr nocapture align 2 %out, ptr addrspace(1) align 4 %global, ptr addrspace(3) align 8 %shared, @@ -27,7 +27,7 @@ entry: ; CHECK: .param .u64 .ptr .shared .align 1 func_noalign_param_3 ; CHECK: .param .u64 .ptr .const .align 1 func_noalign_param_4 ; CHECK: .param .u64 .ptr .local .align 1 func_noalign_param_5 -define void @func_noalign(ptr nocapture readonly %input, +define ptx_kernel void @func_noalign(ptr nocapture readonly %input, ptr nocapture %out, ptr addrspace(1) %global, ptr addrspace(3) %shared, @@ -36,7 +36,3 @@ define void @func_noalign(ptr nocapture readonly %input, entry: ret void } - -!nvvm.annotations = !{!0, !1} -!0 = !{ptr @func_align, !"kernel", i32 1} -!1 = !{ptr @func_noalign, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll b/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll index bdaeccd53fac..dc1917f3b150 100644 --- a/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll +++ b/llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll @@ -10,7 +10,7 @@ target triple = "nvptx64-unknown-unknown" ; SM20: ld.global.f32 ; SM35-LABEL: .visible .entry foo1( ; SM35: ld.global.nc.f32 -define void @foo1(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo1(ptr noalias readonly %from, ptr %to) { %1 = load float, ptr %from store float %1, ptr %to ret void @@ -20,7 +20,7 @@ define void @foo1(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.f64 ; SM35-LABEL: .visible .entry foo2( ; SM35: ld.global.nc.f64 -define void @foo2(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo2(ptr noalias readonly %from, ptr %to) { %1 = load double, ptr %from store double %1, ptr %to ret void @@ -30,7 +30,7 @@ define void @foo2(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u16 ; SM35-LABEL: .visible .entry foo3( ; SM35: ld.global.nc.u16 -define void @foo3(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo3(ptr noalias readonly %from, ptr %to) { %1 = load i16, ptr %from store i16 %1, ptr %to ret void @@ -40,7 +40,7 @@ define void @foo3(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u32 ; SM35-LABEL: .visible .entry foo4( ; SM35: ld.global.nc.u32 -define void @foo4(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo4(ptr noalias readonly %from, ptr %to) { %1 = load i32, ptr %from store i32 %1, ptr %to ret void @@ -50,7 +50,7 @@ define void @foo4(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u64 ; SM35-LABEL: .visible .entry foo5( ; SM35: ld.global.nc.u64 -define void @foo5(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo5(ptr noalias readonly %from, ptr %to) { %1 = load i64, ptr %from store i64 %1, ptr %to ret void @@ -63,7 +63,7 @@ define void @foo5(ptr noalias readonly %from, ptr %to) { ; SM35-LABEL: .visible .entry foo6( ; SM35: ld.global.nc.u64 ; SM35: ld.global.nc.u64 -define void @foo6(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo6(ptr noalias readonly %from, ptr %to) { %1 = load i128, ptr %from store i128 %1, ptr %to ret void @@ -73,7 +73,7 @@ define void @foo6(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.u8 ; SM35-LABEL: .visible .entry foo7( ; SM35: ld.global.nc.v2.u8 -define void @foo7(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo7(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i8>, ptr %from store <2 x i8> %1, ptr %to ret void @@ -83,7 +83,7 @@ define void @foo7(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u32 ; SM35-LABEL: .visible .entry foo8( ; SM35: ld.global.nc.u32 -define void @foo8(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo8(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i16>, ptr %from store <2 x i16> %1, ptr %to ret void @@ -93,7 +93,7 @@ define void @foo8(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.u32 ; SM35-LABEL: .visible .entry foo9( ; SM35: ld.global.nc.v2.u32 -define void @foo9(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo9(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i32>, ptr %from store <2 x i32> %1, ptr %to ret void @@ -103,7 +103,7 @@ define void @foo9(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.u64 ; SM35-LABEL: .visible .entry foo10( ; SM35: ld.global.nc.v2.u64 -define void @foo10(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo10(ptr noalias readonly %from, ptr %to) { %1 = load <2 x i64>, ptr %from store <2 x i64> %1, ptr %to ret void @@ -113,7 +113,7 @@ define void @foo10(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.f32 ; SM35-LABEL: .visible .entry foo11( ; SM35: ld.global.nc.v2.f32 -define void @foo11(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo11(ptr noalias readonly %from, ptr %to) { %1 = load <2 x float>, ptr %from store <2 x float> %1, ptr %to ret void @@ -123,7 +123,7 @@ define void @foo11(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v2.f64 ; SM35-LABEL: .visible .entry foo12( ; SM35: ld.global.nc.v2.f64 -define void @foo12(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo12(ptr noalias readonly %from, ptr %to) { %1 = load <2 x double>, ptr %from store <2 x double> %1, ptr %to ret void @@ -133,7 +133,7 @@ define void @foo12(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u32 ; SM35-LABEL: .visible .entry foo13( ; SM35: ld.global.nc.u32 -define void @foo13(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo13(ptr noalias readonly %from, ptr %to) { %1 = load <4 x i8>, ptr %from store <4 x i8> %1, ptr %to ret void @@ -143,7 +143,7 @@ define void @foo13(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v4.u16 ; SM35-LABEL: .visible .entry foo14( ; SM35: ld.global.nc.v4.u16 -define void @foo14(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo14(ptr noalias readonly %from, ptr %to) { %1 = load <4 x i16>, ptr %from store <4 x i16> %1, ptr %to ret void @@ -153,7 +153,7 @@ define void @foo14(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v4.u32 ; SM35-LABEL: .visible .entry foo15( ; SM35: ld.global.nc.v4.u32 -define void @foo15(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo15(ptr noalias readonly %from, ptr %to) { %1 = load <4 x i32>, ptr %from store <4 x i32> %1, ptr %to ret void @@ -163,7 +163,7 @@ define void @foo15(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.v4.f32 ; SM35-LABEL: .visible .entry foo16( ; SM35: ld.global.nc.v4.f32 -define void @foo16(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo16(ptr noalias readonly %from, ptr %to) { %1 = load <4 x float>, ptr %from store <4 x float> %1, ptr %to ret void @@ -175,7 +175,7 @@ define void @foo16(ptr noalias readonly %from, ptr %to) { ; SM35-LABEL: .visible .entry foo17( ; SM35: ld.global.nc.v2.f64 ; SM35: ld.global.nc.v2.f64 -define void @foo17(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo17(ptr noalias readonly %from, ptr %to) { %1 = load <4 x double>, ptr %from store <4 x double> %1, ptr %to ret void @@ -185,7 +185,7 @@ define void @foo17(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.u64 ; SM35-LABEL: .visible .entry foo18( ; SM35: ld.global.nc.u64 -define void @foo18(ptr noalias readonly %from, ptr %to) { +define ptx_kernel void @foo18(ptr noalias readonly %from, ptr %to) { %1 = load ptr, ptr %from store ptr %1, ptr %to ret void @@ -196,7 +196,7 @@ define void @foo18(ptr noalias readonly %from, ptr %to) { ; SM20: ld.global.f32 ; SM35-LABEL: .visible .entry foo19( ; SM35: ld.global.nc.f32 -define void @foo19(ptr noalias readonly %from, ptr %to, i32 %n) { +define ptx_kernel void @foo19(ptr noalias readonly %from, ptr %to, i32 %n) { entry: br label %loop @@ -243,24 +243,3 @@ define void @notkernel2(ptr addrspace(1) noalias readonly %from, ptr %to) { store float %1, ptr %to ret void } - -!nvvm.annotations = !{!1 ,!2 ,!3 ,!4 ,!5 ,!6, !7 ,!8 ,!9 ,!10 ,!11 ,!12, !13, !14, !15, !16, !17, !18, !19} -!1 = !{ptr @foo1, !"kernel", i32 1} -!2 = !{ptr @foo2, !"kernel", i32 1} -!3 = !{ptr @foo3, !"kernel", i32 1} -!4 = !{ptr @foo4, !"kernel", i32 1} -!5 = !{ptr @foo5, !"kernel", i32 1} -!6 = !{ptr @foo6, !"kernel", i32 1} -!7 = !{ptr @foo7, !"kernel", i32 1} -!8 = !{ptr @foo8, !"kernel", i32 1} -!9 = !{ptr @foo9, !"kernel", i32 1} -!10 = !{ptr @foo10, !"kernel", i32 1} -!11 = !{ptr @foo11, !"kernel", i32 1} -!12 = !{ptr @foo12, !"kernel", i32 1} -!13 = !{ptr @foo13, !"kernel", i32 1} -!14 = !{ptr @foo14, !"kernel", i32 1} -!15 = !{ptr @foo15, !"kernel", i32 1} -!16 = !{ptr @foo16, !"kernel", i32 1} -!17 = !{ptr @foo17, !"kernel", i32 1} -!18 = !{ptr @foo18, !"kernel", i32 1} -!19 = !{ptr @foo19, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/local-stack-frame.ll b/llvm/test/CodeGen/NVPTX/local-stack-frame.ll index e42f2303cdf7..f21ff974a2c6 100644 --- a/llvm/test/CodeGen/NVPTX/local-stack-frame.ll +++ b/llvm/test/CodeGen/NVPTX/local-stack-frame.ll @@ -29,7 +29,7 @@ define void @foo(i32 %a) { ; PTX64: ld.param.u32 %r{{[0-9]+}}, [foo2_param_0]; ; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0; ; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}}; -define void @foo2(i32 %a) { +define ptx_kernel void @foo2(i32 %a) { %local = alloca i32, align 4 store i32 %a, ptr %local call void @bar(ptr %local) @@ -38,8 +38,6 @@ define void @foo2(i32 %a) { declare void @bar(ptr %a) -!nvvm.annotations = !{!0} -!0 = !{ptr @foo2, !"kernel", i32 1} ; PTX32: mov.u32 %SPL, __local_depot{{[0-9]+}}; ; PTX32-NOT: cvta.local.u32 %SP, %SPL; diff --git a/llvm/test/CodeGen/NVPTX/lower-alloca.ll b/llvm/test/CodeGen/NVPTX/lower-alloca.ll index 8f2d55151b31..530b48b3d3e3 100644 --- a/llvm/test/CodeGen/NVPTX/lower-alloca.ll +++ b/llvm/test/CodeGen/NVPTX/lower-alloca.ll @@ -6,7 +6,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" target triple = "nvptx64-unknown-unknown" -define void @kernel() { +define ptx_kernel void @kernel() { ; LABEL: @lower_alloca ; PTX-LABEL: .visible .entry kernel( %A = alloca i32 @@ -37,7 +37,5 @@ define void @alloca_in_explicit_local_as() { declare void @callee(ptr) declare void @callee_addrspace5(ptr addrspace(5)) -!nvvm.annotations = !{!0} !nvvm.annotations = !{!1} -!0 = !{ptr @kernel, !"kernel", i32 1} !1 = !{ptr @alloca_in_explicit_local_as, !"alloca_in_explicit_local_as", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll b/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll index 9cfe9192772b..208d4f0ef32a 100644 --- a/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll +++ b/llvm/test/CodeGen/NVPTX/lower-args-gridconstant.ll @@ -29,7 +29,7 @@ define dso_local noundef i32 @non_kernel_function(ptr nocapture noundef readonly ; PTX-NEXT: .reg .pred %p<2>; ; PTX-NEXT: .reg .b16 %rs<3>; ; PTX-NEXT: .reg .b32 %r<11>; -; PTX-NEXT: .reg .b64 %rd<10>; +; PTX-NEXT: .reg .b64 %rd<9>; ; PTX-EMPTY: ; PTX-NEXT: // %bb.0: // %entry ; PTX-NEXT: mov.u64 %SPL, __local_depot0; @@ -38,23 +38,22 @@ define dso_local noundef i32 @non_kernel_function(ptr nocapture noundef readonly ; PTX-NEXT: and.b16 %rs2, %rs1, 1; ; PTX-NEXT: setp.eq.b16 %p1, %rs2, 1; ; PTX-NEXT: ld.param.s32 %rd1, [non_kernel_function_param_2]; -; PTX-NEXT: add.u64 %rd2, %SP, 0; -; PTX-NEXT: or.b64 %rd3, %rd2, 8; -; PTX-NEXT: ld.param.u64 %rd4, [non_kernel_function_param_0+8]; -; PTX-NEXT: st.u64 [%rd3], %rd4; -; PTX-NEXT: ld.param.u64 %rd5, [non_kernel_function_param_0]; -; PTX-NEXT: st.u64 [%SP], %rd5; -; PTX-NEXT: mov.u64 %rd6, gi; -; PTX-NEXT: cvta.global.u64 %rd7, %rd6; -; PTX-NEXT: selp.b64 %rd8, %rd2, %rd7, %p1; -; PTX-NEXT: add.s64 %rd9, %rd8, %rd1; -; PTX-NEXT: ld.u8 %r1, [%rd9]; -; PTX-NEXT: ld.u8 %r2, [%rd9+1]; +; PTX-NEXT: ld.param.u64 %rd2, [non_kernel_function_param_0+8]; +; PTX-NEXT: st.u64 [%SP+8], %rd2; +; PTX-NEXT: ld.param.u64 %rd3, [non_kernel_function_param_0]; +; PTX-NEXT: st.u64 [%SP], %rd3; +; PTX-NEXT: mov.u64 %rd4, gi; +; PTX-NEXT: cvta.global.u64 %rd5, %rd4; +; PTX-NEXT: add.u64 %rd6, %SP, 0; +; PTX-NEXT: selp.b64 %rd7, %rd6, %rd5, %p1; +; PTX-NEXT: add.s64 %rd8, %rd7, %rd1; +; PTX-NEXT: ld.u8 %r1, [%rd8]; +; PTX-NEXT: ld.u8 %r2, [%rd8+1]; ; PTX-NEXT: shl.b32 %r3, %r2, 8; ; PTX-NEXT: or.b32 %r4, %r3, %r1; -; PTX-NEXT: ld.u8 %r5, [%rd9+2]; +; PTX-NEXT: ld.u8 %r5, [%rd8+2]; ; PTX-NEXT: shl.b32 %r6, %r5, 16; -; PTX-NEXT: ld.u8 %r7, [%rd9+3]; +; PTX-NEXT: ld.u8 %r7, [%rd8+3]; ; PTX-NEXT: shl.b32 %r8, %r7, 24; ; PTX-NEXT: or.b32 %r9, %r8, %r6; ; PTX-NEXT: or.b32 %r10, %r9, %r4; @@ -68,7 +67,7 @@ entry: ret i32 %0, !dbg !23 } -define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %out, i32 %n) { +define ptx_kernel void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %out, i32 %n) { ; PTX-LABEL: grid_const_int( ; PTX: { ; PTX-NEXT: .reg .b32 %r<4>; @@ -82,7 +81,7 @@ define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %ou ; PTX-NEXT: add.s32 %r3, %r2, %r1; ; PTX-NEXT: st.global.u32 [%rd2], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_int( +; OPT-LABEL: define ptx_kernel void @grid_const_int( ; OPT-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], i32 [[INPUT2:%.*]], ptr [[OUT:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUT2:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUT3:%.*]] = addrspacecast ptr addrspace(1) [[OUT2]] to ptr @@ -91,6 +90,7 @@ define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %ou ; OPT-NEXT: [[ADD:%.*]] = add i32 [[TMP]], [[INPUT2]] ; OPT-NEXT: store i32 [[ADD]], ptr [[OUT3]], align 4 ; OPT-NEXT: ret void +; %tmp = load i32, ptr %input1, align 4 %add = add i32 %tmp, %input2 store i32 %add, ptr %out @@ -99,7 +99,7 @@ define void @grid_const_int(ptr byval(i32) align 4 %input1, i32 %input2, ptr %ou %struct.s = type { i32, i32 } -define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ +define ptx_kernel void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ; PTX-LABEL: grid_const_struct( ; PTX: { ; PTX-NEXT: .reg .b32 %r<4>; @@ -113,7 +113,7 @@ define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ; PTX-NEXT: add.s32 %r3, %r1, %r2; ; PTX-NEXT: st.global.u32 [%rd2], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_struct( +; OPT-LABEL: define ptx_kernel void @grid_const_struct( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[OUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUT4:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUT5:%.*]] = addrspacecast ptr addrspace(1) [[OUT4]] to ptr @@ -125,6 +125,7 @@ define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ; OPT-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], [[TMP2]] ; OPT-NEXT: store i32 [[ADD]], ptr [[OUT5]], align 4 ; OPT-NEXT: ret void +; %gep1 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 0 %gep2 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 1 %int1 = load i32, ptr %gep1 @@ -134,7 +135,7 @@ define void @grid_const_struct(ptr byval(%struct.s) align 4 %input, ptr %out){ ret void } -define void @grid_const_escape(ptr byval(%struct.s) align 4 %input) { +define ptx_kernel void @grid_const_escape(ptr byval(%struct.s) align 4 %input) { ; PTX-LABEL: grid_const_escape( ; PTX: { ; PTX-NEXT: .reg .b32 %r<3>; @@ -159,17 +160,18 @@ define void @grid_const_escape(ptr byval(%struct.s) align 4 %input) { ; PTX-NEXT: ld.param.b32 %r1, [retval0]; ; PTX-NEXT: } // callseq 0 ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INPUT_PARAM:%.*]] = addrspacecast ptr [[INPUT]] to ptr addrspace(101) ; OPT-NEXT: [[INPUT_PARAM_GEN:%.*]] = call ptr @llvm.nvvm.ptr.param.to.gen.p0.p101(ptr addrspace(101) [[INPUT_PARAM]]) ; OPT-NEXT: [[CALL:%.*]] = call i32 @escape(ptr [[INPUT_PARAM_GEN]]) ; OPT-NEXT: ret void +; %call = call i32 @escape(ptr %input) ret void } -define void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 %a, ptr byval(i32) align 4 %b) { +define ptx_kernel void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 %a, ptr byval(i32) align 4 %b) { ; PTX-LABEL: multiple_grid_const_escape( ; PTX: { ; PTX-NEXT: .local .align 4 .b8 __local_depot4[4]; @@ -212,7 +214,7 @@ define void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 ; PTX-NEXT: ld.param.b32 %r2, [retval0]; ; PTX-NEXT: } // callseq 1 ; PTX-NEXT: ret; -; OPT-LABEL: define void @multiple_grid_const_escape( +; OPT-LABEL: define ptx_kernel void @multiple_grid_const_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], i32 [[A:%.*]], ptr byval(i32) align 4 [[B:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[B_PARAM:%.*]] = addrspacecast ptr [[B]] to ptr addrspace(101) ; OPT-NEXT: [[B_PARAM_GEN:%.*]] = call ptr @llvm.nvvm.ptr.param.to.gen.p0.p101(ptr addrspace(101) [[B_PARAM]]) @@ -222,13 +224,14 @@ define void @multiple_grid_const_escape(ptr byval(%struct.s) align 4 %input, i32 ; OPT-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 ; OPT-NEXT: [[CALL:%.*]] = call i32 @escape3(ptr [[INPUT_PARAM_GEN]], ptr [[A_ADDR]], ptr [[B_PARAM_GEN]]) ; OPT-NEXT: ret void +; %a.addr = alloca i32, align 4 store i32 %a, ptr %a.addr, align 4 %call = call i32 @escape3(ptr %input, ptr %a.addr, ptr %b) ret void } -define void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr %addr) { +define ptx_kernel void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr %addr) { ; PTX-LABEL: grid_const_memory_escape( ; PTX: { ; PTX-NEXT: .reg .b64 %rd<6>; @@ -241,7 +244,7 @@ define void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr % ; PTX-NEXT: cvta.param.u64 %rd5, %rd4; ; PTX-NEXT: st.global.u64 [%rd3], %rd5; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_memory_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_memory_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[ADDR:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[ADDR4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1) ; OPT-NEXT: [[ADDR5:%.*]] = addrspacecast ptr addrspace(1) [[ADDR4]] to ptr @@ -249,11 +252,12 @@ define void @grid_const_memory_escape(ptr byval(%struct.s) align 4 %input, ptr % ; OPT-NEXT: [[INPUT1:%.*]] = call ptr @llvm.nvvm.ptr.param.to.gen.p0.p101(ptr addrspace(101) [[INPUT_PARAM]]) ; OPT-NEXT: store ptr [[INPUT1]], ptr [[ADDR5]], align 8 ; OPT-NEXT: ret void +; store ptr %input, ptr %addr, align 8 ret void } -define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, ptr %result) { +define ptx_kernel void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, ptr %result) { ; PTX-LABEL: grid_const_inlineasm_escape( ; PTX: { ; PTX-NEXT: .reg .b64 %rd<8>; @@ -271,7 +275,7 @@ define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, pt ; PTX-NEXT: st.global.u64 [%rd6], %rd1; ; PTX-NEXT: ret; ; PTX-NOT .local -; OPT-LABEL: define void @grid_const_inlineasm_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_inlineasm_escape( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT:%.*]], ptr [[RESULT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[RESULT4:%.*]] = addrspacecast ptr [[RESULT]] to ptr addrspace(1) ; OPT-NEXT: [[RESULT5:%.*]] = addrspacecast ptr addrspace(1) [[RESULT4]] to ptr @@ -282,6 +286,7 @@ define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, pt ; OPT-NEXT: [[TMP2:%.*]] = call i64 asm "add.s64 $0, $1, $2 ; OPT-NEXT: store i64 [[TMP2]], ptr [[RESULT5]], align 8 ; OPT-NEXT: ret void +; %tmpptr1 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 0 %tmpptr2 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 1 %1 = call i64 asm "add.s64 $0, $1, $2;", "=l,l,l"(ptr %tmpptr1, ptr %tmpptr2) #1 @@ -289,7 +294,7 @@ define void @grid_const_inlineasm_escape(ptr byval(%struct.s) align 4 %input, pt ret void } -define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { +define ptx_kernel void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ; PTX-LABEL: grid_const_partial_escape( ; PTX: { ; PTX-NEXT: .reg .b32 %r<5>; @@ -319,7 +324,7 @@ define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ; PTX-NEXT: ld.param.b32 %r3, [retval0]; ; PTX-NEXT: } // callseq 2 ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_partial_escape( +; OPT-LABEL: define ptx_kernel void @grid_const_partial_escape( ; OPT-SAME: ptr byval(i32) [[INPUT:%.*]], ptr [[OUTPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUTPUT4:%.*]] = addrspacecast ptr [[OUTPUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUTPUT5:%.*]] = addrspacecast ptr addrspace(1) [[OUTPUT4]] to ptr @@ -330,6 +335,7 @@ define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ; OPT-NEXT: store i32 [[TWICE]], ptr [[OUTPUT5]], align 4 ; OPT-NEXT: [[CALL:%.*]] = call i32 @escape(ptr [[INPUT1_GEN]]) ; OPT-NEXT: ret void +; %val = load i32, ptr %input %twice = add i32 %val, %val store i32 %twice, ptr %output @@ -337,7 +343,7 @@ define void @grid_const_partial_escape(ptr byval(i32) %input, ptr %output) { ret void } -define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %output) { +define ptx_kernel i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %output) { ; PTX-LABEL: grid_const_partial_escapemem( ; PTX: { ; PTX-NEXT: .reg .b32 %r<6>; @@ -369,7 +375,7 @@ define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %outpu ; PTX-NEXT: } // callseq 3 ; PTX-NEXT: st.param.b32 [func_retval0], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define i32 @grid_const_partial_escapemem( +; OPT-LABEL: define ptx_kernel i32 @grid_const_partial_escapemem( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) [[INPUT:%.*]], ptr [[OUTPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[OUTPUT4:%.*]] = addrspacecast ptr [[OUTPUT]] to ptr addrspace(1) ; OPT-NEXT: [[OUTPUT5:%.*]] = addrspacecast ptr addrspace(1) [[OUTPUT4]] to ptr @@ -383,6 +389,7 @@ define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %outpu ; OPT-NEXT: [[ADD:%.*]] = add i32 [[VAL1]], [[VAL2]] ; OPT-NEXT: [[CALL2:%.*]] = call i32 @escape(ptr [[PTR1]]) ; OPT-NEXT: ret i32 [[ADD]] +; %ptr1 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 0 %val1 = load i32, ptr %ptr1 %ptr2 = getelementptr inbounds %struct.s, ptr %input, i32 0, i32 1 @@ -393,7 +400,7 @@ define i32 @grid_const_partial_escapemem(ptr byval(%struct.s) %input, ptr %outpu ret i32 %add } -define void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { +define ptx_kernel void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { ; PTX-LABEL: grid_const_phi( ; PTX: { ; PTX-NEXT: .reg .pred %p<2>; @@ -415,7 +422,7 @@ define void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { ; PTX-NEXT: ld.u32 %r2, [%rd8]; ; PTX-NEXT: st.global.u32 [%rd1], %r2; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_phi( +; OPT-LABEL: define ptx_kernel void @grid_const_phi( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) ; OPT-NEXT: [[INOUT2:%.*]] = addrspacecast ptr addrspace(1) [[INOUT1]] to ptr @@ -435,6 +442,7 @@ define void @grid_const_phi(ptr byval(%struct.s) align 4 %input1, ptr %inout) { ; OPT-NEXT: [[VALLOADED:%.*]] = load i32, ptr [[PTRNEW]], align 4 ; OPT-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; OPT-NEXT: ret void +; %val = load i32, ptr %inout %less = icmp slt i32 %val, 0 @@ -453,7 +461,7 @@ merge: } ; NOTE: %input2 is *not* grid_constant -define void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval(%struct.s) %input2, ptr %inout) { +define ptx_kernel void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval(%struct.s) %input2, ptr %inout) { ; PTX-LABEL: grid_const_phi_ngc( ; PTX: { ; PTX-NEXT: .reg .pred %p<2>; @@ -478,7 +486,7 @@ define void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval( ; PTX-NEXT: ld.u32 %r2, [%rd11]; ; PTX-NEXT: st.global.u32 [%rd1], %r2; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_phi_ngc( +; OPT-LABEL: define ptx_kernel void @grid_const_phi_ngc( ; OPT-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) ; OPT-NEXT: [[INOUT2:%.*]] = addrspacecast ptr addrspace(1) [[INOUT1]] to ptr @@ -500,6 +508,7 @@ define void @grid_const_phi_ngc(ptr byval(%struct.s) align 4 %input1, ptr byval( ; OPT-NEXT: [[VALLOADED:%.*]] = load i32, ptr [[PTRNEW]], align 4 ; OPT-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; OPT-NEXT: ret void +; %val = load i32, ptr %inout %less = icmp slt i32 %val, 0 br i1 %less, label %first, label %second @@ -517,7 +526,7 @@ merge: } ; NOTE: %input2 is *not* grid_constant -define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %inout) { +define ptx_kernel void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %inout) { ; PTX-LABEL: grid_const_select( ; PTX: { ; PTX-NEXT: .reg .pred %p<2>; @@ -539,7 +548,7 @@ define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; PTX-NEXT: ld.u32 %r2, [%rd9]; ; PTX-NEXT: st.global.u32 [%rd3], %r2; ; PTX-NEXT: ret; -; OPT-LABEL: define void @grid_const_select( +; OPT-LABEL: define ptx_kernel void @grid_const_select( ; OPT-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[INOUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) ; OPT-NEXT: [[INOUT2:%.*]] = addrspacecast ptr addrspace(1) [[INOUT1]] to ptr @@ -553,6 +562,7 @@ define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; OPT-NEXT: [[VALLOADED:%.*]] = load i32, ptr [[PTRNEW]], align 4 ; OPT-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; OPT-NEXT: ret void +; %val = load i32, ptr %inout %less = icmp slt i32 %val, 0 %ptrnew = select i1 %less, ptr %input1, ptr %input2 @@ -561,7 +571,7 @@ define void @grid_const_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ret void } -define i32 @grid_const_ptrtoint(ptr byval(i32) %input) { +define ptx_kernel i32 @grid_const_ptrtoint(ptr byval(i32) %input) { ; PTX-LABEL: grid_const_ptrtoint( ; PTX: { ; PTX-NEXT: .reg .b32 %r<4>; @@ -576,7 +586,7 @@ define i32 @grid_const_ptrtoint(ptr byval(i32) %input) { ; PTX-NEXT: add.s32 %r3, %r1, %r2; ; PTX-NEXT: st.param.b32 [func_retval0], %r3; ; PTX-NEXT: ret; -; OPT-LABEL: define i32 @grid_const_ptrtoint( +; OPT-LABEL: define ptx_kernel i32 @grid_const_ptrtoint( ; OPT-SAME: ptr byval(i32) align 4 [[INPUT:%.*]]) #[[ATTR0]] { ; OPT-NEXT: [[INPUT2:%.*]] = addrspacecast ptr [[INPUT]] to ptr addrspace(101) ; OPT-NEXT: [[INPUT3:%.*]] = load i32, ptr addrspace(101) [[INPUT2]], align 4 @@ -584,6 +594,7 @@ define i32 @grid_const_ptrtoint(ptr byval(i32) %input) { ; OPT-NEXT: [[PTRVAL:%.*]] = ptrtoint ptr [[INPUT1]] to i32 ; OPT-NEXT: [[KEEPALIVE:%.*]] = add i32 [[INPUT3]], [[PTRVAL]] ; OPT-NEXT: ret i32 [[KEEPALIVE]] +; %val = load i32, ptr %input %ptrval = ptrtoint ptr %input to i32 %keepalive = add i32 %val, %ptrval @@ -598,40 +609,40 @@ declare dso_local ptr @escape3(ptr, ptr, ptr) local_unnamed_addr !nvvm.annotations = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !20, !21, !22, !23} -!0 = !{ptr @grid_const_int, !"kernel", i32 1, !"grid_constant", !1} +!0 = !{ptr @grid_const_int, !"grid_constant", !1} !1 = !{i32 1} -!2 = !{ptr @grid_const_struct, !"kernel", i32 1, !"grid_constant", !3} +!2 = !{ptr @grid_const_struct, !"grid_constant", !3} !3 = !{i32 1} -!4 = !{ptr @grid_const_escape, !"kernel", i32 1, !"grid_constant", !5} +!4 = !{ptr @grid_const_escape, !"grid_constant", !5} !5 = !{i32 1} -!6 = !{ptr @multiple_grid_const_escape, !"kernel", i32 1, !"grid_constant", !7} +!6 = !{ptr @multiple_grid_const_escape, !"grid_constant", !7} !7 = !{i32 1, i32 3} -!8 = !{ptr @grid_const_memory_escape, !"kernel", i32 1, !"grid_constant", !9} +!8 = !{ptr @grid_const_memory_escape, !"grid_constant", !9} !9 = !{i32 1} -!10 = !{ptr @grid_const_inlineasm_escape, !"kernel", i32 1, !"grid_constant", !11} +!10 = !{ptr @grid_const_inlineasm_escape, !"grid_constant", !11} !11 = !{i32 1} -!12 = !{ptr @grid_const_partial_escape, !"kernel", i32 1, !"grid_constant", !13} +!12 = !{ptr @grid_const_partial_escape, !"grid_constant", !13} !13 = !{i32 1} -!14 = !{ptr @grid_const_partial_escapemem, !"kernel", i32 1, !"grid_constant", !15} +!14 = !{ptr @grid_const_partial_escapemem, !"grid_constant", !15} !15 = !{i32 1} -!16 = !{ptr @grid_const_phi, !"kernel", i32 1, !"grid_constant", !17} +!16 = !{ptr @grid_const_phi, !"grid_constant", !17} !17 = !{i32 1} -!18 = !{ptr @grid_const_phi_ngc, !"kernel", i32 1, !"grid_constant", !19} +!18 = !{ptr @grid_const_phi_ngc, !"grid_constant", !19} !19 = !{i32 1} -!20 = !{ptr @grid_const_select, !"kernel", i32 1, !"grid_constant", !21} +!20 = !{ptr @grid_const_select, !"grid_constant", !21} !21 = !{i32 1} -!22 = !{ptr @grid_const_ptrtoint, !"kernel", i32 1, !"grid_constant", !23} +!22 = !{ptr @grid_const_ptrtoint, !"grid_constant", !23} !23 = !{i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-args.ll b/llvm/test/CodeGen/NVPTX/lower-args.ll index eba4f273fa70..269bba75dc5f 100644 --- a/llvm/test/CodeGen/NVPTX/lower-args.ll +++ b/llvm/test/CodeGen/NVPTX/lower-args.ll @@ -65,7 +65,7 @@ define void @load_padding(ptr nocapture readonly byval(%class.padded) %arg) { } ; COMMON-LABEL: ptr_generic -define void @ptr_generic(ptr %out, ptr %in) { +define ptx_kernel void @ptr_generic(ptr %out, ptr %in) { ; IRC: %in3 = addrspacecast ptr %in to ptr addrspace(1) ; IRC: %in4 = addrspacecast ptr addrspace(1) %in3 to ptr ; IRC: %out1 = addrspacecast ptr %out to ptr addrspace(1) @@ -87,7 +87,7 @@ define void @ptr_generic(ptr %out, ptr %in) { } ; COMMON-LABEL: ptr_nongeneric -define void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { +define ptx_kernel void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { ; IR-NOT: addrspacecast ; PTX-NOT: cvta.to.global ; PTX: ld.const.u32 @@ -98,7 +98,7 @@ define void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { } ; COMMON-LABEL: ptr_as_int - define void @ptr_as_int(i64 noundef %i, i32 noundef %v) { + define ptx_kernel void @ptr_as_int(i64 noundef %i, i32 noundef %v) { ; IR: [[P:%.*]] = inttoptr i64 %i to ptr ; IRC: [[P1:%.*]] = addrspacecast ptr [[P]] to ptr addrspace(1) ; IRC: addrspacecast ptr addrspace(1) [[P1]] to ptr @@ -121,7 +121,7 @@ define void @ptr_nongeneric(ptr addrspace(1) %out, ptr addrspace(4) %in) { %struct.S = type { i64 } ; COMMON-LABEL: ptr_as_int_aggr -define void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) align 8 %s, i32 noundef %v) { +define ptx_kernel void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) align 8 %s, i32 noundef %v) { ; IR: [[S:%.*]] = addrspacecast ptr %s to ptr addrspace(101) ; IR: [[I:%.*]] = load i64, ptr addrspace(101) [[S]], align 8 ; IR: [[P0:%.*]] = inttoptr i64 [[I]] to ptr @@ -146,8 +146,3 @@ define void @ptr_as_int_aggr(ptr nocapture noundef readonly byval(%struct.S) ali ; Function Attrs: convergent nounwind declare dso_local ptr @escape(ptr) local_unnamed_addr -!nvvm.annotations = !{!0, !1, !2, !3} -!0 = !{ptr @ptr_generic, !"kernel", i32 1} -!1 = !{ptr @ptr_nongeneric, !"kernel", i32 1} -!2 = !{ptr @ptr_as_int, !"kernel", i32 1} -!3 = !{ptr @ptr_as_int_aggr, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-byval-args.ll b/llvm/test/CodeGen/NVPTX/lower-byval-args.ll index 5c52626a711f..26102722a483 100644 --- a/llvm/test/CodeGen/NVPTX/lower-byval-args.ll +++ b/llvm/test/CodeGen/NVPTX/lower-byval-args.ll @@ -24,8 +24,8 @@ declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture read declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2 ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only( +define dso_local ptx_kernel void @read_only(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -35,7 +35,7 @@ define dso_local void @read_only(ptr nocapture noundef writeonly %out, ptr nocap ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -45,7 +45,7 @@ define dso_local void @read_only(ptr nocapture noundef writeonly %out, ptr nocap ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only( +; COPY-LABEL: define dso_local ptx_kernel void @read_only( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -62,8 +62,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only_gep(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only_gep( +define dso_local ptx_kernel void @read_only_gep(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only_gep( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -74,7 +74,7 @@ define dso_local void @read_only_gep(ptr nocapture noundef writeonly %out, ptr n ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only_gep( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only_gep( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -85,7 +85,7 @@ define dso_local void @read_only_gep(ptr nocapture noundef writeonly %out, ptr n ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only_gep( +; COPY-LABEL: define dso_local ptx_kernel void @read_only_gep( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -104,8 +104,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only_gep_asc(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only_gep_asc( +define dso_local ptx_kernel void @read_only_gep_asc(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only_gep_asc( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -116,7 +116,7 @@ define dso_local void @read_only_gep_asc(ptr nocapture noundef writeonly %out, p ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only_gep_asc( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only_gep_asc( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -127,7 +127,7 @@ define dso_local void @read_only_gep_asc(ptr nocapture noundef writeonly %out, p ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only_gep_asc( +; COPY-LABEL: define dso_local ptx_kernel void @read_only_gep_asc( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -148,8 +148,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @read_only_gep_asc0( +define dso_local ptx_kernel void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @read_only_gep_asc0( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -164,7 +164,7 @@ define dso_local void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ; SM_60-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @read_only_gep_asc0( +; SM_70-LABEL: define dso_local ptx_kernel void @read_only_gep_asc0( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -179,7 +179,7 @@ define dso_local void @read_only_gep_asc0(ptr nocapture noundef writeonly %out, ; SM_70-NEXT: store i32 [[I]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @read_only_gep_asc0( +; COPY-LABEL: define dso_local ptx_kernel void @read_only_gep_asc0( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -202,8 +202,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr( +define dso_local ptx_kernel void @escape_ptr(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr( ; SM_60-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -214,7 +214,7 @@ define dso_local void @escape_ptr(ptr nocapture noundef readnone %out, ptr nound ; SM_60-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[S3]]) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr( ; SM_70-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -225,7 +225,7 @@ define dso_local void @escape_ptr(ptr nocapture noundef readnone %out, ptr nound ; SM_70-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[S3]]) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr( ; COPY-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -240,8 +240,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr_gep( +define dso_local ptx_kernel void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr_gep( ; SM_60-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -253,7 +253,7 @@ define dso_local void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr n ; SM_60-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[B]]) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr_gep( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr_gep( ; SM_70-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -265,7 +265,7 @@ define dso_local void @escape_ptr_gep(ptr nocapture noundef readnone %out, ptr n ; SM_70-NEXT: call void @_Z6escapePv(ptr noundef nonnull [[B]]) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr_gep( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr_gep( ; COPY-SAME: ptr nocapture noundef readnone [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -282,8 +282,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr_store( +define dso_local ptx_kernel void @escape_ptr_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr_store( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -294,7 +294,7 @@ define dso_local void @escape_ptr_store(ptr nocapture noundef writeonly %out, pt ; SM_60-NEXT: store ptr [[S3]], ptr [[OUT2]], align 8 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr_store( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr_store( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -305,7 +305,7 @@ define dso_local void @escape_ptr_store(ptr nocapture noundef writeonly %out, pt ; SM_70-NEXT: store ptr [[S3]], ptr [[OUT2]], align 8 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr_store( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr_store( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -320,8 +320,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptr_gep_store( +define dso_local ptx_kernel void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptr_gep_store( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -333,7 +333,7 @@ define dso_local void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out ; SM_60-NEXT: store ptr [[B]], ptr [[OUT2]], align 8 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptr_gep_store( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptr_gep_store( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -345,7 +345,7 @@ define dso_local void @escape_ptr_gep_store(ptr nocapture noundef writeonly %out ; SM_70-NEXT: store ptr [[B]], ptr [[OUT2]], align 8 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptr_gep_store( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptr_gep_store( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -362,8 +362,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @escape_ptrtoint( +define dso_local ptx_kernel void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr noundef byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @escape_ptrtoint( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -375,7 +375,7 @@ define dso_local void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr ; SM_60-NEXT: store i64 [[I]], ptr [[OUT2]], align 8 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @escape_ptrtoint( +; SM_70-LABEL: define dso_local ptx_kernel void @escape_ptrtoint( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -387,7 +387,7 @@ define dso_local void @escape_ptrtoint(ptr nocapture noundef writeonly %out, ptr ; SM_70-NEXT: store i64 [[I]], ptr [[OUT2]], align 8 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @escape_ptrtoint( +; COPY-LABEL: define dso_local ptx_kernel void @escape_ptrtoint( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -404,8 +404,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @memcpy_from_param(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @memcpy_from_param( +define dso_local ptx_kernel void @memcpy_from_param(ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @memcpy_from_param( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -414,7 +414,7 @@ define dso_local void @memcpy_from_param(ptr nocapture noundef writeonly %out, p ; SM_60-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @memcpy_from_param( +; SM_70-LABEL: define dso_local ptx_kernel void @memcpy_from_param( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -423,7 +423,7 @@ define dso_local void @memcpy_from_param(ptr nocapture noundef writeonly %out, p ; SM_70-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @memcpy_from_param( +; COPY-LABEL: define dso_local ptx_kernel void @memcpy_from_param( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -438,8 +438,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @memcpy_from_param_noalign (ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @memcpy_from_param_noalign( +define dso_local ptx_kernel void @memcpy_from_param_noalign (ptr nocapture noundef writeonly %out, ptr nocapture noundef readonly byval(%struct.S) %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @memcpy_from_param_noalign( ; SM_60-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -448,7 +448,7 @@ define dso_local void @memcpy_from_param_noalign (ptr nocapture noundef writeonl ; SM_60-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @memcpy_from_param_noalign( +; SM_70-LABEL: define dso_local ptx_kernel void @memcpy_from_param_noalign( ; SM_70-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(101) @@ -457,7 +457,7 @@ define dso_local void @memcpy_from_param_noalign (ptr nocapture noundef writeonl ; SM_70-NEXT: call void @llvm.memcpy.p0.p101.i64(ptr [[OUT2]], ptr addrspace(101) [[S3]], i64 16, i1 true) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @memcpy_from_param_noalign( +; COPY-LABEL: define dso_local ptx_kernel void @memcpy_from_param_noalign( ; COPY-SAME: ptr nocapture noundef writeonly [[OUT:%.*]], ptr nocapture noundef readonly byval([[STRUCT_S:%.*]]) [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 8 @@ -472,8 +472,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr nocapture noundef readnone byval(%struct.S) align 4 %s) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @memcpy_to_param( +define dso_local ptx_kernel void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr nocapture noundef readnone byval(%struct.S) align 4 %s) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @memcpy_to_param( ; SM_60-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef readnone byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[ENTRY:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -484,7 +484,7 @@ define dso_local void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr n ; SM_60-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[S3]], ptr [[IN2]], i64 16, i1 true) ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @memcpy_to_param( +; SM_70-LABEL: define dso_local ptx_kernel void @memcpy_to_param( ; SM_70-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef readnone byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[ENTRY:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -495,7 +495,7 @@ define dso_local void @memcpy_to_param(ptr nocapture noundef readonly %in, ptr n ; SM_70-NEXT: tail call void @llvm.memcpy.p0.p0.i64(ptr [[S3]], ptr [[IN2]], i64 16, i1 true) ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @memcpy_to_param( +; COPY-LABEL: define dso_local ptx_kernel void @memcpy_to_param( ; COPY-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef readnone byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[ENTRY:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -510,8 +510,8 @@ entry: } ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) -define dso_local void @copy_on_store(ptr nocapture noundef readonly %in, ptr nocapture noundef byval(%struct.S) align 4 %s, i1 noundef zeroext %b) local_unnamed_addr #0 { -; SM_60-LABEL: define dso_local void @copy_on_store( +define dso_local ptx_kernel void @copy_on_store(ptr nocapture noundef readonly %in, ptr nocapture noundef byval(%struct.S) align 4 %s, i1 noundef zeroext %b) local_unnamed_addr #0 { +; SM_60-LABEL: define dso_local ptx_kernel void @copy_on_store( ; SM_60-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]], i1 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -523,7 +523,7 @@ define dso_local void @copy_on_store(ptr nocapture noundef readonly %in, ptr noc ; SM_60-NEXT: store i32 [[I]], ptr [[S3]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define dso_local void @copy_on_store( +; SM_70-LABEL: define dso_local ptx_kernel void @copy_on_store( ; SM_70-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]], i1 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[S3:%.*]] = alloca [[STRUCT_S]], align 4 @@ -535,7 +535,7 @@ define dso_local void @copy_on_store(ptr nocapture noundef readonly %in, ptr noc ; SM_70-NEXT: store i32 [[I]], ptr [[S3]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define dso_local void @copy_on_store( +; COPY-LABEL: define dso_local ptx_kernel void @copy_on_store( ; COPY-SAME: ptr nocapture noundef readonly [[IN:%.*]], ptr nocapture noundef byval([[STRUCT_S:%.*]]) align 4 [[S:%.*]], i1 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[S1:%.*]] = alloca [[STRUCT_S]], align 4 @@ -551,8 +551,8 @@ bb: ret void } -define void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { -; SM_60-LABEL: define void @test_select( +define ptx_kernel void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { +; SM_60-LABEL: define ptx_kernel void @test_select( ; SM_60-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[OUT7:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -568,7 +568,7 @@ define void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ; SM_60-NEXT: store i32 [[VALLOADED]], ptr [[OUT8]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define void @test_select( +; SM_70-LABEL: define ptx_kernel void @test_select( ; SM_70-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[OUT1:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -582,7 +582,7 @@ define void @test_select(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ; SM_70-NEXT: store i32 [[VALLOADED]], ptr [[OUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define void @test_select( +; COPY-LABEL: define ptx_kernel void @test_select( ; COPY-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[INPUT23:%.*]] = alloca i32, align 4 @@ -603,8 +603,8 @@ bb: ret void } -define void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { -; SM_60-LABEL: define void @test_select_write( +define ptx_kernel void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %input2, ptr %out, i1 %cond) { +; SM_60-LABEL: define ptx_kernel void @test_select_write( ; SM_60-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[OUT5:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -619,7 +619,7 @@ define void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; SM_60-NEXT: store i32 1, ptr [[PTRNEW]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define void @test_select_write( +; SM_70-LABEL: define ptx_kernel void @test_select_write( ; SM_70-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[OUT5:%.*]] = addrspacecast ptr [[OUT]] to ptr addrspace(1) @@ -634,7 +634,7 @@ define void @test_select_write(ptr byval(i32) align 4 %input1, ptr byval(i32) %i ; SM_70-NEXT: store i32 1, ptr [[PTRNEW]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define void @test_select_write( +; COPY-LABEL: define ptx_kernel void @test_select_write( ; COPY-SAME: ptr byval(i32) align 4 [[INPUT1:%.*]], ptr byval(i32) [[INPUT2:%.*]], ptr [[OUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[INPUT23:%.*]] = alloca i32, align 4 @@ -653,8 +653,8 @@ bb: ret void } -define void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, ptr %inout, i1 %cond) { -; SM_60-LABEL: define void @test_phi( +define ptx_kernel void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, ptr %inout, i1 %cond) { +; SM_60-LABEL: define ptx_kernel void @test_phi( ; SM_60-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_60-NEXT: [[BB:.*:]] ; SM_60-NEXT: [[INOUT7:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) @@ -678,7 +678,7 @@ define void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) ; SM_60-NEXT: store i32 [[VALLOADED]], ptr [[INOUT8]], align 4 ; SM_60-NEXT: ret void ; -; SM_70-LABEL: define void @test_phi( +; SM_70-LABEL: define ptx_kernel void @test_phi( ; SM_70-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; SM_70-NEXT: [[BB:.*:]] ; SM_70-NEXT: [[INOUT1:%.*]] = addrspacecast ptr [[INOUT]] to ptr addrspace(1) @@ -700,7 +700,7 @@ define void @test_phi(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) ; SM_70-NEXT: store i32 [[VALLOADED]], ptr [[INOUT2]], align 4 ; SM_70-NEXT: ret void ; -; COPY-LABEL: define void @test_phi( +; COPY-LABEL: define ptx_kernel void @test_phi( ; COPY-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], ptr [[INOUT:%.*]], i1 [[COND:%.*]]) #[[ATTR3]] { ; COPY-NEXT: [[BB:.*:]] ; COPY-NEXT: [[INPUT23:%.*]] = alloca [[STRUCT_S]], align 8 @@ -740,8 +740,8 @@ merge: ; preds = %second, %first ret void } -define void @test_phi_write(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, i1 %cond) { -; COMMON-LABEL: define void @test_phi_write( +define ptx_kernel void @test_phi_write(ptr byval(%struct.S) align 4 %input1, ptr byval(%struct.S) %input2, i1 %cond) { +; COMMON-LABEL: define ptx_kernel void @test_phi_write( ; COMMON-SAME: ptr byval([[STRUCT_S:%.*]]) align 4 [[INPUT1:%.*]], ptr byval([[STRUCT_S]]) [[INPUT2:%.*]], i1 [[COND:%.*]]) #[[ATTR3:[0-9]+]] { ; COMMON-NEXT: [[BB:.*:]] ; COMMON-NEXT: [[INPUT24:%.*]] = alloca [[STRUCT_S]], align 8 @@ -784,29 +784,11 @@ attributes #1 = { nocallback nofree nounwind willreturn memory(argmem: readwrite attributes #2 = { nocallback nofree nounwind willreturn memory(argmem: write) } !llvm.module.flags = !{!0, !1, !2, !3} -!nvvm.annotations = !{!4, !5, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15, !16, !17, !18, !19, !23} !llvm.ident = !{!20, !21} !0 = !{i32 2, !"SDK Version", [2 x i32] [i32 11, i32 8]} !1 = !{i32 1, !"wchar_size", i32 4} !2 = !{i32 4, !"nvvm-reflect-ftz", i32 0} !3 = !{i32 7, !"frame-pointer", i32 2} -!4 = !{ptr @read_only, !"kernel", i32 1} -!5 = !{ptr @escape_ptr, !"kernel", i32 1} -!6 = !{ptr @escape_ptr_gep, !"kernel", i32 1} -!7 = !{ptr @escape_ptr_store, !"kernel", i32 1} -!8 = !{ptr @escape_ptr_gep_store, !"kernel", i32 1} -!9 = !{ptr @escape_ptrtoint, !"kernel", i32 1} -!10 = !{ptr @memcpy_from_param, !"kernel", i32 1} -!11 = !{ptr @memcpy_to_param, !"kernel", i32 1} -!12 = !{ptr @copy_on_store, !"kernel", i32 1} -!13 = !{ptr @read_only_gep, !"kernel", i32 1} -!14 = !{ptr @read_only_gep_asc, !"kernel", i32 1} -!15 = !{ptr @read_only_gep_asc0, !"kernel", i32 1} -!16 = !{ptr @test_select, !"kernel", i32 1} -!17 = !{ptr @test_phi, !"kernel", i32 1} -!18 = !{ptr @test_phi_write, !"kernel", i32 1} -!19 = !{ptr @test_select_write, !"kernel", i32 1} !20 = !{!"clang version 20.0.0git"} !21 = !{!"clang version 3.8.0 (tags/RELEASE_380/final)"} -!23 = !{ptr @memcpy_from_param_noalign, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll b/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll index f8b3b4b9b8c4..4ee1ca3ad4b1 100644 --- a/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll +++ b/llvm/test/CodeGen/NVPTX/lower-ctor-dtor.ll @@ -43,7 +43,7 @@ define internal void @bar() { ret void } -; CHECK-LABEL: define weak_odr void @"nvptx$device$init"() { +; CHECK-LABEL: define weak_odr ptx_kernel void @"nvptx$device$init"() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[BEGIN:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__init_array_start, align 8 ; CHECK-NEXT: [[STOP:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__init_array_end, align 8 @@ -60,7 +60,7 @@ define internal void @bar() { ; CHECK-NEXT: ret void ; ; -; CHECK-LABEL: define weak_odr void @"nvptx$device$fini"() { +; CHECK-LABEL: define weak_odr ptx_kernel void @"nvptx$device$fini"() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[BEGIN:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__fini_array_start, align 8 ; CHECK-NEXT: [[STOP:%.*]] = load ptr addrspace(1), ptr addrspace(1) @__fini_array_end, align 8 @@ -82,12 +82,10 @@ define internal void @bar() { ; CHECK: while.end: ; CHECK-NEXT: ret void -; CHECK: [[META0:![0-9]+]] = !{ptr @"nvptx$device$init", !"kernel", i32 1} ; CHECK: [[META1:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxntidx", i32 1} ; CHECK: [[META2:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxntidy", i32 1} ; CHECK: [[META3:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxntidz", i32 1} ; CHECK: [[META4:![0-9]+]] = !{ptr @"nvptx$device$init", !"maxclusterrank", i32 1} -; CHECK: [[META5:![0-9]+]] = !{ptr @"nvptx$device$fini", !"kernel", i32 1} ; CHECK: [[META6:![0-9]+]] = !{ptr @"nvptx$device$fini", !"maxntidx", i32 1} ; CHECK: [[META7:![0-9]+]] = !{ptr @"nvptx$device$fini", !"maxntidy", i32 1} ; CHECK: [[META8:![0-9]+]] = !{ptr @"nvptx$device$fini", !"maxntidz", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll b/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll index 9ec690a68e7e..2e64c2559481 100644 --- a/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll +++ b/llvm/test/CodeGen/NVPTX/lower-kernel-ptr-arg.ll @@ -6,7 +6,7 @@ target triple = "nvptx64-nvidia-cuda" ; Verify that both %input and %output are converted to global pointers and then ; addrspacecast'ed back to the original type. -define void @kernel(ptr %input, ptr %output) { +define ptx_kernel void @kernel(ptr %input, ptr %output) { ; CHECK-LABEL: .visible .entry kernel( ; CHECK: cvta.to.global.u64 ; CHECK: cvta.to.global.u64 @@ -17,7 +17,7 @@ define void @kernel(ptr %input, ptr %output) { ret void } -define void @kernel2(ptr addrspace(1) %input, ptr addrspace(1) %output) { +define ptx_kernel void @kernel2(ptr addrspace(1) %input, ptr addrspace(1) %output) { ; CHECK-LABEL: .visible .entry kernel2( ; CHECK-NOT: cvta.to.global.u64 %1 = load float, ptr addrspace(1) %input, align 4 @@ -29,7 +29,7 @@ define void @kernel2(ptr addrspace(1) %input, ptr addrspace(1) %output) { %struct.S = type { ptr, ptr } -define void @ptr_in_byval_kernel(ptr byval(%struct.S) %input, ptr %output) { +define ptx_kernel void @ptr_in_byval_kernel(ptr byval(%struct.S) %input, ptr %output) { ; CHECK-LABEL: .visible .entry ptr_in_byval_kernel( ; CHECK: ld.param.u64 %[[optr:rd.*]], [ptr_in_byval_kernel_param_1] ; CHECK: cvta.to.global.u64 %[[optr_g:.*]], %[[optr]]; @@ -60,7 +60,3 @@ define void @ptr_in_byval_func(ptr byval(%struct.S) %input, ptr %output) { ret void } -!nvvm.annotations = !{!0, !1, !2} -!0 = !{ptr @kernel, !"kernel", i32 1} -!1 = !{ptr @kernel2, !"kernel", i32 1} -!2 = !{ptr @ptr_in_byval_kernel, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/maxclusterrank.ll b/llvm/test/CodeGen/NVPTX/maxclusterrank.ll index 3389e090aac5..c445c34c1842 100644 --- a/llvm/test/CodeGen/NVPTX/maxclusterrank.ll +++ b/llvm/test/CodeGen/NVPTX/maxclusterrank.ll @@ -11,16 +11,15 @@ target triple = "nvptx64-unknown-unknown" ; Make sure that for SM version prior to 90 `.maxclusterrank` directive is ; sielently ignored. -define dso_local void @_Z18TestMaxClusterRankv() { +define dso_local ptx_kernel void @_Z18TestMaxClusterRankv() { entry: %a = alloca i32, align 4 store volatile i32 1, ptr %a, align 4 ret void } -!nvvm.annotations = !{!0, !1, !2, !3} +!nvvm.annotations = !{!1, !2, !3} -!0 = !{ptr @_Z18TestMaxClusterRankv, !"kernel", i32 1} !1 = !{ptr @_Z18TestMaxClusterRankv, !"maxntidx", i32 128} !2 = !{ptr @_Z18TestMaxClusterRankv, !"minctasm", i32 2} !3 = !{ptr @_Z18TestMaxClusterRankv, !"maxclusterrank", i32 8} diff --git a/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll b/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll index 2bc6d4cfa7f6..2a0c5ab7299b 100644 --- a/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll +++ b/llvm/test/CodeGen/NVPTX/noduplicate-syncthreads.ll @@ -66,7 +66,4 @@ if.end17: ; preds = %if.else13, %if.then } ; Function Attrs: noduplicate nounwind -declare void @llvm.nvvm.barrier0() #2 - -!0 = !{ptr @foo, !"kernel", i32 1} -!1 = !{null, !"align", i32 8} +declare void @llvm.nvvm.barrier0() #2
\ No newline at end of file diff --git a/llvm/test/CodeGen/NVPTX/noreturn.ll b/llvm/test/CodeGen/NVPTX/noreturn.ll index 2161d70a8852..6c11d0a9376a 100644 --- a/llvm/test/CodeGen/NVPTX/noreturn.ll +++ b/llvm/test/CodeGen/NVPTX/noreturn.ll @@ -27,7 +27,7 @@ define void @true_noreturn0() #0 { ; CHECK: .entry ignore_kernel_noreturn() ; CHECK-NOT: .noreturn -define void @ignore_kernel_noreturn() #0 { +define ptx_kernel void @ignore_kernel_noreturn() #0 { unreachable } @@ -35,7 +35,7 @@ define void @ignore_kernel_noreturn() #0 { ; CHECK: prototype_{{[0-9]+}} : .callprototype ()_ (.param .b32 _) .noreturn; ; CHECK: prototype_{{[0-9]+}} : .callprototype (.param .b32 _) _ (.param .b32 _); -define void @callprototype_noreturn(i32) { +define ptx_kernel void @callprototype_noreturn(i32) { %fn = load ptr, ptr addrspace(1) @function_pointer call void %fn(i32 %0) #0 %non_void = bitcast ptr %fn to ptr @@ -44,8 +44,3 @@ define void @callprototype_noreturn(i32) { } attributes #0 = { noreturn } - -!nvvm.annotations = !{!0, !1} - -!0 = !{ptr @ignore_kernel_noreturn, !"kernel", i32 1} -!1 = !{ptr @callprototype_noreturn, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll b/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll index 48162eaba257..9a78d31302e1 100644 --- a/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll +++ b/llvm/test/CodeGen/NVPTX/nvcl-param-align.ll @@ -3,7 +3,7 @@ target triple = "nvptx-unknown-nvcl" -define void @foo(i64 %img, i64 %sampler, ptr align 32 %v1, ptr %v2) { +define ptx_kernel void @foo(i64 %img, i64 %sampler, ptr align 32 %v1, ptr %v2) { ; The parameter alignment is determined by the align attribute (default 1). ; CHECK-LABEL: .entry foo( ; CHECK: .param .u64 .ptr .align 32 foo_param_2 @@ -11,7 +11,6 @@ define void @foo(i64 %img, i64 %sampler, ptr align 32 %v1, ptr %v2) { ret void } -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} +!nvvm.annotations = !{!2, !3} !2 = !{ptr @foo, !"rdoimage", i32 0} !3 = !{ptr @foo, !"sampler", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll index ac5875c6ab10..83cb3cde48de 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll @@ -1,9 +1,9 @@ ; Libdevice in recent CUDA versions relies on __CUDA_ARCH reflecting GPU type. ; Verify that __nvvm_reflect() is replaced with an appropriate value. ; -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_20 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_20 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM20 -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_35 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_35 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM35 @"$str" = private addrspace(1) constant [12 x i8] c"__CUDA_ARCH\00" diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll index 9d383218dce8..bf8d6e2cca30 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll @@ -1,8 +1,8 @@ ; Verify that __nvvm_reflect_ocl() is replaced with an appropriate value ; -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_20 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_20 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM20 -; RUN: opt %s -S -passes='default<O2>' -mtriple=nvptx64 -mcpu=sm_35 \ +; RUN: opt %s -S -passes='nvvm-reflect' -mtriple=nvptx64 -mcpu=sm_35 \ ; RUN: | FileCheck %s --check-prefixes=COMMON,SM35 @"$str" = private addrspace(4) constant [12 x i8] c"__CUDA_ARCH\00" diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll index 46ab79d9858c..19c74df30370 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll @@ -3,12 +3,12 @@ ; RUN: cat %s > %t.noftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz -; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK ; RUN: cat %s > %t.ftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz -; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK @str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00" @@ -43,7 +43,7 @@ exit: declare i32 @llvm.nvvm.reflect(ptr) -; CHECK-LABEL: define noundef i32 @intrinsic +; CHECK-LABEL: define i32 @intrinsic define i32 @intrinsic() { ; CHECK-NOT: call i32 @llvm.nvvm.reflect ; USE_FTZ_0: ret i32 0 diff --git a/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll b/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll index 2ed9f7c11bcf..244b44fea9b8 100644 --- a/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll +++ b/llvm/test/CodeGen/NVPTX/nvvm-reflect.ll @@ -3,12 +3,12 @@ ; RUN: cat %s > %t.noftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 0}' >> %t.noftz -; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.noftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_0 --check-prefix=CHECK ; RUN: cat %s > %t.ftz ; RUN: echo '!0 = !{i32 4, !"nvvm-reflect-ftz", i32 1}' >> %t.ftz -; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='default<O2>' \ +; RUN: opt %t.ftz -S -mtriple=nvptx-nvidia-cuda -passes='nvvm-reflect,simplifycfg' \ ; RUN: | FileCheck %s --check-prefix=USE_FTZ_1 --check-prefix=CHECK @str = private unnamed_addr addrspace(4) constant [11 x i8] c"__CUDA_FTZ\00" @@ -43,7 +43,8 @@ exit: declare i32 @llvm.nvvm.reflect(ptr) -; CHECK-LABEL: define noundef i32 @intrinsic +; CHECK-LABEL: define i32 @intrinsic + define i32 @intrinsic() { ; CHECK-NOT: call i32 @llvm.nvvm.reflect ; USE_FTZ_0: ret i32 0 diff --git a/llvm/test/CodeGen/NVPTX/refl1.ll b/llvm/test/CodeGen/NVPTX/refl1.ll index 34db3bb1a1a9..99b83f49ff9b 100644 --- a/llvm/test/CodeGen/NVPTX/refl1.ll +++ b/llvm/test/CodeGen/NVPTX/refl1.ll @@ -5,7 +5,7 @@ target triple = "nvptx-nvidia-cuda" ; Function Attrs: nounwind ; CHECK: .entry foo -define void @foo(ptr nocapture %a) #0 { +define ptx_kernel void @foo(ptr nocapture %a) #0 { %val = load float, ptr %a %tan = tail call fastcc float @__nv_fast_tanf(float %val) store float %tan, ptr %a @@ -34,7 +34,3 @@ entry: attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { alwaysinline inlinehint nounwind readnone } - -!nvvm.annotations = !{!0} - -!0 = !{ptr @foo, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/reg-copy.ll b/llvm/test/CodeGen/NVPTX/reg-copy.ll index f66ef195c625..20396c4cc69f 100644 --- a/llvm/test/CodeGen/NVPTX/reg-copy.ll +++ b/llvm/test/CodeGen/NVPTX/reg-copy.ll @@ -4,7 +4,7 @@ target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" target triple = "nvptx64-unknown-unknown" -define void @PR24303(ptr %f) { +define ptx_kernel void @PR24303(ptr %f) { ; CHECK-LABEL: .visible .entry PR24303( ; Do not use mov.f or mov.u to convert between float and int. ; CHECK-NOT: mov.{{f|u}}{{32|64}} %f{{[0-9]+}}, %r{{[0-9]+}} @@ -217,7 +217,3 @@ _ZN12cuda_builtinmlIfEENS_7complexIT_EERKS3_S5_.exit: ; preds = %if.then.93.i, % } declare float @llvm.nvvm.fabs.f(float) - -!nvvm.annotations = !{!0} - -!0 = !{ptr @PR24303, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/simple-call.ll b/llvm/test/CodeGen/NVPTX/simple-call.ll index 3580604d429d..991ae04b91b6 100644 --- a/llvm/test/CodeGen/NVPTX/simple-call.ll +++ b/llvm/test/CodeGen/NVPTX/simple-call.ll @@ -10,7 +10,7 @@ define float @device_func(float %a) noinline { } ; CHECK: .entry kernel_func -define void @kernel_func(ptr %a) { +define ptx_kernel void @kernel_func(ptr %a) { %val = load float, ptr %a ; CHECK: call.uni (retval0), ; CHECK: device_func, @@ -18,9 +18,3 @@ define void @kernel_func(ptr %a) { store float %mul, ptr %a ret void } - - - -!nvvm.annotations = !{!1} - -!1 = !{ptr @kernel_func, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll b/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll index 504dcdeb3370..7a7904a2f042 100644 --- a/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll +++ b/llvm/test/CodeGen/NVPTX/surf-read-cuda.ll @@ -10,7 +10,7 @@ declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32) declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1)) -define void @foo(i64 %img, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) { ; CHECK-LABEL: foo( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -34,7 +34,7 @@ define void @foo(i64 %img, ptr %red, i32 %idx) { @surf0 = internal addrspace(1) global i64 0, align 8 -define void @bar(ptr %red, i32 %idx) { +define ptx_kernel void @bar(ptr %red, i32 %idx) { ; CHECK-LABEL: bar( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -56,11 +56,5 @@ define void @bar(ptr %red, i32 %idx) { ret void } - - - -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @bar, !"kernel", i32 1} -!3 = !{ptr addrspace(1) @surf0, !"surface", i32 1} - +!nvvm.annotations = !{!1} +!1 = !{ptr addrspace(1) @surf0, !"surface", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/surf-read.ll b/llvm/test/CodeGen/NVPTX/surf-read.ll index e0cebd60d7dd..cd11b5617076 100644 --- a/llvm/test/CodeGen/NVPTX/surf-read.ll +++ b/llvm/test/CodeGen/NVPTX/surf-read.ll @@ -6,7 +6,7 @@ target triple = "nvptx64-unknown-nvcl" declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32) ; CHECK: .entry foo -define void @foo(i64 %img, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) { ; CHECK: suld.b.1d.b32.trap {%r[[RED:[0-9]+]]}, [foo_param_0, {%r{{[0-9]+}}}] %val = tail call i32 @llvm.nvvm.suld.1d.i32.trap(i64 %img, i32 %idx) ; CHECK: cvt.rn.f32.s32 %f[[REDF:[0-9]+]], %r[[RED]] @@ -16,6 +16,5 @@ define void @foo(i64 %img, ptr %red, i32 %idx) { ret void } -!nvvm.annotations = !{!1, !2} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @foo, !"rdwrimage", i32 0} +!nvvm.annotations = !{!1} +!1 = !{ptr @foo, !"rdwrimage", i32 0} diff --git a/llvm/test/CodeGen/NVPTX/surf-tex.py b/llvm/test/CodeGen/NVPTX/surf-tex.py index 9607a58856ba..90d67666f1ed 100644 --- a/llvm/test/CodeGen/NVPTX/surf-tex.py +++ b/llvm/test/CodeGen/NVPTX/surf-tex.py @@ -224,11 +224,6 @@ def get_ptx_surface(target): def get_surface_metadata(target, fun_ty, fun_name, has_surface_param): metadata = [] - md_kernel = '!{{{fun_ty} @{fun_name}, !"kernel", i32 1}}'.format( - fun_ty=fun_ty, fun_name=fun_name - ) - metadata.append(md_kernel) - if target == "cuda": # When a parameter is lowered as a .surfref, it still has the # corresponding ld.param.u64, which is illegal. Do not emit the @@ -263,14 +258,14 @@ def gen_suld_tests(target, global_surf): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} ${reg_ret}, [${reg_surf}, ${reg_access}] ; - define void @${test_name}_param(i64 %s, ${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %s, ${retty}* %ret, ${access}) { %val = tail call ${retty} @${intrinsic}(i64 %s, ${access}) store ${retty} %val, ${retty}* %ret ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} ${reg_ret}, [${global_surf}, ${reg_access}] - define void @${test_name}_global(${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_global(${retty}* %ret, ${access}) { %gs = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_surf}) %val = tail call ${retty} @${intrinsic}(i64 %gs, ${access}) store ${retty} %val, ${retty}* %ret @@ -356,13 +351,13 @@ def gen_sust_tests(target, global_surf): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} [${reg_surf}, ${reg_access}], ${reg_value} ; - define void @${test_name}_param(i64 %s, ${value}, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %s, ${value}, ${access}) { tail call void @${intrinsic}(i64 %s, ${access}, ${value}) ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} [${global_surf}, ${reg_access}], ${reg_value} - define void @${test_name}_global(${value}, ${access}) { + define ptx_kernel void @${test_name}_global(${value}, ${access}) { %gs = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_surf}) tail call void @${intrinsic}(i64 %gs, ${access}, ${value}) ret void @@ -420,19 +415,13 @@ def gen_sust_tests(target, global_surf): generated_items.append((params["intrinsic"], params["instruction"])) fun_name = test_name + "_param" - fun_ty = "void (i64, {value_ty}, {access_ty})*".format( - value_ty=get_llvm_value_type(vec, ctype), - access_ty=get_llvm_surface_access_type(geom), - ) + fun_ty = "ptr" generated_metadata += get_surface_metadata( target, fun_ty, fun_name, has_surface_param=True ) fun_name = test_name + "_global" - fun_ty = "void ({value_ty}, {access_ty})*".format( - value_ty=get_llvm_value_type(vec, ctype), - access_ty=get_llvm_surface_access_type(geom), - ) + fun_ty = "ptr" generated_metadata += get_surface_metadata( target, fun_ty, fun_name, has_surface_param=False ) @@ -559,11 +548,6 @@ def get_ptx_global_sampler(target, global_sampler): def get_texture_metadata(target, fun_ty, fun_name, has_texture_params): metadata = [] - md_kernel = '!{{{fun_ty} @{fun_name}, !"kernel", i32 1}}'.format( - fun_ty=fun_ty, fun_name=fun_name - ) - metadata.append(md_kernel) - if target == "cuda": # When a parameter is lowered as a .texref, it still has the # corresponding ld.param.u64, which is illegal. Do not emit the @@ -615,14 +599,14 @@ def gen_tex_tests(target, global_tex, global_sampler): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} ${ptx_ret}, [${ptx_tex}, ${ptx_access}] - define void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { %val = tail call ${retty} @${intrinsic}(i64 %tex, ${sampler} ${access}) store ${retty} %val, ${retty}* %ret ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} ${ptx_ret}, [${global_tex}, ${ptx_global_sampler} ${ptx_access}] - define void @${test_name}_global(${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_global(${retty}* %ret, ${access}) { %gt = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_tex}) ${get_sampler_handle} %val = tail call ${retty} @${intrinsic}(i64 %gt, ${sampler} ${access}) @@ -799,14 +783,14 @@ def gen_tld4_tests(target, global_tex, global_sampler): ; CHECK-LABEL: .entry ${test_name}_param ; CHECK: ${instruction} ${ptx_ret}, [${ptx_tex}, ${ptx_access}] - define void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_param(i64 %tex, ${sampler} ${retty}* %ret, ${access}) { %val = tail call ${retty} @${intrinsic}(i64 %tex, ${sampler} ${access}) store ${retty} %val, ${retty}* %ret ret void } ; CHECK-LABEL: .entry ${test_name}_global ; CHECK: ${instruction} ${ptx_ret}, [${global_tex}, ${ptx_global_sampler} ${ptx_access}] - define void @${test_name}_global(${retty}* %ret, ${access}) { + define ptx_kernel void @${test_name}_global(${retty}* %ret, ${access}) { %gt = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @${global_tex}) ${get_sampler_handle} %val = tail call ${retty} @${intrinsic}(i64 %gt, ${sampler} ${access}) diff --git a/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll b/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll index 881ea459feb4..5dc44cb1925b 100644 --- a/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll +++ b/llvm/test/CodeGen/NVPTX/surf-write-cuda.ll @@ -10,7 +10,7 @@ declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32) declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1)) -define void @foo(i64 %img, i32 %val, i32 %idx) { +define ptx_kernel void @foo(i64 %img, i32 %val, i32 %idx) { ; CHECK-LABEL: foo( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -30,7 +30,7 @@ define void @foo(i64 %img, i32 %val, i32 %idx) { @surf0 = internal addrspace(1) global i64 0, align 8 -define void @bar(i32 %val, i32 %idx) { +define ptx_kernel void @bar(i32 %val, i32 %idx) { ; CHECK-LABEL: bar( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<3>; @@ -47,8 +47,6 @@ define void @bar(i32 %val, i32 %idx) { } -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @bar, !"kernel", i32 1} -!3 = !{ptr addrspace(1) @surf0, !"surface", i32 1} +!nvvm.annotations = !{!1} +!1 = !{ptr addrspace(1) @surf0, !"surface", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/surf-write.ll b/llvm/test/CodeGen/NVPTX/surf-write.ll index 258bb6d8b5b7..0e1f0cc70099 100644 --- a/llvm/test/CodeGen/NVPTX/surf-write.ll +++ b/llvm/test/CodeGen/NVPTX/surf-write.ll @@ -6,12 +6,11 @@ target triple = "nvptx-unknown-nvcl" declare void @llvm.nvvm.sust.b.1d.i32.trap(i64, i32, i32) ; CHECK: .entry foo -define void @foo(i64 %img, i32 %val, i32 %idx) { +define ptx_kernel void @foo(i64 %img, i32 %val, i32 %idx) { ; CHECK: sust.b.1d.b32.trap [foo_param_0, {%r{{[0-9]+}}}], {%r{{[0-9]+}}} tail call void @llvm.nvvm.sust.b.1d.i32.trap(i64 %img, i32 %idx, i32 %val) ret void } -!nvvm.annotations = !{!1, !2} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @foo, !"wroimage", i32 0} +!nvvm.annotations = !{!1} +!1 = !{ptr @foo, !"wroimage", i32 0} diff --git a/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll b/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll index ba556d2d9bd6..61837bde82ec 100644 --- a/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll +++ b/llvm/test/CodeGen/NVPTX/tex-read-cuda.ll @@ -10,7 +10,7 @@ target triple = "nvptx-unknown-cuda" declare { float, float, float, float } @llvm.nvvm.tex.unified.1d.v4f32.s32(i64, i32) declare i64 @llvm.nvvm.texsurf.handle.internal.p1(ptr addrspace(1)) -define void @foo(i64 %img, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, ptr %red, i32 %idx) { ; CHECK-LABEL: foo( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<2>; @@ -34,7 +34,7 @@ define void @foo(i64 %img, ptr %red, i32 %idx) { @tex0 = internal addrspace(1) global i64 0, align 8 -define void @bar(ptr %red, i32 %idx) { +define ptx_kernel void @bar(ptr %red, i32 %idx) { ; CHECK-LABEL: bar( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<2>; @@ -57,7 +57,7 @@ define void @bar(ptr %red, i32 %idx) { declare float @texfunc(i64) -define void @baz(ptr %red, i32 %idx) { +define ptx_kernel void @baz(ptr %red, i32 %idx) { ; CHECK-LABEL: baz( ; CHECK: { ; CHECK-NEXT: .reg .b32 %r<2>; @@ -93,8 +93,5 @@ define void @baz(ptr %red, i32 %idx) { ret void } -!nvvm.annotations = !{!1, !2, !3, !4} -!1 = !{ptr @foo, !"kernel", i32 1} -!2 = !{ptr @bar, !"kernel", i32 1} -!3 = !{ptr addrspace(1) @tex0, !"texture", i32 1} -!4 = !{ptr @baz, !"kernel", i32 1} +!nvvm.annotations = !{!1} +!1 = !{ptr addrspace(1) @tex0, !"texture", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/tex-read.ll b/llvm/test/CodeGen/NVPTX/tex-read.ll index d11aea45a65f..d74c89f5abc8 100644 --- a/llvm/test/CodeGen/NVPTX/tex-read.ll +++ b/llvm/test/CodeGen/NVPTX/tex-read.ll @@ -6,7 +6,7 @@ target triple = "nvptx64-unknown-nvcl" declare { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64, i64, i32) ; CHECK: .entry foo -define void @foo(i64 %img, i64 %sampler, ptr %red, i32 %idx) { +define ptx_kernel void @foo(i64 %img, i64 %sampler, ptr %red, i32 %idx) { ; CHECK: tex.1d.v4.f32.s32 {%f[[RED:[0-9]+]], %f[[GREEN:[0-9]+]], %f[[BLUE:[0-9]+]], %f[[ALPHA:[0-9]+]]}, [foo_param_0, foo_param_1, {%r{{[0-9]+}}}] %val = tail call { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64 %img, i64 %sampler, i32 %idx) %ret = extractvalue { float, float, float, float } %val, 0 @@ -15,7 +15,6 @@ define void @foo(i64 %img, i64 %sampler, ptr %red, i32 %idx) { ret void } -!nvvm.annotations = !{!1, !2, !3} -!1 = !{ptr @foo, !"kernel", i32 1} +!nvvm.annotations = !{!2, !3} !2 = !{ptr @foo, !"rdoimage", i32 0} !3 = !{ptr @foo, !"sampler", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/unreachable.ll b/llvm/test/CodeGen/NVPTX/unreachable.ll index 286f3588a754..80cf938d48b5 100644 --- a/llvm/test/CodeGen/NVPTX/unreachable.ll +++ b/llvm/test/CodeGen/NVPTX/unreachable.ll @@ -21,7 +21,7 @@ target triple = "nvptx-unknown-cuda" declare void @throw() #0 declare void @llvm.trap() #0 -define void @kernel_func() { +define ptx_kernel void @kernel_func() { ; NO-TRAP-UNREACHABLE-LABEL: kernel_func( ; NO-TRAP-UNREACHABLE: { ; NO-TRAP-UNREACHABLE-EMPTY: @@ -102,6 +102,3 @@ define void @kernel_func_2() { } attributes #0 = { noreturn } - -!nvvm.annotations = !{!1} -!1 = !{ptr @kernel_func, !"kernel", i32 1} diff --git a/llvm/test/CodeGen/NVPTX/variadics-backend.ll b/llvm/test/CodeGen/NVPTX/variadics-backend.ll index cb54812dea6d..f7ed690efabc 100644 --- a/llvm/test/CodeGen/NVPTX/variadics-backend.ll +++ b/llvm/test/CodeGen/NVPTX/variadics-backend.ll @@ -153,7 +153,7 @@ define dso_local i32 @variadics2(i32 noundef %first, ...) { ; CHECK-PTX-NEXT: .reg .b64 %SPL; ; CHECK-PTX-NEXT: .reg .b16 %rs<6>; ; CHECK-PTX-NEXT: .reg .b32 %r<7>; -; CHECK-PTX-NEXT: .reg .b64 %rd<11>; +; CHECK-PTX-NEXT: .reg .b64 %rd<7>; ; CHECK-PTX-EMPTY: ; CHECK-PTX-NEXT: // %bb.0: // %entry ; CHECK-PTX-NEXT: mov.u64 %SPL, __local_depot2; @@ -163,24 +163,20 @@ define dso_local i32 @variadics2(i32 noundef %first, ...) { ; CHECK-PTX-NEXT: add.s64 %rd2, %rd1, 7; ; CHECK-PTX-NEXT: and.b64 %rd3, %rd2, -8; ; CHECK-PTX-NEXT: ld.u32 %r2, [%rd3]; -; CHECK-PTX-NEXT: or.b64 %rd4, %rd3, 4; -; CHECK-PTX-NEXT: ld.s8 %r3, [%rd4]; -; CHECK-PTX-NEXT: or.b64 %rd5, %rd3, 5; -; CHECK-PTX-NEXT: or.b64 %rd6, %rd3, 7; -; CHECK-PTX-NEXT: ld.u8 %rs1, [%rd6]; +; CHECK-PTX-NEXT: ld.s8 %r3, [%rd3+4]; +; CHECK-PTX-NEXT: ld.u8 %rs1, [%rd3+7]; ; CHECK-PTX-NEXT: st.u8 [%SP+2], %rs1; -; CHECK-PTX-NEXT: ld.u8 %rs2, [%rd5]; -; CHECK-PTX-NEXT: or.b64 %rd7, %rd3, 6; -; CHECK-PTX-NEXT: ld.u8 %rs3, [%rd7]; +; CHECK-PTX-NEXT: ld.u8 %rs2, [%rd3+5]; +; CHECK-PTX-NEXT: ld.u8 %rs3, [%rd3+6]; ; CHECK-PTX-NEXT: shl.b16 %rs4, %rs3, 8; ; CHECK-PTX-NEXT: or.b16 %rs5, %rs4, %rs2; ; CHECK-PTX-NEXT: st.u16 [%SP], %rs5; -; CHECK-PTX-NEXT: ld.u64 %rd8, [%rd3+8]; +; CHECK-PTX-NEXT: ld.u64 %rd4, [%rd3+8]; ; CHECK-PTX-NEXT: add.s32 %r4, %r1, %r2; ; CHECK-PTX-NEXT: add.s32 %r5, %r4, %r3; -; CHECK-PTX-NEXT: cvt.u64.u32 %rd9, %r5; -; CHECK-PTX-NEXT: add.s64 %rd10, %rd9, %rd8; -; CHECK-PTX-NEXT: cvt.u32.u64 %r6, %rd10; +; CHECK-PTX-NEXT: cvt.u64.u32 %rd5, %r5; +; CHECK-PTX-NEXT: add.s64 %rd6, %rd5, %rd4; +; CHECK-PTX-NEXT: cvt.u32.u64 %r6, %rd6; ; CHECK-PTX-NEXT: st.param.b32 [func_retval0], %r6; ; CHECK-PTX-NEXT: ret; entry: @@ -219,7 +215,7 @@ define dso_local i32 @bar() { ; CHECK-PTX-NEXT: .reg .b64 %SPL; ; CHECK-PTX-NEXT: .reg .b16 %rs<10>; ; CHECK-PTX-NEXT: .reg .b32 %r<4>; -; CHECK-PTX-NEXT: .reg .b64 %rd<8>; +; CHECK-PTX-NEXT: .reg .b64 %rd<7>; ; CHECK-PTX-EMPTY: ; CHECK-PTX-NEXT: // %bb.0: // %entry ; CHECK-PTX-NEXT: mov.u64 %SPL, __local_depot3; @@ -240,17 +236,16 @@ define dso_local i32 @bar() { ; CHECK-PTX-NEXT: st.u16 [%SP], %rs8; ; CHECK-PTX-NEXT: mov.b32 %r1, 1; ; CHECK-PTX-NEXT: st.u32 [%SP+8], %r1; -; CHECK-PTX-NEXT: add.u64 %rd5, %SP, 8; -; CHECK-PTX-NEXT: or.b64 %rd6, %rd5, 4; ; CHECK-PTX-NEXT: mov.b16 %rs9, 1; -; CHECK-PTX-NEXT: st.u8 [%rd6], %rs9; -; CHECK-PTX-NEXT: mov.b64 %rd7, 1; -; CHECK-PTX-NEXT: st.u64 [%SP+16], %rd7; +; CHECK-PTX-NEXT: st.u8 [%SP+12], %rs9; +; CHECK-PTX-NEXT: mov.b64 %rd5, 1; +; CHECK-PTX-NEXT: st.u64 [%SP+16], %rd5; +; CHECK-PTX-NEXT: add.u64 %rd6, %SP, 8; ; CHECK-PTX-NEXT: { // callseq 1, 0 ; CHECK-PTX-NEXT: .param .b32 param0; ; CHECK-PTX-NEXT: st.param.b32 [param0], 1; ; CHECK-PTX-NEXT: .param .b64 param1; -; CHECK-PTX-NEXT: st.param.b64 [param1], %rd5; +; CHECK-PTX-NEXT: st.param.b64 [param1], %rd6; ; CHECK-PTX-NEXT: .param .b32 retval0; ; CHECK-PTX-NEXT: call.uni (retval0), ; CHECK-PTX-NEXT: variadics2, diff --git a/llvm/test/CodeGen/PowerPC/global-merge-aix-zero-size-struct.ll b/llvm/test/CodeGen/PowerPC/global-merge-aix-zero-size-struct.ll new file mode 100644 index 000000000000..ec6fd7ee4cf4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/global-merge-aix-zero-size-struct.ll @@ -0,0 +1,20 @@ +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 < %s | FileCheck %s + +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 --filetype=obj -o %t.o < %s +; RUN: llvm-objdump --syms %t.o | FileCheck %s --check-prefix=OBJ + +%struct.anon = type {} + +@a = internal constant %struct.anon zeroinitializer, align 1 +@b = internal constant [6 x i8] c"hello\00", align 1 + +; CHECK: .csect L.._MergedGlobals[RO],2 +; CHECK-NEXT: .lglobl a # @_MergedGlobals +; CHECK-NEXT: .lglobl b +; CHECK-NEXT: a: +; CHECK-NEXT: b: +; CHECK-NEXT: .string "hello" + +; OBJ: 0000000000000000 l .text 0000000000000006 L.._MergedGlobals +; OBJ-NEXT: 0000000000000000 l .text (csect: L.._MergedGlobals) 0000000000000000 a +; OBJ-NEXT: 0000000000000000 l .text (csect: L.._MergedGlobals) 0000000000000000 b diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll b/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll index ff56ab193c48..0fd23a7d346d 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll @@ -14,7 +14,7 @@ define i32 @add_positive_low_bound_reject(i32 %a) nounwind { ; ; RV64I-LABEL: add_positive_low_bound_reject: ; RV64I: # %bb.0: -; RV64I-NEXT: addi a0, a0, 2047 +; RV64I-NEXT: addiw a0, a0, 2047 ; RV64I-NEXT: ret %1 = add i32 %a, 2047 ret i32 %1 @@ -30,7 +30,7 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_positive_low_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, 2047 -; RV64I-NEXT: addi a0, a0, 1 +; RV64I-NEXT: addiw a0, a0, 1 ; RV64I-NEXT: ret %1 = add i32 %a, 2048 ret i32 %1 @@ -46,7 +46,7 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_positive_high_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, 2047 -; RV64I-NEXT: addi a0, a0, 2047 +; RV64I-NEXT: addiw a0, a0, 2047 ; RV64I-NEXT: ret %1 = add i32 %a, 4094 ret i32 %1 @@ -63,8 +63,8 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind { ; RV64I-LABEL: add_positive_high_bound_reject: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 1 -; RV64I-NEXT: addiw a1, a1, -1 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addi a1, a1, -1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: ret %1 = add i32 %a, 4095 ret i32 %1 @@ -78,7 +78,7 @@ define i32 @add_negative_high_bound_reject(i32 %a) nounwind { ; ; RV64I-LABEL: add_negative_high_bound_reject: ; RV64I: # %bb.0: -; RV64I-NEXT: addi a0, a0, -2048 +; RV64I-NEXT: addiw a0, a0, -2048 ; RV64I-NEXT: ret %1 = add i32 %a, -2048 ret i32 %1 @@ -94,7 +94,7 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_negative_high_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, -2048 -; RV64I-NEXT: addi a0, a0, -1 +; RV64I-NEXT: addiw a0, a0, -1 ; RV64I-NEXT: ret %1 = add i32 %a, -2049 ret i32 %1 @@ -110,7 +110,7 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind { ; RV64I-LABEL: add_negative_low_bound_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, -2048 -; RV64I-NEXT: addi a0, a0, -2048 +; RV64I-NEXT: addiw a0, a0, -2048 ; RV64I-NEXT: ret %1 = add i32 %a, -4096 ret i32 %1 @@ -127,8 +127,8 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind { ; RV64I-LABEL: add_negative_low_bound_reject: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 1048575 -; RV64I-NEXT: addiw a1, a1, -1 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addi a1, a1, -1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: ret %1 = add i32 %a, -4097 ret i32 %1 @@ -144,7 +144,7 @@ define i32 @add32_accept(i32 %a) nounwind { ; RV64I-LABEL: add32_accept: ; RV64I: # %bb.0: ; RV64I-NEXT: addi a0, a0, 2047 -; RV64I-NEXT: addi a0, a0, 952 +; RV64I-NEXT: addiw a0, a0, 952 ; RV64I-NEXT: ret %1 = add i32 %a, 2999 ret i32 %1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll index ee414992a524..f1c0fccb78a3 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll @@ -37,7 +37,7 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) { ; RV64IM-NEXT: slli a1, a1, 56 ; RV64IM-NEXT: srai a0, a0, 56 ; RV64IM-NEXT: srai a1, a1, 56 -; RV64IM-NEXT: add a0, a0, a1 +; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = sext i8 %a to i32 @@ -58,7 +58,7 @@ define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) { ; RV64IM: # %bb.0: # %entry ; RV64IM-NEXT: andi a0, a0, 255 ; RV64IM-NEXT: andi a1, a1, 255 -; RV64IM-NEXT: add a0, a0, a1 +; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = zext i8 %a to i32 @@ -78,7 +78,7 @@ define i32 @add_i32(i32 %a, i32 %b) { ; ; RV64IM-LABEL: add_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: add a0, a0, a1 +; RV64IM-NEXT: addw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = add i32 %a, %b @@ -93,7 +93,7 @@ define i32 @addi_i32(i32 %a) { ; ; RV64IM-LABEL: addi_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: addi a0, a0, 1234 +; RV64IM-NEXT: addiw a0, a0, 1234 ; RV64IM-NEXT: ret entry: %0 = add i32 %a, 1234 @@ -108,7 +108,7 @@ define i32 @sub_i32(i32 %a, i32 %b) { ; ; RV64IM-LABEL: sub_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: sub a0, a0, a1 +; RV64IM-NEXT: subw a0, a0, a1 ; RV64IM-NEXT: ret entry: %0 = sub i32 %a, %b @@ -123,7 +123,7 @@ define i32 @subi_i32(i32 %a) { ; ; RV64IM-LABEL: subi_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: addi a0, a0, -1234 +; RV64IM-NEXT: addiw a0, a0, -1234 ; RV64IM-NEXT: ret entry: %0 = sub i32 %a, 1234 @@ -138,7 +138,7 @@ define i32 @neg_i32(i32 %a) { ; ; RV64IM-LABEL: neg_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: neg a0, a0 +; RV64IM-NEXT: negw a0, a0 ; RV64IM-NEXT: ret entry: %0 = sub i32 0, %a diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll index 6c848ecf0fff..3a55189076de 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/combine-neg-abs.ll @@ -27,14 +27,13 @@ define i32 @expanded_neg_abs32(i32 %x) { ; ; RV64I-LABEL: expanded_neg_abs32: ; RV64I: # %bb.0: -; RV64I-NEXT: neg a1, a0 -; RV64I-NEXT: sext.w a2, a1 -; RV64I-NEXT: sext.w a3, a0 -; RV64I-NEXT: blt a3, a2, .LBB0_2 +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: blt a2, a1, .LBB0_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: .LBB0_2: -; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: negw a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: expanded_neg_abs32: @@ -42,7 +41,7 @@ define i32 @expanded_neg_abs32(i32 %x) { ; RV64ZBB-NEXT: negw a1, a0 ; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: max a0, a1, a0 -; RV64ZBB-NEXT: neg a0, a0 +; RV64ZBB-NEXT: negw a0, a0 ; RV64ZBB-NEXT: ret %n = sub i32 0, %x %t = call i32 @llvm.smax.i32(i32 %n, i32 %x) @@ -69,14 +68,13 @@ define i32 @expanded_neg_abs32_unsigned(i32 %x) { ; ; RV64I-LABEL: expanded_neg_abs32_unsigned: ; RV64I: # %bb.0: -; RV64I-NEXT: neg a1, a0 -; RV64I-NEXT: sext.w a2, a1 -; RV64I-NEXT: sext.w a3, a0 -; RV64I-NEXT: bltu a3, a2, .LBB1_2 +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: bltu a2, a1, .LBB1_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: .LBB1_2: -; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: negw a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: expanded_neg_abs32_unsigned: @@ -84,7 +82,7 @@ define i32 @expanded_neg_abs32_unsigned(i32 %x) { ; RV64ZBB-NEXT: negw a1, a0 ; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: maxu a0, a1, a0 -; RV64ZBB-NEXT: neg a0, a0 +; RV64ZBB-NEXT: negw a0, a0 ; RV64ZBB-NEXT: ret %n = sub i32 0, %x %t = call i32 @llvm.umax.i32(i32 %n, i32 %x) @@ -251,14 +249,13 @@ define i32 @expanded_neg_inv_abs32(i32 %x) { ; ; RV64I-LABEL: expanded_neg_inv_abs32: ; RV64I: # %bb.0: -; RV64I-NEXT: neg a1, a0 -; RV64I-NEXT: sext.w a2, a1 -; RV64I-NEXT: sext.w a3, a0 -; RV64I-NEXT: blt a2, a3, .LBB4_2 +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: blt a1, a2, .LBB4_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: .LBB4_2: -; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: negw a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: expanded_neg_inv_abs32: @@ -266,7 +263,7 @@ define i32 @expanded_neg_inv_abs32(i32 %x) { ; RV64ZBB-NEXT: negw a1, a0 ; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: min a0, a1, a0 -; RV64ZBB-NEXT: neg a0, a0 +; RV64ZBB-NEXT: negw a0, a0 ; RV64ZBB-NEXT: ret %n = sub i32 0, %x %t = call i32 @llvm.smin.i32(i32 %n, i32 %x) @@ -293,14 +290,13 @@ define i32 @expanded_neg_inv_abs32_unsigned(i32 %x) { ; ; RV64I-LABEL: expanded_neg_inv_abs32_unsigned: ; RV64I: # %bb.0: -; RV64I-NEXT: neg a1, a0 -; RV64I-NEXT: sext.w a2, a1 -; RV64I-NEXT: sext.w a3, a0 -; RV64I-NEXT: bltu a2, a3, .LBB5_2 +; RV64I-NEXT: negw a1, a0 +; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: bltu a1, a2, .LBB5_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: .LBB5_2: -; RV64I-NEXT: neg a0, a1 +; RV64I-NEXT: negw a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: expanded_neg_inv_abs32_unsigned: @@ -308,7 +304,7 @@ define i32 @expanded_neg_inv_abs32_unsigned(i32 %x) { ; RV64ZBB-NEXT: negw a1, a0 ; RV64ZBB-NEXT: sext.w a0, a0 ; RV64ZBB-NEXT: minu a0, a1, a0 -; RV64ZBB-NEXT: neg a0, a0 +; RV64ZBB-NEXT: negw a0, a0 ; RV64ZBB-NEXT: ret %n = sub i32 0, %x %t = call i32 @llvm.umin.i32(i32 %n, i32 %x) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll index 9c7fd6895d37..360e84d37ec8 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll @@ -21,6 +21,7 @@ define i32 @constant_to_rhs(i32 %x) { ; RV64-O0-NEXT: mv a1, a0 ; RV64-O0-NEXT: li a0, 1 ; RV64-O0-NEXT: add a0, a0, a1 +; RV64-O0-NEXT: sext.w a0, a0 ; RV64-O0-NEXT: ret ; ; RV32-OPT-LABEL: constant_to_rhs: @@ -30,7 +31,7 @@ define i32 @constant_to_rhs(i32 %x) { ; ; RV64-OPT-LABEL: constant_to_rhs: ; RV64-OPT: # %bb.0: -; RV64-OPT-NEXT: addi a0, a0, 1 +; RV64-OPT-NEXT: addiw a0, a0, 1 ; RV64-OPT-NEXT: ret %a = add i32 1, %x ret i32 %a diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll b/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll index 385156b3b99d..487869922658 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/double-zfa.ll @@ -1,9 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 - ; RUN: llc -mtriple=riscv32 -mattr=+zfa,d -global-isel < %s \ -; RUN: | FileCheck %s +; RUN: | FileCheck %s --check-prefixes=CHECK,RV32IDZFA ; RUN: llc -mtriple=riscv64 -mattr=+zfa,d -global-isel < %s \ -; RUN: | FileCheck %s +; RUN: | FileCheck %s --check-prefixes=CHECK,RV64DZFA define double @fceil(double %a) { @@ -86,3 +85,32 @@ define double @fminimum(double %a, double %b) { %c = call double @llvm.minimum.f64(double %a, double %b) ret double %c } + +define i64 @fmvh_x_d(double %fa) { +; RV32IDZFA-LABEL: fmvh_x_d: +; RV32IDZFA: # %bb.0: +; RV32IDZFA-NEXT: fmv.x.w a0, fa0 +; RV32IDZFA-NEXT: fmvh.x.d a1, fa0 +; RV32IDZFA-NEXT: ret +; +; RV64DZFA-LABEL: fmvh_x_d: +; RV64DZFA: # %bb.0: +; RV64DZFA-NEXT: fmv.x.d a0, fa0 +; RV64DZFA-NEXT: ret + %i = bitcast double %fa to i64 + ret i64 %i +} + +define double @fmvp_d_x(i64 %a) { +; RV32IDZFA-LABEL: fmvp_d_x: +; RV32IDZFA: # %bb.0: +; RV32IDZFA-NEXT: fmvp.d.x fa0, a0, a1 +; RV32IDZFA-NEXT: ret +; +; RV64DZFA-LABEL: fmvp_d_x: +; RV64DZFA: # %bb.0: +; RV64DZFA-NEXT: fmv.d.x fa0, a0 +; RV64DZFA-NEXT: ret + %or = bitcast i64 %a to double + ret double %or +} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll index 72f0ab159f0a..234f33841206 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll @@ -96,12 +96,19 @@ define ptr @freeze_ptr(ptr %x) { %struct.T = type { i32, i32 } define i32 @freeze_struct(ptr %p) { -; CHECK-LABEL: freeze_struct: -; CHECK: # %bb.0: -; CHECK-NEXT: lw a1, 0(a0) -; CHECK-NEXT: lw a0, 4(a0) -; CHECK-NEXT: add a0, a1, a0 -; CHECK-NEXT: ret +; RV32-LABEL: freeze_struct: +; RV32: # %bb.0: +; RV32-NEXT: lw a1, 0(a0) +; RV32-NEXT: lw a0, 4(a0) +; RV32-NEXT: add a0, a1, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: freeze_struct: +; RV64: # %bb.0: +; RV64-NEXT: lw a1, 0(a0) +; RV64-NEXT: lw a0, 4(a0) +; RV64-NEXT: addw a0, a1, a0 +; RV64-NEXT: ret %s = load %struct.T, ptr %p %y1 = freeze %struct.T %s %v1 = extractvalue %struct.T %y1, 0 @@ -111,12 +118,19 @@ define i32 @freeze_struct(ptr %p) { } define i32 @freeze_anonstruct(ptr %p) { -; CHECK-LABEL: freeze_anonstruct: -; CHECK: # %bb.0: -; CHECK-NEXT: lw a1, 0(a0) -; CHECK-NEXT: lw a0, 4(a0) -; CHECK-NEXT: add a0, a1, a0 -; CHECK-NEXT: ret +; RV32-LABEL: freeze_anonstruct: +; RV32: # %bb.0: +; RV32-NEXT: lw a1, 0(a0) +; RV32-NEXT: lw a0, 4(a0) +; RV32-NEXT: add a0, a1, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: freeze_anonstruct: +; RV64: # %bb.0: +; RV64-NEXT: lw a1, 0(a0) +; RV64-NEXT: lw a0, 4(a0) +; RV64-NEXT: addw a0, a1, a0 +; RV64-NEXT: ret %s = load {i32, i32}, ptr %p %y1 = freeze {i32, i32} %s %v1 = extractvalue {i32, i32} %y1, 0 @@ -141,7 +155,7 @@ define i32 @freeze_anonstruct2(ptr %p) { ; RV64-NEXT: lw a0, 0(a0) ; RV64-NEXT: slli a1, a1, 48 ; RV64-NEXT: srli a1, a1, 48 -; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: addw a0, a0, a1 ; RV64-NEXT: ret %s = load {i32, i16}, ptr %p %y1 = freeze {i32, i16} %s @@ -168,7 +182,7 @@ define i32 @freeze_anonstruct2_sext(ptr %p) { ; RV64-NEXT: lw a0, 0(a0) ; RV64-NEXT: slli a1, a1, 48 ; RV64-NEXT: srai a1, a1, 48 -; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: addw a0, a0, a1 ; RV64-NEXT: ret %s = load {i32, i16}, ptr %p %y1 = freeze {i32, i16} %s @@ -180,12 +194,19 @@ define i32 @freeze_anonstruct2_sext(ptr %p) { } define i32 @freeze_array(ptr %p) nounwind { -; CHECK-LABEL: freeze_array: -; CHECK: # %bb.0: -; CHECK-NEXT: lw a1, 0(a0) -; CHECK-NEXT: lw a0, 4(a0) -; CHECK-NEXT: add a0, a1, a0 -; CHECK-NEXT: ret +; RV32-LABEL: freeze_array: +; RV32: # %bb.0: +; RV32-NEXT: lw a1, 0(a0) +; RV32-NEXT: lw a0, 4(a0) +; RV32-NEXT: add a0, a1, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: freeze_array: +; RV64: # %bb.0: +; RV64-NEXT: lw a1, 0(a0) +; RV64-NEXT: lw a0, 4(a0) +; RV64-NEXT: addw a0, a1, a0 +; RV64-NEXT: ret %s = load [2 x i32], ptr %p %y1 = freeze [2 x i32] %s %v1 = extractvalue [2 x i32] %y1, 0 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll index 1156edffe919..31a78d4f72ce 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll @@ -98,7 +98,7 @@ define i32 @abs32(i32 %x) { ; RV64I-LABEL: abs32: ; RV64I: # %bb.0: ; RV64I-NEXT: sraiw a1, a0, 31 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir index a27e2b80cd98..dbc13840a026 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir @@ -23,7 +23,7 @@ # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # # DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices -# DEBUG-NEXT: .. opcode [[SUB_OPC]] is aliased to [[ADD_OPC]] +# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # @@ -59,7 +59,6 @@ # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # # DEBUG-NEXT: G_AND (opcode {{[0-9]+}}): 1 type index, 0 imm indices -# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}} # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir index 22ce8a0fd0df..78a2227b84a3 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir @@ -86,9 +86,10 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64) ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]] - ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]] - ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32 - ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SEXT_INREG]], [[ASHR]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: abs_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir index 48b65a1dd6ba..8f2b9f36eb9f 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir @@ -69,7 +69,8 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] - ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir index f2ec70933261..eed1aac8f6c1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir @@ -339,7 +339,7 @@ body: | ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] - ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 %2:_(s64) = COPY $x10 @@ -454,10 +454,11 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] - ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 - ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 - ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] - ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG1]](s64), [[SEXT_INREG2]] + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: $x11 = COPY [[ICMP]](s64) ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11 %2:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir index 57fc513dc9e3..e28572d05207 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir @@ -145,7 +145,8 @@ body: | ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -64769 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] - ; CHECK-NEXT: $x10 = COPY [[ADD]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s32) = G_CONSTANT i32 -64769 %1:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir index 6cc5477b85a4..62d731351ffd 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir @@ -59,7 +59,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s8) = G_TRUNC %1(s64) @@ -129,7 +130,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s16) = G_TRUNC %1(s64) @@ -175,16 +177,19 @@ body: | ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C2]](s64) ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]] - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C7]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C8]] ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]] @@ -192,7 +197,8 @@ body: | ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[C10]](s64) ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR8]] - ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: ctlz_i32 @@ -328,7 +334,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s8) = G_TRUNC %1(s64) @@ -398,7 +405,8 @@ body: | ; RV64ZBB-NEXT: [[CLZW:%[0-9]+]]:_(s64) = G_CLZW [[AND]] ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CLZW]], [[C1]] - ; RV64ZBB-NEXT: $x10 = COPY [[SUB]](s64) + ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64ZBB-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s16) = G_TRUNC %1(s64) @@ -444,16 +452,19 @@ body: | ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[C6]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[C2]](s64) ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]] - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C7]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C3]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C8]] ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]] @@ -461,7 +472,8 @@ body: | ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[C10]](s64) ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s64) = G_CONSTANT i64 32 ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[C11]], [[LSHR8]] - ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB1]], 32 + ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: ctlz_zero_undef_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir index 1493514394bd..c61c46df0a43 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir @@ -129,18 +129,21 @@ body: | ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C2]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[C3]](s64) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C4]] - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C4]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C4]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C5]](s64) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG1]], [[C5]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG1]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C6]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG2]], [[C6]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[C7]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir index 252e79280af6..87155bb8b743 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir @@ -131,7 +131,8 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[SEXT_INREG]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] @@ -139,18 +140,21 @@ body: | ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C2]] ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C5]] ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG2]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG2]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD2]], 32 ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG3]], [[C7]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]] @@ -351,7 +355,8 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[C]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[SEXT_INREG]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] @@ -359,18 +364,21 @@ body: | ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1431655765 ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C3]] ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C2]] ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[C4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 858993459 ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[C5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C5]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C5]] ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[ADD1]], [[C6]](s64) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG2]], [[C6]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[SEXT_INREG2]] + ; RV64I-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD2]], 32 ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135 - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[C7]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG3]], [[C7]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009 ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 24 ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[C8]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir index f3bc1ce28cfa..aff7d4d3ec1e 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ext-rv64.mir @@ -30,8 +30,9 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C]] + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C]] ; CHECK-NEXT: $x10 = COPY [[AND]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir index 4689a7dd219a..776f5f53fafb 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir @@ -88,9 +88,10 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]] - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND1]] ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SLLW]], [[SRLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) @@ -233,9 +234,10 @@ body: | ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]] + ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]] ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND]] - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG]], [[C1]] ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND1]] ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SRLW]], [[SLLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir index bf8c8d690f07..d162bfcca1bc 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir @@ -16,8 +16,8 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) @@ -97,7 +97,8 @@ body: | ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483648 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) + ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG3]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) @@ -173,10 +174,11 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) - ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 - ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 - ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]] + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG]](s64) + ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 + ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG1]](s64), [[SEXT_INREG2]] ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[TRUNC]] @@ -250,7 +252,8 @@ body: | ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[C]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2147483648 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) + ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32 + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SEXT_INREG3]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir index da3ab9e1a527..7ab07ee0d70d 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sub-rv64.mir @@ -69,7 +69,8 @@ body: | ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] - ; CHECK-NEXT: $x10 = COPY [[SUB]](s64) + ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32 + ; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll index 0b876fed59c1..9df319e73a11 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll @@ -18,7 +18,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -30,15 +30,15 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -75,7 +75,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -87,15 +87,15 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -133,15 +133,14 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: li s0, 32 -; RV64I-NEXT: addi a0, a0, -1 -; RV64I-NEXT: sext.w a2, a0 +; RV64I-NEXT: addiw a0, a0, -1 ; RV64I-NEXT: li a1, 32 -; RV64I-NEXT: beqz a2, .LBB2_2 +; RV64I-NEXT: beqz a0, .LBB2_2 ; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -153,15 +152,15 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -200,7 +199,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a0, a0, 1 ; RV64I-NEXT: lui a1, 349525 ; RV64I-NEXT: or a0, s0, a0 -; RV64I-NEXT: addiw a1, a1, 1365 +; RV64I-NEXT: addi a1, a1, 1365 ; RV64I-NEXT: srliw a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srliw a2, a0, 4 @@ -212,15 +211,15 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -271,7 +270,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: srliw a0, a0, 2 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srli a2, a0, 2 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: srli a2, a0, 4 @@ -283,15 +282,15 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -299,7 +298,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: li a1, 32 -; RV64I-NEXT: sub a0, a1, a0 +; RV64I-NEXT: subw a0, a1, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: .cfi_restore ra ; RV64I-NEXT: addi sp, sp, 16 @@ -408,19 +407,19 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -451,19 +450,19 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -493,19 +492,19 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a1, s0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -549,19 +548,19 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a1, s0, -1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: addiw a1, a2, 1365 +; RV64I-NEXT: addi a1, a2, 1365 ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -669,18 +668,18 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 -; RV64I-NEXT: addiw a2, a2, 1365 +; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -706,18 +705,18 @@ define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 -; RV64I-NEXT: addiw a2, a2, 1365 +; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -746,19 +745,19 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind { ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lwu a0, 0(a0) ; RV64I-NEXT: lui a1, 349525 -; RV64I-NEXT: addiw a1, a1, 1365 +; RV64I-NEXT: addi a1, a1, 1365 ; RV64I-NEXT: srli a2, a0, 1 ; RV64I-NEXT: and a1, a2, a1 ; RV64I-NEXT: lui a2, 209715 -; RV64I-NEXT: addiw a2, a2, 819 +; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: sub a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 61681 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 -; RV64I-NEXT: add a0, a1, a0 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a2, a2, -241 ; RV64I-NEXT: and a0, a0, a2 @@ -1057,7 +1056,7 @@ define i32 @abs_i32(i32 %x) { ; RV64I-LABEL: abs_i32: ; RV64I: # %bb.0: ; RV64I-NEXT: sraiw a1, a0, 31 -; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll index 4346e04ecda6..daeb2e69c83b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll @@ -97,7 +97,7 @@ define i32 @scmp.32.32(i32 %x, i32 %y) nounwind { ; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: slt a2, a1, a0 ; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.scmp(i32 %x, i32 %y) ret i32 %1 @@ -122,7 +122,7 @@ define i32 @scmp.32.64(i64 %x, i64 %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slt a2, a1, a0 ; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.scmp(i64 %x, i64 %y) ret i32 %1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll index 9784c58dca4f..463883b371ca 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll @@ -97,7 +97,7 @@ define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind { ; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i32 %x, i32 %y) ret i32 %1 @@ -115,7 +115,7 @@ define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i32 %x, i32 %y) ret i32 %1 @@ -135,7 +135,7 @@ define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind { ; RV64I-NEXT: sext.w a1, a1 ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i32 %x, i32 %y) ret i32 %1 @@ -160,7 +160,7 @@ define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: sltu a2, a1, a0 ; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: sub a0, a2, a0 +; RV64I-NEXT: subw a0, a2, a0 ; RV64I-NEXT: ret %1 = call i32 @llvm.ucmp(i64 %x, i64 %y) ret i32 %1 diff --git a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll index fe89b4aa2417..d7f62ae83434 100644 --- a/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll +++ b/llvm/test/CodeGen/RISCV/add_sext_shl_constant.ll @@ -320,6 +320,19 @@ define i64 @add_shl_moreOneUse_sh3add(i64 %x) { ret i64 %add } +;; Covers a case which previously crashed (pr119527) +define i64 @add_shl_sext(i32 %1) { +; RV64-LABEL: add_shl_sext: +; RV64: # %bb.0: +; RV64-NEXT: addi a1, a0, 3 +; RV64-NEXT: sllw a0, a1, a0 +; RV64-NEXT: ret + %3 = add i32 %1, 3 + %4 = shl i32 %3, %1 + %5 = sext i32 %4 to i64 + ret i64 %5 +} + define i64 @add_shl_moreOneUse_sh4add(i64 %x) { ; RV64-LABEL: add_shl_moreOneUse_sh4add: ; RV64: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 7e55e0590ec5..c0fcc6f61111 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -84,6 +84,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm %s -o - | FileCheck --check-prefix=RV32XQCICM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s @@ -397,6 +398,7 @@ ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2" ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p2" ; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2" +; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2" ; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2" ; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2" ; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2" diff --git a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll index 4c47b5f741fa..2c428cf4ac87 100644 --- a/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll +++ b/llvm/test/CodeGen/RISCV/kcfi-isel-mir.ll @@ -20,7 +20,7 @@ define void @f2(ptr noundef %x) #0 { ; CHECK-NEXT: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprtc = COPY $x10 - ; CHECK-NEXT: PseudoTAILIndirect [[COPY]], implicit $x2, cfi-type 12345678 + ; CHECK-NEXT: PseudoTAILIndirect [[COPY]], csr_ilp32_lp64, implicit $x2, cfi-type 12345678 tail call void %x() [ "kcfi"(i32 12345678) ] ret void } diff --git a/llvm/test/CodeGen/RISCV/kcfi-mir.ll b/llvm/test/CodeGen/RISCV/kcfi-mir.ll index f9f383a35358..0c0d39a8bf87 100644 --- a/llvm/test/CodeGen/RISCV/kcfi-mir.ll +++ b/llvm/test/CodeGen/RISCV/kcfi-mir.ll @@ -30,7 +30,7 @@ define void @f2(ptr noundef %x) #0 { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: BUNDLE implicit-def $x6, implicit-def $x6_w, implicit-def $x6_h, implicit-def $x7, implicit-def $x7_w, implicit-def $x7_h, implicit-def $x28, implicit-def $x28_w, implicit-def $x28_h, implicit-def $x29, implicit-def $x29_w, implicit-def $x29_h, implicit-def $x30, implicit-def $x30_w, implicit-def $x30_h, implicit-def $x31, implicit-def $x31_w, implicit-def $x31_h, implicit killed $x10, implicit $x2 { ; CHECK-NEXT: KCFI_CHECK $x10, 12345678, implicit-def $x6, implicit-def $x7, implicit-def $x28, implicit-def $x29, implicit-def $x30, implicit-def $x31 - ; CHECK-NEXT: PseudoTAILIndirect killed $x10, implicit $x2 + ; CHECK-NEXT: PseudoTAILIndirect killed $x10, csr_ilp32_lp64, implicit $x2 ; CHECK-NEXT: } tail call void %x() [ "kcfi"(i32 12345678) ] ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll index 10d24927d9b7..4d34621cd5f2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll @@ -1445,10 +1445,9 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale ; RV32-NEXT: addi a6, sp, 8 ; RV32-NEXT: sw a4, 8(sp) ; RV32-NEXT: sw zero, 12(sp) -; RV32-NEXT: vsetvli a4, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v9, (a6), zero ; RV32-NEXT: lui a4, 61681 -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v10, v8, a3, v0.t ; RV32-NEXT: addi a5, a5, -256 ; RV32-NEXT: vand.vx v11, v8, a5, v0.t @@ -1595,9 +1594,7 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64_unmasked(<vscale x 1 x i64> %va ; RV32-NEXT: vand.vx v13, v8, a1 ; RV32-NEXT: vand.vx v12, v12, a1 ; RV32-NEXT: vor.vv v11, v12, v11 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v12, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v13, v13, a4 ; RV32-NEXT: vor.vv v10, v10, v13 ; RV32-NEXT: vsrl.vi v13, v8, 8 @@ -1730,10 +1727,9 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale ; RV32-NEXT: addi a6, sp, 8 ; RV32-NEXT: sw a4, 8(sp) ; RV32-NEXT: sw zero, 12(sp) -; RV32-NEXT: vsetvli a4, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v10, (a6), zero ; RV32-NEXT: lui a4, 61681 -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v12, v8, a3, v0.t ; RV32-NEXT: addi a5, a5, -256 ; RV32-NEXT: vand.vx v14, v8, a5, v0.t @@ -1880,9 +1876,7 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64_unmasked(<vscale x 2 x i64> %va ; RV32-NEXT: vand.vx v18, v8, a1 ; RV32-NEXT: vand.vx v16, v16, a1 ; RV32-NEXT: vor.vv v10, v16, v10 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v16, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v18, v18, a4 ; RV32-NEXT: vor.vv v12, v12, v18 ; RV32-NEXT: vsrl.vi v18, v8, 8 @@ -2015,10 +2009,9 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale ; RV32-NEXT: addi a6, sp, 8 ; RV32-NEXT: sw a4, 8(sp) ; RV32-NEXT: sw zero, 12(sp) -; RV32-NEXT: vsetvli a4, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v12, (a6), zero ; RV32-NEXT: lui a4, 61681 -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a3, v0.t ; RV32-NEXT: addi a5, a5, -256 ; RV32-NEXT: vand.vx v20, v8, a5, v0.t @@ -2165,9 +2158,7 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64_unmasked(<vscale x 4 x i64> %va ; RV32-NEXT: vand.vx v28, v8, a1 ; RV32-NEXT: vand.vx v24, v24, a1 ; RV32-NEXT: vor.vv v12, v24, v12 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v28, v28, a4 ; RV32-NEXT: vor.vv v16, v16, v28 ; RV32-NEXT: vsrl.vi v28, v8, 8 @@ -2315,7 +2306,6 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 3 @@ -2323,7 +2313,6 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vand.vx v24, v8, a3, v0.t ; RV32-NEXT: vsll.vi v24, v24, 24, v0.t ; RV32-NEXT: addi a5, sp, 16 @@ -2528,9 +2517,7 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64_unmasked(<vscale x 7 x i64> %va ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v0, v8, 8 @@ -2704,7 +2691,6 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 3 @@ -2712,7 +2698,6 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vand.vx v24, v8, a3, v0.t ; RV32-NEXT: vsll.vi v24, v24, 24, v0.t ; RV32-NEXT: addi a5, sp, 16 @@ -2917,9 +2902,7 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v0, v8, 8 diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll index 0dc1d0c32ac4..0c58cca0f947 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll @@ -523,11 +523,9 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v9, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v10, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v10, v8, a0, v0.t ; RV32-NEXT: vlse64.v v11, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v10, v10, a4, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vand.vx v10, v8, a5, v0.t @@ -538,7 +536,7 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t -; RV32-NEXT: vand.vx v12, v12, a1, v0.t +; RV32-NEXT: vand.vx v12, v12, a0, v0.t ; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t ; RV32-NEXT: vand.vx v12, v12, a5, v0.t @@ -609,15 +607,13 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsll.vx v10, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v11, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a4 -; RV32-NEXT: vand.vx v13, v8, a1 -; RV32-NEXT: vand.vx v12, v12, a1 +; RV32-NEXT: vand.vx v13, v8, a0 +; RV32-NEXT: vand.vx v12, v12, a0 ; RV32-NEXT: vor.vv v11, v12, v11 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v12, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v13, v13, a4 ; RV32-NEXT: vor.vv v10, v10, v13 ; RV32-NEXT: vsrl.vi v13, v8, 8 @@ -695,11 +691,9 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v10, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v12, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m2, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v12, v8, a0, v0.t ; RV32-NEXT: vlse64.v v14, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v12, v12, a4, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t ; RV32-NEXT: vand.vx v12, v8, a5, v0.t @@ -710,7 +704,7 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 ; RV32-NEXT: vor.vv v10, v10, v12, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t -; RV32-NEXT: vand.vx v16, v16, a1, v0.t +; RV32-NEXT: vand.vx v16, v16, a0, v0.t ; RV32-NEXT: vor.vv v12, v16, v12, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t ; RV32-NEXT: vand.vx v16, v16, a5, v0.t @@ -781,15 +775,13 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsll.vx v12, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v14, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a4 -; RV32-NEXT: vand.vx v18, v8, a1 -; RV32-NEXT: vand.vx v16, v16, a1 +; RV32-NEXT: vand.vx v18, v8, a0 +; RV32-NEXT: vand.vx v16, v16, a0 ; RV32-NEXT: vor.vv v14, v16, v14 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v16, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsll.vx v18, v18, a4 ; RV32-NEXT: vor.vv v12, v12, v18 ; RV32-NEXT: vsrl.vi v18, v8, 8 @@ -867,11 +859,9 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v20, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m4, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v20, v8, a0, v0.t ; RV32-NEXT: vlse64.v v12, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v20, v20, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v20, v0.t ; RV32-NEXT: vand.vx v20, v8, a5, v0.t @@ -882,7 +872,7 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 ; RV32-NEXT: vor.vv v16, v16, v20, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t -; RV32-NEXT: vand.vx v24, v24, a1, v0.t +; RV32-NEXT: vand.vx v24, v24, a0, v0.t ; RV32-NEXT: vor.vv v20, v24, v20, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t ; RV32-NEXT: vand.vx v24, v24, a5, v0.t @@ -953,15 +943,13 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 ; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsll.vx v16, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v20, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a4 -; RV32-NEXT: vand.vx v28, v8, a1 -; RV32-NEXT: vand.vx v24, v24, a1 +; RV32-NEXT: vand.vx v28, v8, a0 +; RV32-NEXT: vand.vx v24, v24, a0 ; RV32-NEXT: vor.vv v20, v24, v20 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v24, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsll.vx v28, v28, a4 ; RV32-NEXT: vor.vv v16, v16, v28 ; RV32-NEXT: vsrl.vi v28, v8, 8 @@ -1043,51 +1031,49 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v24, v8, a0, v0.t ; RV32-NEXT: vsll.vx v24, v24, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 4 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, 4080 +; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: vsll.vi v24, v24, 24, v0.t +; RV32-NEXT: addi a3, sp, 16 +; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill +; RV32-NEXT: vand.vv v24, v8, v16, v0.t +; RV32-NEXT: vsll.vi v16, v24, 8, v0.t +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 -; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb -; RV32-NEXT: slli a3, a3, 3 +; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; RV32-NEXT: vand.vx v24, v8, a3, v0.t -; RV32-NEXT: vsll.vi v24, v24, 24, v0.t -; RV32-NEXT: addi a0, sp, 16 -; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill -; RV32-NEXT: vand.vv v24, v8, v16, v0.t -; RV32-NEXT: vsll.vi v16, v24, 8, v0.t -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t -; RV32-NEXT: vand.vx v24, v24, a1, v0.t +; RV32-NEXT: vand.vx v24, v24, a0, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t -; RV32-NEXT: vand.vx v24, v24, a3, v0.t +; RV32-NEXT: vand.vx v24, v24, a1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 @@ -1193,24 +1179,22 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v24, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v0, v8, a4 -; RV32-NEXT: vand.vx v0, v0, a1 +; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vor.vv v16, v0, v16 -; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: slli a2, a2, 3 -; RV32-NEXT: add a2, sp, a2 -; RV32-NEXT: addi a2, a2, 16 -; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill -; RV32-NEXT: vand.vx v0, v8, a1 +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vand.vx v0, v8, a0 ; RV32-NEXT: vsll.vx v0, v0, a4 ; RV32-NEXT: vor.vv v16, v24, v0 -; RV32-NEXT: addi a1, sp, 16 -; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: addi a0, sp, 16 +; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vlse64.v v0, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v24, v8, 8 @@ -1221,7 +1205,6 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 ; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v24, v24, 8 ; RV32-NEXT: vor.vv v8, v8, v24 -; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: csrr a0, vlenb @@ -1318,51 +1301,49 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v16, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v24, v8, a0, v0.t ; RV32-NEXT: vsll.vx v24, v24, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 4 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, 4080 +; RV32-NEXT: vand.vx v24, v8, a1, v0.t +; RV32-NEXT: vsll.vi v24, v24, 24, v0.t +; RV32-NEXT: addi a3, sp, 16 +; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill +; RV32-NEXT: vand.vv v24, v8, v16, v0.t +; RV32-NEXT: vsll.vi v16, v24, 8, v0.t +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 -; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a3, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a5), zero +; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload +; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: csrr a3, vlenb -; RV32-NEXT: slli a3, a3, 3 +; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; RV32-NEXT: lui a3, 4080 -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; RV32-NEXT: vand.vx v24, v8, a3, v0.t -; RV32-NEXT: vsll.vi v24, v24, 24, v0.t -; RV32-NEXT: addi a0, sp, 16 -; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill -; RV32-NEXT: vand.vv v24, v8, v16, v0.t -; RV32-NEXT: vsll.vi v16, v24, 8, v0.t -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload -; RV32-NEXT: vor.vv v16, v24, v16, v0.t -; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: add a0, sp, a0 -; RV32-NEXT: addi a0, a0, 16 -; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t -; RV32-NEXT: vand.vx v24, v24, a1, v0.t +; RV32-NEXT: vand.vx v24, v24, a0, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t -; RV32-NEXT: vand.vx v24, v24, a3, v0.t +; RV32-NEXT: vand.vx v24, v24, a1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: slli a0, a0, 3 @@ -1468,24 +1449,22 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsll.vx v24, v8, a2 -; RV32-NEXT: addi a1, a3, -256 +; RV32-NEXT: addi a0, a3, -256 ; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v0, v8, a4 -; RV32-NEXT: vand.vx v0, v0, a1 +; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vor.vv v16, v0, v16 -; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: slli a2, a2, 3 -; RV32-NEXT: add a2, sp, a2 -; RV32-NEXT: addi a2, a2, 16 -; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill -; RV32-NEXT: vand.vx v0, v8, a1 +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vand.vx v0, v8, a0 ; RV32-NEXT: vsll.vx v0, v0, a4 ; RV32-NEXT: vor.vv v16, v24, v0 -; RV32-NEXT: addi a1, sp, 16 -; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: addi a0, sp, 16 +; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vlse64.v v0, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v16, v16, a5 ; RV32-NEXT: vsrl.vi v24, v8, 8 @@ -1496,7 +1475,6 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 ; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v24, v24, 8 ; RV32-NEXT: vor.vv v8, v8, v24 -; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: csrr a0, vlenb @@ -1716,11 +1694,9 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1 ; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v9, v8, a2, v0.t -; RV32-NEXT: addi a1, a3, -256 -; RV32-NEXT: vand.vx v10, v8, a1, v0.t -; RV32-NEXT: vsetvli a3, zero, e64, m1, ta, ma +; RV32-NEXT: addi a0, a3, -256 +; RV32-NEXT: vand.vx v10, v8, a0, v0.t ; RV32-NEXT: vlse64.v v11, (a6), zero -; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsll.vx v10, v10, a4, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vand.vx v10, v8, a5, v0.t @@ -1731,7 +1707,7 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1 ; RV32-NEXT: vor.vv v9, v9, v10, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t -; RV32-NEXT: vand.vx v12, v12, a1, v0.t +; RV32-NEXT: vand.vx v12, v12, a0, v0.t ; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t ; RV32-NEXT: vand.vx v12, v12, a5, v0.t diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll index 15793eaada07..66952cac8e00 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll @@ -1254,12 +1254,10 @@ define void @copysign_neg_trunc_v4f16_v4f32(ptr %x, ptr %y) { define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) { ; ZVFH-LABEL: copysign_neg_trunc_v3f16_v3f32: ; ZVFH: # %bb.0: -; ZVFH-NEXT: vsetivli zero, 3, e32, m1, ta, ma +; ZVFH-NEXT: vsetivli zero, 3, e16, mf2, ta, ma ; ZVFH-NEXT: vle32.v v8, (a1) ; ZVFH-NEXT: vle16.v v9, (a0) -; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFH-NEXT: vfncvt.f.f.w v10, v8 -; ZVFH-NEXT: vsetivli zero, 3, e16, mf2, ta, ma ; ZVFH-NEXT: vfsgnjn.vv v8, v9, v10 ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -1272,9 +1270,7 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) { ; ZVFHMIN-NEXT: lui a1, 8 ; ZVFHMIN-NEXT: addi a2, a1, -1 ; ZVFHMIN-NEXT: vand.vx v8, v8, a2 -; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9 -; ZVFHMIN-NEXT: vsetivli zero, 3, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vxor.vx v9, v10, a1 ; ZVFHMIN-NEXT: vand.vx v9, v9, a1 ; ZVFHMIN-NEXT: vor.vv v8, v8, v9 @@ -4013,9 +4009,10 @@ define void @trunc_v6f16(ptr %x) { ; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -4197,10 +4194,11 @@ define void @ceil_v6f16(ptr %x) { ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 ; ZVFH-NEXT: fsrmi a1, 3 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a1 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -4388,10 +4386,11 @@ define void @floor_v6f16(ptr %x) { ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 ; ZVFH-NEXT: fsrmi a1, 2 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a1 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret @@ -4579,10 +4578,11 @@ define void @round_v6f16(ptr %x) { ; ZVFH-NEXT: vfabs.v v9, v8 ; ZVFH-NEXT: vmflt.vf v0, v9, fa5 ; ZVFH-NEXT: fsrmi a1, 4 +; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a1 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t -; ZVFH-NEXT: vsetivli zero, 6, e16, m1, ta, mu +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; ZVFH-NEXT: vse16.v v8, (a0) ; ZVFH-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll index 59c7feb53ce9..80e462c93769 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll @@ -1142,9 +1142,7 @@ define void @mulhu_v6i16(ptr %x) { ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: lui a1, %hi(.LCPI67_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI67_0) -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v9, (a1) -; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll index 4f0f5dd78c94..bf8baafc4a25 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll @@ -530,7 +530,7 @@ define i32 @reduce_and_16xi32_prefix5(ptr %p) { ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 5, e32, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vmv.v.i v10, -1 ; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; CHECK-NEXT: vredand.vs v8, v8, v10 @@ -725,7 +725,7 @@ define i32 @reduce_umin_16xi32_prefix5(ptr %p) { ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; RV32-NEXT: vle32.v v8, (a0) -; RV32-NEXT: vsetivli zero, 5, e32, m1, ta, ma +; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32-NEXT: vmv.v.i v10, -1 ; RV32-NEXT: vsetivli zero, 5, e32, m2, ta, ma ; RV32-NEXT: vredminu.vs v8, v8, v10 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll index 5d407caf7151..05254e60b65b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll @@ -473,6 +473,7 @@ define <32 x i64> @select_evl_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c) ; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-NEXT: vle64.v v16, (a1) ; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll index 7649d60def11..33fe73a097e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll @@ -582,14 +582,14 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -616,13 +616,13 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -652,14 +652,14 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -686,13 +686,13 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -722,15 +722,15 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v16, v12, v14, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t @@ -758,13 +758,13 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 ; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0 @@ -796,15 +796,15 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v12, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v24, v16, v20, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 ; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t @@ -832,13 +832,13 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0 @@ -876,15 +876,15 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill @@ -927,10 +927,10 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24 ; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v24, v0 @@ -995,64 +995,62 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: csrr a4, vlenb -; ZVFHMIN-NEXT: slli a4, a4, 5 +; ZVFHMIN-NEXT: li a5, 24 +; ZVFHMIN-NEXT: mul a4, a4, a5 ; ZVFHMIN-NEXT: add a4, sp, a4 ; ZVFHMIN-NEXT: addi a4, a4, 16 ; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v0, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb ; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: li a3, 25 +; ZVFHMIN-NEXT: mul a2, a2, a3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vl8r.v v0, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v8, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 @@ -1070,35 +1068,43 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v24, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv8r.v v8, v16 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vmv1r.v v0, v24 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb ; ZVFHMIN-NEXT: li a1, 24 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t +; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload @@ -1110,7 +1116,7 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: li a1, 25 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 @@ -1152,68 +1158,61 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vmv8r.v v0, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v8, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v0, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t +; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 4 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v13, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v13 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload @@ -1221,7 +1220,8 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill @@ -1229,43 +1229,49 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vmv1r.v v0, v7 ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16 ; ZVFHMIN-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll index 8e448fcda9c5..c65712e9965a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll @@ -582,14 +582,14 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -616,13 +616,13 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -652,14 +652,14 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v8, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8, v0.t @@ -686,13 +686,13 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0 @@ -722,15 +722,15 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v10, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v16, v12, v14, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t @@ -758,13 +758,13 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 ; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0 @@ -796,15 +796,15 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v12, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v24, v16, v20, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 ; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t @@ -832,13 +832,13 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12 -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0 ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0 @@ -876,15 +876,15 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vmv1r.v v0, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill @@ -927,10 +927,10 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16 ; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24 ; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v24, v0 @@ -995,64 +995,62 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: csrr a4, vlenb -; ZVFHMIN-NEXT: slli a4, a4, 5 +; ZVFHMIN-NEXT: li a5, 24 +; ZVFHMIN-NEXT: mul a4, a4, a5 ; ZVFHMIN-NEXT: add a4, sp, a4 ; ZVFHMIN-NEXT: addi a4, a4, 16 ; ZVFHMIN-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v0, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v0, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb ; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: li a3, 25 +; ZVFHMIN-NEXT: mul a2, a2, a3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vl8r.v v0, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v8, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a2, a2, 3 ; ZVFHMIN-NEXT: add a2, sp, a2 @@ -1070,35 +1068,43 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v24, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv8r.v v8, v16 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vmv1r.v v0, v24 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb ; ZVFHMIN-NEXT: li a1, 24 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t +; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload @@ -1110,7 +1116,7 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 +; ZVFHMIN-NEXT: li a1, 25 ; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 @@ -1152,68 +1158,61 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: addi sp, sp, -16 ; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 5 +; ZVFHMIN-NEXT: li a2, 25 +; ZVFHMIN-NEXT: mul a1, a1, a2 ; ZVFHMIN-NEXT: sub sp, sp, a1 -; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb -; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a1, a1, a3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vmv8r.v v0, v8 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v12, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v8, v24, a2 +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vs1r.v v8, (a2) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmfeq.vv v13, v24, v24, v0.t -; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 4 ; ZVFHMIN-NEXT: add a3, sp, a3 ; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 -; ZVFHMIN-NEXT: vmv1r.v v0, v13 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: li a4, 24 -; ZVFHMIN-NEXT: mul a3, a3, a4 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma -; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0 +; ZVFHMIN-NEXT: vs8r.v v0, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4 +; ZVFHMIN-NEXT: vmv1r.v v0, v8 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmfeq.vv v12, v24, v24, v0.t +; ZVFHMIN-NEXT: vmv8r.v v0, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 4 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4 ; ZVFHMIN-NEXT: vmv1r.v v0, v12 -; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t -; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma +; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: li a3, 24 -; ZVFHMIN-NEXT: mul a2, a2, a3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: addi a2, sp, 16 +; ZVFHMIN-NEXT: vl1r.v v13, (a2) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vmv1r.v v0, v13 +; ZVFHMIN-NEXT: vmfeq.vv v12, v16, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v12 +; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0 +; ZVFHMIN-NEXT: vmv1r.v v0, v13 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload @@ -1221,7 +1220,8 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 ; ZVFHMIN-NEXT: add a2, sp, a2 ; ZVFHMIN-NEXT: addi a2, a2, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill @@ -1229,43 +1229,49 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: add a1, sp, a1 ; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8 ; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16 ; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vmv1r.v v0, v7 ; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: li a1, 24 -; ZVFHMIN-NEXT: mul a0, a0, a1 +; ZVFHMIN-NEXT: slli a1, a0, 4 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a0, a0, 5 +; ZVFHMIN-NEXT: li a1, 25 +; ZVFHMIN-NEXT: mul a0, a0, a1 ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16 ; ZVFHMIN-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll index 2fda344690bf..6787c8c24c87 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll @@ -18,7 +18,7 @@ entry: define i64 @reduce_add2(<4 x i64> %v) { ; CHECK-LABEL: reduce_add2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, ma +; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vmv.v.i v10, 8 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vredsum.vs v8, v8, v10 diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll index 70b53841bff4..06f48762e24c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll @@ -1658,10 +1658,10 @@ define <vscale x 1 x i1> @fcmp_oeq_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oeq", <vscale x 1 x i1> %m, i32 %evl) @@ -1678,11 +1678,11 @@ define <vscale x 1 x i1> @fcmp_oeq_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1701,11 +1701,11 @@ define <vscale x 1 x i1> @fcmp_oeq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1723,10 +1723,10 @@ define <vscale x 1 x i1> @fcmp_ogt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ogt", <vscale x 1 x i1> %m, i32 %evl) @@ -1743,11 +1743,11 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1766,11 +1766,11 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1788,10 +1788,10 @@ define <vscale x 1 x i1> @fcmp_oge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oge_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oge", <vscale x 1 x i1> %m, i32 %evl) @@ -1808,11 +1808,11 @@ define <vscale x 1 x i1> @fcmp_oge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1831,11 +1831,11 @@ define <vscale x 1 x i1> @fcmp_oge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1853,10 +1853,10 @@ define <vscale x 1 x i1> @fcmp_olt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_olt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"olt", <vscale x 1 x i1> %m, i32 %evl) @@ -1873,11 +1873,11 @@ define <vscale x 1 x i1> @fcmp_olt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1896,11 +1896,11 @@ define <vscale x 1 x i1> @fcmp_olt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1918,10 +1918,10 @@ define <vscale x 1 x i1> @fcmp_ole_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ole_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ole", <vscale x 1 x i1> %m, i32 %evl) @@ -1938,11 +1938,11 @@ define <vscale x 1 x i1> @fcmp_ole_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1961,11 +1961,11 @@ define <vscale x 1 x i1> @fcmp_ole_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -1985,10 +1985,10 @@ define <vscale x 1 x i1> @fcmp_one_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_one_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2009,11 +2009,11 @@ define <vscale x 1 x i1> @fcmp_one_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_one_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2036,11 +2036,11 @@ define <vscale x 1 x i1> @fcmp_one_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v9, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2062,10 +2062,10 @@ define <vscale x 1 x i1> @fcmp_ord_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ord_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v9, v8 @@ -2088,14 +2088,14 @@ define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v9, v8 ; ZVFHMIN-NEXT: ret @@ -2119,14 +2119,14 @@ define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret @@ -2147,10 +2147,10 @@ define <vscale x 1 x i1> @fcmp_ueq_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -2171,11 +2171,11 @@ define <vscale x 1 x i1> @fcmp_ueq_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -2198,11 +2198,11 @@ define <vscale x 1 x i1> @fcmp_ueq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v9, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -2223,10 +2223,10 @@ define <vscale x 1 x i1> @fcmp_ugt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2245,11 +2245,11 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2270,11 +2270,11 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2294,10 +2294,10 @@ define <vscale x 1 x i1> @fcmp_uge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uge_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2316,11 +2316,11 @@ define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2341,11 +2341,11 @@ define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2365,10 +2365,10 @@ define <vscale x 1 x i1> @fcmp_ult_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ult_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2387,11 +2387,11 @@ define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2412,11 +2412,11 @@ define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2436,10 +2436,10 @@ define <vscale x 1 x i1> @fcmp_ule_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ule_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2458,11 +2458,11 @@ define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2483,11 +2483,11 @@ define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v10, v8, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -2506,10 +2506,10 @@ define <vscale x 1 x i1> @fcmp_une_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_une_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v0, v9, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"une", <vscale x 1 x i1> %m, i32 %evl) @@ -2526,11 +2526,11 @@ define <vscale x 1 x i1> @fcmp_une_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_une_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v0, v10, v8, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -2549,11 +2549,11 @@ define <vscale x 1 x i1> @fcmp_une_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v0, v8, v10, v0.t ; ZVFHMIN-NEXT: ret %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 @@ -2573,10 +2573,10 @@ define <vscale x 1 x i1> @fcmp_uno_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uno_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -2599,14 +2599,14 @@ define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 ; ZVFHMIN-NEXT: ret @@ -2630,14 +2630,14 @@ define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v8, v9 ; ZVFHMIN-NEXT: ret @@ -2658,10 +2658,10 @@ define <vscale x 3 x i1> @fcmp_oeq_vv_nxv3f16(<vscale x 3 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv3f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2681,10 +2681,10 @@ define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2703,11 +2703,11 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2728,11 +2728,11 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2752,10 +2752,10 @@ define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2774,11 +2774,11 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2799,11 +2799,11 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2823,10 +2823,10 @@ define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_oge_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2845,11 +2845,11 @@ define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2870,11 +2870,11 @@ define <vscale x 8 x i1> @fcmp_oge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2894,10 +2894,10 @@ define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_olt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2916,11 +2916,11 @@ define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2941,11 +2941,11 @@ define <vscale x 8 x i1> @fcmp_olt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2965,10 +2965,10 @@ define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ole_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -2987,11 +2987,11 @@ define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3012,11 +3012,11 @@ define <vscale x 8 x i1> @fcmp_ole_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3037,10 +3037,10 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_one_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -3061,11 +3061,11 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -3088,11 +3088,11 @@ define <vscale x 8 x i1> @fcmp_one_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v9, v8 @@ -3114,13 +3114,13 @@ define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ord_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3142,14 +3142,14 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v10, v8 ; ZVFHMIN-NEXT: ret @@ -3173,14 +3173,14 @@ define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmand.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3201,10 +3201,10 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -3225,11 +3225,11 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -3252,11 +3252,11 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8 @@ -3277,10 +3277,10 @@ define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3299,11 +3299,11 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3324,11 +3324,11 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3348,10 +3348,10 @@ define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uge_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3370,11 +3370,11 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3395,11 +3395,11 @@ define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3419,10 +3419,10 @@ define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ult_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3441,11 +3441,11 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3466,11 +3466,11 @@ define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3490,10 +3490,10 @@ define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_ule_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3512,11 +3512,11 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3537,11 +3537,11 @@ define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmnot.m v0, v8 ; ZVFHMIN-NEXT: ret @@ -3561,10 +3561,10 @@ define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_une_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3583,11 +3583,11 @@ define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v16, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3608,11 +3608,11 @@ define <vscale x 8 x i1> @fcmp_une_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v16, v12, v0.t ; ZVFHMIN-NEXT: vmv1r.v v0, v8 ; ZVFHMIN-NEXT: ret @@ -3633,13 +3633,13 @@ define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: fcmp_uno_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3661,14 +3661,14 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, ; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v10, v8 ; ZVFHMIN-NEXT: ret @@ -3692,14 +3692,14 @@ define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half ; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vmv.v.x v8, a1 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12, v0.t -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t ; ZVFHMIN-NEXT: vmor.mm v0, v8, v10 ; ZVFHMIN-NEXT: ret @@ -3829,14 +3829,14 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a7, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; ZVFHMIN-NEXT: vmv8r.v v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli t0, a0, 4 -; ZVFHMIN-NEXT: add a0, t0, a0 +; ZVFHMIN-NEXT: slli a7, a0, 4 +; ZVFHMIN-NEXT: add a0, a7, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill @@ -3844,7 +3844,7 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: vmv1r.v v0, v24 ; ZVFHMIN-NEXT: addi a0, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a7, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v6, v16, v8, v0.t ; ZVFHMIN-NEXT: bltu a6, a4, .LBB171_2 ; ZVFHMIN-NEXT: # %bb.1: @@ -3857,16 +3857,16 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a6, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16 ; ZVFHMIN-NEXT: csrr a0, vlenb -; ZVFHMIN-NEXT: slli a7, a0, 4 -; ZVFHMIN-NEXT: add a0, a7, a0 +; ZVFHMIN-NEXT: slli a6, a0, 4 +; ZVFHMIN-NEXT: add a0, a6, a0 ; ZVFHMIN-NEXT: add a0, sp, a0 ; ZVFHMIN-NEXT: addi a0, a0, 16 ; ZVFHMIN-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 -; ZVFHMIN-NEXT: vsetvli zero, a6, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v5, v24, v8, v0.t ; ZVFHMIN-NEXT: add a0, a3, a3 ; ZVFHMIN-NEXT: bltu a2, a5, .LBB171_4 @@ -3881,6 +3881,9 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: vl1r.v v7, (a6) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vsetvli a6, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a3 +; ZVFHMIN-NEXT: sltu a6, a2, a5 +; ZVFHMIN-NEXT: addi a6, a6, -1 +; ZVFHMIN-NEXT: and a5, a6, a5 ; ZVFHMIN-NEXT: csrr a6, vlenb ; ZVFHMIN-NEXT: mv a7, a6 ; ZVFHMIN-NEXT: slli a6, a6, 3 @@ -3890,31 +3893,28 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: add a6, sp, a6 ; ZVFHMIN-NEXT: addi a6, a6, 16 ; ZVFHMIN-NEXT: vl8r.v v16, (a6) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a6, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a5, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: csrr a6, vlenb -; ZVFHMIN-NEXT: slli a7, a6, 4 -; ZVFHMIN-NEXT: add a6, a7, a6 -; ZVFHMIN-NEXT: add a6, sp, a6 -; ZVFHMIN-NEXT: addi a6, a6, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: csrr a6, vlenb -; ZVFHMIN-NEXT: slli a7, a6, 5 -; ZVFHMIN-NEXT: add a6, a7, a6 -; ZVFHMIN-NEXT: add a6, sp, a6 -; ZVFHMIN-NEXT: addi a6, a6, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a6) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a5, vlenb +; ZVFHMIN-NEXT: slli a6, a5, 4 +; ZVFHMIN-NEXT: add a5, a6, a5 +; ZVFHMIN-NEXT: add a5, sp, a5 +; ZVFHMIN-NEXT: addi a5, a5, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: csrr a5, vlenb +; ZVFHMIN-NEXT: slli a6, a5, 5 +; ZVFHMIN-NEXT: add a5, a6, a5 +; ZVFHMIN-NEXT: add a5, sp, a5 +; ZVFHMIN-NEXT: addi a5, a5, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 -; ZVFHMIN-NEXT: sltu a6, a2, a5 -; ZVFHMIN-NEXT: addi a6, a6, -1 -; ZVFHMIN-NEXT: and a5, a6, a5 -; ZVFHMIN-NEXT: csrr a6, vlenb -; ZVFHMIN-NEXT: slli a7, a6, 4 -; ZVFHMIN-NEXT: add a6, a7, a6 -; ZVFHMIN-NEXT: add a6, sp, a6 -; ZVFHMIN-NEXT: addi a6, a6, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a6) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a5, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a5, vlenb +; ZVFHMIN-NEXT: slli a6, a5, 4 +; ZVFHMIN-NEXT: add a5, a6, a5 +; ZVFHMIN-NEXT: add a5, sp, a5 +; ZVFHMIN-NEXT: addi a5, a5, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v4, v24, v8, v0.t ; ZVFHMIN-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslideup.vx v5, v6, a3 @@ -3923,16 +3923,16 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal ; ZVFHMIN-NEXT: mv a2, a4 ; ZVFHMIN-NEXT: .LBB171_6: ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16 -; ZVFHMIN-NEXT: csrr a4, vlenb -; ZVFHMIN-NEXT: slli a5, a4, 5 -; ZVFHMIN-NEXT: add a4, a5, a4 -; ZVFHMIN-NEXT: add a4, sp, a4 -; ZVFHMIN-NEXT: addi a4, a4, 16 -; ZVFHMIN-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a4, a2, 5 +; ZVFHMIN-NEXT: add a2, a4, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslideup.vx v8, v4, a3 diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll index 61cc754e21df..9c733b17dc6e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll @@ -2367,9 +2367,8 @@ define <vscale x 1 x i1> @icmp_eq_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2394,9 +2393,8 @@ define <vscale x 1 x i1> @icmp_eq_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmseq.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2451,9 +2449,8 @@ define <vscale x 1 x i1> @icmp_ne_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsne.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2478,9 +2475,8 @@ define <vscale x 1 x i1> @icmp_ne_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsne.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2535,9 +2531,8 @@ define <vscale x 1 x i1> @icmp_ugt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2562,9 +2557,8 @@ define <vscale x 1 x i1> @icmp_ugt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2619,9 +2613,8 @@ define <vscale x 1 x i1> @icmp_uge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2647,9 +2640,8 @@ define <vscale x 1 x i1> @icmp_uge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsleu.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2704,9 +2696,8 @@ define <vscale x 1 x i1> @icmp_ult_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2731,9 +2722,8 @@ define <vscale x 1 x i1> @icmp_ult_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsltu.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2788,9 +2778,8 @@ define <vscale x 1 x i1> @icmp_sgt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2815,9 +2804,8 @@ define <vscale x 1 x i1> @icmp_sgt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2872,9 +2860,8 @@ define <vscale x 1 x i1> @icmp_sge_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2900,9 +2887,8 @@ define <vscale x 1 x i1> @icmp_sge_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2957,9 +2943,8 @@ define <vscale x 1 x i1> @icmp_slt_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2984,9 +2969,8 @@ define <vscale x 1 x i1> @icmp_slt_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmslt.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -3041,9 +3025,8 @@ define <vscale x 1 x i1> @icmp_sle_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -3068,9 +3051,8 @@ define <vscale x 1 x i1> @icmp_sle_vx_swap_nxv1i64(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmsle.vv v0, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -3129,9 +3111,8 @@ define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmseq.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3158,9 +3139,8 @@ define <vscale x 8 x i1> @icmp_eq_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmseq.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3220,9 +3200,8 @@ define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsne.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3249,9 +3228,8 @@ define <vscale x 8 x i1> @icmp_ne_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 %b ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsne.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3311,9 +3289,8 @@ define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3340,9 +3317,8 @@ define <vscale x 8 x i1> @icmp_ugt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3402,9 +3378,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsleu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3432,9 +3407,8 @@ define <vscale x 8 x i1> @icmp_uge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsleu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3494,9 +3468,8 @@ define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3523,9 +3496,8 @@ define <vscale x 8 x i1> @icmp_ult_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsltu.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3585,9 +3557,8 @@ define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3614,9 +3585,8 @@ define <vscale x 8 x i1> @icmp_sgt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3676,9 +3646,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3706,9 +3675,8 @@ define <vscale x 8 x i1> @icmp_sge_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3768,9 +3736,8 @@ define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3797,9 +3764,8 @@ define <vscale x 8 x i1> @icmp_slt_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmslt.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3859,9 +3825,8 @@ define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -3888,9 +3853,8 @@ define <vscale x 8 x i1> @icmp_sle_vx_swap_nxv8i64(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmsle.vv v16, v24, v8, v0.t ; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll index fee6799e992f..77f3cf3ca498 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll @@ -1487,9 +1487,8 @@ define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1514,9 +1513,8 @@ define <vscale x 1 x i64> @vadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1583,9 +1581,8 @@ define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1610,9 +1607,8 @@ define <vscale x 2 x i64> @vadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1679,9 +1675,8 @@ define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1706,9 +1701,8 @@ define <vscale x 4 x i64> @vadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1775,9 +1769,8 @@ define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1802,9 +1795,8 @@ define <vscale x 8 x i64> @vadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll index b0c5a72f6f9e..4866bb06f19e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll @@ -1314,9 +1314,8 @@ define <vscale x 1 x i64> @vand_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1341,9 +1340,8 @@ define <vscale x 1 x i64> @vand_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1410,9 +1408,8 @@ define <vscale x 2 x i64> @vand_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1437,9 +1434,8 @@ define <vscale x 2 x i64> @vand_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1506,9 +1502,8 @@ define <vscale x 4 x i64> @vand_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1533,9 +1528,8 @@ define <vscale x 4 x i64> @vand_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1602,9 +1596,8 @@ define <vscale x 8 x i64> @vand_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1629,9 +1622,8 @@ define <vscale x 8 x i64> @vand_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll index 32992301bd39..763b2908b102 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll @@ -1115,9 +1115,8 @@ define <vscale x 1 x i64> @vandn_vx_vp_nxv1i64(i64 %a, <vscale x 1 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; CHECK-RV32-NEXT: vlse64.v v9, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1139,9 +1138,8 @@ define <vscale x 1 x i64> @vandn_vx_vp_nxv1i64(i64 %a, <vscale x 1 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v9, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v9, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 @@ -1208,9 +1206,8 @@ define <vscale x 2 x i64> @vandn_vx_vp_nxv2i64(i64 %a, <vscale x 2 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; CHECK-RV32-NEXT: vlse64.v v10, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v10, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1232,9 +1229,8 @@ define <vscale x 2 x i64> @vandn_vx_vp_nxv2i64(i64 %a, <vscale x 2 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v10, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v10, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 @@ -1301,9 +1297,8 @@ define <vscale x 4 x i64> @vandn_vx_vp_nxv4i64(i64 %a, <vscale x 4 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v12, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1325,9 +1320,8 @@ define <vscale x 4 x i64> @vandn_vx_vp_nxv4i64(i64 %a, <vscale x 4 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v12, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v12, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 @@ -1394,9 +1388,8 @@ define <vscale x 8 x i64> @vandn_vx_vp_nxv8i64(i64 %a, <vscale x 8 x i64> %b, <v ; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-RV32-NEXT: addi a0, sp, 8 -; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero ; CHECK-RV32-NEXT: vand.vv v8, v8, v16, v0.t ; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1418,9 +1411,8 @@ define <vscale x 8 x i64> @vandn_vx_vp_nxv8i64(i64 %a, <vscale x 8 x i64> %b, <v ; CHECK-ZVKB32-NEXT: sw a0, 8(sp) ; CHECK-ZVKB32-NEXT: sw a1, 12(sp) ; CHECK-ZVKB32-NEXT: addi a0, sp, 8 -; CHECK-ZVKB32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero ; CHECK-ZVKB32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; CHECK-ZVKB32-NEXT: vlse64.v v16, (a0), zero ; CHECK-ZVKB32-NEXT: vand.vv v8, v8, v16, v0.t ; CHECK-ZVKB32-NEXT: addi sp, sp, 16 ; CHECK-ZVKB32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll index 2814be2792de..03e4e1f445be 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll @@ -893,9 +893,8 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -920,9 +919,8 @@ define <vscale x 1 x i64> @vdiv_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -969,9 +967,8 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -996,9 +993,8 @@ define <vscale x 2 x i64> @vdiv_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1045,9 +1041,8 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1072,9 +1067,8 @@ define <vscale x 4 x i64> @vdiv_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1121,9 +1115,8 @@ define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1148,9 +1141,8 @@ define <vscale x 8 x i64> @vdiv_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdiv.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll index 3e913d4f682e..2f35f91d77a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll @@ -892,9 +892,8 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -919,9 +918,8 @@ define <vscale x 1 x i64> @vdivu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -968,9 +966,8 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -995,9 +992,8 @@ define <vscale x 2 x i64> @vdivu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1044,9 +1040,8 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1071,9 +1066,8 @@ define <vscale x 4 x i64> @vdivu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1120,9 +1114,8 @@ define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1147,9 +1140,8 @@ define <vscale x 8 x i64> @vdivu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vdivu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll index 87bc9f27d6dc..31359c3f68ec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -679,10 +679,10 @@ define <vscale x 1 x half> @vfadd_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -700,10 +700,10 @@ define <vscale x 1 x half> @vfadd_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -722,11 +722,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -747,11 +747,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16_commute(<vscale x 1 x half> %va, ha ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v8, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -772,11 +772,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -797,11 +797,11 @@ define <vscale x 1 x half> @vfadd_vf_nxv1f16_unmasked_commute(<vscale x 1 x half ; ZVFHMIN-LABEL: vfadd_vf_nxv1f16_unmasked_commute: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v8, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -823,10 +823,10 @@ define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -844,10 +844,10 @@ define <vscale x 2 x half> @vfadd_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -866,11 +866,11 @@ define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -891,11 +891,11 @@ define <vscale x 2 x half> @vfadd_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -917,10 +917,10 @@ define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -938,10 +938,10 @@ define <vscale x 4 x half> @vfadd_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -960,11 +960,11 @@ define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -985,11 +985,11 @@ define <vscale x 4 x half> @vfadd_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -1011,10 +1011,10 @@ define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfadd_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1032,10 +1032,10 @@ define <vscale x 8 x half> @vfadd_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfadd_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1054,11 +1054,11 @@ define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1079,11 +1079,11 @@ define <vscale x 8 x half> @vfadd_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfadd_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1105,10 +1105,10 @@ define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfadd_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1126,10 +1126,10 @@ define <vscale x 16 x half> @vfadd_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfadd_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1148,11 +1148,11 @@ define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1173,11 +1173,11 @@ define <vscale x 16 x half> @vfadd_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfadd_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1205,23 +1205,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1231,10 +1230,11 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB48_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1266,22 +1266,21 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1291,9 +1290,10 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB49_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1324,14 +1324,10 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -1352,15 +1348,18 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1370,20 +1369,21 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB50_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1416,16 +1416,10 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -1436,18 +1430,22 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1457,14 +1455,15 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB51_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll index 061af454aa8b..2205769d3494 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -641,10 +641,10 @@ define <vscale x 1 x half> @vfdiv_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -662,10 +662,10 @@ define <vscale x 1 x half> @vfdiv_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -684,11 +684,11 @@ define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -709,11 +709,11 @@ define <vscale x 1 x half> @vfdiv_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -735,10 +735,10 @@ define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -756,10 +756,10 @@ define <vscale x 2 x half> @vfdiv_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -778,11 +778,11 @@ define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -803,11 +803,11 @@ define <vscale x 2 x half> @vfdiv_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -829,10 +829,10 @@ define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -850,10 +850,10 @@ define <vscale x 4 x half> @vfdiv_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -872,11 +872,11 @@ define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -897,11 +897,11 @@ define <vscale x 4 x half> @vfdiv_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -923,10 +923,10 @@ define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -944,10 +944,10 @@ define <vscale x 8 x half> @vfdiv_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -966,11 +966,11 @@ define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -991,11 +991,11 @@ define <vscale x 8 x half> @vfdiv_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfdiv_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1017,10 +1017,10 @@ define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1038,10 +1038,10 @@ define <vscale x 16 x half> @vfdiv_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfdiv_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1060,11 +1060,11 @@ define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1085,11 +1085,11 @@ define <vscale x 16 x half> @vfdiv_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfdiv_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1117,23 +1117,22 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1143,10 +1142,11 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB44_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1178,22 +1178,21 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1203,9 +1202,10 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB45_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1236,14 +1236,10 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -1264,15 +1260,18 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1282,20 +1281,21 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB46_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1328,16 +1328,10 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -1348,18 +1342,22 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1369,14 +1367,15 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB47_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll index 02d6229e9924..5d998c4e739d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll @@ -290,10 +290,10 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -311,10 +311,10 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -334,10 +334,10 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -355,10 +355,10 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -378,10 +378,10 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -399,10 +399,10 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -422,10 +422,10 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -443,10 +443,10 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmax_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -466,10 +466,10 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfmax_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -487,10 +487,10 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfmax_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -516,23 +516,22 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -542,10 +541,11 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB22_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -577,22 +577,21 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -602,9 +601,10 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB23_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll index f7f80299785d..48a4c1386900 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll @@ -290,10 +290,10 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -311,10 +311,10 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -334,10 +334,10 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -355,10 +355,10 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -378,10 +378,10 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -399,10 +399,10 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -422,10 +422,10 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -443,10 +443,10 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmin_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -466,10 +466,10 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfmin_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -487,10 +487,10 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfmin_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -516,23 +516,22 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -542,10 +541,11 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB22_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -577,22 +577,21 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -602,9 +601,10 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB23_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll index 7e5523044a01..06f74dd99574 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -19,10 +19,10 @@ define <vscale x 1 x half> @vfmul_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -40,10 +40,10 @@ define <vscale x 1 x half> @vfmul_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -62,11 +62,11 @@ define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -87,11 +87,11 @@ define <vscale x 1 x half> @vfmul_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -113,10 +113,10 @@ define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -134,10 +134,10 @@ define <vscale x 2 x half> @vfmul_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -156,11 +156,11 @@ define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -181,11 +181,11 @@ define <vscale x 2 x half> @vfmul_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -207,10 +207,10 @@ define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -228,10 +228,10 @@ define <vscale x 4 x half> @vfmul_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -250,11 +250,11 @@ define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -275,11 +275,11 @@ define <vscale x 4 x half> @vfmul_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -301,10 +301,10 @@ define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfmul_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -322,10 +322,10 @@ define <vscale x 8 x half> @vfmul_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfmul_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -344,11 +344,11 @@ define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -369,11 +369,11 @@ define <vscale x 8 x half> @vfmul_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfmul_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -395,10 +395,10 @@ define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfmul_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -416,10 +416,10 @@ define <vscale x 16 x half> @vfmul_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfmul_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -438,11 +438,11 @@ define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -463,11 +463,11 @@ define <vscale x 16 x half> @vfmul_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfmul_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -495,23 +495,22 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -521,10 +520,11 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB20_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -556,22 +556,21 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -581,9 +580,10 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB21_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -614,14 +614,10 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -642,15 +638,18 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -660,20 +659,21 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB22_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -706,16 +706,10 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -726,18 +720,22 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -747,14 +745,15 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB23_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll index b7f2133144e7..575d50d11f0a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll @@ -42,9 +42,9 @@ define <vscale x 2 x i1> @vfptosi_nxv2i1_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptosi_nxv2i1_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t ; ZVFHMIN-NEXT: ret @@ -62,9 +62,9 @@ define <vscale x 2 x i1> @vfptosi_nxv2i1_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptosi_nxv2i1_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll index d990c74c67d5..e33ab98c0f85 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll @@ -130,9 +130,8 @@ define <vscale x 2 x i7> @vfptosi_v4i7_v4f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfptosi_v4i7_v4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -153,9 +152,8 @@ define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptosi_nxv2i8_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -174,9 +172,8 @@ define <vscale x 2 x i8> @vfptosi_nxv2i8_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptosi_nxv2i8_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0 @@ -196,9 +193,8 @@ define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptosi_nxv2i16_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -214,9 +210,8 @@ define <vscale x 2 x i16> @vfptosi_nxv2i16_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptosi_nxv2i16_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptosi.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -235,9 +230,9 @@ define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptosi_nxv2i32_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -254,9 +249,9 @@ define <vscale x 2 x i32> @vfptosi_nxv2i32_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptosi_nxv2i32_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptosi.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -276,9 +271,9 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptosi_nxv2i64_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.rtz.x.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -286,21 +281,13 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc } define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) { -; ZVFH-LABEL: vfptosi_nxv2i64_nxv2f16_unmasked: -; ZVFH: # %bb.0: -; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFH-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFH-NEXT: vfwcvt.rtz.x.f.v v8, v10 -; ZVFH-NEXT: ret -; -; ZVFHMIN-LABEL: vfptosi_nxv2i64_nxv2f16_unmasked: -; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.rtz.x.f.v v8, v10 -; ZVFHMIN-NEXT: ret +; CHECK-LABEL: vfptosi_nxv2i64_nxv2f16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10 +; CHECK-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptosi.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) ret <vscale x 2 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll index 8ac5992bd5eb..e1d0ad475858 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll @@ -42,9 +42,9 @@ define <vscale x 2 x i1> @vfptoui_nxv2i1_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptoui_nxv2i1_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t ; ZVFHMIN-NEXT: ret @@ -62,9 +62,9 @@ define <vscale x 2 x i1> @vfptoui_nxv2i1_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptoui_nxv2i1_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll index 3b24a648d97f..86222ecfadfe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll @@ -130,9 +130,8 @@ define <vscale x 2 x i7> @vfptoui_v4i7_v4f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfptoui_v4i7_v4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -153,9 +152,8 @@ define <vscale x 2 x i8> @vfptoui_nxv2i8_nxv2f16(<vscale x 2 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfptoui_nxv2i8_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0, v0.t @@ -174,9 +172,8 @@ define <vscale x 2 x i8> @vfptoui_nxv2i8_nxv2f16_unmasked(<vscale x 2 x half> %v ; ; ZVFHMIN-LABEL: vfptoui_nxv2i8_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0 @@ -196,9 +193,8 @@ define <vscale x 2 x i16> @vfptoui_nxv2i16_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptoui_nxv2i16_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptoui.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -214,9 +210,8 @@ define <vscale x 2 x i16> @vfptoui_nxv2i16_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptoui_nxv2i16_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i16> @llvm.vp.fptoui.nxv2i16.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -235,9 +230,9 @@ define <vscale x 2 x i32> @vfptoui_nxv2i32_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptoui_nxv2i32_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptoui.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -254,9 +249,9 @@ define <vscale x 2 x i32> @vfptoui_nxv2i32_nxv2f16_unmasked(<vscale x 2 x half> ; ; ZVFHMIN-LABEL: vfptoui_nxv2i32_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9 ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i32> @llvm.vp.fptoui.nxv2i32.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) @@ -276,9 +271,9 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc ; ; ZVFHMIN-LABEL: vfptoui_nxv2i64_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v10, v0.t ; ZVFHMIN-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptoui.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl) @@ -286,21 +281,13 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f16(<vscale x 2 x half> %va, <vsc } define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) { -; ZVFH-LABEL: vfptoui_nxv2i64_nxv2f16_unmasked: -; ZVFH: # %bb.0: -; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; ZVFH-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFH-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; ZVFH-NEXT: vfwcvt.rtz.xu.f.v v8, v10 -; ZVFH-NEXT: ret -; -; ZVFHMIN-LABEL: vfptoui_nxv2i64_nxv2f16_unmasked: -; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; ZVFHMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v10 -; ZVFHMIN-NEXT: ret +; CHECK-LABEL: vfptoui_nxv2i64_nxv2f16_unmasked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vfwcvt.f.f.v v10, v8 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10 +; CHECK-NEXT: ret %v = call <vscale x 2 x i64> @llvm.vp.fptoui.nxv2i64.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl) ret <vscale x 2 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll index 8e57be1e0697..e94d0a60bbfc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll @@ -242,9 +242,9 @@ define <vscale x 1 x half> @vfsqrt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -262,9 +262,9 @@ define <vscale x 1 x half> @vfsqrt_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -284,9 +284,9 @@ define <vscale x 2 x half> @vfsqrt_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -304,9 +304,9 @@ define <vscale x 2 x half> @vfsqrt_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v9, v9 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -326,9 +326,9 @@ define <vscale x 4 x half> @vfsqrt_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v10, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -346,9 +346,9 @@ define <vscale x 4 x half> @vfsqrt_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v10, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -368,9 +368,9 @@ define <vscale x 8 x half> @vfsqrt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v12, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -388,9 +388,9 @@ define <vscale x 8 x half> @vfsqrt_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v12, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -410,9 +410,9 @@ define <vscale x 16 x half> @vfsqrt_vv_nxv16f16(<vscale x 16 x half> %va, <vscal ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -430,9 +430,9 @@ define <vscale x 16 x half> @vfsqrt_vv_nxv16f16_unmasked(<vscale x 16 x half> %v ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -458,13 +458,13 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16(<vscale x 32 x half> %va, <vscal ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 +; ZVFHMIN-NEXT: sltu a4, a0, a3 +; ZVFHMIN-NEXT: addi a4, a4, -1 +; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 -; ZVFHMIN-NEXT: sltu a2, a0, a3 -; ZVFHMIN-NEXT: addi a2, a2, -1 -; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v24, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24 @@ -472,9 +472,10 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16(<vscale x 32 x half> %va, <vscal ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB22_2: +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v16 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -498,14 +499,14 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16_unmasked(<vscale x 32 x half> %v ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 +; ZVFHMIN-NEXT: sltu a4, a0, a3 +; ZVFHMIN-NEXT: addi a4, a4, -1 +; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 -; ZVFHMIN-NEXT: sltu a2, a0, a3 -; ZVFHMIN-NEXT: addi a2, a2, -1 -; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -513,8 +514,9 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16_unmasked(<vscale x 32 x half> %v ; ZVFHMIN-NEXT: # %bb.1: ; ZVFHMIN-NEXT: mv a0, a1 ; ZVFHMIN-NEXT: .LBB23_2: +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsqrt.v v16, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll index d034f65479a1..56ed560f9ec9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -641,10 +641,10 @@ define <vscale x 1 x half> @vfsub_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv1f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -662,10 +662,10 @@ define <vscale x 1 x half> @vfsub_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -684,11 +684,11 @@ define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -709,11 +709,11 @@ define <vscale x 1 x half> @vfsub_vf_nxv1f16_unmasked(<vscale x 1 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv1f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -735,10 +735,10 @@ define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv2f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -756,10 +756,10 @@ define <vscale x 2 x half> @vfsub_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v9, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -778,11 +778,11 @@ define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -803,11 +803,11 @@ define <vscale x 2 x half> @vfsub_vf_nxv2f16_unmasked(<vscale x 2 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv2f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, mf2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v9, v10, v8 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 @@ -829,10 +829,10 @@ define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv4f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v12, v10, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -850,10 +850,10 @@ define <vscale x 4 x half> @vfsub_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v12, v10 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -872,11 +872,11 @@ define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v10, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -897,11 +897,11 @@ define <vscale x 4 x half> @vfsub_vf_nxv4f16_unmasked(<vscale x 4 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv4f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v9, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v10, v10, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 @@ -923,10 +923,10 @@ define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x ; ; ZVFHMIN-LABEL: vfsub_vv_nxv8f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v16, v12, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -944,10 +944,10 @@ define <vscale x 8 x half> @vfsub_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, < ; ; ZVFHMIN-LABEL: vfsub_vv_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v16, v12 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -966,11 +966,11 @@ define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b, < ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v12, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -991,11 +991,11 @@ define <vscale x 8 x half> @vfsub_vf_nxv8f16_unmasked(<vscale x 8 x half> %va, h ; ZVFHMIN-LABEL: vfsub_vf_nxv8f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v10, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v12, v12, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 @@ -1017,10 +1017,10 @@ define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale ; ; ZVFHMIN-LABEL: vfsub_vv_nxv16f16: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1038,10 +1038,10 @@ define <vscale x 16 x half> @vfsub_vv_nxv16f16_unmasked(<vscale x 16 x half> %va ; ; ZVFHMIN-LABEL: vfsub_vv_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1060,11 +1060,11 @@ define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1085,11 +1085,11 @@ define <vscale x 16 x half> @vfsub_vf_nxv16f16_unmasked(<vscale x 16 x half> %va ; ZVFHMIN-LABEL: vfsub_vf_nxv16f16_unmasked: ; ZVFHMIN: # %bb.0: ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 -; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v12, a1 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1117,23 +1117,22 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v7, v0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 -; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1143,10 +1142,11 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale ; ZVFHMIN-NEXT: .LBB44_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 ; ZVFHMIN-NEXT: vmv1r.v v0, v7 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1178,22 +1178,21 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a1, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1203,9 +1202,10 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB45_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1236,14 +1236,10 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: add a1, a2, a1 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v24, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a3, a1, 3 @@ -1264,15 +1260,18 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a4, a3, 3 -; ZVFHMIN-NEXT: add a3, a4, a3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a3, a2, 3 +; ZVFHMIN-NEXT: add a2, a3, a2 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1282,20 +1281,21 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b ; ZVFHMIN-NEXT: .LBB46_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a2, a1, 3 -; ZVFHMIN-NEXT: add a1, a2, a1 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a1, a0, 3 +; ZVFHMIN-NEXT: add a0, a1, a0 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 @@ -1328,16 +1328,10 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: slli a1, a1, 4 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmv8r.v v16, v8 ; ZVFHMIN-NEXT: fmv.x.h a1, fa0 ; ZVFHMIN-NEXT: csrr a2, vlenb -; ZVFHMIN-NEXT: vmset.m v7 -; ZVFHMIN-NEXT: addi a3, sp, 16 -; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma -; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 ; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vmv.v.x v16, a1 ; ZVFHMIN-NEXT: csrr a1, vlenb ; ZVFHMIN-NEXT: slli a1, a1, 3 @@ -1348,18 +1342,22 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: srli a2, a2, 2 ; ZVFHMIN-NEXT: sub a3, a0, a1 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a2 +; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: sltu a2, a0, a3 ; ZVFHMIN-NEXT: addi a2, a2, -1 ; ZVFHMIN-NEXT: and a2, a2, a3 -; ZVFHMIN-NEXT: csrr a3, vlenb -; ZVFHMIN-NEXT: slli a3, a3, 3 -; ZVFHMIN-NEXT: add a3, sp, a3 -; ZVFHMIN-NEXT: addi a3, a3, 16 -; ZVFHMIN-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload -; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m4, ta, ma +; ZVFHMIN-NEXT: vmv8r.v v16, v8 +; ZVFHMIN-NEXT: addi a3, sp, 16 +; ZVFHMIN-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill +; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma +; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20 +; ZVFHMIN-NEXT: csrr a2, vlenb +; ZVFHMIN-NEXT: slli a2, a2, 3 +; ZVFHMIN-NEXT: add a2, sp, a2 +; ZVFHMIN-NEXT: addi a2, a2, 16 +; ZVFHMIN-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28 -; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v8, v16, v0.t ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16 @@ -1369,14 +1367,15 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va ; ZVFHMIN-NEXT: .LBB47_2: ; ZVFHMIN-NEXT: addi a1, sp, 16 ; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24 -; ZVFHMIN-NEXT: csrr a1, vlenb -; ZVFHMIN-NEXT: slli a1, a1, 3 -; ZVFHMIN-NEXT: add a1, sp, a1 -; ZVFHMIN-NEXT: addi a1, a1, 16 -; ZVFHMIN-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; ZVFHMIN-NEXT: csrr a0, vlenb +; ZVFHMIN-NEXT: slli a0, a0, 3 +; ZVFHMIN-NEXT: add a0, sp, a0 +; ZVFHMIN-NEXT: addi a0, a0, 16 +; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0 -; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir index f9b81863d68d..c4a383454610 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir @@ -573,6 +573,86 @@ body: | PseudoVSE8_V_MF2 %x, $noreg, 1, 3 /* e8 */ ... --- +name: vsm_v +body: | + bb.0: + ; CHECK-LABEL: name: vsm_v + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B8 %x, $noreg, 1, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + PseudoVSM_V_B8 %x, $noreg, 1, 0 +... +--- +name: vsm_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vsm_v_incompatible_emul + ; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */ + ; CHECK-NEXT: PseudoVSM_V_B16 %x, $noreg, 1, 0 /* e8 */ + %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 + PseudoVSM_V_B16 %x, $noreg, 1, 0 +... +--- +name: vleN_v +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vleN_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v_incompatible_eew + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 +... +--- +name: vleN_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v_incompatible_emul + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 + %x:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vlm_v +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, 1, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */ + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 +... +--- +name: vlm_v_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v_incompatible_eew + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 +... +--- +name: vlm_v_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vlm_v_incompatible_emul + ; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */ + %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0 + %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 +... +--- name: vsseN_v body: | bb.0: @@ -705,6 +785,56 @@ body: | %y:vr = PseudoVLUXEI8_V_MF2_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 ... --- +name: vluxeiN_v_idx_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 + %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 +... +--- +name: vluxeiN_v_idx_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 +... +--- +name: vluxeiN_v_vd +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_vd + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vluxeiN_v_vd_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_v_vd_incompatible_eew + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0 +... +--- +name: vluxeiN_vd_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vluxeiN_vd_incompatible_emul + ; CHECK: %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- name: vmop_mm body: | bb.0: @@ -1094,3 +1224,116 @@ body: | %x:vr = PseudoVMAND_MM_B1 $noreg, $noreg, -1, 0 %y:vr = PseudoVIOTA_M_MF2 $noreg, %x, 1, 3 /* e8 */, 0 ... +name: vred_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vred_vs1 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 +... +--- +name: vred_vs1_vs2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 +... +--- +name: vred_vs1_vs2_incompatible_eew +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_eew + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 4 /* e16 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_M1_E8 $noreg, %x, %x, 1, 4 /* e16 */, 0 +... +--- +name: vred_vs1_vs2_incompatible_emul +body: | + bb.0: + ; CHECK-LABEL: name: vred_vs1_vs2_incompatible_emul + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDAND_VS_MF2_E8 $noreg, %x, %x, 1, 3 /* e8 */, 0 +... +--- +name: vred_other_user_is_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_other_user_is_vl0 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 +... +--- +name: vred_both_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_both_vl0 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 +... +--- +name: vred_vl0_and_vlreg +body: | + bb.0: + ; CHECK-LABEL: name: vred_vl0_and_vlreg + ; CHECK: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 /* tu, mu */ + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, %vl, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 0, 3 /* e8 */, 0 +... +--- +name: vred_vlreg_and_vl0 +body: | + bb.0: + ; CHECK-LABEL: name: vred_vlreg_and_vl0 + ; CHECK: %vl:gprnox0 = COPY $x1 + ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 /* tu, mu */ + %vl:gprnox0 = COPY $x1 + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 0, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, %vl, 3 /* e8 */, 0 +... +--- +name: vred_other_user_is_vl2 +body: | + bb.0: + ; CHECK-LABEL: name: vred_other_user_is_vl2 + ; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 + %y:vr = PseudoVREDSUM_VS_M1_E8 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 + %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 2, 3 /* e8 */, 0 +... diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir index 3f966b036589..0a366f4fd89c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir @@ -110,4 +110,24 @@ body: | %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 %z:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, -1, 3 /* e8 */, 0 ... +--- +name: vfcvt_x_f_v_nofpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfcvt_x_f_v_nofpexcept + ; CHECK: %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, 1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... +--- +name: vfcvt_x_f_v_fpexcept +body: | + bb.0: + ; CHECK-LABEL: name: vfcvt_x_f_v_fpexcept + ; CHECK: %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e8 */, 0 /* tu, mu */ + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 3 /* e32 */, 0 + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... diff --git a/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir b/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir new file mode 100644 index 000000000000..e8f7957de47c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vlopt-volatile-ld.mir @@ -0,0 +1,13 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vl-optimizer -verify-machineinstrs | FileCheck %s + +--- +name: vleN_v_volatile +body: | + bb.0: + ; CHECK-LABEL: name: vleN_v + ; CHECK: %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */ :: (volatile load (<vscale x 1 x s64>)) + ; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */ + %x:vr = PseudoVLE8_V_M1 $noreg, $noreg, -1, 3 /* e8 */, 0 :: (volatile load (<vscale x 1 x s64>)) + %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 3 /* e8 */, 0 +... diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll index 333117c8dce2..c334e70f1f35 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll @@ -1654,9 +1654,9 @@ define <vscale x 1 x i64> @vmacc_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vmacc.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1685,9 +1685,9 @@ define <vscale x 1 x i64> @vmacc_vx_nxv1i64_unmasked(<vscale x 1 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; RV32-NEXT: vmacc.vv v9, v8, v10 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1729,9 +1729,8 @@ define <vscale x 1 x i64> @vmacc_vx_nxv1i64_ta(<vscale x 1 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmacc.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv.v.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1791,9 +1790,9 @@ define <vscale x 2 x i64> @vmacc_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; RV32-NEXT: vmacc.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1822,9 +1821,9 @@ define <vscale x 2 x i64> @vmacc_vx_nxv2i64_unmasked(<vscale x 2 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, ma ; RV32-NEXT: vmacc.vv v10, v8, v12 ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1866,9 +1865,8 @@ define <vscale x 2 x i64> @vmacc_vx_nxv2i64_ta(<vscale x 2 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmacc.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1928,9 +1926,9 @@ define <vscale x 4 x i64> @vmacc_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; RV32-NEXT: vmacc.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -1959,9 +1957,9 @@ define <vscale x 4 x i64> @vmacc_vx_nxv4i64_unmasked(<vscale x 4 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, ma ; RV32-NEXT: vmacc.vv v12, v8, v16 ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2003,9 +2001,8 @@ define <vscale x 4 x i64> @vmacc_vx_nxv4i64_ta(<vscale x 4 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmacc.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2067,9 +2064,9 @@ define <vscale x 8 x i64> @vmacc_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu ; RV32-NEXT: vmacc.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2098,9 +2095,9 @@ define <vscale x 8 x i64> @vmacc_vx_nxv8i64_unmasked(<vscale x 8 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, ma ; RV32-NEXT: vmacc.vv v16, v8, v24 ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2143,9 +2140,8 @@ define <vscale x 8 x i64> @vmacc_vx_nxv8i64_ta(<vscale x 8 x i64> %a, i64 %b, <v ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vmacc.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll index 7818e99c5562..3df0763fdc75 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll @@ -1124,9 +1124,8 @@ define <vscale x 1 x i64> @vmax_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1151,9 +1150,8 @@ define <vscale x 1 x i64> @vmax_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1200,9 +1198,8 @@ define <vscale x 2 x i64> @vmax_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1227,9 +1224,8 @@ define <vscale x 2 x i64> @vmax_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1276,9 +1272,8 @@ define <vscale x 4 x i64> @vmax_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1303,9 +1298,8 @@ define <vscale x 4 x i64> @vmax_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1352,9 +1346,8 @@ define <vscale x 8 x i64> @vmax_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1379,9 +1372,8 @@ define <vscale x 8 x i64> @vmax_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmax.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll index 674b0b806000..8147d467be04 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll @@ -1123,9 +1123,8 @@ define <vscale x 1 x i64> @vmaxu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1150,9 +1149,8 @@ define <vscale x 1 x i64> @vmaxu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1199,9 +1197,8 @@ define <vscale x 2 x i64> @vmaxu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1226,9 +1223,8 @@ define <vscale x 2 x i64> @vmaxu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1275,9 +1271,8 @@ define <vscale x 4 x i64> @vmaxu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1302,9 +1297,8 @@ define <vscale x 4 x i64> @vmaxu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1351,9 +1345,8 @@ define <vscale x 8 x i64> @vmaxu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1378,9 +1371,8 @@ define <vscale x 8 x i64> @vmaxu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmaxu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll index 79631cd80594..614bd4cbde9e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll @@ -1124,9 +1124,8 @@ define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1151,9 +1150,8 @@ define <vscale x 1 x i64> @vmin_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1200,9 +1198,8 @@ define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1227,9 +1224,8 @@ define <vscale x 2 x i64> @vmin_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1276,9 +1272,8 @@ define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1303,9 +1298,8 @@ define <vscale x 4 x i64> @vmin_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1352,9 +1346,8 @@ define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1379,9 +1372,8 @@ define <vscale x 8 x i64> @vmin_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmin.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll index bc93b62fab7f..21160553af59 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll @@ -1123,9 +1123,8 @@ define <vscale x 1 x i64> @vminu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1150,9 +1149,8 @@ define <vscale x 1 x i64> @vminu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1199,9 +1197,8 @@ define <vscale x 2 x i64> @vminu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1226,9 +1223,8 @@ define <vscale x 2 x i64> @vminu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1275,9 +1271,8 @@ define <vscale x 4 x i64> @vminu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1302,9 +1297,8 @@ define <vscale x 4 x i64> @vminu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1351,9 +1345,8 @@ define <vscale x 8 x i64> @vminu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1378,9 +1371,8 @@ define <vscale x 8 x i64> @vminu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vminu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll index b63098b64e29..f0907e41cd43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll @@ -934,9 +934,8 @@ define <vscale x 1 x i64> @vmul_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -961,9 +960,8 @@ define <vscale x 1 x i64> @vmul_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1010,9 +1008,8 @@ define <vscale x 2 x i64> @vmul_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1037,9 +1034,8 @@ define <vscale x 2 x i64> @vmul_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1086,9 +1082,8 @@ define <vscale x 4 x i64> @vmul_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1113,9 +1108,8 @@ define <vscale x 4 x i64> @vmul_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1162,9 +1156,8 @@ define <vscale x 8 x i64> @vmul_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1189,9 +1182,8 @@ define <vscale x 8 x i64> @vmul_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll index 2e0daa66c82a..3484d288088a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll @@ -1654,9 +1654,9 @@ define <vscale x 1 x i64> @vnmsac_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu ; RV32-NEXT: vnmsac.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1685,9 +1685,9 @@ define <vscale x 1 x i64> @vnmsac_vx_nxv1i64_unmasked(<vscale x 1 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; RV32-NEXT: vlse64.v v10, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m1, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; RV32-NEXT: vnmsac.vv v9, v8, v10 ; RV32-NEXT: vmv1r.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1729,9 +1729,8 @@ define <vscale x 1 x i64> @vnmsac_vx_nxv1i64_ta(<vscale x 1 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vnmsac.vv v9, v8, v10, v0.t ; RV32-NEXT: vmv.v.v v8, v9 ; RV32-NEXT: addi sp, sp, 16 @@ -1791,9 +1790,9 @@ define <vscale x 2 x i64> @vnmsac_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, mu ; RV32-NEXT: vnmsac.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1822,9 +1821,9 @@ define <vscale x 2 x i64> @vnmsac_vx_nxv2i64_unmasked(<vscale x 2 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; RV32-NEXT: vlse64.v v12, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m2, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m2, tu, ma ; RV32-NEXT: vnmsac.vv v10, v8, v12 ; RV32-NEXT: vmv2r.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1866,9 +1865,8 @@ define <vscale x 2 x i64> @vnmsac_vx_nxv2i64_ta(<vscale x 2 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vnmsac.vv v10, v8, v12, v0.t ; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: addi sp, sp, 16 @@ -1928,9 +1926,9 @@ define <vscale x 4 x i64> @vnmsac_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, mu ; RV32-NEXT: vnmsac.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -1959,9 +1957,9 @@ define <vscale x 4 x i64> @vnmsac_vx_nxv4i64_unmasked(<vscale x 4 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; RV32-NEXT: vlse64.v v16, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m4, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m4, tu, ma ; RV32-NEXT: vnmsac.vv v12, v8, v16 ; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2003,9 +2001,8 @@ define <vscale x 4 x i64> @vnmsac_vx_nxv4i64_ta(<vscale x 4 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vnmsac.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: addi sp, sp, 16 @@ -2067,9 +2064,9 @@ define <vscale x 8 x i64> @vnmsac_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, mu +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, mu ; RV32-NEXT: vnmsac.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2098,9 +2095,9 @@ define <vscale x 8 x i64> @vnmsac_vx_nxv8i64_unmasked(<vscale x 8 x i64> %a, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vlse64.v v24, (a0), zero -; RV32-NEXT: vsetvli zero, a2, e64, m8, tu, ma +; RV32-NEXT: vsetvli zero, zero, e64, m8, tu, ma ; RV32-NEXT: vnmsac.vv v16, v8, v24 ; RV32-NEXT: vmv8r.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 @@ -2143,9 +2140,8 @@ define <vscale x 8 x i64> @vnmsac_vx_nxv8i64_ta(<vscale x 8 x i64> %a, i64 %b, < ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu +; RV32-NEXT: vlse64.v v24, (a0), zero ; RV32-NEXT: vnmsac.vv v16, v8, v24, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll index ef281c52838f..e864d71fdad1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll @@ -1326,9 +1326,8 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1353,9 +1352,8 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1422,9 +1420,8 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1449,9 +1446,8 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1518,9 +1514,8 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1545,9 +1540,8 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1614,9 +1608,8 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscal ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1641,9 +1634,8 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 % ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll index 3273274a70b4..66ba2697fe5f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll @@ -893,9 +893,8 @@ define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -920,9 +919,8 @@ define <vscale x 1 x i64> @vrem_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -969,9 +967,8 @@ define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -996,9 +993,8 @@ define <vscale x 2 x i64> @vrem_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1045,9 +1041,8 @@ define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1072,9 +1067,8 @@ define <vscale x 4 x i64> @vrem_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1121,9 +1115,8 @@ define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1148,9 +1141,8 @@ define <vscale x 8 x i64> @vrem_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vrem.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll index 6b588d0917ff..4608661eb5df 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll @@ -892,9 +892,8 @@ define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -919,9 +918,8 @@ define <vscale x 1 x i64> @vremu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -968,9 +966,8 @@ define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -995,9 +992,8 @@ define <vscale x 2 x i64> @vremu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1044,9 +1040,8 @@ define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1071,9 +1066,8 @@ define <vscale x 4 x i64> @vremu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1120,9 +1114,8 @@ define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1147,9 +1140,8 @@ define <vscale x 8 x i64> @vremu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vremu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll index 0f38e9408fb5..c41139c64eb0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll @@ -842,9 +842,8 @@ define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v9, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -869,9 +868,8 @@ define <vscale x 1 x i64> @vrsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v9, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -918,9 +916,8 @@ define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v10, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -945,9 +942,8 @@ define <vscale x 2 x i64> @vrsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v10, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -994,9 +990,8 @@ define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v12, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1021,9 +1016,8 @@ define <vscale x 4 x i64> @vrsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v12, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1070,9 +1064,8 @@ define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1097,9 +1090,8 @@ define <vscale x 8 x i64> @vrsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v16, v8 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll index 575d041b091d..e471f4b2e92b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll @@ -1425,9 +1425,8 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1452,9 +1451,8 @@ define <vscale x 1 x i64> @vsadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1521,9 +1519,8 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1548,9 +1545,8 @@ define <vscale x 2 x i64> @vsadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1617,9 +1613,8 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1644,9 +1639,8 @@ define <vscale x 4 x i64> @vsadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1713,9 +1707,8 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1740,9 +1733,8 @@ define <vscale x 8 x i64> @vsadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsadd.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll index c9ed72bc63da..f76a2b4b78bc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll @@ -1424,9 +1424,8 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1451,9 +1450,8 @@ define <vscale x 1 x i64> @vsaddu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1520,9 +1518,8 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1547,9 +1544,8 @@ define <vscale x 2 x i64> @vsaddu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1616,9 +1612,8 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1643,9 +1638,8 @@ define <vscale x 4 x i64> @vsaddu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1712,9 +1706,8 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1739,9 +1732,8 @@ define <vscale x 8 x i64> @vsaddu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsaddu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll index c0da928a72e9..ebf8d5eeb40b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll @@ -1468,9 +1468,8 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1495,9 +1494,8 @@ define <vscale x 1 x i64> @vssub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1566,9 +1564,8 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1593,9 +1590,8 @@ define <vscale x 2 x i64> @vssub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1664,9 +1660,8 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1691,9 +1686,8 @@ define <vscale x 4 x i64> @vssub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1762,9 +1756,8 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsc ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1789,9 +1782,8 @@ define <vscale x 8 x i64> @vssub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssub.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll index b602f11e2c80..d54901c93d53 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll @@ -1466,9 +1466,8 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1493,9 +1492,8 @@ define <vscale x 1 x i64> @vssubu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1564,9 +1562,8 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1591,9 +1588,8 @@ define <vscale x 2 x i64> @vssubu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1662,9 +1658,8 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1689,9 +1684,8 @@ define <vscale x 4 x i64> @vssubu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1760,9 +1754,8 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vs ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1787,9 +1780,8 @@ define <vscale x 8 x i64> @vssubu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i6 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vssubu.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll index 65ba791fe780..e28da6bc4ec6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll @@ -922,9 +922,8 @@ define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -949,9 +948,8 @@ define <vscale x 1 x i64> @vsub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -998,9 +996,8 @@ define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1025,9 +1022,8 @@ define <vscale x 2 x i64> @vsub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1074,9 +1070,8 @@ define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1101,9 +1096,8 @@ define <vscale x 4 x i64> @vsub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1150,9 +1144,8 @@ define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1177,9 +1170,8 @@ define <vscale x 8 x i64> @vsub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll index f3dd7ec48881..1694a7af0a0b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll @@ -1694,9 +1694,8 @@ define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v9, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1721,9 +1720,8 @@ define <vscale x 1 x i64> @vxor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma +; RV32-NEXT: vlse64.v v9, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v9 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1810,9 +1808,8 @@ define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v10, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1837,9 +1834,8 @@ define <vscale x 2 x i64> @vxor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma +; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v10 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1926,9 +1922,8 @@ define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v12, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -1953,9 +1948,8 @@ define <vscale x 4 x i64> @vxor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma +; RV32-NEXT: vlse64.v v12, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v12 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2042,9 +2036,8 @@ define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vsca ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v16, v0.t ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 @@ -2069,9 +2062,8 @@ define <vscale x 8 x i64> @vxor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 ; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: addi a0, sp, 8 -; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vxor.vv v8, v8, v16 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 diff --git a/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll b/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll index f8207c56a565..5ce4a1954c5f 100644 --- a/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll +++ b/llvm/test/CodeGen/SPIRV/AtomicCompareExchange.ll @@ -1,6 +1,6 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; CHECK-SPIRV: %[[#Int:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#Int:]] = OpTypeInt 32 0 ; CHECK-SPIRV-DAG: %[[#MemScope_CrossDevice:]] = OpConstant %[[#Int]] 0 ; CHECK-SPIRV-DAG: %[[#MemSemEqual_SeqCst:]] = OpConstant %[[#Int]] 16 ; CHECK-SPIRV-DAG: %[[#MemSemUnequal_Acquire:]] = OpConstant %[[#Int]] 2 diff --git a/llvm/test/CodeGen/SPIRV/event-zero-const.ll b/llvm/test/CodeGen/SPIRV/event-zero-const.ll index f3f20a0fb2f4..523d2ad9825f 100644 --- a/llvm/test/CodeGen/SPIRV/event-zero-const.ll +++ b/llvm/test/CodeGen/SPIRV/event-zero-const.ll @@ -4,10 +4,10 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK: %[[#LongTy:]] = OpTypeInt 64 0 -; CHECK: %[[#EventTy:]] = OpTypeEvent -; CHECK: %[[#LongNull:]] = OpConstantNull %[[#LongTy]] -; CHECK: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] +; CHECK-DAG: %[[#LongTy:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#EventTy:]] = OpTypeEvent +; CHECK-DAG: %[[#LongNull:]] = OpConstantNull %[[#LongTy]] +; CHECK-DAG: %[[#EventNull:]] = OpConstantNull %[[#EventTy]] ; CHECK: OpFunction ; CHECK: OpINotEqual %[[#]] %[[#]] %[[#LongNull]] ; CHECK: OpGroupAsyncCopy %[[#EventTy]] %[[#]] %[[#]] %[[#]] %[[#]] %[[#]] %[[#EventNull]] diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll index 368c5d4a3298..80309e96db00 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp-simple-hierarchy.ll @@ -1,16 +1,17 @@ -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled -; XFAIL: expensive_checks - ; CHECK-DAG: OpName %[[I9:.*]] "_ZN13BaseIncrement9incrementEPi" ; CHECK-DAG: OpName %[[I29:.*]] "_ZN12IncrementBy29incrementEPi" ; CHECK-DAG: OpName %[[I49:.*]] "_ZN12IncrementBy49incrementEPi" ; CHECK-DAG: OpName %[[I89:.*]] "_ZN12IncrementBy89incrementEPi" +; CHECK-DAG: OpName %[[Foo:.*]] "foo" ; CHECK-DAG: %[[TyVoid:.*]] = OpTypeVoid -; CHECK-DAG: %[[TyArr:.*]] = OpTypeArray +; CHECK-DAG: %[[TyInt32:.*]] = OpTypeInt 32 0 +; CHECK-DAG: %[[TyInt8:.*]] = OpTypeInt 8 0 +; CHECK-DAG: %[[Const8:.*]] = OpConstant %[[TyInt32]] 8 +; CHECK-DAG: %[[TyArr:.*]] = OpTypeArray %[[TyInt8]] %[[Const8]] ; CHECK-DAG: %[[TyStruct1:.*]] = OpTypeStruct %[[TyArr]] ; CHECK-DAG: %[[TyStruct2:.*]] = OpTypeStruct %[[TyStruct1]] ; CHECK-DAG: %[[TyPtrStruct2:.*]] = OpTypePointer Generic %[[TyStruct2]] @@ -18,16 +19,21 @@ ; CHECK-DAG: %[[TyPtrFun:.*]] = OpTypePointer Generic %[[TyFun]] ; CHECK-DAG: %[[TyPtrPtrFun:.*]] = OpTypePointer Generic %[[TyPtrFun]] -; CHECK: %[[I9]] = OpFunction -; CHECK: %[[I29]] = OpFunction -; CHECK: %[[I49]] = OpFunction -; CHECK: %[[I89]] = OpFunction +; CHECK-DAG: %[[I9]] = OpFunction +; CHECK-DAG: %[[I29]] = OpFunction +; CHECK-DAG: %[[I49]] = OpFunction +; CHECK-DAG: %[[I89]] = OpFunction + +; CHECK: %[[Foo]] = OpFunction +; CHECK-4: OpFunctionParameter ; CHECK: %[[Arg1:.*]] = OpPhi %[[TyPtrStruct2]] ; CHECK: %[[VTbl:.*]] = OpBitcast %[[TyPtrPtrFun]] %[[#]] ; CHECK: %[[FP:.*]] = OpLoad %[[TyPtrFun]] %[[VTbl]] ; CHECK: %[[#]] = OpFunctionPointerCallINTEL %[[TyVoid]] %[[FP]] %[[Arg1]] %[[#]] +; CHECK-NO: OpFunction + %"cls::id" = type { %"cls::detail::array" } %"cls::detail::array" = type { [1 x i64] } %struct.obj_storage_t = type { %"struct.aligned_storage<BaseIncrement, IncrementBy2, IncrementBy4, IncrementBy8>::type" } diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll index 75ad382f05ff..b96da631c0a8 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fp_const.ll @@ -1,9 +1,6 @@ -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_function_pointers %s -o - | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled -; XFAIL: expensive_checks - ; CHECK-DAG: OpCapability FunctionPointersINTEL ; CHECK-DAG: OpCapability Int64 ; CHECK: OpExtension "SPV_INTEL_function_pointers" diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll index d38de216c223..8edecc1329d0 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_function_pointers/fun-ptr-addrcast.ll @@ -2,15 +2,9 @@ ; pointers/PtrCast-null-in-OpSpecConstantOp.ll (that is OpSpecConstantOp with ptr-cast operation) correctly ; work also for function pointers. -; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - --spirv-ext=+SPV_INTEL_function_pointers | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - --spirv-ext=+SPV_INTEL_function_pointers | FileCheck %s ; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This test currently fails with LLVM_ENABLE_EXPENSIVE_CHECKS enabled -; XFAIL: expensive_checks - -; Running with -verify-machineinstrs would lead to "Reading virtual register without a def" -; error, because OpConstantFunctionPointerINTEL forward-refers to a function definition. - ; CHECK-COUNT-3: %[[#]] = OpSpecConstantOp %[[#]] 121 %[[#]] ; CHECK-COUNT-3: OpPtrCastToGeneric diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll index e006651d49e4..91286d5bf32e 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_inline_assembly/inline_asm.ll @@ -31,20 +31,20 @@ ; CHECK-DAG: %[[#Const123:]] = OpConstant %[[#Int32Ty]] 123 ; CHECK-DAG: %[[#Const42:]] = OpConstant %[[#DoubleTy:]] 42 -; CHECK: %[[#Dialect:]] = OpAsmTargetINTEL "spirv64-unknown-unknown" +; CHECK-DAG: %[[#Dialect:]] = OpAsmTargetINTEL "spirv64-unknown-unknown" ; CHECK-NO: OpAsmTargetINTEL -; CHECK: %[[#Asm1:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "" -; CHECK: %[[#Asm2:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "nop" "" -; CHECK: %[[#Asm3:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "~{cc},~{memory}" -; CHECK: %[[#Asm4:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun2Ty:]] %[[#Dialect]] "clobber_out $0" "=&r" -; CHECK: %[[#Asm5:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun3Ty]] %[[#Dialect]] "icmd $0 $1" "=r,r" -; CHECK: %[[#Asm6:]] = OpAsmINTEL %[[#FloatTy]] %[[#Fun4Ty]] %[[#Dialect]] "fcmd $0 $1" "=r,r" -; CHECK: %[[#Asm7:]] = OpAsmINTEL %[[#HalfTy]] %[[#Fun5Ty]] %[[#Dialect]] "fcmdext $0 $1 $2" "=r,r,r" -; CHECK: %[[#Asm8:]] = OpAsmINTEL %[[#Int8Ty]] %[[#Fun6Ty]] %[[#Dialect]] "cmdext $0 $3 $1 $2" "=r,r,r,r" -; CHECK: %[[#Asm9:]] = OpAsmINTEL %[[#Int64Ty]] %[[#Fun7Ty]] %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r" -; CHECK: %[[#Asm10:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "r,r" -; CHECK: %[[#Asm11:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "i,i" +; CHECK-DAG: %[[#Asm1:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "" +; CHECK-DAG: %[[#Asm2:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "nop" "" +; CHECK-DAG: %[[#Asm3:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun1Ty]] %[[#Dialect]] "" "~{cc},~{memory}" +; CHECK-DAG: %[[#Asm4:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun2Ty:]] %[[#Dialect]] "clobber_out $0" "=&r" +; CHECK-DAG: %[[#Asm5:]] = OpAsmINTEL %[[#Int32Ty]] %[[#Fun3Ty]] %[[#Dialect]] "icmd $0 $1" "=r,r" +; CHECK-DAG: %[[#Asm6:]] = OpAsmINTEL %[[#FloatTy]] %[[#Fun4Ty]] %[[#Dialect]] "fcmd $0 $1" "=r,r" +; CHECK-DAG: %[[#Asm7:]] = OpAsmINTEL %[[#HalfTy]] %[[#Fun5Ty]] %[[#Dialect]] "fcmdext $0 $1 $2" "=r,r,r" +; CHECK-DAG: %[[#Asm8:]] = OpAsmINTEL %[[#Int8Ty]] %[[#Fun6Ty]] %[[#Dialect]] "cmdext $0 $3 $1 $2" "=r,r,r,r" +; CHECK-DAG: %[[#Asm9:]] = OpAsmINTEL %[[#Int64Ty]] %[[#Fun7Ty]] %[[#Dialect]] "icmdext $0 $3 $1 $2" "=r,r,r,r" +; CHECK-DAG: %[[#Asm10:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "r,r" +; CHECK-DAG: %[[#Asm11:]] = OpAsmINTEL %[[#VoidTy]] %[[#Fun8Ty]] %[[#Dialect]] "constcmd $0 $1" "i,i" ; CHECK-NO: OpAsmINTEL ; CHECK: OpFunction diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll index 8ecd0a2b25eb..bd07ba1316ec 100644 --- a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_shader_clock/shader_clock.ll @@ -6,9 +6,11 @@ ; CHECK: OpCapability ShaderClockKHR ; CHECK: OpExtension "SPV_KHR_shader_clock" -; CHECK-DAG: [[uint:%[a-z0-9_]+]] = OpTypeInt 32 +; CHECK-DAG: [[uint:%[a-z0-9_]+]] = OpTypeInt 32 0 ; CHECK-DAG: [[ulong:%[a-z0-9_]+]] = OpTypeInt 64 ; CHECK-DAG: [[v2uint:%[a-z0-9_]+]] = OpTypeVector [[uint]] 2 +; CHECK-DAG: OpConstant [[uint]] 8 +; CHECK-DAG: OpConstant [[uint]] 16 ; CHECK-DAG: [[uint_1:%[a-z0-9_]+]] = OpConstant [[uint]] 1 ; CHECK-DAG: [[uint_2:%[a-z0-9_]+]] = OpConstant [[uint]] 2 ; CHECK-DAG: [[uint_3:%[a-z0-9_]+]] = OpConstant [[uint]] 3 diff --git a/llvm/test/CodeGen/SPIRV/global-var-name-linkage.ll b/llvm/test/CodeGen/SPIRV/global-var-name-linkage.ll new file mode 100644 index 000000000000..4501819ce494 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/global-var-name-linkage.ll @@ -0,0 +1,59 @@ +; Check names and decoration of global variables. + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: OpName %[[#id18:]] "G1" +; CHECK-DAG: OpName %[[#id22:]] "g1" +; CHECK-DAG: OpName %[[#id23:]] "g2" +; CHECK-DAG: OpName %[[#id27:]] "g4" +; CHECK-DAG: OpName %[[#id30:]] "c1" +; CHECK-DAG: OpName %[[#id31:]] "n_t" +; CHECK-DAG: OpName %[[#id32:]] "w" +; CHECK-DAG: OpName %[[#id34:]] "a.b" +; CHECK-DAG: OpName %[[#id35:]] "e" +; CHECK-DAG: OpName %[[#id36:]] "y.z" +; CHECK-DAG: OpName %[[#id38:]] "x" + +; CHECK-NOT: OpDecorate %[[#id18]] LinkageAttributes +; CHECK-DAG: OpDecorate %[[#id18]] Constant +; CHECK-DAG: OpDecorate %[[#id22]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id22]] LinkageAttributes "g1" Export +; CHECK-DAG: OpDecorate %[[#id23]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id27]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id27]] LinkageAttributes "g4" Export +; CHECK-DAG: OpDecorate %[[#id30]] Constant +; CHECK-DAG: OpDecorate %[[#id30]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id30]] LinkageAttributes "c1" Export +; CHECK-DAG: OpDecorate %[[#id31]] Constant +; CHECK-DAG: OpDecorate %[[#id31]] LinkageAttributes "n_t" Import +; CHECK-DAG: OpDecorate %[[#id32]] Constant +; CHECK-DAG: OpDecorate %[[#id32]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id32]] LinkageAttributes "w" Export +; CHECK-DAG: OpDecorate %[[#id34]] Constant +; CHECK-DAG: OpDecorate %[[#id34]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id35]] LinkageAttributes "e" Import +; CHECK-DAG: OpDecorate %[[#id36]] Alignment 4 +; CHECK-DAG: OpDecorate %[[#id38]] Constant +; CHECK-DAG: OpDecorate %[[#id38]] Alignment 4 + +%"class.sycl::_V1::nd_item" = type { i8 } + +@G1 = private unnamed_addr addrspace(1) constant %"class.sycl::_V1::nd_item" poison, align 1 +@g1 = addrspace(1) global i32 1, align 4 +@g2 = internal addrspace(1) global i32 2, align 4 +@g4 = common addrspace(1) global i32 0, align 4 +@c1 = addrspace(2) constant [2 x i32] [i32 0, i32 1], align 4 +@n_t = external addrspace(2) constant [256 x i32] +@w = addrspace(1) constant i32 0, align 4 +@a.b = internal addrspace(2) constant [2 x i32] [i32 2, i32 3], align 4 +@e = external addrspace(1) global i32 +@y.z = internal addrspace(1) global i32 0, align 4 +@x = internal addrspace(2) constant float 1.000000e+00, align 4 + +define internal spir_func void @foo(ptr addrspace(4) align 1 %arg) { + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll index 2e0eb8c429ac..b1625c07111e 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cross.ll @@ -15,7 +15,7 @@ entry: ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec3_float_16]]
; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec3_float_16]]
; CHECK: %[[#]] = OpExtInst %[[#vec3_float_16]] %[[#op_ext_glsl]] Cross %[[#arg0]] %[[#arg1]]
- %hlsl.cross = call <3 x half> @llvm.spv.cross.v4f16(<3 x half> %a, <3 x half> %b)
+ %hlsl.cross = call <3 x half> @llvm.spv.cross.v3f16(<3 x half> %a, <3 x half> %b)
ret <3 x half> %hlsl.cross
}
@@ -25,9 +25,9 @@ entry: ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec3_float_32]]
; CHECK: %[[#arg1:]] = OpFunctionParameter %[[#vec3_float_32]]
; CHECK: %[[#]] = OpExtInst %[[#vec3_float_32]] %[[#op_ext_glsl]] Cross %[[#arg0]] %[[#arg1]]
- %hlsl.cross = call <3 x float> @llvm.spv.cross.v4f32(<3 x float> %a, <3 x float> %b)
+ %hlsl.cross = call <3 x float> @llvm.spv.cross.v3f32(<3 x float> %a, <3 x float> %b)
ret <3 x float> %hlsl.cross
}
-declare <3 x half> @llvm.spv.cross.v4f16(<3 x half>, <3 x half>)
-declare <3 x float> @llvm.spv.cross.v4f32(<3 x float>, <3 x float>)
+declare <3 x half> @llvm.spv.cross.v3f16(<3 x half>, <3 x half>)
+declare <3 x float> @llvm.spv.cross.v3f32(<3 x float>, <3 x float>)
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll index b4a9d8e0664b..1ac862b79a3f 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/length.ll @@ -11,19 +11,21 @@ define noundef half @length_half4(<4 x half> noundef %a) {
entry:
- ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
+ ; CHECK: %[[#]] = OpFunction %[[#float_16]] None %[[#]]
+ ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] Length %[[#arg0]]
- %hlsl.length = call half @llvm.spv.length.v4f16(<4 x half> %a)
+ %hlsl.length = call half @llvm.spv.length.f16(<4 x half> %a)
ret half %hlsl.length
}
define noundef float @length_float4(<4 x float> noundef %a) {
entry:
- ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]]
+ ; CHECK: %[[#]] = OpFunction %[[#float_32]] None %[[#]]
+ ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] Length %[[#arg0]]
- %hlsl.length = call float @llvm.spv.length.v4f32(<4 x float> %a)
+ %hlsl.length = call float @llvm.spv.length.f32(<4 x float> %a)
ret float %hlsl.length
}
-declare half @llvm.spv.length.v4f16(<4 x half>)
-declare float @llvm.spv.length.v4f32(<4 x float>)
+declare half @llvm.spv.length.f16(<4 x half>)
+declare float @llvm.spv.length.f32(<4 x float>)
diff --git a/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll b/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll index 8f14eba21b63..49aaa45afed1 100644 --- a/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll +++ b/llvm/test/CodeGen/SPIRV/iaddcarry-builtin.ll @@ -25,9 +25,7 @@ ; CHECK-SPIRV-DAG: [[v4uint:%[a-z0-9_]+]] = OpTypeVector [[uint]] 4 ; CHECK-SPIRV-DAG: [[vecstruct:%[a-z0-9_]+]] = OpTypeStruct [[v4uint]] [[v4uint]] ; CHECK-SPIRV-DAG: [[_ptr_Function_vecstruct:%[a-z0-9_]+]] = OpTypePointer Function [[vecstruct]] -; CHECK-SPIRV-DAG: [[struct_anon:%[a-z0-9_.]+]] = OpTypeStruct [[uint]] [[uint]] -; CHECK-SPIRV-DAG: [[_ptr_Function_struct_anon:%[a-z0-9_]+]] = OpTypePointer Function [[struct_anon]] -; CHECK-SPIRV-DAG: [[_ptr_Generic_struct_anon:%[a-z0-9_]+]] = OpTypePointer Generic [[struct_anon]] +; CHECK-SPIRV-DAG: [[_ptr_Generic_i32struct:%[a-z0-9_]+]] = OpTypePointer Generic [[i32struct]] define spir_func void @test_builtin_iaddcarrycc(i8 %a, i8 %b) { entry: @@ -116,9 +114,9 @@ define spir_func void @test_builtin_iaddcarry_anon(i32 %a, i32 %b) { ; CHECK-SPIRV: [[a_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[b_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[entry_4:%[a-z0-9_]+]] = OpLabel -; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_struct_anon]] Function -; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_struct_anon]] [[var_59]] -; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpIAddCarry [[struct_anon]] [[a_4]] [[b_4]] +; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_i32struct]] Function +; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_i32struct]] [[var_59]] +; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpIAddCarry [[i32struct]] [[a_4]] [[b_4]] ; CHECK-SPIRV: OpStore [[var_61]] [[var_62]] declare void @_Z17__spirv_IAddCarryIiiE4anonIT_T0_ES1_S2_(ptr addrspace(4) sret(%struct.anon) align 4, i32, i32) diff --git a/llvm/test/CodeGen/SPIRV/image-unoptimized.ll b/llvm/test/CodeGen/SPIRV/image-unoptimized.ll index 0ce9c73ab103..d7d5b1d6b756 100644 --- a/llvm/test/CodeGen/SPIRV/image-unoptimized.ll +++ b/llvm/test/CodeGen/SPIRV/image-unoptimized.ll @@ -1,7 +1,7 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s -; CHECK: %[[#TypeImage:]] = OpTypeImage -; CHECK: %[[#TypeSampler:]] = OpTypeSampler +; CHECK-DAG: %[[#TypeImage:]] = OpTypeImage +; CHECK-DAG: %[[#TypeSampler:]] = OpTypeSampler ; CHECK-DAG: %[[#TypeImagePtr:]] = OpTypePointer {{.*}} %[[#TypeImage]] ; CHECK-DAG: %[[#TypeSamplerPtr:]] = OpTypePointer {{.*}} %[[#TypeSampler]] diff --git a/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll b/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll index 08b4d2a1fa8e..ca842d2f9557 100644 --- a/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll +++ b/llvm/test/CodeGen/SPIRV/isubborrow-builtin.ll @@ -23,9 +23,7 @@ ; CHECK-SPIRV-DAG: [[v4uint:%[a-z0-9_]+]] = OpTypeVector [[uint]] 4 ; CHECK-SPIRV-DAG: [[vecstruct:%[a-z0-9_]+]] = OpTypeStruct [[v4uint]] [[v4uint]] ; CHECK-SPIRV-DAG: [[_ptr_Function_vecstruct:%[a-z0-9_]+]] = OpTypePointer Function [[vecstruct]] -; CHECK-SPIRV-DAG: [[struct_anon:%[a-z0-9_.]+]] = OpTypeStruct [[uint]] [[uint]] -; CHECK-SPIRV-DAG: [[_ptr_Function_struct_anon:%[a-z0-9_]+]] = OpTypePointer Function [[struct_anon]] -; CHECK-SPIRV-DAG: [[_ptr_Generic_struct_anon:%[a-z0-9_]+]] = OpTypePointer Generic [[struct_anon]] +; CHECK-SPIRV-DAG: [[_ptr_Generic_i32struct:%[a-z0-9_]+]] = OpTypePointer Generic [[i32struct]] define spir_func void @test_builtin_isubborrowcc(i8 %a, i8 %b) { entry: @@ -114,9 +112,9 @@ define spir_func void @test_builtin_isubborrow_anon(i32 %a, i32 %b) { ; CHECK-SPIRV: [[a_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[b_4:%[a-z0-9_]+]] = OpFunctionParameter [[uint]] ; CHECK-SPIRV: [[entry_4:%[a-z0-9_]+]] = OpLabel -; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_struct_anon]] Function -; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_struct_anon]] [[var_59]] -; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpISubBorrow [[struct_anon]] [[a_4]] [[b_4]] +; CHECK-SPIRV: [[var_59:%[a-z0-9_]+]] = OpVariable [[_ptr_Function_i32struct]] Function +; CHECK-SPIRV: [[var_61:%[a-z0-9_]+]] = OpPtrCastToGeneric [[_ptr_Generic_i32struct]] [[var_59]] +; CHECK-SPIRV: [[var_62:%[a-z0-9_]+]] = OpISubBorrow [[i32struct]] [[a_4]] [[b_4]] ; CHECK-SPIRV: OpStore [[var_61]] [[var_62]] declare void @_Z18__spirv_ISubBorrowIiiE4anonIT_T0_ES1_S2_(ptr addrspace(4) sret(%struct.anon) align 4, i32, i32) diff --git a/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll b/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll index 0dc86233f8e1..61d06fe2752e 100644 --- a/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll +++ b/llvm/test/CodeGen/SPIRV/keep-tracked-const.ll @@ -3,9 +3,9 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-SPIRV: %[[#Int:]] = OpTypeInt 32 0 -; CHECK-SPIRV: %[[#C0:]] = OpConstant %[[#Int]] 0 -; CHECK-SPIRV: %[[#C1:]] = OpConstant %[[#Int]] 1 +; CHECK-SPIRV-DAG: %[[#Int:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#C0:]] = OpConstant %[[#Int]] 0 +; CHECK-SPIRV-DAG: %[[#C1:]] = OpConstant %[[#Int]] 1 ; CHECK-SPIRV: OpSelect %[[#Int]] %[[#]] %[[#C1]] %[[#C0]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll index 2d5b30978aa2..25b530461012 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshl.ll @@ -1,21 +1,21 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_32:]] "spirv.llvm_fshl_i32" -; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_16:]] "spirv.llvm_fshl_i16" -; CHECK-SPIRV: OpName %[[#NAME_FSHL_FUNC_VEC_INT_16:]] "spirv.llvm_fshl_v2i16" -; CHECK-SPIRV: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHL_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_FSHL_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHL_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] -; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_32:]] = OpConstant %[[#TYPE_INT_32]] 8 -; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_16:]] = OpConstant %[[#TYPE_INT_16]] 8 -; CHECK-SPIRV: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] -; CHECK-SPIRV-DAG: %[[#CONST_TYPE_SIZE_32:]] = OpConstant %[[#TYPE_INT_32]] 32 +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHL_FUNC_32:]] "spirv.llvm_fshl_i32" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHL_FUNC_16:]] "spirv.llvm_fshl_i16" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHL_FUNC_VEC_INT_16:]] "spirv.llvm_fshl_v2i16" +; CHECK-SPIRV-DAG: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHL_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHL_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHL_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_32:]] = OpConstant %[[#TYPE_INT_32]] 8 +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_16:]] = OpConstant %[[#TYPE_INT_16]] 8 +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] +; CHECK-SPIRV-DAG: %[[#CONST_TYPE_SIZE_32:]] = OpConstant %[[#TYPE_INT_32]] 32 ; CHECK-SPIRV: %[[#]] = OpFunction %[[#TYPE_INT_32]] {{.*}} %[[#TYPE_ORIG_FUNC_32]] ; CHECK-SPIRV: %[[#X:]] = OpFunctionParameter %[[#TYPE_INT_32]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll index 4cf5ca53a411..55fb2d9079e1 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/fshr.ll @@ -1,20 +1,20 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_32:]] "spirv.llvm_fshr_i32" -; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_16:]] "spirv.llvm_fshr_i16" -; CHECK-SPIRV: OpName %[[#NAME_FSHR_FUNC_VEC_INT_16:]] "spirv.llvm_fshr_v2i16" -; CHECK-SPIRV: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 -; CHECK-SPIRV: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHR_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] -; CHECK-SPIRV: %[[#TYPE_FSHR_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] -; CHECK-SPIRV: %[[#TYPE_FSHR_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHR_FUNC_32:]] "spirv.llvm_fshr_i32" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHR_FUNC_16:]] "spirv.llvm_fshr_i16" +; CHECK-SPIRV-DAG: OpName %[[#NAME_FSHR_FUNC_VEC_INT_16:]] "spirv.llvm_fshr_v2i16" +; CHECK-SPIRV-DAG: %[[#TYPE_INT_32:]] = OpTypeInt 32 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_INT_16:]] = OpTypeInt 16 0 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_VEC_INT_16:]] = OpTypeVector %[[#TYPE_INT_16]] 2 +; CHECK-SPIRV-DAG: %[[#TYPE_ORIG_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHR_FUNC_32:]] = OpTypeFunction %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] %[[#TYPE_INT_32]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHR_FUNC_16:]] = OpTypeFunction %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] %[[#TYPE_INT_16]] +; CHECK-SPIRV-DAG: %[[#TYPE_FSHR_FUNC_VEC_INT_16:]] = OpTypeFunction %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] %[[#TYPE_VEC_INT_16]] ; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_32:]] = OpConstant %[[#TYPE_INT_32]] 8 ; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_16:]] = OpConstant %[[#TYPE_INT_16]] 8 -; CHECK-SPIRV: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] +; CHECK-SPIRV-DAG: %[[#CONST_ROTATE_VEC_INT_16:]] = OpConstantComposite %[[#TYPE_VEC_INT_16]] %[[#CONST_ROTATE_16]] %[[#CONST_ROTATE_16]] ; CHECK-SPIRV-DAG: %[[#CONST_TYPE_SIZE_32:]] = OpConstant %[[#TYPE_INT_32]] 32 ; CHECK-SPIRV: %[[#]] = OpFunction %[[#TYPE_INT_32]] {{.*}} %[[#TYPE_ORIG_FUNC_32]] diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll index e7a986980f25..d5e70ae9e7aa 100644 --- a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll +++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/memset.ll @@ -12,17 +12,17 @@ ; CHECK-DAG: %[[#Int8Ptr:]] = OpTypePointer Generic %[[#Int8]] ; CHECK-DAG: %[[#Const4:]] = OpConstant %[[#Int32]] 4 -; CHECK: %[[#Int8x4:]] = OpTypeArray %[[#Int8]] %[[#Const4]] +; CHECK-DAG: %[[#Int8x4:]] = OpTypeArray %[[#Int8]] %[[#Const4]] ; CHECK-DAG: %[[#Const12:]] = OpConstant %[[#Int32]] 12 -; CHECK: %[[#Int8x12:]] = OpTypeArray %[[#Int8]] %[[#Const12]] +; CHECK-DAG: %[[#Int8x12:]] = OpTypeArray %[[#Int8]] %[[#Const12]] ; CHECK-DAG: %[[#Const21:]] = OpConstant %[[#Int8]] 21 ; CHECK-DAG: %[[#False:]] = OpConstantFalse %[[#]] ; CHECK-DAG: %[[#ConstComp:]] = OpConstantComposite %[[#Int8x4]] %[[#Const21]] %[[#Const21]] %[[#Const21]] %[[#Const21]] ; CHECK-DAG: %[[#ConstNull:]] = OpConstantNull %[[#Int8x12]] -; CHECK: %[[#VarComp:]] = OpVariable %[[#]] UniformConstant %[[#ConstComp]] -; CHECK: %[[#VarNull:]] = OpVariable %[[#]] UniformConstant %[[#ConstNull]] +; CHECK-DAG: %[[#VarComp:]] = OpVariable %[[#]] UniformConstant %[[#ConstComp]] +; CHECK-DAG: %[[#VarNull:]] = OpVariable %[[#]] UniformConstant %[[#ConstNull]] ; CHECK-DAG: %[[#Int8PtrConst:]] = OpTypePointer UniformConstant %[[#Int8]] ; CHECK: OpCopyMemorySized %[[#Target:]] %[[#Source:]] %[[#Const12]] Aligned 4 diff --git a/llvm/test/CodeGen/SPIRV/logical-access-chain.ll b/llvm/test/CodeGen/SPIRV/logical-access-chain.ll index 39f6d33712ef..d56678ecfc2c 100644 --- a/llvm/test/CodeGen/SPIRV/logical-access-chain.ll +++ b/llvm/test/CodeGen/SPIRV/logical-access-chain.ll @@ -1,10 +1,10 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; CHECK: [[uint:%[0-9]+]] = OpTypeInt 32 0 -; CHECK: [[uint2:%[0-9]+]] = OpTypeVector [[uint]] 2 -; CHECK: [[uint_1:%[0-9]+]] = OpConstant [[uint]] 1 -; CHECK: [[ptr_uint:%[0-9]+]] = OpTypePointer Function [[uint]] -; CHECK: [[ptr_uint2:%[0-9]+]] = OpTypePointer Function [[uint2]] +; CHECK-DAG: [[uint:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[uint2:%[0-9]+]] = OpTypeVector [[uint]] 2 +; CHECK-DAG: [[uint_1:%[0-9]+]] = OpConstant [[uint]] 1 +; CHECK-DAG: [[ptr_uint:%[0-9]+]] = OpTypePointer Function [[uint]] +; CHECK-DAG: [[ptr_uint2:%[0-9]+]] = OpTypePointer Function [[uint2]] define void @main() #1 { entry: diff --git a/llvm/test/CodeGen/SPIRV/opencl/degrees.ll b/llvm/test/CodeGen/SPIRV/opencl/degrees.ll index 88f97835fe71..b8d4f52a2879 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/degrees.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/degrees.ll @@ -3,7 +3,7 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "OpenCL.std" +; CHECK-DAG: %[[#op_ext_ocl:]] = OpExtInstImport "OpenCL.std" ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 @@ -20,7 +20,7 @@ declare <4 x half> @llvm.spv.degrees.v4f16(<4 x half>) define noundef float @degrees_float(float noundef %a) { entry: ; CHECK: %[[#float_32_arg:]] = OpFunctionParameter %[[#float_32]] -; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] degrees %[[#float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_ocl]] degrees %[[#float_32_arg]] %elt.degrees = call float @llvm.spv.degrees.f32(float %a) ret float %elt.degrees } @@ -28,7 +28,7 @@ entry: define noundef half @degrees_half(half noundef %a) { entry: ; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]] -; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] degrees %[[#float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_ocl]] degrees %[[#float_16_arg]] %elt.degrees = call half @llvm.spv.degrees.f16(half %a) ret half %elt.degrees } @@ -36,7 +36,7 @@ entry: define noundef <4 x float> @degrees_float_vector(<4 x float> noundef %a) { entry: ; CHECK: %[[#vec4_float_32_arg:]] = OpFunctionParameter %[[#vec4_float_32]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] degrees %[[#vec4_float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_ocl]] degrees %[[#vec4_float_32_arg]] %elt.degrees = call <4 x float> @llvm.spv.degrees.v4f32(<4 x float> %a) ret <4 x float> %elt.degrees } @@ -44,7 +44,7 @@ entry: define noundef <4 x half> @degrees_half_vector(<4 x half> noundef %a) { entry: ; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] degrees %[[#vec4_float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_ocl]] degrees %[[#vec4_float_16_arg]] %elt.degrees = call <4 x half> @llvm.spv.degrees.v4f16(<4 x half> %a) ret <4 x half> %elt.degrees } diff --git a/llvm/test/CodeGen/SPIRV/opencl/radians.ll b/llvm/test/CodeGen/SPIRV/opencl/radians.ll index f7bb8d5226cd..5b4f26a13a4c 100644 --- a/llvm/test/CodeGen/SPIRV/opencl/radians.ll +++ b/llvm/test/CodeGen/SPIRV/opencl/radians.ll @@ -3,7 +3,7 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "OpenCL.std" +; CHECK-DAG: %[[#op_ext_ocl:]] = OpExtInstImport "OpenCL.std" ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 ; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 @@ -20,7 +20,7 @@ declare <4 x half> @llvm.spv.radians.v4f16(<4 x half>) define noundef float @radians_float(float noundef %a) { entry: ; CHECK: %[[#float_32_arg:]] = OpFunctionParameter %[[#float_32]] -; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_glsl]] radians %[[#float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext_ocl]] radians %[[#float_32_arg]] %elt.radians = call float @llvm.spv.radians.f32(float %a) ret float %elt.radians } @@ -28,7 +28,7 @@ entry: define noundef half @radians_half(half noundef %a) { entry: ; CHECK: %[[#float_16_arg:]] = OpFunctionParameter %[[#float_16]] -; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_glsl]] radians %[[#float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext_ocl]] radians %[[#float_16_arg]] %elt.radians = call half @llvm.spv.radians.f16(half %a) ret half %elt.radians } @@ -36,7 +36,7 @@ entry: define noundef <4 x float> @radians_float_vector(<4 x float> noundef %a) { entry: ; CHECK: %[[#vec4_float_32_arg:]] = OpFunctionParameter %[[#vec4_float_32]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_glsl]] radians %[[#vec4_float_32_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext_ocl]] radians %[[#vec4_float_32_arg]] %elt.radians = call <4 x float> @llvm.spv.radians.v4f32(<4 x float> %a) ret <4 x float> %elt.radians } @@ -44,7 +44,7 @@ entry: define noundef <4 x half> @radians_half_vector(<4 x half> noundef %a) { entry: ; CHECK: %[[#vec4_float_16_arg:]] = OpFunctionParameter %[[#vec4_float_16]] -; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_glsl]] radians %[[#vec4_float_16_arg]] +; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext_ocl]] radians %[[#vec4_float_16_arg]] %elt.radians = call <4 x half> @llvm.spv.radians.v4f16(<4 x half> %a) ret <4 x half> %elt.radians } diff --git a/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll b/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll index 99e2c3e6d396..dee16da7e099 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/PtrCast-null-in-OpSpecConstantOp.ll @@ -5,10 +5,8 @@ ; CHECK-DAG: %[[Struct:.*]] = OpTypeStruct %[[Array]] ; CHECK-DAG: %[[Zero:.*]] = OpTypeInt 64 0 ; CHECK-DAG: %[[Null:.*]] = OpConstantNull %[[Zero]] -; CHECK-DAG: %[[R1:.*]] = OpConstantComposite %[[Array]] %[[Null]] -; CHECK-DAG: %[[#]] = OpConstantComposite %[[Struct]] %[[R1]] -; CHECK-DAG: %[[R2:.*]] = OpConstantComposite %[[Array]] %[[Null]] -; CHECK-DAG: %[[#]] = OpConstantComposite %[[Struct]] %[[R2]] +; CHECK-DAG: %[[R:.*]] = OpConstantComposite %[[Array]] %[[Null]] +; CHECK-DAG: %[[#]] = OpConstantComposite %[[Struct]] %[[R]] @G1 = addrspace(1) constant { [1 x ptr addrspace(4)] } { [1 x ptr addrspace(4)] [ptr addrspace(4) addrspacecast (ptr null to ptr addrspace(4))] } @G2 = addrspace(1) constant { [1 x ptr addrspace(4)] } { [1 x ptr addrspace(4)] [ptr addrspace(4) addrspacecast (ptr addrspace(1) null to ptr addrspace(4))] } diff --git a/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll b/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll index 03ecf5e8d839..59a24231769c 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/struct-opaque-pointers.ll @@ -1,12 +1,12 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK: %[[TyInt64:.*]] = OpTypeInt 64 0 -; CHECK: %[[TyInt64Ptr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt64]] -; CHECK: %[[TyStruct:.*]] = OpTypeStruct %[[TyInt64Ptr]] %[[TyInt64Ptr]] -; CHECK: %[[ConstStruct:.*]] = OpConstantComposite %[[TyStruct]] %[[ConstField:.*]] %[[ConstField]] -; CHECK: %[[TyStructPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyStruct]] -; CHECK: OpVariable %[[TyStructPtr]] {{[a-zA-Z]+}} %[[ConstStruct]] +; CHECK-DAG: %[[TyInt64:.*]] = OpTypeInt 64 0 +; CHECK-DAG: %[[TyInt64Ptr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt64]] +; CHECK-DAG: %[[TyStruct:.*]] = OpTypeStruct %[[TyInt64Ptr]] %[[TyInt64Ptr]] +; CHECK-DAG: %[[ConstStruct:.*]] = OpConstantComposite %[[TyStruct]] %[[ConstField:.*]] %[[ConstField]] +; CHECK-DAG: %[[TyStructPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyStruct]] +; CHECK-DAG: OpVariable %[[TyStructPtr]] {{[a-zA-Z]+}} %[[ConstStruct]] @a = addrspace(1) constant i64 42 @struct = addrspace(1) global {ptr addrspace(1), ptr addrspace(1)} { ptr addrspace(1) @a, ptr addrspace(1) @a } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll b/llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll deleted file mode 100644 index 9911b3119ce5..000000000000 --- a/llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint-pass-check.ll +++ /dev/null @@ -1,90 +0,0 @@ -; RUN: opt -passes='spirv-structurizer' -S -mtriple=spirv-unknown-unknown %s | FileCheck %s - -; CHECK-LABEL: define spir_func noundef i32 @test_branch -; CHECK: call void @llvm.spv.selection.merge.p0(ptr blockaddress(@test_branch, %if.end), i32 1) -; CHECK-NEXT: br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !{{[0-9]+}} -define spir_func noundef i32 @test_branch(i32 noundef %X) { -entry: - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !0 - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} - -; CHECK-LABEL: define spir_func noundef i32 @test_flatten -; CHECK: call void @llvm.spv.selection.merge.p0(ptr blockaddress(@test_flatten, %if.end), i32 2) -; CHECK-NEXT: br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !{{[0-9]+}} -define spir_func noundef i32 @test_flatten(i32 noundef %X) { -entry: - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !1 - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} -; CHECK-LABEL: define spir_func noundef i32 @test_no_attr -; CHECK: call void @llvm.spv.selection.merge.p0(ptr blockaddress(@test_no_attr, %if.end), i32 0) -; CHECK-NEXT: br i1 %cmp, label %if.then, label %if.else -define spir_func noundef i32 @test_no_attr(i32 noundef %X) { -entry: - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} - -!0 = !{!"hlsl.controlflow.hint", i32 1} -!1 = !{!"hlsl.controlflow.hint", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint.ll b/llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint.ll deleted file mode 100644 index 848eaf70f5a1..000000000000 --- a/llvm/test/CodeGen/SPIRV/structurizer/HLSLControlFlowHint.ll +++ /dev/null @@ -1,91 +0,0 @@ -; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} - - -define spir_func noundef i32 @test_branch(i32 noundef %X) { -entry: -; CHECK-LABEL: ; -- Begin function test_branch -; OpSelectionMerge %[[#]] DontFlatten - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !0 - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} - - -define spir_func noundef i32 @test_flatten(i32 noundef %X) { -entry: -; CHECK-LABEL: ; -- Begin function test_flatten -; OpSelectionMerge %[[#]] Flatten - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !1 - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} - -define spir_func noundef i32 @test_no_attr(i32 noundef %X) { -entry: -; CHECK-LABEL: ; -- Begin function test_no_attr -; OpSelectionMerge %[[#]] None - %X.addr = alloca i32, align 4 - %resp = alloca i32, align 4 - store i32 %X, ptr %X.addr, align 4 - %0 = load i32, ptr %X.addr, align 4 - %cmp = icmp sgt i32 %0, 0 - br i1 %cmp, label %if.then, label %if.else - -if.then: ; preds = %entry - %1 = load i32, ptr %X.addr, align 4 - %sub = sub nsw i32 0, %1 - store i32 %sub, ptr %resp, align 4 - br label %if.end - -if.else: ; preds = %entry - %2 = load i32, ptr %X.addr, align 4 - %mul = mul nsw i32 %2, 2 - store i32 %mul, ptr %resp, align 4 - br label %if.end - -if.end: ; preds = %if.else, %if.then - %3 = load i32, ptr %resp, align 4 - ret i32 %3 -} - -!0 = !{!"hlsl.controlflow.hint", i32 1} -!1 = !{!"hlsl.controlflow.hint", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll b/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll index e4c7bdb9e9c8..8a90e40e8881 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/SampledImage.ll @@ -24,12 +24,10 @@ ; CHECK-SPIRV: OpName %[[#sample_kernel_float:]] "sample_kernel_float" ; CHECK-SPIRV: OpName %[[#sample_kernel_int:]] "sample_kernel_int" -; CHECK-SPIRV: %[[#TypeSampler:]] = OpTypeSampler +; CHECK-SPIRV-DAG: %[[#TypeSampler:]] = OpTypeSampler ; CHECK-SPIRV-DAG: %[[#SampledImageTy:]] = OpTypeSampledImage ; CHECK-SPIRV-DAG: %[[#ConstSampler1:]] = OpConstantSampler %[[#TypeSampler]] None 0 Linear ; CHECK-SPIRV-DAG: %[[#ConstSampler2:]] = OpConstantSampler %[[#TypeSampler]] Repeat 0 Nearest -; CHECK-SPIRV-DAG: %[[#ConstSampler3:]] = OpConstantSampler %[[#TypeSampler]] None 0 Linear -; CHECK-SPIRV-DAG: %[[#ConstSampler4:]] = OpConstantSampler %[[#TypeSampler]] Repeat 0 Nearest ; CHECK-SPIRV: %[[#sample_kernel_float]] = OpFunction %{{.*}} ; CHECK-SPIRV: %[[#InputImage:]] = OpFunctionParameter %{{.*}} @@ -65,13 +63,13 @@ declare spir_func target("spirv.Sampler") @__translate_sampler_initializer(i32) ; CHECK-SPIRV: %[[#InputImage:]] = OpFunctionParameter %{{.*}} ; CHECK-SPIRV: %[[#argSampl:]] = OpFunctionParameter %[[#TypeSampler]] -; CHECK-SPIRV: %[[#SampledImage4:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler3]] +; CHECK-SPIRV: %[[#SampledImage4:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler1]] ; CHECK-SPIRV: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#SampledImage4]] ; CHECK-SPIRV: %[[#SampledImage5:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#argSampl]] ; CHECK-SPIRV: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#SampledImage5]] -; CHECK-SPIRV: %[[#SampledImage6:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler4]] +; CHECK-SPIRV: %[[#SampledImage6:]] = OpSampledImage %[[#SampledImageTy]] %[[#InputImage]] %[[#ConstSampler2]] ; CHECK-SPIRV: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#SampledImage6]] define dso_local spir_kernel void @sample_kernel_int(target("spirv.Image", void, 1, 0, 0, 0, 0, 0, 0) %input, <2 x float> noundef %coords, <4 x i32> addrspace(1)* nocapture noundef writeonly %results, target("spirv.Sampler") %argSampl) local_unnamed_addr { diff --git a/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll b/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll index 8b326e265502..55f1125706f6 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/cl-types.ll @@ -39,7 +39,7 @@ ; CHECK-SPIRV-DAG: %[[#SAMP:]] = OpTypeSampler ; CHECK-SPIRV-DAG: %[[#SAMPIMG:]] = OpTypeSampledImage %[[#IMG2D_RD]] -; CHECK-SPIRV: %[[#SAMP_CONST:]] = OpConstantSampler %[[#SAMP]] None 0 Linear +; CHECK-SPIRV-DAG: %[[#SAMP_CONST:]] = OpConstantSampler %[[#SAMP]] None 0 Linear ; CHECK-SPIRV: %[[#]] = OpFunctionParameter %[[#PIPE_RD]] ; CHECK-SPIRV: %[[#]] = OpFunctionParameter %[[#PIPE_WR]] diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll index 74dbaab63e03..5810d9c59ee3 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-private-array-initialization.ll @@ -14,19 +14,19 @@ ; CHECK-SPIRV-DAG: %[[#twelve:]] = OpConstant %[[#i32]] 12 ; CHECK-SPIRV-DAG: %[[#const_i32x3_ptr:]] = OpTypePointer UniformConstant %[[#i32x3]] -; CHECK-SPIRV: %[[#test_arr2:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] -; CHECK-SPIRV: %[[#test_arr:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] +; CHECK-SPIRV-DAG: %[[#test_arr1:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] +; CHECK-SPIRV-DAG: %[[#test_arr2:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] ; CHECK-SPIRV-DAG: %[[#i32x3_ptr:]] = OpTypePointer Function %[[#i32x3]] -; CHECK-SPIRV: %[[#arr:]] = OpVariable %[[#i32x3_ptr]] Function +; CHECK-SPIRV: %[[#arr1:]] = OpVariable %[[#i32x3_ptr]] Function ; CHECK-SPIRV: %[[#arr2:]] = OpVariable %[[#i32x3_ptr]] Function -; CHECK-SPIRV-32: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#twelve]] Aligned 4 +; CHECK-SPIRV-32: OpCopyMemorySized %[[#arr1]] %[[#test_arr1]] %[[#twelve]] Aligned 4 ; CHECK-SPIRV-32: OpCopyMemorySized %[[#arr2]] %[[#test_arr2]] %[[#twelve]] Aligned 4 ; CHECK-SPIRV-64: %[[#twelvezext1:]] = OpUConvert %[[#i64:]] %[[#twelve:]] -; CHECK-SPIRV-64: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#twelvezext1]] Aligned 4 +; CHECK-SPIRV-64: OpCopyMemorySized %[[#arr1]] %[[#test_arr1]] %[[#twelvezext1]] Aligned 4 ; CHECK-SPIRV-64: %[[#twelvezext2:]] = OpUConvert %[[#i64:]] %[[#twelve:]] ; CHECK-SPIRV-64: OpCopyMemorySized %[[#arr2]] %[[#test_arr2]] %[[#twelvezext2]] Aligned 4 diff --git a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll index adf73fe153de..62b09f6fe685 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/sub_group_non_uniform_arithmetic.ll @@ -329,12 +329,12 @@ ; CHECK-SPIRV-DAG: %[[#double:]] = OpTypeFloat 64 ; CHECK-SPIRV-DAG: %[[#false:]] = OpConstantFalse %[[#bool]] +; CHECK-SPIRV-DAG: %[[#int_32:]] = OpConstant %[[#int]] 32 ; CHECK-SPIRV-DAG: %[[#ScopeSubgroup:]] = OpConstant %[[#int]] 3 ; CHECK-SPIRV-DAG: %[[#char_0:]] = OpConstant %[[#char]] 0 ; CHECK-SPIRV-DAG: %[[#char_10:]] = OpConstant %[[#char]] 10 ; CHECK-SPIRV-DAG: %[[#short_0:]] = OpConstant %[[#short]] 0 ; CHECK-SPIRV-DAG: %[[#int_0:]] = OpConstant %[[#int]] 0 -; CHECK-SPIRV-DAG: %[[#int_32:]] = OpConstant %[[#int]] 32 ; CHECK-SPIRV-DAG: %[[#long_0:]] = OpConstantNull %[[#long]] ; CHECK-SPIRV-DAG: %[[#half_0:]] = OpConstant %[[#half]] 0 ; CHECK-SPIRV-DAG: %[[#float_0:]] = OpConstant %[[#float]] 0 diff --git a/llvm/test/CodeGen/SPIRV/unnamed-global.ll b/llvm/test/CodeGen/SPIRV/unnamed-global.ll index f72334bd7752..90bac50507c0 100644 --- a/llvm/test/CodeGen/SPIRV/unnamed-global.ll +++ b/llvm/test/CodeGen/SPIRV/unnamed-global.ll @@ -4,10 +4,10 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK: %[[TyInt:.*]] = OpTypeInt 8 0 -; CHECK: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123 -; CHECK: %[[TyPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt]] -; CHECK: %[[VarId:.*]] = OpVariable %[[TyPtr]] {{[a-zA-Z]+}} %[[ConstInt]] +; CHECK-DAG: %[[TyInt:.*]] = OpTypeInt 8 0 +; CHECK-DAG: %[[ConstInt:.*]] = OpConstant %[[TyInt]] 123 +; CHECK-DAG: %[[TyPtr:.*]] = OpTypePointer {{[a-zA-Z]+}} %[[TyInt]] +; CHECK-DAG: %[[VarId:.*]] = OpVariable %[[TyPtr]] {{[a-zA-Z]+}} %[[ConstInt]] @0 = addrspace(1) global i8 123 diff --git a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll index c611e89f2786..f3070cd55903 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll +++ b/llvm/test/CodeGen/X86/codegen-prepare-addrmode-sext.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' %s -o - | FileCheck %s ; This file tests the different cases what are involved when codegen prepare ; tries to get sign/zero extension out of the way of addressing mode. @@ -9,14 +10,17 @@ target triple = "x86_64-apple-macosx" ; Check that we correctly promote both operands of the promotable add. -; CHECK-LABEL: @twoArgsPromotion -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64 -; CHECK: [[ARG2SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg2 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], [[ARG2SEXT]] -; CHECK: inttoptr i64 [[PROMOTED]] to ptr -; CHECK: ret define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) { - %add = add nsw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @twoArgsPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i32 [[ARG1]] to i64 +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i32 [[ARG2]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], [[PROMOTED2]] +; CHECK-NEXT: [[BASE:%.*]] = inttoptr i64 [[ADD]] to ptr +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[BASE]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, %arg2 %sextadd = sext i32 %add to i64 %base = inttoptr i64 %sextadd to ptr %res = load i8, ptr %base @@ -28,11 +32,16 @@ define i8 @twoArgsPromotion(i32 %arg1, i32 %arg2) { ; Otherwise, we will increase the number of instruction executed. ; (This is a heuristic of course, because the new sext could have been ; merged with something else.) -; CHECK-LABEL: @twoArgsNoPromotion -; CHECK: add nsw i32 %arg1, %arg2 -; CHECK: ret define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, ptr %base) { - %add = add nsw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @twoArgsNoPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i32 [[ADD]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, %arg2 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -41,11 +50,16 @@ define i8 @twoArgsNoPromotion(i32 %arg1, i32 %arg2, ptr %base) { ; Check that we do not promote when the related instruction does not have ; the nsw flag. -; CHECK-LABEL: @noPromotion -; CHECK-NOT: add i64 -; CHECK: ret define i8 @noPromotion(i32 %arg1, i32 %arg2, ptr %base) { - %add = add i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @noPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i32 [[ADD]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add i32 %arg1, %arg2 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -53,13 +67,16 @@ define i8 @noPromotion(i32 %arg1, i32 %arg2, ptr %base) { } ; Check that we correctly promote constant arguments. -; CHECK-LABEL: @oneArgPromotion -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i32 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotion(i32 %arg1, ptr %base) { - %add = add nsw i32 %arg1, 1 +; CHECK-LABEL: define i8 @oneArgPromotion( +; CHECK-SAME: i32 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i32 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, 1 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -67,14 +84,17 @@ define i8 @oneArgPromotion(i32 %arg1, ptr %base) { } ; Check that we are able to merge a sign extension with a zero extension. -; CHECK-LABEL: @oneArgPromotionZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionZExt(i8 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionZExt( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %zext = zext i8 %arg1 to i32 - %add = add nsw i32 %zext, 1 + %add = add nsw i32 %zext, 1 %sextadd = sext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -88,11 +108,14 @@ define i8 @oneArgPromotionZExt(i8 %arg1, ptr %base) { ; more thing in the addressing mode. Therefore the modification is ; rolled back. ; Still, this test case exercises the desired code path. -; CHECK-LABEL: @oneArgPromotionCstZExt -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 0, 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionCstZExt(ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionCstZExt( +; CHECK-SAME: ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 0, 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %cst = zext i16 undef to i32 %add = add nsw i32 %cst, 1 %sextadd = sext i32 %add to i64 @@ -103,15 +126,18 @@ define i8 @oneArgPromotionCstZExt(ptr %base) { ; Check that we do not promote truncate when we cannot determine the ; bits that are dropped. -; CHECK-LABEL: @oneArgPromotionBlockTrunc1 -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 %arg1 to i8 -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockTrunc1( +; CHECK-SAME: i32 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %trunc = trunc i32 %arg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -120,17 +146,20 @@ define i8 @oneArgPromotionBlockTrunc1(i32 %arg1, ptr %base) { ; Check that we do not promote truncate when we cannot determine all the ; bits that are dropped. -; CHECK-LABEL: @oneArgPromotionBlockTrunc2 -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i16 %arg1 to i32 -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8 -; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockTrunc2( +; CHECK-SAME: i16 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i16 [[ARG1]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEXTARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i16 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -139,15 +168,18 @@ define i8 @oneArgPromotionBlockTrunc2(i16 %arg1, ptr %base) { ; Check that we are able to promote truncate when we know all the bits ; that are dropped. -; CHECK-LABEL: @oneArgPromotionPassTruncKeepSExt -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionPassTruncKeepSExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i1 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -156,17 +188,19 @@ define i8 @oneArgPromotionPassTruncKeepSExt(i1 %arg1, ptr %base) { ; On X86 truncate are free. Check that we are able to promote the add ; to be used as addressing mode and that we insert a truncate for the other -; use. -; CHECK-LABEL: @oneArgPromotionTruncInsert -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8 -; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, ptr [[GEP]] -; CHECK: add i8 [[LOAD]], [[TRUNC]] -; CHECK: ret +; use. define i8 @oneArgPromotionTruncInsert(i8 %arg1, ptr %base) { - %add = add nsw i8 %arg1, 1 +; CHECK-LABEL: define i8 @oneArgPromotionTruncInsert( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[PROMOTED:%.*]] = trunc i64 [[ADD]] to i8 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[FINALRES:%.*]] = add i8 [[RES]], [[PROMOTED]] +; CHECK-NEXT: ret i8 [[FINALRES]] +; + %add = add nsw i8 %arg1, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -175,15 +209,20 @@ define i8 @oneArgPromotionTruncInsert(i8 %arg1, ptr %base) { } ; Cannot sext from a larger type than the promoted type. -; CHECK-LABEL: @oneArgPromotionLargerType -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i128 %arg1 to i8 -; CHECK: [[ARG1SEXT64:%[a-zA-Z_0-9-]+]] = sext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT64]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionLargerType(i128 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionLargerType( +; CHECK-SAME: i128 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i128 [[ARG1]] to i8 +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[PROMOTED:%.*]] = trunc i64 [[ADD]] to i8 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[FINALRES:%.*]] = add i8 [[RES]], [[PROMOTED]] +; CHECK-NEXT: ret i8 [[FINALRES]] +; %trunc = trunc i128 %arg1 to i8 - %add = add nsw i8 %trunc, 1 + %add = add nsw i8 %trunc, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -194,18 +233,20 @@ define i8 @oneArgPromotionLargerType(i128 %arg1, ptr %base) { ; Use same inserted trunc ; On X86 truncate are free. Check that we are able to promote the add ; to be used as addressing mode and that we insert a truncate for -; *all* the other uses. -; CHECK-LABEL: @oneArgPromotionTruncInsertSeveralUse -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i64 [[PROMOTED]] to i8 -; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, ptr [[GEP]] -; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = add i8 [[LOAD]], [[TRUNC]] -; CHECK: add i8 [[ADDRES]], [[TRUNC]] -; CHECK: ret +; *all* the other uses. define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, ptr %base) { - %add = add nsw i8 %arg1, 1 +; CHECK-LABEL: define i8 @oneArgPromotionTruncInsertSeveralUse( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[PROMOTED:%.*]] = trunc i64 [[ADD]] to i8 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ALMOSTFINALRES:%.*]] = add i8 [[RES]], [[PROMOTED]] +; CHECK-NEXT: [[FINALRES:%.*]] = add i8 [[ALMOSTFINALRES]], [[PROMOTED]] +; CHECK-NEXT: ret i8 [[FINALRES]] +; + %add = add nsw i8 %arg1, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -216,16 +257,18 @@ define i8 @oneArgPromotionTruncInsertSeveralUse(i8 %arg1, ptr %base) { ; Check that the promoted instruction is used for all uses of the original ; sign extension. -; CHECK-LABEL: @oneArgPromotionSExtSeveralUse -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ARG1SEXT]], 1 -; CHECK: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: [[LOAD:%[a-zA-Z_0-9-]+]] = load i8, ptr [[GEP]] -; CHECK: [[ADDRES:%[a-zA-Z_0-9-]+]] = zext i8 [[LOAD]] to i64 -; CHECK: add i64 [[ADDRES]], [[PROMOTED]] -; CHECK: ret define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, ptr %base) { - %add = add nsw i8 %arg1, 1 +; CHECK-LABEL: define i64 @oneArgPromotionSExtSeveralUse( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = sext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ALMOSTFINALRES:%.*]] = zext i8 [[RES]] to i64 +; CHECK-NEXT: [[FINALRES:%.*]] = add i64 [[ALMOSTFINALRES]], [[ADD]] +; CHECK-NEXT: ret i64 [[FINALRES]] +; + %add = add nsw i8 %arg1, 1 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -249,16 +292,19 @@ define i64 @oneArgPromotionSExtSeveralUse(i8 %arg1, ptr %base) { ; - Setting the operands of the promoted instruction with the promoted values. ; - Moving instruction around (mainly sext when promoting instruction). ; Each type of those promotions has to be undo at least once during this -; specific test. -; CHECK-LABEL: @twoArgsPromotionNest -; CHECK: [[ORIG:%[a-zA-Z_0-9-]+]] = add nsw i32 %arg1, %arg2 -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ORIG]], [[ORIG]] -; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[SEXT]] -; CHECK: ret +; specific test. define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, ptr %base) { +; CHECK-LABEL: define i8 @twoArgsPromotionNest( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTABLEADD1:%.*]] = add nsw i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[PROMOTABLEADD2:%.*]] = add nsw i32 [[PROMOTABLEADD1]], [[PROMOTABLEADD1]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i32 [[PROMOTABLEADD2]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %promotableadd1 = add nsw i32 %arg1, %arg2 - %promotableadd2 = add nsw i32 %promotableadd1, %promotableadd1 + %promotableadd2 = add nsw i32 %promotableadd1, %promotableadd1 %sextadd = sext i32 %promotableadd2 to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -270,18 +316,21 @@ define i8 @twoArgsPromotionNest(i32 %arg1, i32 %arg2, ptr %base) { ; The matcher first promotes the add, removes the trunc and promotes ; the sext of arg1. ; Then, the matcher cannot use an addressing mode r + r + r, thus it -; rolls back. -; CHECK-LABEL: @twoArgsNoPromotionRemove -; CHECK: [[SEXTARG1:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i32 -; CHECK: [[TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[SEXTARG1]] to i8 -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[TRUNC]], %arg2 -; CHECK: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i64 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[SEXT]] -; CHECK: ret +; rolls back. define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, ptr %base) { +; CHECK-LABEL: define i8 @twoArgsNoPromotionRemove( +; CHECK-SAME: i1 [[ARG1:%.*]], i8 [[ARG2:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i1 [[ARG1]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEXTARG1]] to i8 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[TRUNC]], [[ARG2]] +; CHECK-NEXT: [[SEXTADD:%.*]] = sext i8 [[ADD]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[SEXTADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nsw i8 %trunc, %arg2 + %add = add nsw i8 %trunc, %arg2 %sextadd = sext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %sextadd %res = load i8, ptr %arrayidx @@ -301,29 +350,40 @@ define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, ptr %base) { ; Check that we did not promote anything in the final matching. ; ; <rdar://problem/16020230> -; CHECK-LABEL: @checkProfitability -; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64 -; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg2 to i64 -; CHECK: [[SHL:%[a-zA-Z_0-9-]+]] = shl nsw i32 %arg1, 1 -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2 -; CHECK: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64 ; BB then -; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to ptr -; CHECK: [[FULL1:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr [[BASE1]], i64 48 -; CHECK: load i32, ptr [[FULL1]] ; BB else -; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[SEXTADD]] to ptr -; CHECK: [[FULL2:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr [[BASE2]], i64 48 -; CHECK: load i32, ptr [[FULL2]] -; CHECK: ret define i32 @checkProfitability(i32 %arg1, i32 %arg2, i1 %test) { +; CHECK-LABEL: define i32 @checkProfitability( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], i1 [[TEST:%.*]]) { +; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[ARG1]], 1 +; CHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[SHL]], [[ARG2]] +; CHECK-NEXT: [[SEXTIDX1:%.*]] = sext i32 [[ADD1]] to i64 +; CHECK-NEXT: br i1 [[TEST]], label %[[THEN:.*]], label %[[ELSE:.*]] +; CHECK: [[THEN]]: +; CHECK-NEXT: [[SUNKADDR:%.*]] = inttoptr i64 [[SEXTIDX1]] to ptr +; CHECK-NEXT: [[SUNKADDR13:%.*]] = getelementptr i8, ptr [[SUNKADDR]], i64 48 +; CHECK-NEXT: [[RES1:%.*]] = load i32, ptr [[SUNKADDR13]], align 4 +; CHECK-NEXT: br label %[[END:.*]] +; CHECK: [[ELSE]]: +; CHECK-NEXT: [[SUNKADDR17:%.*]] = inttoptr i64 [[SEXTIDX1]] to ptr +; CHECK-NEXT: [[SUNKADDR18:%.*]] = getelementptr i8, ptr [[SUNKADDR17]], i64 48 +; CHECK-NEXT: [[RES2:%.*]] = load i32, ptr [[SUNKADDR18]], align 4 +; CHECK-NEXT: br label %[[END]] +; CHECK: [[END]]: +; CHECK-NEXT: [[TMP:%.*]] = phi i32 [ [[RES1]], %[[THEN]] ], [ [[RES2]], %[[ELSE]] ] +; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[SEXTIDX1]] to i32 +; CHECK-NEXT: [[RES:%.*]] = add i32 [[TMP]], [[TMP1]] +; CHECK-NEXT: [[ADDR:%.*]] = inttoptr i32 [[RES]] to ptr +; CHECK-NEXT: [[FINAL:%.*]] = load i32, ptr [[ADDR]], align 4 +; CHECK-NEXT: ret i32 [[FINAL]] +; %shl = shl nsw i32 %arg1, 1 %add1 = add nsw i32 %shl, %arg2 %sextidx1 = sext i32 %add1 to i64 %tmpptr = inttoptr i64 %sextidx1 to ptr %arrayidx1 = getelementptr i32, ptr %tmpptr, i64 12 br i1 %test, label %then, label %else -then: +then: %res1 = load i32, ptr %arrayidx1 br label %end else: @@ -346,15 +406,47 @@ end: ; We used to crash on this function because we did not return the right ; promoted instruction for %conv.i. ; Make sure we generate the right code now. -; CHECK-LABEL: @fn3 ; %conv.i is used twice and only one of its use is being promoted. ; Use it at the starting point for the matching. -; CHECK: %conv.i = zext i16 [[PLAIN_OPND:%[.a-zA-Z_0-9-]+]] to i32 -; CHECK-NEXT: [[PROMOTED_CONV:%[.a-zA-Z_0-9-]+]] = zext i16 [[PLAIN_OPND]] to i64 -; CHECK-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr %P, i64 [[PROMOTED_CONV]] -; CHECK-NEXT: [[ADDR:%[a-zA-Z_0-9-]+]] = getelementptr i8, ptr [[ADD]], i64 7 -; CHECK-NEXT: load i8, ptr [[ADDR]], align 1 define signext i16 @fn3(ptr nocapture readonly %P) { +; CHECK-LABEL: define signext i16 @fn3( +; CHECK-SAME: ptr nocapture readonly [[P:%.*]]) { +; CHECK-NEXT: [[ENTRY:.*]]: +; CHECK-NEXT: br label %[[WHILE_BODY_I_I:.*]] +; CHECK: [[WHILE_BODY_I_I]]: +; CHECK-NEXT: [[SRC_ADDR_0_I_I:%.*]] = phi i16 [ 0, %[[ENTRY]] ], [ [[INC_I_I:%.*]], %[[WHILE_BODY_I_I]] ] +; CHECK-NEXT: [[INC_I_I]] = add i16 [[SRC_ADDR_0_I_I]], 1 +; CHECK-NEXT: [[IDXPROM_I_I:%.*]] = sext i16 [[SRC_ADDR_0_I_I]] to i64 +; CHECK-NEXT: [[SUNKADDR:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 [[IDXPROM_I_I]] +; CHECK-NEXT: [[SUNKADDR2:%.*]] = getelementptr inbounds i8, ptr [[SUNKADDR]], i64 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SUNKADDR2]], align 1 +; CHECK-NEXT: [[CONV2_I_I:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: [[AND_I_I:%.*]] = and i32 [[CONV2_I_I]], 15 +; CHECK-NEXT: store i32 [[AND_I_I]], ptr @a, align 4 +; CHECK-NEXT: [[TOBOOL_I_I:%.*]] = icmp eq i32 [[AND_I_I]], 0 +; CHECK-NEXT: br i1 [[TOBOOL_I_I]], label %[[WHILE_BODY_I_I]], label %[[FN1_EXIT_I:.*]] +; CHECK: [[FN1_EXIT_I]]: +; CHECK-NEXT: [[CONV_I:%.*]] = zext i16 [[INC_I_I]] to i32 +; CHECK-NEXT: [[PROMOTED4:%.*]] = zext i16 [[INC_I_I]] to i64 +; CHECK-NEXT: [[SUNKADDR5:%.*]] = getelementptr i8, ptr [[P]], i64 [[PROMOTED4]] +; CHECK-NEXT: [[SUNKADDR6:%.*]] = getelementptr i8, ptr [[SUNKADDR5]], i64 7 +; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[SUNKADDR6]], align 1 +; CHECK-NEXT: [[CONV2_I:%.*]] = sext i8 [[TMP2]] to i16 +; CHECK-NEXT: store i16 [[CONV2_I]], ptr @b, align 2 +; CHECK-NEXT: [[SUB4_I:%.*]] = sub nsw i32 0, [[CONV_I]] +; CHECK-NEXT: [[CONV5_I:%.*]] = zext i16 [[CONV2_I]] to i32 +; CHECK-NEXT: [[CMP_I:%.*]] = icmp sgt i32 [[CONV5_I]], [[SUB4_I]] +; CHECK-NEXT: br i1 [[CMP_I]], label %[[IF_THEN_I:.*]], label %[[FN2_EXIT:.*]] +; CHECK: [[IF_THEN_I]]: +; CHECK-NEXT: [[END_I:%.*]] = getelementptr inbounds [[STRUCT_DNS_PACKET:%.*]], ptr [[P]], i64 0, i32 1 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[END_I]], align 4 +; CHECK-NEXT: [[SUB7_I:%.*]] = add i32 [[TMP3]], 65535 +; CHECK-NEXT: [[CONV8_I:%.*]] = trunc i32 [[SUB7_I]] to i16 +; CHECK-NEXT: br label %[[FN2_EXIT]] +; CHECK: [[FN2_EXIT]]: +; CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i16 [ [[CONV8_I]], %[[IF_THEN_I]] ], [ undef, %[[FN1_EXIT_I]] ] +; CHECK-NEXT: ret i16 [[RETVAL_0_I]] +; entry: %tmp = getelementptr inbounds %struct.dns_packet, ptr %P, i64 0, i32 2 br label %while.body.i.i @@ -399,13 +491,16 @@ fn2.exit: ; preds = %if.then.i, %fn1.exi ; Check that we do not promote an extension if the non-wrapping flag does not ; match the kind of the extension. -; CHECK-LABEL: @noPromotionFlag -; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 %arg1, %arg2 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = zext i32 [[ADD]] to i64 -; CHECK: inttoptr i64 [[PROMOTED]] to ptr -; CHECK: ret define i8 @noPromotionFlag(i32 %arg1, i32 %arg2) { - %add = add nsw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @noPromotionFlag( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) { +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: [[ZEXTADD:%.*]] = zext i32 [[ADD]] to i64 +; CHECK-NEXT: [[BASE:%.*]] = inttoptr i64 [[ZEXTADD]] to ptr +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[BASE]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nsw i32 %arg1, %arg2 %zextadd = zext i32 %add to i64 %base = inttoptr i64 %zextadd to ptr %res = load i8, ptr %base @@ -413,14 +508,17 @@ define i8 @noPromotionFlag(i32 %arg1, i32 %arg2) { } ; Check that we correctly promote both operands of the promotable add with zext. -; CHECK-LABEL: @twoArgsPromotionZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i32 %arg1 to i64 -; CHECK: [[ARG2ZEXT:%[a-zA-Z_0-9-]+]] = zext i32 %arg2 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], [[ARG2ZEXT]] -; CHECK: inttoptr i64 [[PROMOTED]] to ptr -; CHECK: ret define i8 @twoArgsPromotionZExt(i32 %arg1, i32 %arg2) { - %add = add nuw i32 %arg1, %arg2 +; CHECK-LABEL: define i8 @twoArgsPromotionZExt( +; CHECK-SAME: i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i32 [[ARG1]] to i64 +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i32 [[ARG2]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], [[PROMOTED2]] +; CHECK-NEXT: [[BASE:%.*]] = inttoptr i64 [[ADD]] to ptr +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[BASE]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nuw i32 %arg1, %arg2 %zextadd = zext i32 %add to i64 %base = inttoptr i64 %zextadd to ptr %res = load i8, ptr %base @@ -428,13 +526,16 @@ define i8 @twoArgsPromotionZExt(i32 %arg1, i32 %arg2) { } ; Check that we correctly promote constant arguments. -; CHECK-LABEL: @oneArgPromotionNegativeCstZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 255 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionNegativeCstZExt(i8 %arg1, ptr %base) { - %add = add nuw i8 %arg1, -1 +; CHECK-LABEL: define i8 @oneArgPromotionNegativeCstZExt( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], 255 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; + %add = add nuw i8 %arg1, -1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -442,14 +543,17 @@ define i8 @oneArgPromotionNegativeCstZExt(i8 %arg1, ptr %base) { } ; Check that we are able to merge two zero extensions. -; CHECK-LABEL: @oneArgPromotionZExtZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionZExtZExt(i8 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionZExtZExt( +; CHECK-SAME: i8 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i8 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %zext = zext i8 %arg1 to i32 - %add = add nuw i32 %zext, 1 + %add = add nuw i32 %zext, 1 %zextadd = zext i32 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -458,17 +562,20 @@ define i8 @oneArgPromotionZExtZExt(i8 %arg1, ptr %base) { ; Check that we do not promote truncate when the dropped bits ; are of a different kind. -; CHECK-LABEL: @oneArgPromotionBlockTruncZExt -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i32 -; CHECK: [[ARG1TRUNC:%[a-zA-Z_0-9-]+]] = trunc i32 [[ARG1SEXT]] to i8 -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[ARG1TRUNC]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockTruncZExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockTruncZExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i1 [[ARG1]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SEXTARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i8 [[TRUNC]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nuw i8 %trunc, 1 + %add = add nuw i8 %trunc, 1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -477,15 +584,18 @@ define i8 @oneArgPromotionBlockTruncZExt(i1 %arg1, ptr %base) { ; Check that we are able to promote truncate when we know all the bits ; that are dropped. -; CHECK-LABEL: @oneArgPromotionPassTruncZExt -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i1 %arg1 to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionPassTruncZExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionPassTruncZExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[PROMOTED2:%.*]] = zext i1 [[ARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED2]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = zext i1 %arg1 to i32 %trunc = trunc i32 %sextarg1 to i8 - %add = add nuw i8 %trunc, 1 + %add = add nuw i8 %trunc, 1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx @@ -493,15 +603,18 @@ define i8 @oneArgPromotionPassTruncZExt(i1 %arg1, ptr %base) { } ; Check that we do not promote sext with zext. -; CHECK-LABEL: @oneArgPromotionBlockSExtZExt -; CHECK: [[ARG1SEXT:%[a-zA-Z_0-9-]+]] = sext i1 %arg1 to i8 -; CHECK: [[ARG1ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[ARG1SEXT]] to i64 -; CHECK: [[PROMOTED:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ARG1ZEXT]], 1 -; CHECK: getelementptr inbounds i8, ptr %base, i64 [[PROMOTED]] -; CHECK: ret define i8 @oneArgPromotionBlockSExtZExt(i1 %arg1, ptr %base) { +; CHECK-LABEL: define i8 @oneArgPromotionBlockSExtZExt( +; CHECK-SAME: i1 [[ARG1:%.*]], ptr [[BASE:%.*]]) { +; CHECK-NEXT: [[SEXTARG1:%.*]] = sext i1 [[ARG1]] to i8 +; CHECK-NEXT: [[PROMOTED:%.*]] = zext i8 [[SEXTARG1]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add nuw i64 [[PROMOTED]], 1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[BASE]], i64 [[ADD]] +; CHECK-NEXT: [[RES:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: ret i8 [[RES]] +; %sextarg1 = sext i1 %arg1 to i8 - %add = add nuw i8 %sextarg1, 1 + %add = add nuw i8 %sextarg1, 1 %zextadd = zext i8 %add to i64 %arrayidx = getelementptr inbounds i8, ptr %base, i64 %zextadd %res = load i8, ptr %arrayidx diff --git a/llvm/test/CodeGen/X86/uint_to_half.ll b/llvm/test/CodeGen/X86/uint_to_half.ll new file mode 100644 index 000000000000..b62a07eec1ce --- /dev/null +++ b/llvm/test/CodeGen/X86/uint_to_half.ll @@ -0,0 +1,198 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx,+f16c | FileCheck %s -check-prefixes=AVX1 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2,+f16c | FileCheck %s -check-prefixes=AVX2 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl | FileCheck %s -check-prefixes=AVX512 + +define <8 x half> @test_uitofp_v8i32_v8f16(<8 x i32> %a) { +; AVX1-LABEL: test_uitofp_v8i32_v8f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 +; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_uitofp_v8i32_v8f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_uitofp_v8i32_v8f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %ymm0, %ymm0 +; AVX512-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %vec = uitofp <8 x i32> %a to <8 x half> + ret <8 x half> %vec +} + +define <8 x half> @test_strict_uitofp_v8i32_v8f16(<8 x i32> %a) { +; AVX1-LABEL: test_strict_uitofp_v8i32_v8f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm1 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vpsrld $16, %xmm2, %xmm2 +; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vmulps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 +; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_strict_uitofp_v8i32_v8f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm2 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_strict_uitofp_v8i32_v8f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %ymm0, %ymm0 +; AVX512-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %vec = tail call <8 x half> @llvm.experimental.constrained.uitofp.f16.i32(<8 x i32> %a, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret <8 x half> %vec +} + +define <16 x half> @test_uitofp_v16i32_v16f16(<16 x i32> %a) { +; AVX1-LABEL: test_uitofp_v16i32_v16f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpsrld $16, %xmm3, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4] +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm4 = [65535,65535,65535,65535,65535,65535,65535,65535] +; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm2, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vpsrld $16, %xmm1, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vpsrld $16, %xmm5, %xmm5 +; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vandps %ymm4, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX1-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_uitofp_v16i32_v16f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm3 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm4 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7],ymm0[8],ymm4[9],ymm0[10],ymm4[11],ymm0[12],ymm4[13],ymm0[14],ymm4[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm5 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm5, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0],ymm2[1],ymm1[2],ymm2[3],ymm1[4],ymm2[5],ymm1[6],ymm2[7],ymm1[8],ymm2[9],ymm1[10],ymm2[11],ymm1[12],ymm2[13],ymm1[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm4[1],ymm1[2],ymm4[3],ymm1[4],ymm4[5],ymm1[6],ymm4[7],ymm1[8],ymm4[9],ymm1[10],ymm4[11],ymm1[12],ymm4[13],ymm1[14],ymm4[15] +; AVX2-NEXT: vsubps %ymm5, %ymm1, %ymm1 +; AVX2-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_uitofp_v16i32_v16f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %zmm0, %zmm0 +; AVX512-NEXT: vcvtps2ph $4, %zmm0, %ymm0 +; AVX512-NEXT: retq + %vec = uitofp <16 x i32> %a to <16 x half> + ret <16 x half> %vec +} + +define <16 x half> @test_strict_uitofp_v16i32_v16f16(<16 x i32> %a) { +; AVX1-LABEL: test_strict_uitofp_v16i32_v16f16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrld $16, %xmm0, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 +; AVX1-NEXT: vpsrld $16, %xmm3, %xmm3 +; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4,6.5536E+4] +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} ymm4 = [65535,65535,65535,65535,65535,65535,65535,65535] +; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0 +; AVX1-NEXT: vcvtdq2ps %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm2, %ymm0 +; AVX1-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX1-NEXT: vpsrld $16, %xmm1, %xmm2 +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 +; AVX1-NEXT: vpsrld $16, %xmm5, %xmm5 +; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2 +; AVX1-NEXT: vcvtdq2ps %ymm2, %ymm2 +; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm2 +; AVX1-NEXT: vandps %ymm4, %ymm1, %ymm1 +; AVX1-NEXT: vcvtdq2ps %ymm1, %ymm1 +; AVX1-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX1-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: test_strict_uitofp_v16i32_v16f16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200,1258291200] +; AVX2-NEXT: vpblendw {{.*#+}} ymm3 = ymm0[0],ymm2[1],ymm0[2],ymm2[3],ymm0[4],ymm2[5],ymm0[6],ymm2[7],ymm0[8],ymm2[9],ymm0[10],ymm2[11],ymm0[12],ymm2[13],ymm0[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm4 = [1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928,1392508928] +; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7],ymm0[8],ymm4[9],ymm0[10],ymm4[11],ymm0[12],ymm4[13],ymm0[14],ymm4[15] +; AVX2-NEXT: vbroadcastss {{.*#+}} ymm5 = [5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11,5.49764202E+11] +; AVX2-NEXT: vsubps %ymm5, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm3, %ymm0 +; AVX2-NEXT: vcvtps2ph $4, %ymm0, %xmm0 +; AVX2-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0],ymm2[1],ymm1[2],ymm2[3],ymm1[4],ymm2[5],ymm1[6],ymm2[7],ymm1[8],ymm2[9],ymm1[10],ymm2[11],ymm1[12],ymm2[13],ymm1[14],ymm2[15] +; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 +; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0],ymm4[1],ymm1[2],ymm4[3],ymm1[4],ymm4[5],ymm1[6],ymm4[7],ymm1[8],ymm4[9],ymm1[10],ymm4[11],ymm1[12],ymm4[13],ymm1[14],ymm4[15] +; AVX2-NEXT: vsubps %ymm5, %ymm1, %ymm1 +; AVX2-NEXT: vaddps %ymm1, %ymm2, %ymm1 +; AVX2-NEXT: vcvtps2ph $4, %ymm1, %xmm1 +; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test_strict_uitofp_v16i32_v16f16: +; AVX512: # %bb.0: +; AVX512-NEXT: vcvtudq2ps %zmm0, %zmm0 +; AVX512-NEXT: vcvtps2ph $4, %zmm0, %ymm0 +; AVX512-NEXT: retq + %vec = tail call <16 x half> @llvm.experimental.constrained.uitofp.f16.i32(<16 x i32> %a, metadata !"round.dynamic", metadata !"fpexcept.strict") + ret <16 x half> %vec +} diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll index 4f42d5c65528..15e287d66754 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll @@ -4129,6 +4129,62 @@ define <32 x i8> @shuffle_v32i8_56_zz_zz_zz_57_zz_zz_zz_58_zz_zz_zz__zz_59_zz_zz ret <32 x i8> %shuffle } +; PR121823 +define <32 x i8> @shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz(<32 x i8> %a) { +; AVX1-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[1,9,0,3] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,9,0,3,11,2,5,13,4,7,15,6],zero,zero,zero,zero +; AVX1-NEXT: vpor %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[11,2,5,13,4,7,15,6],zero,zero,zero,zero,zero,zero,zero,zero +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX2: # %bb.0: +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,9,0,3,11,2,5,13,4,7,15,6,u,u,u,u,17,25,16,19,27,18,21,29,20,23,31,22,u,u,u,u] +; AVX2-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,2,4,5,6,0,0] +; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0 +; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; AVX2-NEXT: retq +; +; AVX512VLBW-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX512VLBW: # %bb.0: +; AVX512VLBW-NEXT: vpshufb {{.*#+}} ymm1 = ymm0[1,9,0,3,11,2,5,13,4,7,15,6,u,u,u,u,17,25,16,19,27,18,21,29,20,23,31,22,u,u,u,u] +; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512VLBW-NEXT: vpmovsxbd {{.*#+}} ymm0 = [0,1,2,4,5,6,14,15] +; AVX512VLBW-NEXT: vpermi2d %ymm2, %ymm1, %ymm0 +; AVX512VLBW-NEXT: retq +; +; AVX512VLVBMI-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; AVX512VLVBMI: # %bb.0: +; AVX512VLVBMI-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; AVX512VLVBMI-NEXT: vmovdqa {{.*#+}} ymm2 = [1,9,0,3,11,2,5,13,4,7,15,6,17,25,16,19,27,18,21,29,20,23,31,22,56,57,58,59,60,61,62,63] +; AVX512VLVBMI-NEXT: vpermt2b %ymm1, %ymm2, %ymm0 +; AVX512VLVBMI-NEXT: retq +; +; XOPAVX1-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; XOPAVX1: # %bb.0: +; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; XOPAVX1-NEXT: vpperm {{.*#+}} xmm0 = xmm0[1,9,0,3,11,2,5,13,4,7,15,6],xmm1[1,9,0,3] +; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[11,2,5,13,4,7,15,6],zero,zero,zero,zero,zero,zero,zero,zero +; XOPAVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; XOPAVX1-NEXT: retq +; +; XOPAVX2-LABEL: shuffle_v32i8_01_09_00_03_11_02_05_13_04_07_15_06_17_25_16_19_27_18_21_29_20_23_31_22_zz_zz_zz_zz_zz_zz_zz_zz: +; XOPAVX2: # %bb.0: +; XOPAVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[1,9,0,3,11,2,5,13,4,7,15,6,u,u,u,u,17,25,16,19,27,18,21,29,20,23,31,22,u,u,u,u] +; XOPAVX2-NEXT: vpmovsxbd {{.*#+}} ymm1 = [0,1,2,4,5,6,0,0] +; XOPAVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0 +; XOPAVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; XOPAVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; XOPAVX2-NEXT: retq + %r = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 9, i32 0, i32 3, i32 11, i32 2, i32 5, i32 13, i32 4, i32 7, i32 15, i32 6, i32 17, i32 25, i32 16, i32 19, i32 27, i32 18, i32 21, i32 29, i32 20, i32 23, i32 31, i32 22, i32 32, i32 32, i32 32, i32 32, i32 48, i32 48, i32 48, i32 48> + ret <32 x i8> %r +} + define <32 x i8> @shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30(<32 x i8> %a, <32 x i8> %b) { ; AVX1-LABEL: shuffle_v32i8_47_00_01_02_03_04_05_06_07_08_09_10_11_12_13_14_63_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30: ; AVX1: # %bb.0: |