Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format

1 files changed, 236 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/RISCV/rvv/vqdotus.ll b/llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
new file mode 100644
index 000000000000..94413369dd99
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vqdotus.ll
@@ -0,0 +1,236 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvqdotq \
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvqdotq \
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+declare <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  i32,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_vqdotus_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_vx_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma
+; CHECK-NEXT:    vqdotus.vx v8, v9, a0
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+declare <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  i32,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_vqdotus_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_vx_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma
+; CHECK-NEXT:    vqdotus.vx v8, v9, a0
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+declare <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  i32,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_vqdotus_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_vx_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma
+; CHECK-NEXT:    vqdotus.vx v8, v10, a0
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+declare <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  i32,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_vqdotus_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_vx_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma
+; CHECK-NEXT:    vqdotus.vx v8, v12, a0
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+declare <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 64 x i8>,
+  i32,
+  iXLen,
+  iXLen);
+
+define <vscale x 16 x i32>  @intrinsic_vqdotus_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_vx_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, ma
+; CHECK-NEXT:    vqdotus.vx v8, v16, a0
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 64 x i8> %1,
+    i32 %2,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 16 x i32> %a
+}
+declare <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 4 x i8>,
+  i32,
+  <vscale x 1 x i1>,
+  iXLen,
+  iXLen);
+
+define <vscale x 1 x i32>  @intrinsic_vqdotus_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
+; CHECK-NEXT:    vqdotus.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2,
+    <vscale x 1 x i1> %m,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 1 x i32> %a
+}
+declare <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i8>,
+  i32,
+  <vscale x 2 x i1>,
+  iXLen,
+  iXLen);
+
+define <vscale x 2 x i32>  @intrinsic_vqdotus_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
+; CHECK-NEXT:    vqdotus.vx v8, v9, a0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2,
+    <vscale x 2 x i1> %m,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 2 x i32> %a
+}
+declare <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 16 x i8>,
+  i32,
+  <vscale x 4 x i1>,
+  iXLen,
+  iXLen);
+
+define <vscale x 4 x i32>  @intrinsic_vqdotus_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
+; CHECK-NEXT:    vqdotus.vx v8, v10, a0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2,
+    <vscale x 4 x i1> %m,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 4 x i32> %a
+}
+declare <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 32 x i8>,
+  i32,
+  <vscale x 8 x i1>,
+  iXLen,
+  iXLen);
+
+define <vscale x 8 x i32>  @intrinsic_vqdotus_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu
+; CHECK-NEXT:    vqdotus.vx v8, v12, a0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2,
+    <vscale x 8 x i1> %m,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 8 x i32> %a
+}
+declare <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 64 x i8>,
+  i32,
+  <vscale x 16 x i1>,
+  iXLen,
+  iXLen);
+
+define <vscale x 16 x i32>  @intrinsic_vqdotus_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {
+; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, mu
+; CHECK-NEXT:    vqdotus.vx v8, v16, a0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 64 x i8> %1,
+    i32 %2,
+    <vscale x 16 x i1> %m,
+    iXLen %3, iXLen 0)
+
+  ret <vscale x 16 x i32> %a
+}