Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format

1 files changed, 81 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll
index 8584579b8138..a838d54ad5e9 100644
--- a/llvm/test/CodeGen/RISCV/jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/jumptable.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL
+; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -mattr=+experimental-xqcili  < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32IXQCILI-SMALL
 ; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM
 ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs < %s \
@@ -13,6 +15,8 @@
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV64I-PIC
 ; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL-7-ENTRIES
+; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 -mattr=+experimental-xqcili < %s \
+; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32IXQCILI-SMALL-7-ENTRIES
 ; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
 ; RUN:   | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM-7-ENTRIES
 ; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \
@@ -114,6 +118,39 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
 ; RV32I-SMALL-NEXT:  .LBB1_9: # %exit
 ; RV32I-SMALL-NEXT:    ret
 ;
+; RV32IXQCILI-SMALL-LABEL: above_threshold:
+; RV32IXQCILI-SMALL:       # %bb.0: # %entry
+; RV32IXQCILI-SMALL-NEXT:    addi a0, a0, -1
+; RV32IXQCILI-SMALL-NEXT:    li a2, 5
+; RV32IXQCILI-SMALL-NEXT:    bltu a2, a0, .LBB1_9
+; RV32IXQCILI-SMALL-NEXT:  # %bb.1: # %entry
+; RV32IXQCILI-SMALL-NEXT:    slli a0, a0, 2
+; RV32IXQCILI-SMALL-NEXT:    qc.e.li a2, .LJTI1_0
+; RV32IXQCILI-SMALL-NEXT:    add a0, a0, a2
+; RV32IXQCILI-SMALL-NEXT:    lw a0, 0(a0)
+; RV32IXQCILI-SMALL-NEXT:    jr a0
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_2: # %bb1
+; RV32IXQCILI-SMALL-NEXT:    li a0, 4
+; RV32IXQCILI-SMALL-NEXT:    j .LBB1_8
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_3: # %bb5
+; RV32IXQCILI-SMALL-NEXT:    li a0, 100
+; RV32IXQCILI-SMALL-NEXT:    j .LBB1_8
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_4: # %bb3
+; RV32IXQCILI-SMALL-NEXT:    li a0, 2
+; RV32IXQCILI-SMALL-NEXT:    j .LBB1_8
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_5: # %bb4
+; RV32IXQCILI-SMALL-NEXT:    li a0, 1
+; RV32IXQCILI-SMALL-NEXT:    j .LBB1_8
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_6: # %bb2
+; RV32IXQCILI-SMALL-NEXT:    li a0, 3
+; RV32IXQCILI-SMALL-NEXT:    j .LBB1_8
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_7: # %bb6
+; RV32IXQCILI-SMALL-NEXT:    li a0, 200
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_8: # %exit
+; RV32IXQCILI-SMALL-NEXT:    sw a0, 0(a1)
+; RV32IXQCILI-SMALL-NEXT:  .LBB1_9: # %exit
+; RV32IXQCILI-SMALL-NEXT:    ret
+;
 ; RV32I-MEDIUM-LABEL: above_threshold:
 ; RV32I-MEDIUM:       # %bb.0: # %entry
 ; RV32I-MEDIUM-NEXT:    addi a0, a0, -1
@@ -334,6 +371,50 @@ define void @above_threshold(i32 signext %in, ptr %out) nounwind {
 ; RV32I-SMALL-7-ENTRIES-NEXT:  .LBB1_14: # %exit
 ; RV32I-SMALL-7-ENTRIES-NEXT:    ret
 ;
+; RV32IXQCILI-SMALL-7-ENTRIES-LABEL: above_threshold:
+; RV32IXQCILI-SMALL-7-ENTRIES:       # %bb.0: # %entry
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a2, 3
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    blt a2, a0, .LBB1_5
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  # %bb.1: # %entry
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a2, 1
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_9
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  # %bb.2: # %entry
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a2, 2
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_11
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  # %bb.3: # %entry
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a2, 3
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  # %bb.4: # %bb3
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a0, 2
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  .LBB1_5: # %entry
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a2, 4
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_10
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  # %bb.6: # %entry
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a2, 5
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    beq a0, a2, .LBB1_12
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  # %bb.7: # %entry
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a2, 6
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    bne a0, a2, .LBB1_14
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  # %bb.8: # %bb6
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a0, 200
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  .LBB1_9: # %bb1
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a0, 4
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  .LBB1_10: # %bb4
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a0, 1
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  .LBB1_11: # %bb2
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a0, 3
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    j .LBB1_13
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  .LBB1_12: # %bb5
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    li a0, 100
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  .LBB1_13: # %exit
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    sw a0, 0(a1)
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:  .LBB1_14: # %exit
+; RV32IXQCILI-SMALL-7-ENTRIES-NEXT:    ret
+;
 ; RV32I-MEDIUM-7-ENTRIES-LABEL: above_threshold:
 ; RV32I-MEDIUM-7-ENTRIES:       # %bb.0: # %entry
 ; RV32I-MEDIUM-7-ENTRIES-NEXT:    li a2, 3