Bug fixusers/pcc/spr/elf-add-preferred-function-alignment-flag

Created using spr 1.3.6-beta.1

7 files changed, 245 insertions, 120 deletions

diff --git a/llvm/test/CodeGen/PowerPC/copysignl.ll b/llvm/test/CodeGen/PowerPC/copysignl.ll
index 40ed3d803094..9fdfb8fc548d 100644
--- a/llvm/test/CodeGen/PowerPC/copysignl.ll
+++ b/llvm/test/CodeGen/PowerPC/copysignl.ll
@@ -20,6 +20,23 @@ entry:
   ret double %conv
 }
 
+define double @foo_d_ll_freeze(ppc_fp128 %a, ppc_fp128 %b) #0 {
+; CHECK-LABEL: foo_d_ll_freeze:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fcpsgn 1, 3, 1
+; CHECK-NEXT:    blr
+;
+; CHECK-VSX-LABEL: foo_d_ll_freeze:
+; CHECK-VSX:       # %bb.0: # %entry
+; CHECK-VSX-NEXT:    xscpsgndp 1, 3, 1
+; CHECK-VSX-NEXT:    blr
+entry:
+  %call = tail call ppc_fp128 @copysignl(ppc_fp128 %a, ppc_fp128 %b) #0
+  %freeze = freeze ppc_fp128 %call
+  %conv = fptrunc ppc_fp128 %freeze to double
+  ret double %conv
+}
+
 declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) #0
 
 define double @foo_dl(double %a, ppc_fp128 %b) #0 {
@@ -46,9 +63,9 @@ define ppc_fp128 @foo_ll(double %a, ppc_fp128 %b) #0 {
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stdu 1, -112(1)
 ; CHECK-NEXT:    fmr 3, 2
-; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
+; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK-NEXT:    std 0, 128(1)
-; CHECK-NEXT:    lfs 2, .LCPI2_0@toc@l(3)
+; CHECK-NEXT:    lfs 2, .LCPI3_0@toc@l(3)
 ; CHECK-NEXT:    bl copysignl
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 112
@@ -81,9 +98,9 @@ define ppc_fp128 @foo_ld(double %a, double %b) #0 {
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stdu 1, -112(1)
 ; CHECK-NEXT:    fmr 3, 2
-; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
 ; CHECK-NEXT:    std 0, 128(1)
-; CHECK-NEXT:    lfs 2, .LCPI3_0@toc@l(3)
+; CHECK-NEXT:    lfs 2, .LCPI4_0@toc@l(3)
 ; CHECK-NEXT:    bl copysignl
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 112
@@ -117,9 +134,9 @@ define ppc_fp128 @foo_lf(double %a, float %b) #0 {
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stdu 1, -112(1)
 ; CHECK-NEXT:    fmr 3, 2
-; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
+; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
 ; CHECK-NEXT:    std 0, 128(1)
-; CHECK-NEXT:    lfs 2, .LCPI4_0@toc@l(3)
+; CHECK-NEXT:    lfs 2, .LCPI5_0@toc@l(3)
 ; CHECK-NEXT:    bl copysignl
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi 1, 1, 112
diff --git a/llvm/test/CodeGen/PowerPC/exp10-libcall.ll b/llvm/test/CodeGen/PowerPC/exp10-libcall.ll
index 49a1ac3025c0..68f701cab5a3 100644
--- a/llvm/test/CodeGen/PowerPC/exp10-libcall.ll
+++ b/llvm/test/CodeGen/PowerPC/exp10-libcall.ll
@@ -2,14 +2,12 @@
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
-define float @call_exp10f(float %a) {
+define float @call_exp10f(float %a) nounwind {
 ; CHECK-LABEL: call_exp10f:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    bl exp10f
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
@@ -20,14 +18,12 @@ define float @call_exp10f(float %a) {
   ret float %result
 }
 
-define double @call_exp10(double %a) {
+define double @call_exp10(double %a) nounwind {
 ; CHECK-LABEL: call_exp10:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    bl exp10
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
@@ -38,14 +34,12 @@ define double @call_exp10(double %a) {
   ret double %result
 }
 
-define ppc_fp128 @call_exp10l(ppc_fp128 %a) {
+define ppc_fp128 @call_exp10l(ppc_fp128 %a) nounwind {
 ; CHECK-LABEL: call_exp10l:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    bl exp10l
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
diff --git a/llvm/test/CodeGen/PowerPC/ldexp-libcall.ll b/llvm/test/CodeGen/PowerPC/ldexp-libcall.ll
index e531516c37e8..680c99bd1e98 100644
--- a/llvm/test/CodeGen/PowerPC/ldexp-libcall.ll
+++ b/llvm/test/CodeGen/PowerPC/ldexp-libcall.ll
@@ -2,15 +2,13 @@
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
-define float @call_ldexpf(float %a, i32 %b) {
+define float @call_ldexpf(float %a, i32 %b) nounwind {
 ; CHECK-LABEL: call_ldexpf:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
-; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    extsw r4, r4
+; CHECK-NEXT:    std r0, 48(r1)
 ; CHECK-NEXT:    bl ldexpf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
@@ -21,15 +19,13 @@ define float @call_ldexpf(float %a, i32 %b) {
   ret float %result
 }
 
-define double @call_ldexp(double %a, i32 %b) {
+define double @call_ldexp(double %a, i32 %b) nounwind {
 ; CHECK-LABEL: call_ldexp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
-; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    extsw r4, r4
+; CHECK-NEXT:    std r0, 48(r1)
 ; CHECK-NEXT:    bl ldexp
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
@@ -40,15 +36,13 @@ define double @call_ldexp(double %a, i32 %b) {
   ret double %result
 }
 
-define ppc_fp128 @call_ldexpl(ppc_fp128 %a, i32 %b) {
+define ppc_fp128 @call_ldexpl(ppc_fp128 %a, i32 %b) nounwind {
 ; CHECK-LABEL: call_ldexpl:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
-; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    clrldi r5, r5, 32
+; CHECK-NEXT:    std r0, 48(r1)
 ; CHECK-NEXT:    bl ldexpl
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
diff --git a/llvm/test/CodeGen/PowerPC/ldexp.ll b/llvm/test/CodeGen/PowerPC/ldexp.ll
index ffc826cc86de..8d7253b5ce8e 100644
--- a/llvm/test/CodeGen/PowerPC/ldexp.ll
+++ b/llvm/test/CodeGen/PowerPC/ldexp.ll
@@ -2,16 +2,14 @@
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
-define float @ldexp_f32(i8 zeroext %x) {
+define float @ldexp_f32(i8 zeroext %x) nounwind {
 ; CHECK-LABEL: ldexp_f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
-; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    vspltisw v2, 1
 ; CHECK-NEXT:    mr r4, r3
+; CHECK-NEXT:    std r0, 48(r1)
 ; CHECK-NEXT:    xvcvsxwdp vs1, v2
 ; CHECK-NEXT:    bl ldexpf
 ; CHECK-NEXT:    nop
@@ -24,16 +22,14 @@ define float @ldexp_f32(i8 zeroext %x) {
   ret float %ldexp
 }
 
-define double @ldexp_f64(i8 zeroext %x) {
+define double @ldexp_f64(i8 zeroext %x) nounwind {
 ; CHECK-LABEL: ldexp_f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
-; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    vspltisw v2, 1
 ; CHECK-NEXT:    mr r4, r3
+; CHECK-NEXT:    std r0, 48(r1)
 ; CHECK-NEXT:    xvcvsxwdp vs1, v2
 ; CHECK-NEXT:    bl ldexp
 ; CHECK-NEXT:    nop
@@ -46,27 +42,22 @@ define double @ldexp_f64(i8 zeroext %x) {
   ret double %ldexp
 }
 
-define <2 x float> @ldexp_v2f32(<2 x float> %val, <2 x i32> %exp) {
+define <2 x float> @ldexp_v2f32(<2 x float> %val, <2 x i32> %exp) nounwind {
 ; CHECK-LABEL: ldexp_v2f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -80(r1)
-; CHECK-NEXT:    std r0, 96(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
-; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    .cfi_offset v29, -48
-; CHECK-NEXT:    .cfi_offset v30, -32
-; CHECK-NEXT:    .cfi_offset v31, -16
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    xxsldwi vs0, v2, v2, 3
-; CHECK-NEXT:    stxv v29, 32(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    std r0, 96(r1)
 ; CHECK-NEXT:    xscvspdpn f1, vs0
 ; CHECK-NEXT:    vextuwrx r3, r3, v3
+; CHECK-NEXT:    stxv v29, 32(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v30, 48(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v31, 64(r1) # 16-byte Folded Spill
-; CHECK-NEXT:    extsw r4, r3
 ; CHECK-NEXT:    vmr v31, v3
 ; CHECK-NEXT:    vmr v30, v2
+; CHECK-NEXT:    extsw r4, r3
 ; CHECK-NEXT:    bl ldexpf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    li r3, 4
@@ -90,23 +81,17 @@ define <2 x float> @ldexp_v2f32(<2 x float> %val, <2 x i32> %exp) {
   ret <2 x float> %1
 }
 
-define <4 x float> @ldexp_v4f32(<4 x float> %val, <4 x i32> %exp) {
+define <4 x float> @ldexp_v4f32(<4 x float> %val, <4 x i32> %exp) nounwind {
 ; CHECK-LABEL: ldexp_v4f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -96(r1)
-; CHECK-NEXT:    std r0, 112(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 96
-; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    .cfi_offset v28, -64
-; CHECK-NEXT:    .cfi_offset v29, -48
-; CHECK-NEXT:    .cfi_offset v30, -32
-; CHECK-NEXT:    .cfi_offset v31, -16
 ; CHECK-NEXT:    li r3, 4
 ; CHECK-NEXT:    xxswapd vs0, v2
-; CHECK-NEXT:    stxv v28, 32(r1) # 16-byte Folded Spill
+; CHECK-NEXT:    std r0, 112(r1)
 ; CHECK-NEXT:    xscvspdpn f1, vs0
 ; CHECK-NEXT:    vextuwrx r3, r3, v3
+; CHECK-NEXT:    stxv v28, 32(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v29, 48(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v30, 64(r1) # 16-byte Folded Spill
 ; CHECK-NEXT:    stxv v31, 80(r1) # 16-byte Folded Spill
@@ -153,14 +138,12 @@ define <4 x float> @ldexp_v4f32(<4 x float> %val, <4 x i32> %exp) {
   ret <4 x float> %1
 }
 
-define half @ldexp_f16(half %arg0, i32 %arg1) {
+define half @ldexp_f16(half %arg0, i32 %arg1) nounwind {
 ; CHECK-LABEL: ldexp_f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
 ; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    xscvdphp f0, f1
 ; CHECK-NEXT:    extsw r4, r4
 ; CHECK-NEXT:    mffprwz r3, f0
@@ -177,15 +160,13 @@ define half @ldexp_f16(half %arg0, i32 %arg1) {
   ret half %ldexp
 }
 
-define ppc_fp128 @ldexp_fp128(ppc_fp128 %arg0, i32 %arg1) {
+define ppc_fp128 @ldexp_fp128(ppc_fp128 %arg0, i32 %arg1) nounwind {
 ; CHECK-LABEL: ldexp_fp128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -32(r1)
-; CHECK-NEXT:    std r0, 48(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    clrldi r5, r5, 32
+; CHECK-NEXT:    std r0, 48(r1)
 ; CHECK-NEXT:    bl ldexpl
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 32
diff --git a/llvm/test/CodeGen/PowerPC/llvm.frexp.ll b/llvm/test/CodeGen/PowerPC/llvm.frexp.ll
index 2c522c4d10cd..95d763d7179e 100644
--- a/llvm/test/CodeGen/PowerPC/llvm.frexp.ll
+++ b/llvm/test/CodeGen/PowerPC/llvm.frexp.ll
@@ -2,14 +2,12 @@
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
-define { half, i32 } @test_frexp_f16_i32(half %a) {
+define { half, i32 } @test_frexp_f16_i32(half %a) nounwind {
 ; CHECK-LABEL: test_frexp_f16_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    xscvdphp f0, f1
 ; CHECK-NEXT:    addi r4, r1, 44
 ; CHECK-NEXT:    mffprwz r3, f0
@@ -27,14 +25,12 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
   ret { half, i32 } %result
 }
 
-define half @test_frexp_f16_i32_only_use_fract(half %a) {
+define half @test_frexp_f16_i32_only_use_fract(half %a) nounwind {
 ; CHECK-LABEL: test_frexp_f16_i32_only_use_fract:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    xscvdphp f0, f1
 ; CHECK-NEXT:    addi r4, r1, 44
 ; CHECK-NEXT:    mffprwz r3, f0
@@ -52,14 +48,12 @@ define half @test_frexp_f16_i32_only_use_fract(half %a) {
   ret half %result.0
 }
 
-define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
+define i32 @test_frexp_f16_i32_only_use_exp(half %a) nounwind {
 ; CHECK-LABEL: test_frexp_f16_i32_only_use_exp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    xscvdphp f0, f1
 ; CHECK-NEXT:    addi r4, r1, 44
 ; CHECK-NEXT:    mffprwz r3, f0
@@ -78,16 +72,10 @@ define i32 @test_frexp_f16_i32_only_use_exp(half %a) {
   ret i32 %result.0
 }
 
-define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
+define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) nounwind {
 ; CHECK-LABEL: test_frexp_v2f16_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
-; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    .cfi_offset r29, -40
-; CHECK-NEXT:    .cfi_offset r30, -32
-; CHECK-NEXT:    .cfi_offset f30, -16
-; CHECK-NEXT:    .cfi_offset f31, -8
 ; CHECK-NEXT:    std r29, -40(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
@@ -131,14 +119,10 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) {
   ret { <2 x half>, <2 x i32> } %result
 }
 
-define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
+define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) nounwind {
 ; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_fract:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
-; CHECK-NEXT:    .cfi_def_cfa_offset 64
-; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    .cfi_offset f30, -16
-; CHECK-NEXT:    .cfi_offset f31, -8
 ; CHECK-NEXT:    stfd f30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stdu r1, -64(r1)
@@ -174,15 +158,10 @@ define <2 x half> @test_frexp_v2f16_v2i32_only_use_fract(<2 x half> %a) {
   ret <2 x half> %result.0
 }
 
-define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
+define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) nounwind {
 ; CHECK-LABEL: test_frexp_v2f16_v2i32_only_use_exp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
-; CHECK-NEXT:    .cfi_offset lr, 16
-; CHECK-NEXT:    .cfi_offset r29, -32
-; CHECK-NEXT:    .cfi_offset r30, -24
-; CHECK-NEXT:    .cfi_offset f31, -8
 ; CHECK-NEXT:    std r29, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stfd f31, -8(r1) # 8-byte Folded Spill
@@ -222,15 +201,13 @@ define <2 x i32> @test_frexp_v2f16_v2i32_only_use_exp(<2 x half> %a) {
   ret <2 x i32> %result.1
 }
 
-define { float, i32 } @test_frexp_f32_i32(float %a) {
+define { float, i32 } @test_frexp_f32_i32(float %a) nounwind {
 ; CHECK-LABEL: test_frexp_f32_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
-; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addi r4, r1, 44
+; CHECK-NEXT:    std r0, 64(r1)
 ; CHECK-NEXT:    bl frexpf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    lwz r3, 44(r1)
@@ -242,15 +219,13 @@ define { float, i32 } @test_frexp_f32_i32(float %a) {
   ret { float, i32 } %result
 }
 
-define float @test_frexp_f32_i32_only_use_fract(float %a) {
+define float @test_frexp_f32_i32_only_use_fract(float %a) nounwind {
 ; CHECK-LABEL: test_frexp_f32_i32_only_use_fract:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
-; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addi r4, r1, 44
+; CHECK-NEXT:    std r0, 64(r1)
 ; CHECK-NEXT:    bl frexpf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 48
@@ -262,15 +237,13 @@ define float @test_frexp_f32_i32_only_use_fract(float %a) {
   ret float %result.0
 }
 
-define i32 @test_frexp_f32_i32_only_use_exp(float %a) {
+define i32 @test_frexp_f32_i32_only_use_exp(float %a) nounwind {
 ; CHECK-LABEL: test_frexp_f32_i32_only_use_exp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
-; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addi r4, r1, 44
+; CHECK-NEXT:    std r0, 64(r1)
 ; CHECK-NEXT:    bl frexpf
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    lwz r3, 44(r1)
@@ -284,32 +257,30 @@ define i32 @test_frexp_f32_i32_only_use_exp(float %a) {
 }
 
 ; FIXME
-; define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) {
+; define { <2 x float>, <2 x i32> } @test_frexp_v2f32_v2i32(<2 x float> %a) nounwind {
 ;   %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
 ;   ret { <2 x float>, <2 x i32> } %result
 ; }
 
-; define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) {
+; define <2 x float> @test_frexp_v2f32_v2i32_only_use_fract(<2 x float> %a) nounwind {
 ;   %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
 ;   %result.0 = extractvalue { <2 x float>, <2 x i32> } %result, 0
 ;   ret <2 x float> %result.0
 ; }
 
-; define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) {
+; define <2 x i32> @test_frexp_v2f32_v2i32_only_use_exp(<2 x float> %a) nounwind {
 ;   %result = call { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float> %a)
 ;   %result.1 = extractvalue { <2 x float>, <2 x i32> } %result, 1
 ;   ret <2 x i32> %result.1
 ; }
 
-define { double, i32 } @test_frexp_f64_i32(double %a) {
+define { double, i32 } @test_frexp_f64_i32(double %a) nounwind {
 ; CHECK-LABEL: test_frexp_f64_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
-; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addi r4, r1, 44
+; CHECK-NEXT:    std r0, 64(r1)
 ; CHECK-NEXT:    bl frexp
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    lwz r3, 44(r1)
@@ -321,15 +292,13 @@ define { double, i32 } @test_frexp_f64_i32(double %a) {
   ret { double, i32 } %result
 }
 
-define double @test_frexp_f64_i32_only_use_fract(double %a) {
+define double @test_frexp_f64_i32_only_use_fract(double %a) nounwind {
 ; CHECK-LABEL: test_frexp_f64_i32_only_use_fract:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
-; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addi r4, r1, 44
+; CHECK-NEXT:    std r0, 64(r1)
 ; CHECK-NEXT:    bl frexp
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    addi r1, r1, 48
@@ -341,15 +310,13 @@ define double @test_frexp_f64_i32_only_use_fract(double %a) {
   ret double %result.0
 }
 
-define i32 @test_frexp_f64_i32_only_use_exp(double %a) {
+define i32 @test_frexp_f64_i32_only_use_exp(double %a) nounwind {
 ; CHECK-LABEL: test_frexp_f64_i32_only_use_exp:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    stdu r1, -48(r1)
-; CHECK-NEXT:    std r0, 64(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 48
-; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    addi r4, r1, 44
+; CHECK-NEXT:    std r0, 64(r1)
 ; CHECK-NEXT:    bl frexp
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    lwz r3, 44(r1)
@@ -363,36 +330,36 @@ define i32 @test_frexp_f64_i32_only_use_exp(double %a) {
 }
 
 ; FIXME: Widen vector result
-; define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) {
+; define { <2 x double>, <2 x i32> } @test_frexp_v2f64_v2i32(<2 x double> %a) nounwind {
 ;   %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
 ;   ret { <2 x double>, <2 x i32> } %result
 ; }
 
-; define <2 x double> @test_frexp_v2f64_v2i32_only_use_fract(<2 x double> %a) {
+; define <2 x double> @test_frexp_v2f64_v2i32_only_use_fract(<2 x double> %a) nounwind {
 ;   %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
 ;   %result.0 = extractvalue { <2 x double>, <2 x i32> } %result, 0
 ;   ret <2 x double> %result.0
 ; }
 
-; define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) {
+; define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) nounwind {
 ;   %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
 ;   %result.1 = extractvalue { <2 x double>, <2 x i32> } %result, 1
 ;   ret <2 x i32> %result.1
 ; }
 
 ; FIXME: f128 ExpandFloatResult
-; define { ppc_fp128, i32 } @test_frexp_f128_i32(ppc_fp128 %a) {
+; define { ppc_fp128, i32 } @test_frexp_f128_i32(ppc_fp128 %a) nounwind {
 ;   %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
 ;   ret { ppc_fp128, i32 } %result
 ; }
 
-; define ppc_fp128 @test_frexp_f128_i32_only_use_fract(ppc_fp128 %a) {
+; define ppc_fp128 @test_frexp_f128_i32_only_use_fract(ppc_fp128 %a) nounwind {
 ;   %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
 ;   %result.0 = extractvalue { ppc_fp128, i32 } %result, 0
 ;   ret ppc_fp128 %result.0
 ; }
 
-; define i32 @test_frexp_f128_i32_only_use_exp(ppc_fp128 %a) {
+; define i32 @test_frexp_f128_i32_only_use_exp(ppc_fp128 %a) nounwind {
 ;   %result = call { ppc_fp128, i32 } @llvm.frexp.f128.i32(ppc_fp128 %a)
 ;   %result.0 = extractvalue { ppc_fp128, i32 } %result, 1
 ;   ret i32 %result.0
diff --git a/llvm/test/CodeGen/PowerPC/spe-vsx-incompatibility.ll b/llvm/test/CodeGen/PowerPC/spe-vsx-incompatibility.ll
new file mode 100644
index 000000000000..06c8f9a3b4bb
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/spe-vsx-incompatibility.ll
@@ -0,0 +1,8 @@
+; Adding -enable-matrix, which is disabled by default, forces the initialization
+; of the PPCSubtarget which verifies the incompatible CPU features.
+; RUN: not llc -mtriple=powerpcspe -mattr=+vsx -enable-matrix < %s 2>&1  | FileCheck %s
+
+; CHECK: SPE and traditional floating point cannot both be enabled
+define void @test() {
+    ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/stack-protector-target.ll b/llvm/test/CodeGen/PowerPC/stack-protector-target.ll
new file mode 100644
index 000000000000..03ffa0b4c142
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/stack-protector-target.ll
@@ -0,0 +1,164 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=powerpc-unknown-openbsd < %s | FileCheck -check-prefix=OPENBSD32 %s
+; RUN: llc -mtriple=powerpc64-unknown-openbsd < %s | FileCheck -check-prefix=OPENBSD64 %s
+; RUN: llc -mtriple=powerpc-unknown-linux < %s | FileCheck -check-prefix=LINUX32 %s
+; RUN: llc -mtriple=powerpc64-unknown-linux < %s | FileCheck -check-prefix=LINUX64 %s
+; RUN: llc -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck -check-prefix=AIX32 %s
+; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck -check-prefix=AIX64 %s
+
+define void @func() sspreq nounwind {
+; OPENBSD32-LABEL: func:
+; OPENBSD32:       # %bb.0:
+; OPENBSD32-NEXT:    mflr 0
+; OPENBSD32-NEXT:    stwu 1, -32(1)
+; OPENBSD32-NEXT:    stw 0, 36(1)
+; OPENBSD32-NEXT:    stw 30, 24(1) # 4-byte Folded Spill
+; OPENBSD32-NEXT:    lis 30, __guard_local@ha
+; OPENBSD32-NEXT:    lwz 3, __guard_local@l(30)
+; OPENBSD32-NEXT:    stw 3, 20(1)
+; OPENBSD32-NEXT:    addi 3, 1, 16
+; OPENBSD32-NEXT:    bl capture
+; OPENBSD32-NEXT:    lwz 3, __guard_local@l(30)
+; OPENBSD32-NEXT:    lwz 4, 20(1)
+; OPENBSD32-NEXT:    cmplw 3, 4
+; OPENBSD32-NEXT:    bne- 0, .LBB0_2
+; OPENBSD32-NEXT:  # %bb.1: # %SP_return
+; OPENBSD32-NEXT:    lwz 30, 24(1) # 4-byte Folded Reload
+; OPENBSD32-NEXT:    lwz 0, 36(1)
+; OPENBSD32-NEXT:    addi 1, 1, 32
+; OPENBSD32-NEXT:    mtlr 0
+; OPENBSD32-NEXT:    blr
+; OPENBSD32-NEXT:  .LBB0_2: # %CallStackCheckFailBlk
+; OPENBSD32-NEXT:    lis 3, .LSSH@ha
+; OPENBSD32-NEXT:    la 3, .LSSH@l(3)
+; OPENBSD32-NEXT:    bl __stack_smash_handler
+;
+; OPENBSD64-LABEL: func:
+; OPENBSD64:       # %bb.0:
+; OPENBSD64-NEXT:    mflr 0
+; OPENBSD64-NEXT:    std 30, -16(1) # 8-byte Folded Spill
+; OPENBSD64-NEXT:    stdu 1, -64(1)
+; OPENBSD64-NEXT:    std 0, 80(1)
+; OPENBSD64-NEXT:    addis 30, 2, __guard_local@toc@ha
+; OPENBSD64-NEXT:    ld 3, __guard_local@toc@l(30)
+; OPENBSD64-NEXT:    std 3, 40(1)
+; OPENBSD64-NEXT:    addi 3, 1, 36
+; OPENBSD64-NEXT:    bl capture
+; OPENBSD64-NEXT:    nop
+; OPENBSD64-NEXT:    ld 3, __guard_local@toc@l(30)
+; OPENBSD64-NEXT:    ld 4, 40(1)
+; OPENBSD64-NEXT:    cmpld 3, 4
+; OPENBSD64-NEXT:    bne- 0, .LBB0_2
+; OPENBSD64-NEXT:  # %bb.1: # %SP_return
+; OPENBSD64-NEXT:    addi 1, 1, 64
+; OPENBSD64-NEXT:    ld 0, 16(1)
+; OPENBSD64-NEXT:    mtlr 0
+; OPENBSD64-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
+; OPENBSD64-NEXT:    blr
+; OPENBSD64-NEXT:  .LBB0_2: # %CallStackCheckFailBlk
+; OPENBSD64-NEXT:    addis 3, 2, .LSSH@toc@ha
+; OPENBSD64-NEXT:    addi 3, 3, .LSSH@toc@l
+; OPENBSD64-NEXT:    bl __stack_smash_handler
+; OPENBSD64-NEXT:    nop
+;
+; LINUX32-LABEL: func:
+; LINUX32:       # %bb.0:
+; LINUX32-NEXT:    mflr 0
+; LINUX32-NEXT:    stwu 1, -16(1)
+; LINUX32-NEXT:    stw 0, 20(1)
+; LINUX32-NEXT:    lwz 3, -28680(2)
+; LINUX32-NEXT:    stw 3, 12(1)
+; LINUX32-NEXT:    addi 3, 1, 8
+; LINUX32-NEXT:    bl capture
+; LINUX32-NEXT:    lwz 3, 12(1)
+; LINUX32-NEXT:    lwz 4, -28680(2)
+; LINUX32-NEXT:    cmplw 4, 3
+; LINUX32-NEXT:    bne 0, .LBB0_2
+; LINUX32-NEXT:  # %bb.1:
+; LINUX32-NEXT:    lwz 0, 20(1)
+; LINUX32-NEXT:    addi 1, 1, 16
+; LINUX32-NEXT:    mtlr 0
+; LINUX32-NEXT:    blr
+; LINUX32-NEXT:  .LBB0_2:
+; LINUX32-NEXT:    bl __stack_chk_fail
+;
+; LINUX64-LABEL: func:
+; LINUX64:       # %bb.0:
+; LINUX64-NEXT:    mflr 0
+; LINUX64-NEXT:    stdu 1, -128(1)
+; LINUX64-NEXT:    std 0, 144(1)
+; LINUX64-NEXT:    ld 3, -28688(13)
+; LINUX64-NEXT:    std 3, 120(1)
+; LINUX64-NEXT:    addi 3, 1, 116
+; LINUX64-NEXT:    bl capture
+; LINUX64-NEXT:    nop
+; LINUX64-NEXT:    ld 3, 120(1)
+; LINUX64-NEXT:    ld 4, -28688(13)
+; LINUX64-NEXT:    cmpld 4, 3
+; LINUX64-NEXT:    bne 0, .LBB0_2
+; LINUX64-NEXT:  # %bb.1:
+; LINUX64-NEXT:    addi 1, 1, 128
+; LINUX64-NEXT:    ld 0, 16(1)
+; LINUX64-NEXT:    mtlr 0
+; LINUX64-NEXT:    blr
+; LINUX64-NEXT:  .LBB0_2:
+; LINUX64-NEXT:    bl __stack_chk_fail
+; LINUX64-NEXT:    nop
+;
+; AIX32-LABEL: func:
+; AIX32:       # %bb.0:
+; AIX32-NEXT:    mflr 0
+; AIX32-NEXT:    stwu 1, -80(1)
+; AIX32-NEXT:    stw 0, 88(1)
+; AIX32-NEXT:    stw 31, 76(1) # 4-byte Folded Spill
+; AIX32-NEXT:    lwz 31, L..C0(2) # @__ssp_canary_word
+; AIX32-NEXT:    lwz 3, 0(31)
+; AIX32-NEXT:    stw 3, 72(1)
+; AIX32-NEXT:    addi 3, 1, 68
+; AIX32-NEXT:    bl .capture[PR]
+; AIX32-NEXT:    nop
+; AIX32-NEXT:    lwz 3, 0(31)
+; AIX32-NEXT:    lwz 4, 72(1)
+; AIX32-NEXT:    cmplw 3, 4
+; AIX32-NEXT:    bne 0, L..BB0_2
+; AIX32-NEXT:  # %bb.1:
+; AIX32-NEXT:    lwz 31, 76(1) # 4-byte Folded Reload
+; AIX32-NEXT:    addi 1, 1, 80
+; AIX32-NEXT:    lwz 0, 8(1)
+; AIX32-NEXT:    mtlr 0
+; AIX32-NEXT:    blr
+; AIX32-NEXT:  L..BB0_2:
+; AIX32-NEXT:    bl .__stack_chk_fail[PR]
+; AIX32-NEXT:    nop
+;
+; AIX64-LABEL: func:
+; AIX64:       # %bb.0:
+; AIX64-NEXT:    mflr 0
+; AIX64-NEXT:    stdu 1, -144(1)
+; AIX64-NEXT:    std 0, 160(1)
+; AIX64-NEXT:    std 31, 136(1) # 8-byte Folded Spill
+; AIX64-NEXT:    ld 31, L..C0(2) # @__ssp_canary_word
+; AIX64-NEXT:    ld 3, 0(31)
+; AIX64-NEXT:    std 3, 128(1)
+; AIX64-NEXT:    addi 3, 1, 124
+; AIX64-NEXT:    bl .capture[PR]
+; AIX64-NEXT:    nop
+; AIX64-NEXT:    ld 3, 0(31)
+; AIX64-NEXT:    ld 4, 128(1)
+; AIX64-NEXT:    cmpld 3, 4
+; AIX64-NEXT:    bne 0, L..BB0_2
+; AIX64-NEXT:  # %bb.1:
+; AIX64-NEXT:    ld 31, 136(1) # 8-byte Folded Reload
+; AIX64-NEXT:    addi 1, 1, 144
+; AIX64-NEXT:    ld 0, 16(1)
+; AIX64-NEXT:    mtlr 0
+; AIX64-NEXT:    blr
+; AIX64-NEXT:  L..BB0_2:
+; AIX64-NEXT:    bl .__stack_chk_fail[PR]
+; AIX64-NEXT:    nop
+  %alloca = alloca i32, align 4
+  call void @capture(ptr %alloca)
+  ret void
+}
+
+declare void @capture(ptr)