diff options
| author | Mingming Liu <mingmingl@google.com> | 2025-09-10 15:25:31 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-10 15:25:31 -0700 |
| commit | 1417dafa1db9cb1b2b09438aa9f53ea5ab6e36e2 (patch) | |
| tree | 57f4b1f313c8cf74eed8819870f39c36ea263c68 /llvm/test/CodeGen/PowerPC | |
| parent | 898b813bc8a6d0276bf0f4769f5f2f64b34e632d (diff) | |
| parent | b8cefcb601ddaa18482555c4ff363c01a270c2fe (diff) | |
Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
27 files changed, 27881 insertions, 26927 deletions
diff --git a/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll b/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll index b7852c3c3e6e..2d8e0e869a86 100644 --- a/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll +++ b/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll @@ -19,51 +19,53 @@ define signext i32 @main() nounwind { ; CHECK-NEXT: addi 3, 1, 46 ; CHECK-NEXT: lharx 4, 0, 3 ; CHECK-NEXT: cmplwi 4, 33059 -; CHECK-NEXT: bne 0, .LBB0_4 +; CHECK-NEXT: bne- 0, .LBB0_4 ; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore ; CHECK-NEXT: sync ; CHECK-NEXT: li 4, 234 -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB0_2: # %cmpxchg.trystore ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 4, 0, 3 -; CHECK-NEXT: beq 0, .LBB0_7 +; CHECK-NEXT: beq+ 0, .LBB0_5 ; CHECK-NEXT: # %bb.3: # %cmpxchg.releasedload ; CHECK-NEXT: # ; CHECK-NEXT: lharx 5, 0, 3 ; CHECK-NEXT: cmplwi 5, 33059 -; CHECK-NEXT: beq 0, .LBB0_2 +; CHECK-NEXT: beq+ 0, .LBB0_2 ; CHECK-NEXT: .LBB0_4: # %cmpxchg.nostore ; CHECK-NEXT: lwsync -; CHECK-NEXT: b .LBB0_8 -; CHECK-NEXT: .LBB0_5: # %L.B0000 +; CHECK-NEXT: crxor 20, 20, 20 +; CHECK-NEXT: b .LBB0_6 +; CHECK-NEXT: .LBB0_5: # %cmpxchg.success +; CHECK-NEXT: lwsync +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: .LBB0_6: # %cmpxchg.end +; CHECK-NEXT: bc 4, 20, .LBB0_9 +; CHECK-NEXT: # %bb.7: # %L.B0000 ; CHECK-NEXT: lhz 3, 46(1) ; CHECK-NEXT: cmplwi 3, 234 -; CHECK-NEXT: bne 0, .LBB0_9 -; CHECK-NEXT: # %bb.6: # %L.B0001 +; CHECK-NEXT: bne 0, .LBB0_10 +; CHECK-NEXT: # %bb.8: # %L.B0001 ; CHECK-NEXT: addis 3, 2, .L_MergedGlobals@toc@ha ; CHECK-NEXT: addi 3, 3, .L_MergedGlobals@toc@l ; CHECK-NEXT: bl puts ; CHECK-NEXT: nop ; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: b .LBB0_11 -; CHECK-NEXT: .LBB0_7: # %cmpxchg.success -; CHECK-NEXT: lwsync -; CHECK-NEXT: b .LBB0_5 -; CHECK-NEXT: .LBB0_8: # %L.B0003 +; CHECK-NEXT: b .LBB0_12 +; CHECK-NEXT: .LBB0_9: # %L.B0003 ; CHECK-NEXT: addis 3, 2, .L_MergedGlobals@toc@ha ; CHECK-NEXT: addi 3, 3, .L_MergedGlobals@toc@l ; CHECK-NEXT: addi 3, 3, 16 -; CHECK-NEXT: b .LBB0_10 -; CHECK-NEXT: .LBB0_9: # %L.B0005 +; CHECK-NEXT: b .LBB0_11 +; CHECK-NEXT: .LBB0_10: # %L.B0005 ; CHECK-NEXT: addis 3, 2, .L_MergedGlobals@toc@ha ; CHECK-NEXT: addi 3, 3, .L_MergedGlobals@toc@l ; CHECK-NEXT: addi 3, 3, 64 -; CHECK-NEXT: .LBB0_10: # %L.B0003 +; CHECK-NEXT: .LBB0_11: # %L.B0003 ; CHECK-NEXT: bl puts ; CHECK-NEXT: nop ; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: .LBB0_11: # %L.B0003 +; CHECK-NEXT: .LBB0_12: # %L.B0003 ; CHECK-NEXT: addi 1, 1, 48 ; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: mtlr 0 @@ -83,7 +85,7 @@ define signext i32 @main() nounwind { ; CHECK-P7-NEXT: srw 6, 5, 4 ; CHECK-P7-NEXT: clrlwi 6, 6, 16 ; CHECK-P7-NEXT: cmplwi 6, 33059 -; CHECK-P7-NEXT: bne 0, .LBB0_4 +; CHECK-P7-NEXT: bne- 0, .LBB0_4 ; CHECK-P7-NEXT: # %bb.1: # %cmpxchg.fencedstore ; CHECK-P7-NEXT: lis 6, 0 ; CHECK-P7-NEXT: li 7, 234 @@ -92,51 +94,53 @@ define signext i32 @main() nounwind { ; CHECK-P7-NEXT: slw 7, 7, 4 ; CHECK-P7-NEXT: slw 6, 6, 4 ; CHECK-P7-NEXT: not 6, 6 -; CHECK-P7-NEXT: .p2align 4 ; CHECK-P7-NEXT: .LBB0_2: # %cmpxchg.trystore ; CHECK-P7-NEXT: # ; CHECK-P7-NEXT: and 5, 5, 6 ; CHECK-P7-NEXT: or 5, 5, 7 ; CHECK-P7-NEXT: stwcx. 5, 0, 3 -; CHECK-P7-NEXT: beq 0, .LBB0_7 +; CHECK-P7-NEXT: beq+ 0, .LBB0_5 ; CHECK-P7-NEXT: # %bb.3: # %cmpxchg.releasedload ; CHECK-P7-NEXT: # ; CHECK-P7-NEXT: lwarx 5, 0, 3 ; CHECK-P7-NEXT: srw 8, 5, 4 ; CHECK-P7-NEXT: clrlwi 8, 8, 16 ; CHECK-P7-NEXT: cmplwi 8, 33059 -; CHECK-P7-NEXT: beq 0, .LBB0_2 +; CHECK-P7-NEXT: beq+ 0, .LBB0_2 ; CHECK-P7-NEXT: .LBB0_4: # %cmpxchg.nostore +; CHECK-P7-NEXT: crxor 20, 20, 20 ; CHECK-P7-NEXT: lwsync -; CHECK-P7-NEXT: b .LBB0_8 -; CHECK-P7-NEXT: .LBB0_5: # %L.B0000 +; CHECK-P7-NEXT: b .LBB0_6 +; CHECK-P7-NEXT: .LBB0_5: # %cmpxchg.success +; CHECK-P7-NEXT: lwsync +; CHECK-P7-NEXT: creqv 20, 20, 20 +; CHECK-P7-NEXT: .LBB0_6: # %cmpxchg.end +; CHECK-P7-NEXT: bc 4, 20, .LBB0_9 +; CHECK-P7-NEXT: # %bb.7: # %L.B0000 ; CHECK-P7-NEXT: lhz 3, 46(1) ; CHECK-P7-NEXT: cmplwi 3, 234 -; CHECK-P7-NEXT: bne 0, .LBB0_9 -; CHECK-P7-NEXT: # %bb.6: # %L.B0001 +; CHECK-P7-NEXT: bne 0, .LBB0_10 +; CHECK-P7-NEXT: # %bb.8: # %L.B0001 ; CHECK-P7-NEXT: addis 3, 2, .L_MergedGlobals@toc@ha ; CHECK-P7-NEXT: addi 3, 3, .L_MergedGlobals@toc@l ; CHECK-P7-NEXT: bl puts ; CHECK-P7-NEXT: nop ; CHECK-P7-NEXT: li 3, 0 -; CHECK-P7-NEXT: b .LBB0_11 -; CHECK-P7-NEXT: .LBB0_7: # %cmpxchg.success -; CHECK-P7-NEXT: lwsync -; CHECK-P7-NEXT: b .LBB0_5 -; CHECK-P7-NEXT: .LBB0_8: # %L.B0003 +; CHECK-P7-NEXT: b .LBB0_12 +; CHECK-P7-NEXT: .LBB0_9: # %L.B0003 ; CHECK-P7-NEXT: addis 3, 2, .L_MergedGlobals@toc@ha ; CHECK-P7-NEXT: addi 3, 3, .L_MergedGlobals@toc@l ; CHECK-P7-NEXT: addi 3, 3, 16 -; CHECK-P7-NEXT: b .LBB0_10 -; CHECK-P7-NEXT: .LBB0_9: # %L.B0005 +; CHECK-P7-NEXT: b .LBB0_11 +; CHECK-P7-NEXT: .LBB0_10: # %L.B0005 ; CHECK-P7-NEXT: addis 3, 2, .L_MergedGlobals@toc@ha ; CHECK-P7-NEXT: addi 3, 3, .L_MergedGlobals@toc@l ; CHECK-P7-NEXT: addi 3, 3, 64 -; CHECK-P7-NEXT: .LBB0_10: # %L.B0003 +; CHECK-P7-NEXT: .LBB0_11: # %L.B0003 ; CHECK-P7-NEXT: bl puts ; CHECK-P7-NEXT: nop ; CHECK-P7-NEXT: li 3, 1 -; CHECK-P7-NEXT: .LBB0_11: # %L.B0003 +; CHECK-P7-NEXT: .LBB0_12: # %L.B0003 ; CHECK-P7-NEXT: addi 1, 1, 48 ; CHECK-P7-NEXT: ld 0, 16(1) ; CHECK-P7-NEXT: mtlr 0 diff --git a/llvm/test/CodeGen/PowerPC/all-atomics.ll b/llvm/test/CodeGen/PowerPC/all-atomics.ll index 07afea75aec6..7e892fc4ae6e 100644 --- a/llvm/test/CodeGen/PowerPC/all-atomics.ll +++ b/llvm/test/CodeGen/PowerPC/all-atomics.ll @@ -4347,19 +4347,18 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 8, sc@toc@l(4) ; CHECK-NEXT: lbarx 5, 0, 6 ; CHECK-NEXT: cmplw 5, 7 -; CHECK-NEXT: bne 0, .LBB3_4 +; CHECK-NEXT: bne- 0, .LBB3_4 ; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore276 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_2: # %cmpxchg.trystore275 ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 8, 0, 6 -; CHECK-NEXT: beq 0, .LBB3_4 +; CHECK-NEXT: beq+ 0, .LBB3_4 ; CHECK-NEXT: # %bb.3: # %cmpxchg.releasedload274 ; CHECK-NEXT: # ; CHECK-NEXT: lbarx 5, 0, 6 ; CHECK-NEXT: cmplw 5, 7 -; CHECK-NEXT: beq 0, .LBB3_2 +; CHECK-NEXT: beq+ 0, .LBB3_2 ; CHECK-NEXT: .LBB3_4: # %cmpxchg.nostore272 ; CHECK-NEXT: addi 7, 3, uc@toc@l ; CHECK-NEXT: lwsync @@ -4367,20 +4366,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 9, uc@toc@l(3) ; CHECK-NEXT: lbarx 8, 0, 7 ; CHECK-NEXT: cmplw 8, 9 -; CHECK-NEXT: bne 0, .LBB3_8 +; CHECK-NEXT: bne- 0, .LBB3_8 ; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore257 ; CHECK-NEXT: sync ; CHECK-NEXT: clrlwi 5, 5, 24 -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_6: # %cmpxchg.trystore256 ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 5, 0, 7 -; CHECK-NEXT: beq 0, .LBB3_8 +; CHECK-NEXT: beq+ 0, .LBB3_8 ; CHECK-NEXT: # %bb.7: # %cmpxchg.releasedload255 ; CHECK-NEXT: # ; CHECK-NEXT: lbarx 8, 0, 7 ; CHECK-NEXT: cmplw 8, 9 -; CHECK-NEXT: beq 0, .LBB3_6 +; CHECK-NEXT: beq+ 0, .LBB3_6 ; CHECK-NEXT: .LBB3_8: # %cmpxchg.nostore253 ; CHECK-NEXT: addis 5, 2, ss@toc@ha ; CHECK-NEXT: lwsync @@ -4390,21 +4388,20 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: addi 8, 5, ss@toc@l ; CHECK-NEXT: lharx 9, 0, 8 ; CHECK-NEXT: cmplw 9, 10 -; CHECK-NEXT: bne 0, .LBB3_12 +; CHECK-NEXT: bne- 0, .LBB3_12 ; CHECK-NEXT: # %bb.9: # %cmpxchg.fencedstore238 ; CHECK-NEXT: extsb 11, 11 ; CHECK-NEXT: sync ; CHECK-NEXT: clrlwi 11, 11, 16 -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_10: # %cmpxchg.trystore237 ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 11, 0, 8 -; CHECK-NEXT: beq 0, .LBB3_12 +; CHECK-NEXT: beq+ 0, .LBB3_12 ; CHECK-NEXT: # %bb.11: # %cmpxchg.releasedload236 ; CHECK-NEXT: # ; CHECK-NEXT: lharx 9, 0, 8 ; CHECK-NEXT: cmplw 9, 10 -; CHECK-NEXT: beq 0, .LBB3_10 +; CHECK-NEXT: beq+ 0, .LBB3_10 ; CHECK-NEXT: .LBB3_12: # %cmpxchg.nostore234 ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 9, ss@toc@l(5) @@ -4414,21 +4411,20 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: addi 9, 5, us@toc@l ; CHECK-NEXT: lharx 10, 0, 9 ; CHECK-NEXT: cmplw 10, 11 -; CHECK-NEXT: bne 0, .LBB3_16 +; CHECK-NEXT: bne- 0, .LBB3_16 ; CHECK-NEXT: # %bb.13: # %cmpxchg.fencedstore219 ; CHECK-NEXT: extsb 12, 12 ; CHECK-NEXT: sync ; CHECK-NEXT: clrlwi 12, 12, 16 -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_14: # %cmpxchg.trystore218 ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 12, 0, 9 -; CHECK-NEXT: beq 0, .LBB3_16 +; CHECK-NEXT: beq+ 0, .LBB3_16 ; CHECK-NEXT: # %bb.15: # %cmpxchg.releasedload217 ; CHECK-NEXT: # ; CHECK-NEXT: lharx 10, 0, 9 ; CHECK-NEXT: cmplw 10, 11 -; CHECK-NEXT: beq 0, .LBB3_14 +; CHECK-NEXT: beq+ 0, .LBB3_14 ; CHECK-NEXT: .LBB3_16: # %cmpxchg.nostore215 ; CHECK-NEXT: lwsync ; CHECK-NEXT: sth 10, us@toc@l(5) @@ -4438,20 +4434,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: addi 10, 5, si@toc@l ; CHECK-NEXT: lwarx 11, 0, 10 ; CHECK-NEXT: cmplw 11, 12 -; CHECK-NEXT: bne 0, .LBB3_20 +; CHECK-NEXT: bne- 0, .LBB3_20 ; CHECK-NEXT: # %bb.17: # %cmpxchg.fencedstore200 ; CHECK-NEXT: extsb 0, 0 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_18: # %cmpxchg.trystore199 ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 0, 0, 10 -; CHECK-NEXT: beq 0, .LBB3_20 +; CHECK-NEXT: beq+ 0, .LBB3_20 ; CHECK-NEXT: # %bb.19: # %cmpxchg.releasedload198 ; CHECK-NEXT: # ; CHECK-NEXT: lwarx 11, 0, 10 ; CHECK-NEXT: cmplw 11, 12 -; CHECK-NEXT: beq 0, .LBB3_18 +; CHECK-NEXT: beq+ 0, .LBB3_18 ; CHECK-NEXT: .LBB3_20: # %cmpxchg.nostore196 ; CHECK-NEXT: lwsync ; CHECK-NEXT: stw 11, si@toc@l(5) @@ -4461,20 +4456,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: addi 11, 5, ui@toc@l ; CHECK-NEXT: lwarx 12, 0, 11 ; CHECK-NEXT: cmplw 12, 0 -; CHECK-NEXT: bne 0, .LBB3_24 +; CHECK-NEXT: bne- 0, .LBB3_24 ; CHECK-NEXT: # %bb.21: # %cmpxchg.fencedstore181 ; CHECK-NEXT: extsb 30, 30 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_22: # %cmpxchg.trystore180 ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 30, 0, 11 -; CHECK-NEXT: beq 0, .LBB3_24 +; CHECK-NEXT: beq+ 0, .LBB3_24 ; CHECK-NEXT: # %bb.23: # %cmpxchg.releasedload179 ; CHECK-NEXT: # ; CHECK-NEXT: lwarx 12, 0, 11 ; CHECK-NEXT: cmplw 12, 0 -; CHECK-NEXT: beq 0, .LBB3_22 +; CHECK-NEXT: beq+ 0, .LBB3_22 ; CHECK-NEXT: .LBB3_24: # %cmpxchg.nostore177 ; CHECK-NEXT: addis 30, 2, sll@toc@ha ; CHECK-NEXT: lwsync @@ -4484,20 +4478,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: addi 12, 30, sll@toc@l ; CHECK-NEXT: ldarx 0, 0, 12 ; CHECK-NEXT: cmpld 0, 29 -; CHECK-NEXT: bne 0, .LBB3_28 +; CHECK-NEXT: bne- 0, .LBB3_28 ; CHECK-NEXT: # %bb.25: # %cmpxchg.fencedstore162 ; CHECK-NEXT: extsb 28, 28 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_26: # %cmpxchg.trystore161 ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 28, 0, 12 -; CHECK-NEXT: beq 0, .LBB3_28 +; CHECK-NEXT: beq+ 0, .LBB3_28 ; CHECK-NEXT: # %bb.27: # %cmpxchg.releasedload160 ; CHECK-NEXT: # ; CHECK-NEXT: ldarx 0, 0, 12 ; CHECK-NEXT: cmpld 0, 29 -; CHECK-NEXT: beq 0, .LBB3_26 +; CHECK-NEXT: beq+ 0, .LBB3_26 ; CHECK-NEXT: .LBB3_28: # %cmpxchg.nostore158 ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 0, sll@toc@l(30) @@ -4507,20 +4500,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: addi 0, 30, ull@toc@l ; CHECK-NEXT: ldarx 29, 0, 0 ; CHECK-NEXT: cmpld 29, 28 -; CHECK-NEXT: bne 0, .LBB3_32 +; CHECK-NEXT: bne- 0, .LBB3_32 ; CHECK-NEXT: # %bb.29: # %cmpxchg.fencedstore143 ; CHECK-NEXT: extsb 27, 27 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_30: # %cmpxchg.trystore142 ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 27, 0, 0 -; CHECK-NEXT: beq 0, .LBB3_32 +; CHECK-NEXT: beq+ 0, .LBB3_32 ; CHECK-NEXT: # %bb.31: # %cmpxchg.releasedload141 ; CHECK-NEXT: # ; CHECK-NEXT: ldarx 29, 0, 0 ; CHECK-NEXT: cmpld 29, 28 -; CHECK-NEXT: beq 0, .LBB3_30 +; CHECK-NEXT: beq+ 0, .LBB3_30 ; CHECK-NEXT: .LBB3_32: # %cmpxchg.nostore139 ; CHECK-NEXT: lwsync ; CHECK-NEXT: std 29, ull@toc@l(30) @@ -4528,19 +4520,18 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 29, sc@toc@l(4) ; CHECK-NEXT: lbarx 28, 0, 6 ; CHECK-NEXT: cmplw 28, 30 -; CHECK-NEXT: bne 0, .LBB3_36 +; CHECK-NEXT: bne- 0, .LBB3_36 ; CHECK-NEXT: # %bb.33: # %cmpxchg.fencedstore124 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_34: # %cmpxchg.trystore123 ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 29, 0, 6 -; CHECK-NEXT: beq 0, .LBB3_37 +; CHECK-NEXT: beq+ 0, .LBB3_37 ; CHECK-NEXT: # %bb.35: # %cmpxchg.releasedload122 ; CHECK-NEXT: # ; CHECK-NEXT: lbarx 28, 0, 6 ; CHECK-NEXT: cmplw 28, 30 -; CHECK-NEXT: beq 0, .LBB3_34 +; CHECK-NEXT: beq+ 0, .LBB3_34 ; CHECK-NEXT: .LBB3_36: # %cmpxchg.nostore120 ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4557,19 +4548,18 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 6, uc@toc@l(3) ; CHECK-NEXT: lbarx 29, 0, 7 ; CHECK-NEXT: cmplw 29, 6 -; CHECK-NEXT: bne 0, .LBB3_42 +; CHECK-NEXT: bne- 0, .LBB3_42 ; CHECK-NEXT: # %bb.39: # %cmpxchg.fencedstore105 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_40: # %cmpxchg.trystore104 ; CHECK-NEXT: # ; CHECK-NEXT: stbcx. 30, 0, 7 -; CHECK-NEXT: beq 0, .LBB3_43 +; CHECK-NEXT: beq+ 0, .LBB3_43 ; CHECK-NEXT: # %bb.41: # %cmpxchg.releasedload103 ; CHECK-NEXT: # ; CHECK-NEXT: lbarx 29, 0, 7 ; CHECK-NEXT: cmplw 29, 6 -; CHECK-NEXT: beq 0, .LBB3_40 +; CHECK-NEXT: beq+ 0, .LBB3_40 ; CHECK-NEXT: .LBB3_42: # %cmpxchg.nostore101 ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4586,21 +4576,20 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 6, uc@toc@l(3) ; CHECK-NEXT: lharx 30, 0, 8 ; CHECK-NEXT: cmplw 30, 6 -; CHECK-NEXT: bne 0, .LBB3_48 +; CHECK-NEXT: bne- 0, .LBB3_48 ; CHECK-NEXT: # %bb.45: # %cmpxchg.fencedstore86 ; CHECK-NEXT: extsb 7, 7 ; CHECK-NEXT: sync ; CHECK-NEXT: clrlwi 7, 7, 16 -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_46: # %cmpxchg.trystore85 ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 7, 0, 8 -; CHECK-NEXT: beq 0, .LBB3_49 +; CHECK-NEXT: beq+ 0, .LBB3_49 ; CHECK-NEXT: # %bb.47: # %cmpxchg.releasedload84 ; CHECK-NEXT: # ; CHECK-NEXT: lharx 30, 0, 8 ; CHECK-NEXT: cmplw 30, 6 -; CHECK-NEXT: beq 0, .LBB3_46 +; CHECK-NEXT: beq+ 0, .LBB3_46 ; CHECK-NEXT: .LBB3_48: # %cmpxchg.nostore82 ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4617,21 +4606,20 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 6, uc@toc@l(3) ; CHECK-NEXT: lharx 8, 0, 9 ; CHECK-NEXT: cmplw 8, 6 -; CHECK-NEXT: bne 0, .LBB3_54 +; CHECK-NEXT: bne- 0, .LBB3_54 ; CHECK-NEXT: # %bb.51: # %cmpxchg.fencedstore67 ; CHECK-NEXT: extsb 7, 7 ; CHECK-NEXT: sync ; CHECK-NEXT: clrlwi 7, 7, 16 -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_52: # %cmpxchg.trystore66 ; CHECK-NEXT: # ; CHECK-NEXT: sthcx. 7, 0, 9 -; CHECK-NEXT: beq 0, .LBB3_55 +; CHECK-NEXT: beq+ 0, .LBB3_55 ; CHECK-NEXT: # %bb.53: # %cmpxchg.releasedload65 ; CHECK-NEXT: # ; CHECK-NEXT: lharx 8, 0, 9 ; CHECK-NEXT: cmplw 8, 6 -; CHECK-NEXT: beq 0, .LBB3_52 +; CHECK-NEXT: beq+ 0, .LBB3_52 ; CHECK-NEXT: .LBB3_54: # %cmpxchg.nostore63 ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4648,20 +4636,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 6, uc@toc@l(3) ; CHECK-NEXT: lwarx 8, 0, 10 ; CHECK-NEXT: cmplw 8, 6 -; CHECK-NEXT: bne 0, .LBB3_60 +; CHECK-NEXT: bne- 0, .LBB3_60 ; CHECK-NEXT: # %bb.57: # %cmpxchg.fencedstore48 ; CHECK-NEXT: extsb 7, 7 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_58: # %cmpxchg.trystore47 ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 7, 0, 10 -; CHECK-NEXT: beq 0, .LBB3_61 +; CHECK-NEXT: beq+ 0, .LBB3_61 ; CHECK-NEXT: # %bb.59: # %cmpxchg.releasedload46 ; CHECK-NEXT: # ; CHECK-NEXT: lwarx 8, 0, 10 ; CHECK-NEXT: cmplw 8, 6 -; CHECK-NEXT: beq 0, .LBB3_58 +; CHECK-NEXT: beq+ 0, .LBB3_58 ; CHECK-NEXT: .LBB3_60: # %cmpxchg.nostore44 ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4678,20 +4665,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 6, uc@toc@l(3) ; CHECK-NEXT: lwarx 8, 0, 11 ; CHECK-NEXT: cmplw 8, 6 -; CHECK-NEXT: bne 0, .LBB3_66 +; CHECK-NEXT: bne- 0, .LBB3_66 ; CHECK-NEXT: # %bb.63: # %cmpxchg.fencedstore29 ; CHECK-NEXT: extsb 7, 7 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_64: # %cmpxchg.trystore28 ; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 7, 0, 11 -; CHECK-NEXT: beq 0, .LBB3_67 +; CHECK-NEXT: beq+ 0, .LBB3_67 ; CHECK-NEXT: # %bb.65: # %cmpxchg.releasedload27 ; CHECK-NEXT: # ; CHECK-NEXT: lwarx 8, 0, 11 ; CHECK-NEXT: cmplw 8, 6 -; CHECK-NEXT: beq 0, .LBB3_64 +; CHECK-NEXT: beq+ 0, .LBB3_64 ; CHECK-NEXT: .LBB3_66: # %cmpxchg.nostore25 ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4708,20 +4694,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: lbz 6, uc@toc@l(3) ; CHECK-NEXT: ldarx 8, 0, 12 ; CHECK-NEXT: cmpld 8, 6 -; CHECK-NEXT: bne 0, .LBB3_72 +; CHECK-NEXT: bne- 0, .LBB3_72 ; CHECK-NEXT: # %bb.69: # %cmpxchg.fencedstore10 ; CHECK-NEXT: extsb 7, 7 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_70: # %cmpxchg.trystore9 ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 7, 0, 12 -; CHECK-NEXT: beq 0, .LBB3_73 +; CHECK-NEXT: beq+ 0, .LBB3_73 ; CHECK-NEXT: # %bb.71: # %cmpxchg.releasedload8 ; CHECK-NEXT: # ; CHECK-NEXT: ldarx 8, 0, 12 ; CHECK-NEXT: cmpld 8, 6 -; CHECK-NEXT: beq 0, .LBB3_70 +; CHECK-NEXT: beq+ 0, .LBB3_70 ; CHECK-NEXT: .LBB3_72: # %cmpxchg.nostore6 ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4738,20 +4723,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; CHECK-NEXT: stw 6, ui@toc@l(5) ; CHECK-NEXT: ldarx 6, 0, 0 ; CHECK-NEXT: cmpld 6, 3 -; CHECK-NEXT: bne 0, .LBB3_78 +; CHECK-NEXT: bne- 0, .LBB3_78 ; CHECK-NEXT: # %bb.75: # %cmpxchg.fencedstore ; CHECK-NEXT: extsb 4, 4 ; CHECK-NEXT: sync -; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .LBB3_76: # %cmpxchg.trystore ; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 4, 0, 0 -; CHECK-NEXT: beq 0, .LBB3_79 +; CHECK-NEXT: beq+ 0, .LBB3_79 ; CHECK-NEXT: # %bb.77: # %cmpxchg.releasedload ; CHECK-NEXT: # ; CHECK-NEXT: ldarx 6, 0, 0 ; CHECK-NEXT: cmpld 6, 3 -; CHECK-NEXT: beq 0, .LBB3_76 +; CHECK-NEXT: beq+ 0, .LBB3_76 ; CHECK-NEXT: .LBB3_78: # %cmpxchg.nostore ; CHECK-NEXT: lwsync ; CHECK-NEXT: crxor 20, 20, 20 @@ -4807,24 +4791,23 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 6, 3, 26 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 4 -; AIX32-NEXT: bne 0, L..BB3_4 +; AIX32-NEXT: bne- 0, L..BB3_4 ; AIX32-NEXT: # %bb.1: # %cmpxchg.fencedstore289 ; AIX32-NEXT: sync ; AIX32-NEXT: slw 5, 5, 26 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_2: # %cmpxchg.trystore288 ; AIX32-NEXT: # ; AIX32-NEXT: and 6, 3, 25 ; AIX32-NEXT: or 6, 6, 5 ; AIX32-NEXT: stwcx. 6, 0, 27 -; AIX32-NEXT: beq 0, L..BB3_4 +; AIX32-NEXT: beq+ 0, L..BB3_4 ; AIX32-NEXT: # %bb.3: # %cmpxchg.releasedload287 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 3, 0, 27 ; AIX32-NEXT: srw 6, 3, 26 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 4 -; AIX32-NEXT: beq 0, L..BB3_2 +; AIX32-NEXT: beq+ 0, L..BB3_2 ; AIX32-NEXT: L..BB3_4: # %cmpxchg.nostore285 ; AIX32-NEXT: not 4, 30 ; AIX32-NEXT: srw 5, 3, 26 @@ -4840,25 +4823,24 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 6, 4, 23 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: bne 0, L..BB3_8 +; AIX32-NEXT: bne- 0, L..BB3_8 ; AIX32-NEXT: # %bb.5: # %cmpxchg.fencedstore256 ; AIX32-NEXT: clrlwi 5, 5, 24 ; AIX32-NEXT: sync ; AIX32-NEXT: slw 5, 5, 23 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_6: # %cmpxchg.trystore255 ; AIX32-NEXT: # ; AIX32-NEXT: and 6, 4, 22 ; AIX32-NEXT: or 6, 6, 5 ; AIX32-NEXT: stwcx. 6, 0, 24 -; AIX32-NEXT: beq 0, L..BB3_8 +; AIX32-NEXT: beq+ 0, L..BB3_8 ; AIX32-NEXT: # %bb.7: # %cmpxchg.releasedload254 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 4, 0, 24 ; AIX32-NEXT: srw 6, 4, 23 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: beq 0, L..BB3_6 +; AIX32-NEXT: beq+ 0, L..BB3_6 ; AIX32-NEXT: L..BB3_8: # %cmpxchg.nostore252 ; AIX32-NEXT: srw 4, 4, 23 ; AIX32-NEXT: lwsync @@ -4878,26 +4860,25 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 8, 5, 20 ; AIX32-NEXT: clrlwi 8, 8, 16 ; AIX32-NEXT: cmplw 8, 6 -; AIX32-NEXT: bne 0, L..BB3_12 +; AIX32-NEXT: bne- 0, L..BB3_12 ; AIX32-NEXT: # %bb.9: # %cmpxchg.fencedstore223 ; AIX32-NEXT: extsb 7, 7 ; AIX32-NEXT: sync ; AIX32-NEXT: clrlwi 7, 7, 16 ; AIX32-NEXT: slw 7, 7, 20 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_10: # %cmpxchg.trystore222 ; AIX32-NEXT: # ; AIX32-NEXT: and 8, 5, 19 ; AIX32-NEXT: or 8, 8, 7 ; AIX32-NEXT: stwcx. 8, 0, 21 -; AIX32-NEXT: beq 0, L..BB3_12 +; AIX32-NEXT: beq+ 0, L..BB3_12 ; AIX32-NEXT: # %bb.11: # %cmpxchg.releasedload221 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 5, 0, 21 ; AIX32-NEXT: srw 8, 5, 20 ; AIX32-NEXT: clrlwi 8, 8, 16 ; AIX32-NEXT: cmplw 8, 6 -; AIX32-NEXT: beq 0, L..BB3_10 +; AIX32-NEXT: beq+ 0, L..BB3_10 ; AIX32-NEXT: L..BB3_12: # %cmpxchg.nostore219 ; AIX32-NEXT: srw 5, 5, 20 ; AIX32-NEXT: lwsync @@ -4915,26 +4896,25 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 7, 3, 17 ; AIX32-NEXT: clrlwi 7, 7, 16 ; AIX32-NEXT: cmplw 7, 5 -; AIX32-NEXT: bne 0, L..BB3_16 +; AIX32-NEXT: bne- 0, L..BB3_16 ; AIX32-NEXT: # %bb.13: # %cmpxchg.fencedstore190 ; AIX32-NEXT: extsb 6, 6 ; AIX32-NEXT: sync ; AIX32-NEXT: clrlwi 6, 6, 16 ; AIX32-NEXT: slw 6, 6, 17 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_14: # %cmpxchg.trystore189 ; AIX32-NEXT: # ; AIX32-NEXT: and 7, 3, 16 ; AIX32-NEXT: or 7, 7, 6 ; AIX32-NEXT: stwcx. 7, 0, 18 -; AIX32-NEXT: beq 0, L..BB3_16 +; AIX32-NEXT: beq+ 0, L..BB3_16 ; AIX32-NEXT: # %bb.15: # %cmpxchg.releasedload188 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 3, 0, 18 ; AIX32-NEXT: srw 7, 3, 17 ; AIX32-NEXT: clrlwi 7, 7, 16 ; AIX32-NEXT: cmplw 7, 5 -; AIX32-NEXT: beq 0, L..BB3_14 +; AIX32-NEXT: beq+ 0, L..BB3_14 ; AIX32-NEXT: L..BB3_16: # %cmpxchg.nostore186 ; AIX32-NEXT: srw 3, 3, 17 ; AIX32-NEXT: lwsync @@ -4944,20 +4924,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: lbz 4, 0(30) ; AIX32-NEXT: lwarx 3, 0, 15 ; AIX32-NEXT: cmplw 3, 4 -; AIX32-NEXT: bne 0, L..BB3_20 +; AIX32-NEXT: bne- 0, L..BB3_20 ; AIX32-NEXT: # %bb.17: # %cmpxchg.fencedstore171 ; AIX32-NEXT: extsb 5, 5 ; AIX32-NEXT: sync -; AIX32-NEXT: .align 5 ; AIX32-NEXT: L..BB3_18: # %cmpxchg.trystore170 ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 5, 0, 15 -; AIX32-NEXT: beq 0, L..BB3_20 +; AIX32-NEXT: beq+ 0, L..BB3_20 ; AIX32-NEXT: # %bb.19: # %cmpxchg.releasedload169 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 3, 0, 15 ; AIX32-NEXT: cmplw 3, 4 -; AIX32-NEXT: beq 0, L..BB3_18 +; AIX32-NEXT: beq+ 0, L..BB3_18 ; AIX32-NEXT: L..BB3_20: # %cmpxchg.nostore167 ; AIX32-NEXT: lwsync ; AIX32-NEXT: lwz 28, L..C5(2) # @ui @@ -4966,20 +4945,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: lbz 5, 0(29) ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: cmplw 3, 4 -; AIX32-NEXT: bne 0, L..BB3_24 +; AIX32-NEXT: bne- 0, L..BB3_24 ; AIX32-NEXT: # %bb.21: # %cmpxchg.fencedstore152 ; AIX32-NEXT: extsb 5, 5 ; AIX32-NEXT: sync -; AIX32-NEXT: .align 5 ; AIX32-NEXT: L..BB3_22: # %cmpxchg.trystore151 ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 5, 0, 28 -; AIX32-NEXT: beq 0, L..BB3_24 +; AIX32-NEXT: beq+ 0, L..BB3_24 ; AIX32-NEXT: # %bb.23: # %cmpxchg.releasedload150 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 3, 0, 28 ; AIX32-NEXT: cmplw 3, 4 -; AIX32-NEXT: beq 0, L..BB3_22 +; AIX32-NEXT: beq+ 0, L..BB3_22 ; AIX32-NEXT: L..BB3_24: # %cmpxchg.nostore148 ; AIX32-NEXT: lwsync ; AIX32-NEXT: stw 3, 0(28) @@ -5024,24 +5002,23 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 6, 4, 26 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: bne 0, L..BB3_28 +; AIX32-NEXT: bne- 0, L..BB3_28 ; AIX32-NEXT: # %bb.25: # %cmpxchg.fencedstore119 ; AIX32-NEXT: sync ; AIX32-NEXT: slw 5, 5, 26 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_26: # %cmpxchg.trystore118 ; AIX32-NEXT: # ; AIX32-NEXT: and 4, 4, 25 ; AIX32-NEXT: or 4, 4, 5 ; AIX32-NEXT: stwcx. 4, 0, 27 -; AIX32-NEXT: beq 0, L..BB3_29 +; AIX32-NEXT: beq+ 0, L..BB3_29 ; AIX32-NEXT: # %bb.27: # %cmpxchg.releasedload117 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 4, 0, 27 ; AIX32-NEXT: srw 6, 4, 26 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: beq 0, L..BB3_26 +; AIX32-NEXT: beq+ 0, L..BB3_26 ; AIX32-NEXT: L..BB3_28: # %cmpxchg.nostore115 ; AIX32-NEXT: crxor 20, 20, 20 ; AIX32-NEXT: lwsync @@ -5060,24 +5037,23 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 6, 4, 23 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: bne 0, L..BB3_34 +; AIX32-NEXT: bne- 0, L..BB3_34 ; AIX32-NEXT: # %bb.31: # %cmpxchg.fencedstore86 ; AIX32-NEXT: sync ; AIX32-NEXT: slw 5, 5, 23 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_32: # %cmpxchg.trystore85 ; AIX32-NEXT: # ; AIX32-NEXT: and 4, 4, 22 ; AIX32-NEXT: or 4, 4, 5 ; AIX32-NEXT: stwcx. 4, 0, 24 -; AIX32-NEXT: beq 0, L..BB3_35 +; AIX32-NEXT: beq+ 0, L..BB3_35 ; AIX32-NEXT: # %bb.33: # %cmpxchg.releasedload84 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 4, 0, 24 ; AIX32-NEXT: srw 6, 4, 23 ; AIX32-NEXT: clrlwi 6, 6, 24 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: beq 0, L..BB3_32 +; AIX32-NEXT: beq+ 0, L..BB3_32 ; AIX32-NEXT: L..BB3_34: # %cmpxchg.nostore82 ; AIX32-NEXT: crxor 20, 20, 20 ; AIX32-NEXT: lwsync @@ -5096,26 +5072,25 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 6, 4, 20 ; AIX32-NEXT: clrlwi 6, 6, 16 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: bne 0, L..BB3_40 +; AIX32-NEXT: bne- 0, L..BB3_40 ; AIX32-NEXT: # %bb.37: # %cmpxchg.fencedstore53 ; AIX32-NEXT: extsb 5, 5 ; AIX32-NEXT: sync ; AIX32-NEXT: clrlwi 5, 5, 16 ; AIX32-NEXT: slw 5, 5, 20 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_38: # %cmpxchg.trystore52 ; AIX32-NEXT: # ; AIX32-NEXT: and 4, 4, 19 ; AIX32-NEXT: or 4, 4, 5 ; AIX32-NEXT: stwcx. 4, 0, 21 -; AIX32-NEXT: beq 0, L..BB3_41 +; AIX32-NEXT: beq+ 0, L..BB3_41 ; AIX32-NEXT: # %bb.39: # %cmpxchg.releasedload51 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 4, 0, 21 ; AIX32-NEXT: srw 6, 4, 20 ; AIX32-NEXT: clrlwi 6, 6, 16 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: beq 0, L..BB3_38 +; AIX32-NEXT: beq+ 0, L..BB3_38 ; AIX32-NEXT: L..BB3_40: # %cmpxchg.nostore49 ; AIX32-NEXT: crxor 20, 20, 20 ; AIX32-NEXT: lwsync @@ -5134,26 +5109,25 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: srw 6, 4, 17 ; AIX32-NEXT: clrlwi 6, 6, 16 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: bne 0, L..BB3_46 +; AIX32-NEXT: bne- 0, L..BB3_46 ; AIX32-NEXT: # %bb.43: # %cmpxchg.fencedstore29 ; AIX32-NEXT: extsb 5, 5 ; AIX32-NEXT: sync ; AIX32-NEXT: clrlwi 5, 5, 16 ; AIX32-NEXT: slw 5, 5, 17 -; AIX32-NEXT: .align 4 ; AIX32-NEXT: L..BB3_44: # %cmpxchg.trystore28 ; AIX32-NEXT: # ; AIX32-NEXT: and 4, 4, 16 ; AIX32-NEXT: or 4, 4, 5 ; AIX32-NEXT: stwcx. 4, 0, 18 -; AIX32-NEXT: beq 0, L..BB3_47 +; AIX32-NEXT: beq+ 0, L..BB3_47 ; AIX32-NEXT: # %bb.45: # %cmpxchg.releasedload27 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 4, 0, 18 ; AIX32-NEXT: srw 6, 4, 17 ; AIX32-NEXT: clrlwi 6, 6, 16 ; AIX32-NEXT: cmplw 6, 3 -; AIX32-NEXT: beq 0, L..BB3_44 +; AIX32-NEXT: beq+ 0, L..BB3_44 ; AIX32-NEXT: L..BB3_46: # %cmpxchg.nostore25 ; AIX32-NEXT: crxor 20, 20, 20 ; AIX32-NEXT: lwsync @@ -5170,20 +5144,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: lbz 3, 0(30) ; AIX32-NEXT: lwarx 5, 0, 15 ; AIX32-NEXT: cmplw 5, 3 -; AIX32-NEXT: bne 0, L..BB3_52 +; AIX32-NEXT: bne- 0, L..BB3_52 ; AIX32-NEXT: # %bb.49: # %cmpxchg.fencedstore10 ; AIX32-NEXT: extsb 4, 4 ; AIX32-NEXT: sync -; AIX32-NEXT: .align 5 ; AIX32-NEXT: L..BB3_50: # %cmpxchg.trystore9 ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 4, 0, 15 -; AIX32-NEXT: beq 0, L..BB3_53 +; AIX32-NEXT: beq+ 0, L..BB3_53 ; AIX32-NEXT: # %bb.51: # %cmpxchg.releasedload8 ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 5, 0, 15 ; AIX32-NEXT: cmplw 5, 3 -; AIX32-NEXT: beq 0, L..BB3_50 +; AIX32-NEXT: beq+ 0, L..BB3_50 ; AIX32-NEXT: L..BB3_52: # %cmpxchg.nostore6 ; AIX32-NEXT: crxor 20, 20, 20 ; AIX32-NEXT: lwsync @@ -5200,20 +5173,19 @@ define dso_local void @test_compare_and_swap() local_unnamed_addr #0 { ; AIX32-NEXT: lbz 3, 0(30) ; AIX32-NEXT: lwarx 5, 0, 28 ; AIX32-NEXT: cmplw 5, 3 -; AIX32-NEXT: bne 0, L..BB3_58 +; AIX32-NEXT: bne- 0, L..BB3_58 ; AIX32-NEXT: # %bb.55: # %cmpxchg.fencedstore ; AIX32-NEXT: extsb 4, 4 ; AIX32-NEXT: sync -; AIX32-NEXT: .align 5 ; AIX32-NEXT: L..BB3_56: # %cmpxchg.trystore ; AIX32-NEXT: # ; AIX32-NEXT: stwcx. 4, 0, 28 -; AIX32-NEXT: beq 0, L..BB3_59 +; AIX32-NEXT: beq+ 0, L..BB3_59 ; AIX32-NEXT: # %bb.57: # %cmpxchg.releasedload ; AIX32-NEXT: # ; AIX32-NEXT: lwarx 5, 0, 28 ; AIX32-NEXT: cmplw 5, 3 -; AIX32-NEXT: beq 0, L..BB3_56 +; AIX32-NEXT: beq+ 0, L..BB3_56 ; AIX32-NEXT: L..BB3_58: # %cmpxchg.nostore ; AIX32-NEXT: crxor 20, 20, 20 ; AIX32-NEXT: lwsync @@ -5838,21 +5810,20 @@ define dso_local i64 @cmpswplp(ptr noundef %ptr, ptr nocapture noundef readnone ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldarx 4, 0, 3 ; CHECK-NEXT: cmpld 4, 5 -; CHECK-NEXT: bne 0, .LBB6_2 +; CHECK-NEXT: bne- 0, .LBB6_3 ; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore ; CHECK-NEXT: addi 4, 5, 1 +; CHECK-NEXT: creqv 20, 20, 20 ; CHECK-NEXT: stdcx. 4, 0, 3 -; CHECK-NEXT: beq 0, .LBB6_4 -; CHECK-NEXT: .LBB6_2: # %cmpxchg.failure -; CHECK-NEXT: crxor 20, 20, 20 -; CHECK-NEXT: .LBB6_3: # %cmpxchg.end +; CHECK-NEXT: bne- 0, .LBB6_3 +; CHECK-NEXT: .LBB6_2: # %cmpxchg.end ; CHECK-NEXT: li 3, 66 ; CHECK-NEXT: li 4, 55 ; CHECK-NEXT: isel 3, 4, 3, 20 ; CHECK-NEXT: blr -; CHECK-NEXT: .LBB6_4: -; CHECK-NEXT: creqv 20, 20, 20 -; CHECK-NEXT: b .LBB6_3 +; CHECK-NEXT: .LBB6_3: # %cmpxchg.failure +; CHECK-NEXT: crxor 20, 20, 20 +; CHECK-NEXT: b .LBB6_2 ; ; AIX32-LABEL: cmpswplp: ; AIX32: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll b/llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll index 65a12a6222f2..ae071194b447 100644 --- a/llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll +++ b/llvm/test/CodeGen/PowerPC/atomic-compare-exchange-weak.ll @@ -19,13 +19,14 @@ define i32 @foo(ptr noundef %cp, ptr noundef %old, i32 noundef %c) { ; CHECK-NEXT: stw r5, -16(r1) ; CHECK-NEXT: lwarx r6, 0, r3 ; CHECK-NEXT: cmplw r6, r7 -; CHECK-NEXT: bne cr0, L..BB0_2 +; CHECK-NEXT: bne- cr0, L..BB0_5 ; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore +; CHECK-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt ; CHECK-NEXT: stwcx. r5, 0, r3 -; CHECK-NEXT: beq cr0, L..BB0_5 -; CHECK-NEXT: L..BB0_2: # %cmpxchg.failure -; CHECK-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt -; CHECK-NEXT: # %bb.3: # %cmpxchg.store_expected +; CHECK-NEXT: bne- cr0, L..BB0_5 +; CHECK-NEXT: # %bb.2: # %cmpxchg.end +; CHECK-NEXT: bc 12, 4*cr5+lt, L..BB0_4 +; CHECK-NEXT: L..BB0_3: # %cmpxchg.store_expected ; CHECK-NEXT: stw r6, 0(r4) ; CHECK-NEXT: L..BB0_4: # %cmpxchg.continue ; CHECK-NEXT: li r3, 0 @@ -33,9 +34,9 @@ define i32 @foo(ptr noundef %cp, ptr noundef %old, i32 noundef %c) { ; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt ; CHECK-NEXT: stb r3, -17(r1) ; CHECK-NEXT: blr -; CHECK-NEXT: L..BB0_5: -; CHECK-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt -; CHECK-NEXT: b L..BB0_4 +; CHECK-NEXT: L..BB0_5: # %cmpxchg.failure +; CHECK-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt +; CHECK-NEXT: b L..BB0_3 ; ; CHECK64-LABEL: foo: ; CHECK64: # %bb.0: # %entry @@ -46,13 +47,14 @@ define i32 @foo(ptr noundef %cp, ptr noundef %old, i32 noundef %c) { ; CHECK64-NEXT: stw r5, -24(r1) ; CHECK64-NEXT: lwarx r6, 0, r3 ; CHECK64-NEXT: cmplw r6, r7 -; CHECK64-NEXT: bne cr0, L..BB0_2 +; CHECK64-NEXT: bne- cr0, L..BB0_5 ; CHECK64-NEXT: # %bb.1: # %cmpxchg.fencedstore +; CHECK64-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt ; CHECK64-NEXT: stwcx. r5, 0, r3 -; CHECK64-NEXT: beq cr0, L..BB0_5 -; CHECK64-NEXT: L..BB0_2: # %cmpxchg.failure -; CHECK64-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt -; CHECK64-NEXT: # %bb.3: # %cmpxchg.store_expected +; CHECK64-NEXT: bne- cr0, L..BB0_5 +; CHECK64-NEXT: # %bb.2: # %cmpxchg.end +; CHECK64-NEXT: bc 12, 4*cr5+lt, L..BB0_4 +; CHECK64-NEXT: L..BB0_3: # %cmpxchg.store_expected ; CHECK64-NEXT: stw r6, 0(r4) ; CHECK64-NEXT: L..BB0_4: # %cmpxchg.continue ; CHECK64-NEXT: li r3, 0 @@ -63,9 +65,9 @@ define i32 @foo(ptr noundef %cp, ptr noundef %old, i32 noundef %c) { ; CHECK64-NEXT: li r3, 0 ; CHECK64-NEXT: isel r3, r4, r3, 4*cr5+lt ; CHECK64-NEXT: blr -; CHECK64-NEXT: L..BB0_5: -; CHECK64-NEXT: creqv 4*cr5+lt, 4*cr5+lt, 4*cr5+lt -; CHECK64-NEXT: b L..BB0_4 +; CHECK64-NEXT: L..BB0_5: # %cmpxchg.failure +; CHECK64-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt +; CHECK64-NEXT: b L..BB0_3 entry: %cp.addr = alloca ptr, align 4 %old.addr = alloca ptr, align 4 diff --git a/llvm/test/CodeGen/PowerPC/atomic-float.ll b/llvm/test/CodeGen/PowerPC/atomic-float.ll index 600d28936c16..8232a44c7da2 100644 --- a/llvm/test/CodeGen/PowerPC/atomic-float.ll +++ b/llvm/test/CodeGen/PowerPC/atomic-float.ll @@ -9,37 +9,36 @@ define float @test_add(ptr %ptr, float %incr) { ; CHECK-64: # %bb.0: # %entry ; CHECK-64-NEXT: sync ; CHECK-64-NEXT: lfs 0, 0(3) -; CHECK-64-NEXT: b .LBB0_3 -; CHECK-64-NEXT: .LBB0_1: # %cmpxchg.nostore -; CHECK-64-NEXT: # in Loop: Header=BB0_3 Depth=1 -; CHECK-64-NEXT: crxor 20, 20, 20 -; CHECK-64-NEXT: .LBB0_2: # %cmpxchg.end -; CHECK-64-NEXT: # in Loop: Header=BB0_3 Depth=1 -; CHECK-64-NEXT: stw 4, -12(1) -; CHECK-64-NEXT: lfs 0, -12(1) -; CHECK-64-NEXT: bc 12, 20, .LBB0_7 -; CHECK-64-NEXT: .LBB0_3: # %atomicrmw.start -; CHECK-64-NEXT: # =>This Loop Header: Depth=1 -; CHECK-64-NEXT: # Child Loop BB0_4 Depth 2 +; CHECK-64-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-64-NEXT: # =>This Loop Header: Depth=1 +; CHECK-64-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-64-NEXT: fadds 2, 0, 1 ; CHECK-64-NEXT: stfs 2, -4(1) ; CHECK-64-NEXT: stfs 0, -8(1) ; CHECK-64-NEXT: lwz 5, -4(1) ; CHECK-64-NEXT: lwz 6, -8(1) -; CHECK-64-NEXT: .LBB0_4: # %cmpxchg.start -; CHECK-64-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-64-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-64-NEXT: .LBB0_2: # %cmpxchg.start +; CHECK-64-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-64-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-64-NEXT: lwarx 4, 0, 3 -; CHECK-64-NEXT: cmplw 4, 6 -; CHECK-64-NEXT: bne 0, .LBB0_1 -; CHECK-64-NEXT: # %bb.5: # %cmpxchg.fencedstore -; CHECK-64-NEXT: # in Loop: Header=BB0_4 Depth=2 +; CHECK-64-NEXT: cmplw 4, 6 +; CHECK-64-NEXT: bne- 0, .LBB0_5 +; CHECK-64-NEXT: # %bb.3: # %cmpxchg.fencedstore +; CHECK-64-NEXT: # ; CHECK-64-NEXT: stwcx. 5, 0, 3 -; CHECK-64-NEXT: bne 0, .LBB0_4 -; CHECK-64-NEXT: # %bb.6: # in Loop: Header=BB0_3 Depth=1 ; CHECK-64-NEXT: creqv 20, 20, 20 -; CHECK-64-NEXT: b .LBB0_2 -; CHECK-64-NEXT: .LBB0_7: # %atomicrmw.end +; CHECK-64-NEXT: bne- 0, .LBB0_2 +; CHECK-64-NEXT: .LBB0_4: # %cmpxchg.end +; CHECK-64-NEXT: # +; CHECK-64-NEXT: stw 4, -12(1) +; CHECK-64-NEXT: lfs 0, -12(1) +; CHECK-64-NEXT: bc 4, 20, .LBB0_1 +; CHECK-64-NEXT: b .LBB0_6 +; CHECK-64-NEXT: .LBB0_5: # %cmpxchg.nostore +; CHECK-64-NEXT: # +; CHECK-64-NEXT: crxor 20, 20, 20 +; CHECK-64-NEXT: b .LBB0_4 +; CHECK-64-NEXT: .LBB0_6: # %atomicrmw.end ; CHECK-64-NEXT: fmr 1, 0 ; CHECK-64-NEXT: lwsync ; CHECK-64-NEXT: blr @@ -50,37 +49,36 @@ define float @test_add(ptr %ptr, float %incr) { ; CHECK-32-NEXT: .cfi_def_cfa_offset 32 ; CHECK-32-NEXT: sync ; CHECK-32-NEXT: lfs 0, 0(3) -; CHECK-32-NEXT: b .LBB0_3 -; CHECK-32-NEXT: .LBB0_1: # %cmpxchg.nostore -; CHECK-32-NEXT: # in Loop: Header=BB0_3 Depth=1 -; CHECK-32-NEXT: crxor 20, 20, 20 -; CHECK-32-NEXT: .LBB0_2: # %cmpxchg.end -; CHECK-32-NEXT: # in Loop: Header=BB0_3 Depth=1 -; CHECK-32-NEXT: stw 4, 20(1) -; CHECK-32-NEXT: lfs 0, 20(1) -; CHECK-32-NEXT: bc 12, 20, .LBB0_7 -; CHECK-32-NEXT: .LBB0_3: # %atomicrmw.start -; CHECK-32-NEXT: # =>This Loop Header: Depth=1 -; CHECK-32-NEXT: # Child Loop BB0_4 Depth 2 +; CHECK-32-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-32-NEXT: # =>This Loop Header: Depth=1 +; CHECK-32-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-32-NEXT: fadds 2, 0, 1 ; CHECK-32-NEXT: stfs 2, 28(1) ; CHECK-32-NEXT: stfs 0, 24(1) ; CHECK-32-NEXT: lwz 5, 28(1) ; CHECK-32-NEXT: lwz 6, 24(1) -; CHECK-32-NEXT: .LBB0_4: # %cmpxchg.start -; CHECK-32-NEXT: # Parent Loop BB0_3 Depth=1 -; CHECK-32-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-32-NEXT: .LBB0_2: # %cmpxchg.start +; CHECK-32-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-32-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-32-NEXT: lwarx 4, 0, 3 -; CHECK-32-NEXT: cmplw 4, 6 -; CHECK-32-NEXT: bne 0, .LBB0_1 -; CHECK-32-NEXT: # %bb.5: # %cmpxchg.fencedstore -; CHECK-32-NEXT: # in Loop: Header=BB0_4 Depth=2 +; CHECK-32-NEXT: cmplw 4, 6 +; CHECK-32-NEXT: bne- 0, .LBB0_5 +; CHECK-32-NEXT: # %bb.3: # %cmpxchg.fencedstore +; CHECK-32-NEXT: # ; CHECK-32-NEXT: stwcx. 5, 0, 3 -; CHECK-32-NEXT: bne 0, .LBB0_4 -; CHECK-32-NEXT: # %bb.6: # in Loop: Header=BB0_3 Depth=1 ; CHECK-32-NEXT: creqv 20, 20, 20 -; CHECK-32-NEXT: b .LBB0_2 -; CHECK-32-NEXT: .LBB0_7: # %atomicrmw.end +; CHECK-32-NEXT: bne- 0, .LBB0_2 +; CHECK-32-NEXT: .LBB0_4: # %cmpxchg.end +; CHECK-32-NEXT: # +; CHECK-32-NEXT: stw 4, 20(1) +; CHECK-32-NEXT: lfs 0, 20(1) +; CHECK-32-NEXT: bc 4, 20, .LBB0_1 +; CHECK-32-NEXT: b .LBB0_6 +; CHECK-32-NEXT: .LBB0_5: # %cmpxchg.nostore +; CHECK-32-NEXT: # +; CHECK-32-NEXT: crxor 20, 20, 20 +; CHECK-32-NEXT: b .LBB0_4 +; CHECK-32-NEXT: .LBB0_6: # %atomicrmw.end ; CHECK-32-NEXT: fmr 1, 0 ; CHECK-32-NEXT: lwsync ; CHECK-32-NEXT: addi 1, 1, 32 diff --git a/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll index 27a26aaca8b2..ff176c80ab34 100644 --- a/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll +++ b/llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll @@ -6,45 +6,49 @@ define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: not 3, 3 +; CHECK-NEXT: not 3, 3 ; CHECK-NEXT: li 6, 255 ; CHECK-NEXT: lwz 8, 0(5) ; CHECK-NEXT: rlwinm 3, 3, 3, 27, 28 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 7, 4, 24 -; CHECK-NEXT: b .LBB0_2 -; CHECK-NEXT: .LBB0_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: .LBB0_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB0_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 7, 4, 24 +; CHECK-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB0_4 Depth 2 ; CHECK-NEXT: srw 9, 8, 3 -; CHECK-NEXT: clrlwi 10, 9, 24 -; CHECK-NEXT: cmplw 10, 7 -; CHECK-NEXT: blt 0, .LBB0_4 -; CHECK-NEXT: # %bb.3: # in Loop: Header=BB0_2 Depth=1 -; CHECK-NEXT: sub 9, 9, 4 -; CHECK-NEXT: .LBB0_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 -; CHECK-NEXT: clrlwi 9, 9, 24 +; CHECK-NEXT: clrlwi 10, 9, 24 +; CHECK-NEXT: cmplw 10, 7 +; CHECK-NEXT: blt 0, .LBB0_3 +; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: sub 9, 9, 4 +; CHECK-NEXT: .LBB0_3: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: clrlwi 9, 9, 24 ; CHECK-NEXT: slw 9, 9, 3 ; CHECK-NEXT: and 10, 8, 6 ; CHECK-NEXT: or 10, 10, 9 -; CHECK-NEXT: .LBB0_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB0_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB0_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 9, 0, 5 -; CHECK-NEXT: cmplw 9, 8 -; CHECK-NEXT: bne 0, .LBB0_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB0_5 Depth=2 +; CHECK-NEXT: cmplw 9, 8 +; CHECK-NEXT: bne- 0, .LBB0_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 10, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB0_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: bc 4, 20, .LBB0_1 +; CHECK-NEXT: b .LBB0_8 +; CHECK-NEXT: .LBB0_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: b .LBB0_1 +; CHECK-NEXT: .LBB0_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 9, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -57,47 +61,51 @@ define i16 @atomicrmw_usub_cond_i16(ptr %ptr, i16 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: clrlwi 3, 3, 30 +; CHECK-NEXT: clrlwi 3, 3, 30 ; CHECK-NEXT: lis 6, 0 ; CHECK-NEXT: xori 3, 3, 2 ; CHECK-NEXT: lwz 8, 0(5) ; CHECK-NEXT: ori 6, 6, 65535 ; CHECK-NEXT: slwi 3, 3, 3 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 7, 4, 16 -; CHECK-NEXT: b .LBB1_2 -; CHECK-NEXT: .LBB1_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: .LBB1_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB1_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 7, 4, 16 +; CHECK-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB1_4 Depth 2 ; CHECK-NEXT: srw 9, 8, 3 -; CHECK-NEXT: clrlwi 10, 9, 16 -; CHECK-NEXT: cmplw 10, 7 -; CHECK-NEXT: blt 0, .LBB1_4 -; CHECK-NEXT: # %bb.3: # in Loop: Header=BB1_2 Depth=1 -; CHECK-NEXT: sub 9, 9, 4 -; CHECK-NEXT: .LBB1_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 -; CHECK-NEXT: clrlwi 9, 9, 16 +; CHECK-NEXT: clrlwi 10, 9, 16 +; CHECK-NEXT: cmplw 10, 7 +; CHECK-NEXT: blt 0, .LBB1_3 +; CHECK-NEXT: # %bb.2: +; CHECK-NEXT: sub 9, 9, 4 +; CHECK-NEXT: .LBB1_3: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: clrlwi 9, 9, 16 ; CHECK-NEXT: slw 9, 9, 3 ; CHECK-NEXT: and 10, 8, 6 ; CHECK-NEXT: or 10, 10, 9 -; CHECK-NEXT: .LBB1_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB1_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB1_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB1_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 9, 0, 5 -; CHECK-NEXT: cmplw 9, 8 -; CHECK-NEXT: bne 0, .LBB1_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=2 +; CHECK-NEXT: cmplw 9, 8 +; CHECK-NEXT: bne- 0, .LBB1_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 10, 0, 5 -; CHECK-NEXT: bne 0, .LBB1_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB1_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: bc 4, 20, .LBB1_1 +; CHECK-NEXT: b .LBB1_8 +; CHECK-NEXT: .LBB1_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: b .LBB1_1 +; CHECK-NEXT: .LBB1_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 9, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -110,34 +118,38 @@ define i32 @atomicrmw_usub_cond_i32(ptr %ptr, i32 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: lwz 6, 0(3) -; CHECK-NEXT: b .LBB2_2 -; CHECK-NEXT: .LBB2_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB2_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB2_5 Depth 2 -; CHECK-NEXT: cmplw 6, 4 -; CHECK-NEXT: bge 0, .LBB2_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: mr 7, 6 -; CHECK-NEXT: b .LBB2_5 -; CHECK-NEXT: .LBB2_4: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: sub 7, 6, 4 -; CHECK-NEXT: .LBB2_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB2_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB2_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB2_4 Depth 2 +; CHECK-NEXT: cmplw 6, 4 +; CHECK-NEXT: bge 0, .LBB2_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 6 +; CHECK-NEXT: b .LBB2_4 +; CHECK-NEXT: .LBB2_3: +; CHECK-NEXT: sub 7, 6, 4 +; CHECK-NEXT: .LBB2_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB2_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 5, 0, 3 -; CHECK-NEXT: cmplw 5, 6 -; CHECK-NEXT: bne 0, .LBB2_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB2_5 Depth=2 +; CHECK-NEXT: cmplw 5, 6 +; CHECK-NEXT: bne- 0, .LBB2_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB2_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB2_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB2_1 +; CHECK-NEXT: b .LBB2_8 +; CHECK-NEXT: .LBB2_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB2_1 +; CHECK-NEXT: .LBB2_8: # %atomicrmw.end ; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -150,34 +162,38 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: ld 6, 0(3) -; CHECK-NEXT: b .LBB3_2 -; CHECK-NEXT: .LBB3_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB3_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB3_5 Depth 2 -; CHECK-NEXT: cmpld 6, 4 -; CHECK-NEXT: bge 0, .LBB3_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 -; CHECK-NEXT: mr 7, 6 -; CHECK-NEXT: b .LBB3_5 -; CHECK-NEXT: .LBB3_4: # in Loop: Header=BB3_2 Depth=1 -; CHECK-NEXT: sub 7, 6, 4 -; CHECK-NEXT: .LBB3_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB3_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB3_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB3_4 Depth 2 +; CHECK-NEXT: cmpld 6, 4 +; CHECK-NEXT: bge 0, .LBB3_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 6 +; CHECK-NEXT: b .LBB3_4 +; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: sub 7, 6, 4 +; CHECK-NEXT: .LBB3_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB3_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ldarx 5, 0, 3 -; CHECK-NEXT: cmpld 5, 6 -; CHECK-NEXT: bne 0, .LBB3_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB3_5 Depth=2 +; CHECK-NEXT: cmpld 5, 6 +; CHECK-NEXT: bne- 0, .LBB3_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB3_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB3_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB3_1 +; CHECK-NEXT: b .LBB3_8 +; CHECK-NEXT: .LBB3_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB3_1 +; CHECK-NEXT: .LBB3_8: # %atomicrmw.end ; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -190,47 +206,51 @@ define i8 @atomicrmw_usub_sat_i8(ptr %ptr, i8 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: not 3, 3 +; CHECK-NEXT: not 3, 3 ; CHECK-NEXT: li 6, 255 ; CHECK-NEXT: lwz 7, 0(5) ; CHECK-NEXT: rlwinm 3, 3, 3, 27, 28 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 4, 4, 24 -; CHECK-NEXT: b .LBB4_2 -; CHECK-NEXT: .LBB4_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: .LBB4_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB4_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 4, 4, 24 +; CHECK-NEXT: .LBB4_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB4_4 Depth 2 ; CHECK-NEXT: srw 8, 7, 3 -; CHECK-NEXT: clrlwi 9, 8, 24 -; CHECK-NEXT: sub 8, 9, 4 -; CHECK-NEXT: cmplw 8, 9 +; CHECK-NEXT: clrlwi 9, 8, 24 +; CHECK-NEXT: sub 8, 9, 4 +; CHECK-NEXT: cmplw 8, 9 ; CHECK-NEXT: li 9, 0 -; CHECK-NEXT: bgt 0, .LBB4_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 -; CHECK-NEXT: mr 9, 8 -; CHECK-NEXT: .LBB4_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 +; CHECK-NEXT: bgt 0, .LBB4_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: mr 9, 8 +; CHECK-NEXT: .LBB4_3: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: slw 8, 9, 3 ; CHECK-NEXT: and 9, 7, 6 ; CHECK-NEXT: or 9, 9, 8 -; CHECK-NEXT: .LBB4_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB4_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB4_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB4_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 8, 0, 5 -; CHECK-NEXT: cmplw 8, 7 -; CHECK-NEXT: bne 0, .LBB4_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB4_5 Depth=2 +; CHECK-NEXT: cmplw 8, 7 +; CHECK-NEXT: bne- 0, .LBB4_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 9, 0, 5 -; CHECK-NEXT: bne 0, .LBB4_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB4_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: bc 4, 20, .LBB4_1 +; CHECK-NEXT: b .LBB4_8 +; CHECK-NEXT: .LBB4_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: b .LBB4_1 +; CHECK-NEXT: .LBB4_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 8, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -243,49 +263,53 @@ define i16 @atomicrmw_usub_sat_i16(ptr %ptr, i16 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: clrlwi 3, 3, 30 +; CHECK-NEXT: clrlwi 3, 3, 30 ; CHECK-NEXT: lis 6, 0 ; CHECK-NEXT: xori 3, 3, 2 ; CHECK-NEXT: lwz 7, 0(5) ; CHECK-NEXT: ori 6, 6, 65535 ; CHECK-NEXT: slwi 3, 3, 3 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 4, 4, 16 -; CHECK-NEXT: b .LBB5_2 -; CHECK-NEXT: .LBB5_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: .LBB5_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB5_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 4, 4, 16 +; CHECK-NEXT: .LBB5_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB5_4 Depth 2 ; CHECK-NEXT: srw 8, 7, 3 -; CHECK-NEXT: clrlwi 9, 8, 16 -; CHECK-NEXT: sub 8, 9, 4 -; CHECK-NEXT: cmplw 8, 9 +; CHECK-NEXT: clrlwi 9, 8, 16 +; CHECK-NEXT: sub 8, 9, 4 +; CHECK-NEXT: cmplw 8, 9 ; CHECK-NEXT: li 9, 0 -; CHECK-NEXT: bgt 0, .LBB5_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 -; CHECK-NEXT: mr 9, 8 -; CHECK-NEXT: .LBB5_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: bgt 0, .LBB5_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: mr 9, 8 +; CHECK-NEXT: .LBB5_3: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: slw 8, 9, 3 ; CHECK-NEXT: and 9, 7, 6 ; CHECK-NEXT: or 9, 9, 8 -; CHECK-NEXT: .LBB5_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB5_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB5_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB5_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 8, 0, 5 -; CHECK-NEXT: cmplw 8, 7 -; CHECK-NEXT: bne 0, .LBB5_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB5_5 Depth=2 +; CHECK-NEXT: cmplw 8, 7 +; CHECK-NEXT: bne- 0, .LBB5_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 9, 0, 5 -; CHECK-NEXT: bne 0, .LBB5_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB5_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: bc 4, 20, .LBB5_1 +; CHECK-NEXT: b .LBB5_8 +; CHECK-NEXT: .LBB5_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: b .LBB5_1 +; CHECK-NEXT: .LBB5_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 8, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -298,33 +322,37 @@ define i32 @atomicrmw_usub_sat_i32(ptr %ptr, i32 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: lwz 6, 0(3) -; CHECK-NEXT: b .LBB6_2 -; CHECK-NEXT: .LBB6_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB6_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB6_4 Depth 2 -; CHECK-NEXT: sub 5, 6, 4 -; CHECK-NEXT: cmplw 5, 6 +; CHECK-NEXT: .LBB6_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB6_3 Depth 2 +; CHECK-NEXT: sub 5, 6, 4 +; CHECK-NEXT: cmplw 5, 6 ; CHECK-NEXT: li 7, 0 -; CHECK-NEXT: bgt 0, .LBB6_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1 -; CHECK-NEXT: mr 7, 5 -; CHECK-NEXT: .LBB6_4: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB6_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: bgt 0, .LBB6_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 5 +; CHECK-NEXT: .LBB6_3: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB6_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 5, 0, 3 -; CHECK-NEXT: cmplw 5, 6 -; CHECK-NEXT: bne 0, .LBB6_1 -; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB6_4 Depth=2 +; CHECK-NEXT: cmplw 5, 6 +; CHECK-NEXT: bne- 0, .LBB6_6 +; CHECK-NEXT: # %bb.4: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB6_4 -; CHECK-NEXT: # %bb.6: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.7: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB6_3 +; CHECK-NEXT: # %bb.5: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB6_1 +; CHECK-NEXT: b .LBB6_7 +; CHECK-NEXT: .LBB6_6: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB6_1 +; CHECK-NEXT: .LBB6_7: # %atomicrmw.end ; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -337,33 +365,37 @@ define i64 @atomicrmw_usub_sat_i64(ptr %ptr, i64 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: ld 6, 0(3) -; CHECK-NEXT: b .LBB7_2 -; CHECK-NEXT: .LBB7_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB7_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB7_4 Depth 2 -; CHECK-NEXT: subc 5, 6, 4 +; CHECK-NEXT: .LBB7_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB7_3 Depth 2 +; CHECK-NEXT: subc 5, 6, 4 ; CHECK-NEXT: li 7, 0 ; CHECK-NEXT: addze. 8, 7 -; CHECK-NEXT: beq 0, .LBB7_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1 -; CHECK-NEXT: mr 7, 5 -; CHECK-NEXT: .LBB7_4: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB7_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: beq 0, .LBB7_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 5 +; CHECK-NEXT: .LBB7_3: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB7_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ldarx 5, 0, 3 -; CHECK-NEXT: cmpld 5, 6 -; CHECK-NEXT: bne 0, .LBB7_1 -; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB7_4 Depth=2 +; CHECK-NEXT: cmpld 5, 6 +; CHECK-NEXT: bne- 0, .LBB7_6 +; CHECK-NEXT: # %bb.4: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB7_4 -; CHECK-NEXT: # %bb.6: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.7: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB7_3 +; CHECK-NEXT: # %bb.5: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB7_1 +; CHECK-NEXT: b .LBB7_7 +; CHECK-NEXT: .LBB7_6: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB7_1 +; CHECK-NEXT: .LBB7_7: # %atomicrmw.end ; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll index 6ced47bd6bcb..4dc6d0ad3d5c 100644 --- a/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll @@ -6,47 +6,51 @@ define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: not 3, 3 +; CHECK-NEXT: not 3, 3 ; CHECK-NEXT: li 6, 255 ; CHECK-NEXT: lwz 7, 0(5) ; CHECK-NEXT: rlwinm 3, 3, 3, 27, 28 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 4, 4, 24 -; CHECK-NEXT: b .LBB0_2 -; CHECK-NEXT: .LBB0_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: .LBB0_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB0_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 4, 4, 24 +; CHECK-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB0_4 Depth 2 ; CHECK-NEXT: srw 8, 7, 3 -; CHECK-NEXT: clrlwi 9, 8, 24 -; CHECK-NEXT: cmplw 9, 4 +; CHECK-NEXT: clrlwi 9, 8, 24 +; CHECK-NEXT: cmplw 9, 4 ; CHECK-NEXT: li 9, 0 -; CHECK-NEXT: bge 0, .LBB0_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 +; CHECK-NEXT: bge 0, .LBB0_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 9, 8, 1 -; CHECK-NEXT: .LBB0_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1 -; CHECK-NEXT: clrlwi 8, 9, 24 +; CHECK-NEXT: .LBB0_3: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: clrlwi 8, 9, 24 ; CHECK-NEXT: slw 8, 8, 3 ; CHECK-NEXT: and 9, 7, 6 ; CHECK-NEXT: or 9, 9, 8 -; CHECK-NEXT: .LBB0_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB0_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB0_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 8, 0, 5 -; CHECK-NEXT: cmplw 8, 7 -; CHECK-NEXT: bne 0, .LBB0_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB0_5 Depth=2 +; CHECK-NEXT: cmplw 8, 7 +; CHECK-NEXT: bne- 0, .LBB0_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 9, 0, 5 -; CHECK-NEXT: bne 0, .LBB0_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB0_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: bc 4, 20, .LBB0_1 +; CHECK-NEXT: b .LBB0_8 +; CHECK-NEXT: .LBB0_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: b .LBB0_1 +; CHECK-NEXT: .LBB0_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 8, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -59,49 +63,53 @@ define i16 @atomicrmw_uinc_wrap_i16(ptr %ptr, i16 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: clrlwi 3, 3, 30 +; CHECK-NEXT: clrlwi 3, 3, 30 ; CHECK-NEXT: lis 6, 0 ; CHECK-NEXT: xori 3, 3, 2 ; CHECK-NEXT: lwz 7, 0(5) ; CHECK-NEXT: ori 6, 6, 65535 ; CHECK-NEXT: slwi 3, 3, 3 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 4, 4, 16 -; CHECK-NEXT: b .LBB1_2 -; CHECK-NEXT: .LBB1_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: .LBB1_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB1_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 4, 4, 16 +; CHECK-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB1_4 Depth 2 ; CHECK-NEXT: srw 8, 7, 3 -; CHECK-NEXT: clrlwi 9, 8, 16 -; CHECK-NEXT: cmplw 9, 4 +; CHECK-NEXT: clrlwi 9, 8, 16 +; CHECK-NEXT: cmplw 9, 4 ; CHECK-NEXT: li 9, 0 -; CHECK-NEXT: bge 0, .LBB1_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 +; CHECK-NEXT: bge 0, .LBB1_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 9, 8, 1 -; CHECK-NEXT: .LBB1_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1 -; CHECK-NEXT: clrlwi 8, 9, 16 +; CHECK-NEXT: .LBB1_3: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: clrlwi 8, 9, 16 ; CHECK-NEXT: slw 8, 8, 3 ; CHECK-NEXT: and 9, 7, 6 ; CHECK-NEXT: or 9, 9, 8 -; CHECK-NEXT: .LBB1_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB1_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB1_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB1_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 8, 0, 5 -; CHECK-NEXT: cmplw 8, 7 -; CHECK-NEXT: bne 0, .LBB1_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB1_5 Depth=2 +; CHECK-NEXT: cmplw 8, 7 +; CHECK-NEXT: bne- 0, .LBB1_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 9, 0, 5 -; CHECK-NEXT: bne 0, .LBB1_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 7, 8 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB1_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: bc 4, 20, .LBB1_1 +; CHECK-NEXT: b .LBB1_8 +; CHECK-NEXT: .LBB1_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 7, 8 +; CHECK-NEXT: b .LBB1_1 +; CHECK-NEXT: .LBB1_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 8, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -114,32 +122,36 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: lwz 6, 0(3) -; CHECK-NEXT: b .LBB2_2 -; CHECK-NEXT: .LBB2_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB2_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB2_4 Depth 2 -; CHECK-NEXT: cmplw 6, 4 +; CHECK-NEXT: .LBB2_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB2_3 Depth 2 +; CHECK-NEXT: cmplw 6, 4 ; CHECK-NEXT: li 7, 0 -; CHECK-NEXT: bge 0, .LBB2_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 +; CHECK-NEXT: bge 0, .LBB2_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 7, 6, 1 -; CHECK-NEXT: .LBB2_4: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB2_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB2_3: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB2_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 5, 0, 3 -; CHECK-NEXT: cmplw 5, 6 -; CHECK-NEXT: bne 0, .LBB2_1 -; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB2_4 Depth=2 +; CHECK-NEXT: cmplw 5, 6 +; CHECK-NEXT: bne- 0, .LBB2_6 +; CHECK-NEXT: # %bb.4: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB2_4 -; CHECK-NEXT: # %bb.6: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.7: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB2_3 +; CHECK-NEXT: # %bb.5: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB2_1 +; CHECK-NEXT: b .LBB2_7 +; CHECK-NEXT: .LBB2_6: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB2_1 +; CHECK-NEXT: .LBB2_7: # %atomicrmw.end ; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -152,32 +164,36 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: ld 6, 0(3) -; CHECK-NEXT: b .LBB3_2 -; CHECK-NEXT: .LBB3_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB3_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB3_4 Depth 2 -; CHECK-NEXT: cmpld 6, 4 +; CHECK-NEXT: .LBB3_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB3_3 Depth 2 +; CHECK-NEXT: cmpld 6, 4 ; CHECK-NEXT: li 7, 0 -; CHECK-NEXT: bge 0, .LBB3_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1 +; CHECK-NEXT: bge 0, .LBB3_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 7, 6, 1 -; CHECK-NEXT: .LBB3_4: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB3_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB3_3: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB3_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ldarx 5, 0, 3 -; CHECK-NEXT: cmpld 5, 6 -; CHECK-NEXT: bne 0, .LBB3_1 -; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB3_4 Depth=2 +; CHECK-NEXT: cmpld 5, 6 +; CHECK-NEXT: bne- 0, .LBB3_6 +; CHECK-NEXT: # %bb.4: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB3_4 -; CHECK-NEXT: # %bb.6: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.7: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB3_3 +; CHECK-NEXT: # %bb.5: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB3_1 +; CHECK-NEXT: b .LBB3_7 +; CHECK-NEXT: .LBB3_6: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB3_1 +; CHECK-NEXT: .LBB3_7: # %atomicrmw.end ; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -190,48 +206,52 @@ define i8 @atomicrmw_udec_wrap_i8(ptr %ptr, i8 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: not 3, 3 +; CHECK-NEXT: not 3, 3 ; CHECK-NEXT: li 6, 255 ; CHECK-NEXT: lwz 8, 0(5) ; CHECK-NEXT: rlwinm 3, 3, 3, 27, 28 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 7, 4, 24 -; CHECK-NEXT: b .LBB4_2 -; CHECK-NEXT: .LBB4_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: .LBB4_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB4_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 7, 4, 24 +; CHECK-NEXT: .LBB4_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB4_4 Depth 2 ; CHECK-NEXT: srw 9, 8, 3 ; CHECK-NEXT: andi. 10, 9, 255 ; CHECK-NEXT: cmplw 1, 10, 7 ; CHECK-NEXT: cror 20, 2, 5 -; CHECK-NEXT: mr 10, 4 -; CHECK-NEXT: bc 12, 20, .LBB4_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 +; CHECK-NEXT: mr 10, 4 +; CHECK-NEXT: bc 12, 20, .LBB4_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 10, 9, -1 -; CHECK-NEXT: .LBB4_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1 -; CHECK-NEXT: clrlwi 9, 10, 24 +; CHECK-NEXT: .LBB4_3: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: clrlwi 9, 10, 24 ; CHECK-NEXT: slw 9, 9, 3 ; CHECK-NEXT: and 10, 8, 6 ; CHECK-NEXT: or 10, 10, 9 -; CHECK-NEXT: .LBB4_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB4_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB4_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB4_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 9, 0, 5 -; CHECK-NEXT: cmplw 9, 8 -; CHECK-NEXT: bne 0, .LBB4_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB4_5 Depth=2 +; CHECK-NEXT: cmplw 9, 8 +; CHECK-NEXT: bne- 0, .LBB4_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 10, 0, 5 -; CHECK-NEXT: bne 0, .LBB4_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB4_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: bc 4, 20, .LBB4_1 +; CHECK-NEXT: b .LBB4_8 +; CHECK-NEXT: .LBB4_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: b .LBB4_1 +; CHECK-NEXT: .LBB4_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 9, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -244,50 +264,54 @@ define i16 @atomicrmw_udec_wrap_i16(ptr %ptr, i16 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: rldicr 5, 3, 0, 61 -; CHECK-NEXT: clrlwi 3, 3, 30 +; CHECK-NEXT: clrlwi 3, 3, 30 ; CHECK-NEXT: lis 6, 0 ; CHECK-NEXT: xori 3, 3, 2 ; CHECK-NEXT: lwz 8, 0(5) ; CHECK-NEXT: ori 6, 6, 65535 ; CHECK-NEXT: slwi 3, 3, 3 ; CHECK-NEXT: slw 6, 6, 3 -; CHECK-NEXT: not 6, 6 -; CHECK-NEXT: clrlwi 7, 4, 16 -; CHECK-NEXT: b .LBB5_2 -; CHECK-NEXT: .LBB5_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: .LBB5_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB5_5 Depth 2 +; CHECK-NEXT: not 6, 6 +; CHECK-NEXT: clrlwi 7, 4, 16 +; CHECK-NEXT: .LBB5_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB5_4 Depth 2 ; CHECK-NEXT: srw 9, 8, 3 ; CHECK-NEXT: andi. 10, 9, 65535 ; CHECK-NEXT: cmplw 1, 10, 7 ; CHECK-NEXT: cror 20, 2, 5 -; CHECK-NEXT: mr 10, 4 -; CHECK-NEXT: bc 12, 20, .LBB5_4 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 +; CHECK-NEXT: mr 10, 4 +; CHECK-NEXT: bc 12, 20, .LBB5_3 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 10, 9, -1 -; CHECK-NEXT: .LBB5_4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1 -; CHECK-NEXT: clrlwi 9, 10, 16 +; CHECK-NEXT: .LBB5_3: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: clrlwi 9, 10, 16 ; CHECK-NEXT: slw 9, 9, 3 ; CHECK-NEXT: and 10, 8, 6 ; CHECK-NEXT: or 10, 10, 9 -; CHECK-NEXT: .LBB5_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB5_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB5_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB5_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 9, 0, 5 -; CHECK-NEXT: cmplw 9, 8 -; CHECK-NEXT: bne 0, .LBB5_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB5_5 Depth=2 +; CHECK-NEXT: cmplw 9, 8 +; CHECK-NEXT: bne- 0, .LBB5_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 10, 0, 5 -; CHECK-NEXT: bne 0, .LBB5_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 8, 9 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB5_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: bc 4, 20, .LBB5_1 +; CHECK-NEXT: b .LBB5_8 +; CHECK-NEXT: .LBB5_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 8, 9 +; CHECK-NEXT: b .LBB5_1 +; CHECK-NEXT: .LBB5_8: # %atomicrmw.end ; CHECK-NEXT: srw 3, 9, 3 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -300,37 +324,41 @@ define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: lwz 6, 0(3) -; CHECK-NEXT: b .LBB6_2 -; CHECK-NEXT: .LBB6_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB6_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB6_5 Depth 2 -; CHECK-NEXT: cmpwi 6, 0 -; CHECK-NEXT: mr 7, 4 -; CHECK-NEXT: bc 12, 2, .LBB6_5 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1 -; CHECK-NEXT: cmplw 6, 4 -; CHECK-NEXT: mr 7, 4 -; CHECK-NEXT: bc 12, 1, .LBB6_5 -; CHECK-NEXT: # %bb.4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1 +; CHECK-NEXT: .LBB6_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB6_4 Depth 2 +; CHECK-NEXT: cmpwi 6, 0 +; CHECK-NEXT: mr 7, 4 +; CHECK-NEXT: bc 12, 2, .LBB6_4 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: cmplw 6, 4 +; CHECK-NEXT: mr 7, 4 +; CHECK-NEXT: bc 12, 1, .LBB6_4 +; CHECK-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 7, 6, -1 -; CHECK-NEXT: .LBB6_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB6_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB6_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB6_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: lwarx 5, 0, 3 -; CHECK-NEXT: cmplw 5, 6 -; CHECK-NEXT: bne 0, .LBB6_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB6_5 Depth=2 +; CHECK-NEXT: cmplw 5, 6 +; CHECK-NEXT: bne- 0, .LBB6_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB6_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB6_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB6_1 +; CHECK-NEXT: b .LBB6_8 +; CHECK-NEXT: .LBB6_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB6_1 +; CHECK-NEXT: .LBB6_8: # %atomicrmw.end ; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr @@ -343,38 +371,42 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: sync ; CHECK-NEXT: ld 6, 0(3) -; CHECK-NEXT: b .LBB7_2 -; CHECK-NEXT: .LBB7_1: # %cmpxchg.nostore -; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1 -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: .LBB7_2: # %atomicrmw.start -; CHECK-NEXT: # =>This Loop Header: Depth=1 -; CHECK-NEXT: # Child Loop BB7_5 Depth 2 -; CHECK-NEXT: cmpdi 6, 0 -; CHECK-NEXT: mr 7, 4 -; CHECK-NEXT: bc 12, 2, .LBB7_5 -; CHECK-NEXT: # %bb.3: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1 -; CHECK-NEXT: cmpld 6, 4 -; CHECK-NEXT: mr 7, 4 -; CHECK-NEXT: bc 12, 1, .LBB7_5 -; CHECK-NEXT: # %bb.4: # %atomicrmw.start -; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1 +; CHECK-NEXT: .LBB7_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB7_4 Depth 2 +; CHECK-NEXT: cmpdi 6, 0 +; CHECK-NEXT: mr 7, 4 +; CHECK-NEXT: bc 12, 2, .LBB7_4 +; CHECK-NEXT: # %bb.2: # %atomicrmw.start +; CHECK-NEXT: # +; CHECK-NEXT: cmpld 6, 4 +; CHECK-NEXT: mr 7, 4 +; CHECK-NEXT: bc 12, 1, .LBB7_4 +; CHECK-NEXT: # %bb.3: # %atomicrmw.start +; CHECK-NEXT: # ; CHECK-NEXT: addi 7, 6, -1 -; CHECK-NEXT: .LBB7_5: # %cmpxchg.start -; CHECK-NEXT: # Parent Loop BB7_2 Depth=1 -; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: .LBB7_4: # %cmpxchg.start +; CHECK-NEXT: # Parent Loop BB7_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 ; CHECK-NEXT: ldarx 5, 0, 3 -; CHECK-NEXT: cmpld 5, 6 -; CHECK-NEXT: bne 0, .LBB7_1 -; CHECK-NEXT: # %bb.6: # %cmpxchg.fencedstore -; CHECK-NEXT: # in Loop: Header=BB7_5 Depth=2 +; CHECK-NEXT: cmpld 5, 6 +; CHECK-NEXT: bne- 0, .LBB7_7 +; CHECK-NEXT: # %bb.5: # %cmpxchg.fencedstore +; CHECK-NEXT: # ; CHECK-NEXT: stdcx. 7, 0, 3 -; CHECK-NEXT: bne 0, .LBB7_5 -; CHECK-NEXT: # %bb.7: -; CHECK-NEXT: mr 6, 5 -; CHECK-NEXT: # %bb.8: # %atomicrmw.end -; CHECK-NEXT: mr 3, 5 +; CHECK-NEXT: creqv 20, 20, 20 +; CHECK-NEXT: bne- 0, .LBB7_4 +; CHECK-NEXT: # %bb.6: # %cmpxchg.end +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: bc 4, 20, .LBB7_1 +; CHECK-NEXT: b .LBB7_8 +; CHECK-NEXT: .LBB7_7: # %cmpxchg.nostore +; CHECK-NEXT: # +; CHECK-NEXT: mr 6, 5 +; CHECK-NEXT: b .LBB7_1 +; CHECK-NEXT: .LBB7_8: # %atomicrmw.end +; CHECK-NEXT: mr 3, 5 ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr %result = atomicrmw udec_wrap ptr %ptr, i64 %val seq_cst diff --git a/llvm/test/CodeGen/PowerPC/atomics-regression.ll b/llvm/test/CodeGen/PowerPC/atomics-regression.ll index 0474a479a1fe..90990bbb4124 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-regression.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-regression.ll @@ -402,16 +402,15 @@ define void @test40(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 24 ; PPC64LE-NEXT: clrlwi 4, 4, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB40_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB40_1 +; PPC64LE-NEXT: bne- 0, .LBB40_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic @@ -423,16 +422,15 @@ define void @test41(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 24 ; PPC64LE-NEXT: clrlwi 4, 4, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB41_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB41_1 +; PPC64LE-NEXT: bne- 0, .LBB41_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -445,16 +443,15 @@ define void @test42(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 24 ; PPC64LE-NEXT: clrlwi 4, 4, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB42_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB42_3 +; PPC64LE-NEXT: bne- 0, .LBB42_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB42_1 +; PPC64LE-NEXT: bne- 0, .LBB42_1 ; PPC64LE-NEXT: .LBB42_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -468,7 +465,7 @@ define void @test43(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 @@ -476,12 +473,12 @@ define void @test43(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: .LBB43_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB43_2 +; PPC64LE-NEXT: beq+ 0, .LBB43_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic ret void @@ -493,7 +490,7 @@ define void @test44(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB44_4 +; PPC64LE-NEXT: bne- 0, .LBB44_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 @@ -501,12 +498,12 @@ define void @test44(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: .LBB44_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB44_2 +; PPC64LE-NEXT: beq+ 0, .LBB44_2 ; PPC64LE-NEXT: .LBB44_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -520,23 +517,21 @@ define void @test45(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB45_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB45_5 +; PPC64LE-NEXT: beq+ 0, .LBB45_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB45_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB45_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB45_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB45_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic @@ -549,20 +544,19 @@ define void @test46(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB46_4 +; PPC64LE-NEXT: bne- 0, .LBB46_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB46_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB46_4 +; PPC64LE-NEXT: beq+ 0, .LBB46_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB46_2 +; PPC64LE-NEXT: beq+ 0, .LBB46_2 ; PPC64LE-NEXT: .LBB46_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -576,23 +570,21 @@ define void @test47(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB47_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB47_5 +; PPC64LE-NEXT: beq+ 0, .LBB47_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB47_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB47_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB47_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB47_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic @@ -605,20 +597,19 @@ define void @test48(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB48_4 +; PPC64LE-NEXT: bne- 0, .LBB48_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB48_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB48_4 +; PPC64LE-NEXT: beq+ 0, .LBB48_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB48_2 +; PPC64LE-NEXT: beq+ 0, .LBB48_2 ; PPC64LE-NEXT: .LBB48_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -632,20 +623,19 @@ define void @test49(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB49_4 +; PPC64LE-NEXT: bne- 0, .LBB49_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB49_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB49_4 +; PPC64LE-NEXT: beq+ 0, .LBB49_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB49_2 +; PPC64LE-NEXT: beq+ 0, .LBB49_2 ; PPC64LE-NEXT: .LBB49_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -658,16 +648,15 @@ define void @test50(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 16 ; PPC64LE-NEXT: clrlwi 4, 4, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB50_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB50_1 +; PPC64LE-NEXT: bne- 0, .LBB50_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic @@ -679,16 +668,15 @@ define void @test51(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 16 ; PPC64LE-NEXT: clrlwi 4, 4, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB51_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB51_1 +; PPC64LE-NEXT: bne- 0, .LBB51_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -701,16 +689,15 @@ define void @test52(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 16 ; PPC64LE-NEXT: clrlwi 4, 4, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB52_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB52_3 +; PPC64LE-NEXT: bne- 0, .LBB52_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB52_1 +; PPC64LE-NEXT: bne- 0, .LBB52_1 ; PPC64LE-NEXT: .LBB52_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -724,7 +711,7 @@ define void @test53(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 @@ -732,12 +719,12 @@ define void @test53(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: .LBB53_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB53_2 +; PPC64LE-NEXT: beq+ 0, .LBB53_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic ret void @@ -749,7 +736,7 @@ define void @test54(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB54_4 +; PPC64LE-NEXT: bne- 0, .LBB54_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 @@ -757,12 +744,12 @@ define void @test54(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: .LBB54_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB54_2 +; PPC64LE-NEXT: beq+ 0, .LBB54_2 ; PPC64LE-NEXT: .LBB54_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -776,23 +763,21 @@ define void @test55(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB55_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB55_5 +; PPC64LE-NEXT: beq+ 0, .LBB55_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB55_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB55_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB55_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB55_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic @@ -805,20 +790,19 @@ define void @test56(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB56_4 +; PPC64LE-NEXT: bne- 0, .LBB56_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB56_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB56_4 +; PPC64LE-NEXT: beq+ 0, .LBB56_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB56_2 +; PPC64LE-NEXT: beq+ 0, .LBB56_2 ; PPC64LE-NEXT: .LBB56_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -832,23 +816,21 @@ define void @test57(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB57_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB57_5 +; PPC64LE-NEXT: beq+ 0, .LBB57_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB57_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB57_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB57_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB57_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic @@ -861,20 +843,19 @@ define void @test58(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB58_4 +; PPC64LE-NEXT: bne- 0, .LBB58_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB58_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB58_4 +; PPC64LE-NEXT: beq+ 0, .LBB58_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB58_2 +; PPC64LE-NEXT: beq+ 0, .LBB58_2 ; PPC64LE-NEXT: .LBB58_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -888,20 +869,19 @@ define void @test59(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB59_4 +; PPC64LE-NEXT: bne- 0, .LBB59_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB59_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB59_4 +; PPC64LE-NEXT: beq+ 0, .LBB59_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB59_2 +; PPC64LE-NEXT: beq+ 0, .LBB59_2 ; PPC64LE-NEXT: .LBB59_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -912,16 +892,15 @@ define void @test59(ptr %ptr, i16 %cmp, i16 %val) { define void @test60(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test60: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB60_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB60_1 +; PPC64LE-NEXT: bne- 0, .LBB60_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic @@ -931,16 +910,15 @@ define void @test60(ptr %ptr, i32 %cmp, i32 %val) { define void @test61(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test61: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB61_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB61_1 +; PPC64LE-NEXT: bne- 0, .LBB61_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -951,16 +929,15 @@ define void @test61(ptr %ptr, i32 %cmp, i32 %val) { define void @test62(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test62: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB62_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB62_3 +; PPC64LE-NEXT: bne- 0, .LBB62_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB62_1 +; PPC64LE-NEXT: bne- 0, .LBB62_1 ; PPC64LE-NEXT: .LBB62_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -973,19 +950,19 @@ define void @test63(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB63_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB63_2 +; PPC64LE-NEXT: beq+ 0, .LBB63_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic ret void @@ -996,19 +973,19 @@ define void @test64(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB64_4 +; PPC64LE-NEXT: bne- 0, .LBB64_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB64_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB64_2 +; PPC64LE-NEXT: beq+ 0, .LBB64_2 ; PPC64LE-NEXT: .LBB64_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1021,22 +998,20 @@ define void @test65(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB65_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB65_5 +; PPC64LE-NEXT: beq+ 0, .LBB65_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB65_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB65_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB65_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB65_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic @@ -1048,19 +1023,18 @@ define void @test66(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB66_4 +; PPC64LE-NEXT: bne- 0, .LBB66_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB66_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB66_4 +; PPC64LE-NEXT: beq+ 0, .LBB66_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB66_2 +; PPC64LE-NEXT: beq+ 0, .LBB66_2 ; PPC64LE-NEXT: .LBB66_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1073,22 +1047,20 @@ define void @test67(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB67_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB67_5 +; PPC64LE-NEXT: beq+ 0, .LBB67_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB67_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB67_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB67_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB67_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic @@ -1100,19 +1072,18 @@ define void @test68(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB68_4 +; PPC64LE-NEXT: bne- 0, .LBB68_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB68_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB68_4 +; PPC64LE-NEXT: beq+ 0, .LBB68_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB68_2 +; PPC64LE-NEXT: beq+ 0, .LBB68_2 ; PPC64LE-NEXT: .LBB68_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1125,19 +1096,18 @@ define void @test69(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB69_4 +; PPC64LE-NEXT: bne- 0, .LBB69_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB69_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB69_4 +; PPC64LE-NEXT: beq+ 0, .LBB69_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB69_2 +; PPC64LE-NEXT: beq+ 0, .LBB69_2 ; PPC64LE-NEXT: .LBB69_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1148,16 +1118,15 @@ define void @test69(ptr %ptr, i32 %cmp, i32 %val) { define void @test70(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test70: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB70_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB70_1 +; PPC64LE-NEXT: bne- 0, .LBB70_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val monotonic monotonic @@ -1167,16 +1136,15 @@ define void @test70(ptr %ptr, i64 %cmp, i64 %val) { define void @test71(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test71: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB71_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB71_1 +; PPC64LE-NEXT: bne- 0, .LBB71_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1187,16 +1155,15 @@ define void @test71(ptr %ptr, i64 %cmp, i64 %val) { define void @test72(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test72: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB72_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB72_3 +; PPC64LE-NEXT: bne- 0, .LBB72_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB72_1 +; PPC64LE-NEXT: bne- 0, .LBB72_1 ; PPC64LE-NEXT: .LBB72_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1209,19 +1176,19 @@ define void @test73(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB73_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB73_2 +; PPC64LE-NEXT: beq+ 0, .LBB73_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release monotonic ret void @@ -1232,19 +1199,19 @@ define void @test74(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB74_4 +; PPC64LE-NEXT: bne- 0, .LBB74_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB74_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB74_2 +; PPC64LE-NEXT: beq+ 0, .LBB74_2 ; PPC64LE-NEXT: .LBB74_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1257,22 +1224,20 @@ define void @test75(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB75_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB75_5 +; PPC64LE-NEXT: beq+ 0, .LBB75_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB75_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB75_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB75_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB75_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel monotonic @@ -1284,19 +1249,18 @@ define void @test76(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB76_4 +; PPC64LE-NEXT: bne- 0, .LBB76_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB76_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB76_4 +; PPC64LE-NEXT: beq+ 0, .LBB76_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB76_2 +; PPC64LE-NEXT: beq+ 0, .LBB76_2 ; PPC64LE-NEXT: .LBB76_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1309,22 +1273,20 @@ define void @test77(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB77_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB77_5 +; PPC64LE-NEXT: beq+ 0, .LBB77_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB77_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB77_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB77_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB77_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic @@ -1336,19 +1298,18 @@ define void @test78(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB78_4 +; PPC64LE-NEXT: bne- 0, .LBB78_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB78_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB78_4 +; PPC64LE-NEXT: beq+ 0, .LBB78_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB78_2 +; PPC64LE-NEXT: beq+ 0, .LBB78_2 ; PPC64LE-NEXT: .LBB78_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1361,19 +1322,18 @@ define void @test79(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB79_4 +; PPC64LE-NEXT: bne- 0, .LBB79_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB79_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB79_4 +; PPC64LE-NEXT: beq+ 0, .LBB79_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB79_2 +; PPC64LE-NEXT: beq+ 0, .LBB79_2 ; PPC64LE-NEXT: .LBB79_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1386,16 +1346,15 @@ define void @test80(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 24 ; PPC64LE-NEXT: clrlwi 4, 4, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB80_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB80_1 +; PPC64LE-NEXT: bne- 0, .LBB80_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic @@ -1407,16 +1366,15 @@ define void @test81(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 24 ; PPC64LE-NEXT: clrlwi 4, 4, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB81_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB81_1 +; PPC64LE-NEXT: bne- 0, .LBB81_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1429,16 +1387,15 @@ define void @test82(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 24 ; PPC64LE-NEXT: clrlwi 4, 4, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB82_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB82_3 +; PPC64LE-NEXT: bne- 0, .LBB82_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB82_1 +; PPC64LE-NEXT: bne- 0, .LBB82_1 ; PPC64LE-NEXT: .LBB82_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1452,7 +1409,7 @@ define void @test83(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 @@ -1460,12 +1417,12 @@ define void @test83(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: .LBB83_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB83_2 +; PPC64LE-NEXT: beq+ 0, .LBB83_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic ret void @@ -1477,7 +1434,7 @@ define void @test84(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB84_4 +; PPC64LE-NEXT: bne- 0, .LBB84_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 @@ -1485,12 +1442,12 @@ define void @test84(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: .LBB84_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB84_2 +; PPC64LE-NEXT: beq+ 0, .LBB84_2 ; PPC64LE-NEXT: .LBB84_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1504,23 +1461,21 @@ define void @test85(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB85_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB85_5 +; PPC64LE-NEXT: beq+ 0, .LBB85_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB85_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB85_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB85_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB85_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic @@ -1533,20 +1488,19 @@ define void @test86(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB86_4 +; PPC64LE-NEXT: bne- 0, .LBB86_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB86_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB86_4 +; PPC64LE-NEXT: beq+ 0, .LBB86_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB86_2 +; PPC64LE-NEXT: beq+ 0, .LBB86_2 ; PPC64LE-NEXT: .LBB86_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1560,23 +1514,21 @@ define void @test87(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB87_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB87_5 +; PPC64LE-NEXT: beq+ 0, .LBB87_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB87_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB87_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB87_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB87_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic @@ -1589,20 +1541,19 @@ define void @test88(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB88_4 +; PPC64LE-NEXT: bne- 0, .LBB88_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB88_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB88_4 +; PPC64LE-NEXT: beq+ 0, .LBB88_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB88_2 +; PPC64LE-NEXT: beq+ 0, .LBB88_2 ; PPC64LE-NEXT: .LBB88_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1616,20 +1567,19 @@ define void @test89(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 24 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB89_4 +; PPC64LE-NEXT: bne- 0, .LBB89_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB89_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB89_4 +; PPC64LE-NEXT: beq+ 0, .LBB89_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB89_2 +; PPC64LE-NEXT: beq+ 0, .LBB89_2 ; PPC64LE-NEXT: .LBB89_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1642,16 +1592,15 @@ define void @test90(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 16 ; PPC64LE-NEXT: clrlwi 4, 4, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB90_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB90_1 +; PPC64LE-NEXT: bne- 0, .LBB90_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic @@ -1663,16 +1612,15 @@ define void @test91(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 16 ; PPC64LE-NEXT: clrlwi 4, 4, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB91_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB91_1 +; PPC64LE-NEXT: bne- 0, .LBB91_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1685,16 +1633,15 @@ define void @test92(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 16 ; PPC64LE-NEXT: clrlwi 4, 4, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB92_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB92_3 +; PPC64LE-NEXT: bne- 0, .LBB92_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB92_1 +; PPC64LE-NEXT: bne- 0, .LBB92_1 ; PPC64LE-NEXT: .LBB92_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1708,7 +1655,7 @@ define void @test93(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 @@ -1716,12 +1663,12 @@ define void @test93(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: .LBB93_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB93_2 +; PPC64LE-NEXT: beq+ 0, .LBB93_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic ret void @@ -1733,7 +1680,7 @@ define void @test94(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB94_4 +; PPC64LE-NEXT: bne- 0, .LBB94_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 @@ -1741,12 +1688,12 @@ define void @test94(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: .LBB94_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB94_2 +; PPC64LE-NEXT: beq+ 0, .LBB94_2 ; PPC64LE-NEXT: .LBB94_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1760,23 +1707,21 @@ define void @test95(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB95_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB95_5 +; PPC64LE-NEXT: beq+ 0, .LBB95_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB95_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB95_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB95_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB95_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic @@ -1789,20 +1734,19 @@ define void @test96(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB96_4 +; PPC64LE-NEXT: bne- 0, .LBB96_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB96_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB96_4 +; PPC64LE-NEXT: beq+ 0, .LBB96_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB96_2 +; PPC64LE-NEXT: beq+ 0, .LBB96_2 ; PPC64LE-NEXT: .LBB96_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1816,23 +1760,21 @@ define void @test97(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB97_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB97_5 +; PPC64LE-NEXT: beq+ 0, .LBB97_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB97_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB97_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB97_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB97_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic @@ -1845,20 +1787,19 @@ define void @test98(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB98_4 +; PPC64LE-NEXT: bne- 0, .LBB98_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB98_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB98_4 +; PPC64LE-NEXT: beq+ 0, .LBB98_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB98_2 +; PPC64LE-NEXT: beq+ 0, .LBB98_2 ; PPC64LE-NEXT: .LBB98_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1872,20 +1813,19 @@ define void @test99(ptr %ptr, i16 %cmp, i16 %val) { ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: clrlwi 4, 4, 16 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB99_4 +; PPC64LE-NEXT: bne- 0, .LBB99_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: clrlwi 5, 5, 16 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB99_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: sthcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB99_4 +; PPC64LE-NEXT: beq+ 0, .LBB99_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB99_2 +; PPC64LE-NEXT: beq+ 0, .LBB99_2 ; PPC64LE-NEXT: .LBB99_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1896,16 +1836,15 @@ define void @test99(ptr %ptr, i16 %cmp, i16 %val) { define void @test100(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test100: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB100_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB100_1 +; PPC64LE-NEXT: bne- 0, .LBB100_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic @@ -1915,16 +1854,15 @@ define void @test100(ptr %ptr, i32 %cmp, i32 %val) { define void @test101(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test101: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB101_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB101_1 +; PPC64LE-NEXT: bne- 0, .LBB101_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1935,16 +1873,15 @@ define void @test101(ptr %ptr, i32 %cmp, i32 %val) { define void @test102(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE-LABEL: test102: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB102_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB102_3 +; PPC64LE-NEXT: bne- 0, .LBB102_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB102_1 +; PPC64LE-NEXT: bne- 0, .LBB102_1 ; PPC64LE-NEXT: .LBB102_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -1957,19 +1894,19 @@ define void @test103(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB103_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB103_2 +; PPC64LE-NEXT: beq+ 0, .LBB103_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic ret void @@ -1980,19 +1917,19 @@ define void @test104(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB104_4 +; PPC64LE-NEXT: bne- 0, .LBB104_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB104_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB104_2 +; PPC64LE-NEXT: beq+ 0, .LBB104_2 ; PPC64LE-NEXT: .LBB104_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2005,22 +1942,20 @@ define void @test105(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB105_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB105_5 +; PPC64LE-NEXT: beq+ 0, .LBB105_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB105_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB105_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB105_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB105_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel monotonic @@ -2032,19 +1967,18 @@ define void @test106(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB106_4 +; PPC64LE-NEXT: bne- 0, .LBB106_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB106_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB106_4 +; PPC64LE-NEXT: beq+ 0, .LBB106_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB106_2 +; PPC64LE-NEXT: beq+ 0, .LBB106_2 ; PPC64LE-NEXT: .LBB106_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2057,22 +1991,20 @@ define void @test107(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB107_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB107_5 +; PPC64LE-NEXT: beq+ 0, .LBB107_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB107_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB107_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB107_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB107_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst monotonic @@ -2084,19 +2016,18 @@ define void @test108(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB108_4 +; PPC64LE-NEXT: bne- 0, .LBB108_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB108_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB108_4 +; PPC64LE-NEXT: beq+ 0, .LBB108_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB108_2 +; PPC64LE-NEXT: beq+ 0, .LBB108_2 ; PPC64LE-NEXT: .LBB108_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2109,19 +2040,18 @@ define void @test109(ptr %ptr, i32 %cmp, i32 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bne 0, .LBB109_4 +; PPC64LE-NEXT: bne- 0, .LBB109_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB109_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stwcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB109_4 +; PPC64LE-NEXT: beq+ 0, .LBB109_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lwarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: beq 0, .LBB109_2 +; PPC64LE-NEXT: beq+ 0, .LBB109_2 ; PPC64LE-NEXT: .LBB109_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2132,16 +2062,15 @@ define void @test109(ptr %ptr, i32 %cmp, i32 %val) { define void @test110(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test110: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB110_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB110_1 +; PPC64LE-NEXT: bne- 0, .LBB110_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic @@ -2151,16 +2080,15 @@ define void @test110(ptr %ptr, i64 %cmp, i64 %val) { define void @test111(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test111: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB111_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB111_1 +; PPC64LE-NEXT: bne- 0, .LBB111_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2171,16 +2099,15 @@ define void @test111(ptr %ptr, i64 %cmp, i64 %val) { define void @test112(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE-LABEL: test112: ; PPC64LE: # %bb.0: -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB112_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB112_3 +; PPC64LE-NEXT: bne- 0, .LBB112_3 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB112_1 +; PPC64LE-NEXT: bne- 0, .LBB112_1 ; PPC64LE-NEXT: .LBB112_3: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2193,19 +2120,19 @@ define void @test113(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB113_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB113_2 +; PPC64LE-NEXT: beq+ 0, .LBB113_2 ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic ret void @@ -2216,19 +2143,19 @@ define void @test114(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB114_4 +; PPC64LE-NEXT: bne- 0, .LBB114_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB114_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beqlr 0 +; PPC64LE-NEXT: beqlr+ 0 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB114_2 +; PPC64LE-NEXT: beq+ 0, .LBB114_2 ; PPC64LE-NEXT: .LBB114_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2241,22 +2168,20 @@ define void @test115(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB115_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB115_5 +; PPC64LE-NEXT: beq+ 0, .LBB115_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB115_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB115_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB115_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB115_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel monotonic @@ -2268,19 +2193,18 @@ define void @test116(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB116_4 +; PPC64LE-NEXT: bne- 0, .LBB116_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: lwsync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB116_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB116_4 +; PPC64LE-NEXT: beq+ 0, .LBB116_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB116_2 +; PPC64LE-NEXT: beq+ 0, .LBB116_2 ; PPC64LE-NEXT: .LBB116_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2293,22 +2217,20 @@ define void @test117(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB117_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB117_5 +; PPC64LE-NEXT: beq+ 0, .LBB117_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB117_2 -; PPC64LE-NEXT: # %bb.4: # %cmpxchg.end +; PPC64LE-NEXT: beq+ 0, .LBB117_2 ; PPC64LE-NEXT: blr -; PPC64LE-NEXT: .LBB117_5: # %cmpxchg.success +; PPC64LE-NEXT: .LBB117_4: # %cmpxchg.success ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst monotonic @@ -2320,19 +2242,18 @@ define void @test118(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB118_4 +; PPC64LE-NEXT: bne- 0, .LBB118_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB118_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB118_4 +; PPC64LE-NEXT: beq+ 0, .LBB118_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB118_2 +; PPC64LE-NEXT: beq+ 0, .LBB118_2 ; PPC64LE-NEXT: .LBB118_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr @@ -2345,19 +2266,18 @@ define void @test119(ptr %ptr, i64 %cmp, i64 %val) { ; PPC64LE: # %bb.0: # %cmpxchg.start ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: bne 0, .LBB119_4 +; PPC64LE-NEXT: bne- 0, .LBB119_4 ; PPC64LE-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64LE-NEXT: sync -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB119_2: # %cmpxchg.trystore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stdcx. 5, 0, 3 -; PPC64LE-NEXT: beq 0, .LBB119_4 +; PPC64LE-NEXT: beq+ 0, .LBB119_4 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.releasedload ; PPC64LE-NEXT: # ; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: cmpld 6, 4 -; PPC64LE-NEXT: beq 0, .LBB119_2 +; PPC64LE-NEXT: beq+ 0, .LBB119_2 ; PPC64LE-NEXT: .LBB119_4: # %cmpxchg.nostore ; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/atomics.ll b/llvm/test/CodeGen/PowerPC/atomics.ll index 40786057ead5..183c8e1323f2 100644 --- a/llvm/test/CodeGen/PowerPC/atomics.ll +++ b/llvm/test/CodeGen/PowerPC/atomics.ll @@ -138,67 +138,67 @@ define void @store_i64_seq_cst(ptr %mem) { ; Atomic CmpXchg define i8 @cas_strong_i8_sc_sc(ptr %mem) { ; PPC32-LABEL: cas_strong_i8_sc_sc: -; PPC32: # %bb.0: +; PPC32: # %bb.0: # %cmpxchg.start ; PPC32-NEXT: rlwinm r5, r3, 0, 0, 29 ; PPC32-NEXT: lwarx r4, 0, r5 -; PPC32-NEXT: not r3, r3 +; PPC32-NEXT: not r3, r3 ; PPC32-NEXT: rlwinm r3, r3, 3, 27, 28 ; PPC32-NEXT: srw r6, r4, r3 ; PPC32-NEXT: andi. r6, r6, 255 -; PPC32-NEXT: bne cr0, .LBB8_4 -; PPC32-NEXT: # %bb.1: # %cmpxchg.fencedstore +; PPC32-NEXT: bne- cr0, .LBB8_4 +; PPC32-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC32-NEXT: li r6, 255 ; PPC32-NEXT: li r7, 1 ; PPC32-NEXT: slw r6, r6, r3 -; PPC32-NEXT: not r6, r6 +; PPC32-NEXT: not r6, r6 ; PPC32-NEXT: slw r7, r7, r3 ; PPC32-NEXT: sync -; PPC32-NEXT: .LBB8_2: # %cmpxchg.trystore -; PPC32-NEXT: # =>This Inner Loop Header: Depth=1 +; PPC32-NEXT: .LBB8_2: # %cmpxchg.trystore +; PPC32-NEXT: # ; PPC32-NEXT: and r8, r4, r6 ; PPC32-NEXT: or r8, r8, r7 ; PPC32-NEXT: stwcx. r8, 0, r5 -; PPC32-NEXT: beq cr0, .LBB8_4 -; PPC32-NEXT: # %bb.3: # %cmpxchg.releasedload -; PPC32-NEXT: # in Loop: Header=BB8_2 Depth=1 +; PPC32-NEXT: beq+ cr0, .LBB8_4 +; PPC32-NEXT: # %bb.3: # %cmpxchg.releasedload +; PPC32-NEXT: # ; PPC32-NEXT: lwarx r4, 0, r5 ; PPC32-NEXT: srw r8, r4, r3 ; PPC32-NEXT: andi. r8, r8, 255 -; PPC32-NEXT: beq cr0, .LBB8_2 -; PPC32-NEXT: .LBB8_4: # %cmpxchg.nostore +; PPC32-NEXT: beq+ cr0, .LBB8_2 +; PPC32-NEXT: .LBB8_4: # %cmpxchg.nostore ; PPC32-NEXT: srw r3, r4, r3 ; PPC32-NEXT: lwsync ; PPC32-NEXT: blr ; ; PPC64-LABEL: cas_strong_i8_sc_sc: -; PPC64: # %bb.0: +; PPC64: # %bb.0: # %cmpxchg.start ; PPC64-NEXT: rldicr r5, r3, 0, 61 -; PPC64-NEXT: not r3, r3 +; PPC64-NEXT: not r3, r3 ; PPC64-NEXT: lwarx r4, 0, r5 ; PPC64-NEXT: rlwinm r3, r3, 3, 27, 28 ; PPC64-NEXT: srw r6, r4, r3 ; PPC64-NEXT: andi. r6, r6, 255 -; PPC64-NEXT: bne cr0, .LBB8_4 -; PPC64-NEXT: # %bb.1: # %cmpxchg.fencedstore +; PPC64-NEXT: bne- cr0, .LBB8_4 +; PPC64-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64-NEXT: li r6, 255 ; PPC64-NEXT: li r7, 1 ; PPC64-NEXT: slw r6, r6, r3 -; PPC64-NEXT: not r6, r6 +; PPC64-NEXT: not r6, r6 ; PPC64-NEXT: slw r7, r7, r3 ; PPC64-NEXT: sync -; PPC64-NEXT: .LBB8_2: # %cmpxchg.trystore -; PPC64-NEXT: # =>This Inner Loop Header: Depth=1 +; PPC64-NEXT: .LBB8_2: # %cmpxchg.trystore +; PPC64-NEXT: # ; PPC64-NEXT: and r8, r4, r6 ; PPC64-NEXT: or r8, r8, r7 ; PPC64-NEXT: stwcx. r8, 0, r5 -; PPC64-NEXT: beq cr0, .LBB8_4 -; PPC64-NEXT: # %bb.3: # %cmpxchg.releasedload -; PPC64-NEXT: # in Loop: Header=BB8_2 Depth=1 +; PPC64-NEXT: beq+ cr0, .LBB8_4 +; PPC64-NEXT: # %bb.3: # %cmpxchg.releasedload +; PPC64-NEXT: # ; PPC64-NEXT: lwarx r4, 0, r5 ; PPC64-NEXT: srw r8, r4, r3 ; PPC64-NEXT: andi. r8, r8, 255 -; PPC64-NEXT: beq cr0, .LBB8_2 -; PPC64-NEXT: .LBB8_4: # %cmpxchg.nostore +; PPC64-NEXT: beq+ cr0, .LBB8_2 +; PPC64-NEXT: .LBB8_4: # %cmpxchg.nostore ; PPC64-NEXT: srw r3, r4, r3 ; PPC64-NEXT: lwsync ; PPC64-NEXT: blr @@ -208,54 +208,50 @@ define i8 @cas_strong_i8_sc_sc(ptr %mem) { } define i16 @cas_weak_i16_acquire_acquire(ptr %mem) { ; PPC32-LABEL: cas_weak_i16_acquire_acquire: -; PPC32: # %bb.0: +; PPC32: # %bb.0: # %cmpxchg.start ; PPC32-NEXT: rlwinm r4, r3, 0, 0, 29 ; PPC32-NEXT: lwarx r5, 0, r4 -; PPC32-NEXT: clrlwi r3, r3, 30 +; PPC32-NEXT: clrlwi r3, r3, 30 ; PPC32-NEXT: xori r3, r3, 2 ; PPC32-NEXT: slwi r6, r3, 3 ; PPC32-NEXT: srw r3, r5, r6 ; PPC32-NEXT: andi. r7, r3, 65535 -; PPC32-NEXT: beq cr0, .LBB9_2 -; PPC32-NEXT: # %bb.1: # %cmpxchg.failure -; PPC32-NEXT: lwsync -; PPC32-NEXT: blr -; PPC32-NEXT: .LBB9_2: # %cmpxchg.fencedstore +; PPC32-NEXT: bne- cr0, .LBB9_2 +; PPC32-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC32-NEXT: lis r7, 0 ; PPC32-NEXT: ori r7, r7, 65535 ; PPC32-NEXT: slw r7, r7, r6 ; PPC32-NEXT: li r8, 1 -; PPC32-NEXT: not r7, r7 +; PPC32-NEXT: not r7, r7 ; PPC32-NEXT: slw r6, r8, r6 ; PPC32-NEXT: and r5, r5, r7 ; PPC32-NEXT: or r5, r5, r6 ; PPC32-NEXT: stwcx. r5, 0, r4 +; PPC32-NEXT: .LBB9_2: # %cmpxchg.failure ; PPC32-NEXT: lwsync ; PPC32-NEXT: blr ; ; PPC64-LABEL: cas_weak_i16_acquire_acquire: -; PPC64: # %bb.0: -; PPC64-NEXT: rldicr r4, r3, 0, 61 -; PPC64-NEXT: clrlwi r3, r3, 30 +; PPC64: # %bb.0: # %cmpxchg.start +; PPC64-NEXT: rldicr r4, r3, 0, 61 +; PPC64-NEXT: clrlwi r3, r3, 30 ; PPC64-NEXT: lwarx r5, 0, r4 ; PPC64-NEXT: xori r3, r3, 2 ; PPC64-NEXT: slwi r6, r3, 3 ; PPC64-NEXT: srw r3, r5, r6 ; PPC64-NEXT: andi. r7, r3, 65535 -; PPC64-NEXT: beq cr0, .LBB9_2 -; PPC64-NEXT: # %bb.1: # %cmpxchg.failure -; PPC64-NEXT: lwsync -; PPC64-NEXT: blr -; PPC64-NEXT: .LBB9_2: # %cmpxchg.fencedstore +; PPC64-NEXT: bne- cr0, .LBB9_2 +; PPC64-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64-NEXT: lis r7, 0 ; PPC64-NEXT: ori r7, r7, 65535 ; PPC64-NEXT: slw r7, r7, r6 ; PPC64-NEXT: li r8, 1 -; PPC64-NEXT: not r7, r7 +; PPC64-NEXT: not r7, r7 ; PPC64-NEXT: slw r6, r8, r6 ; PPC64-NEXT: and r5, r5, r7 ; PPC64-NEXT: or r5, r5, r6 ; PPC64-NEXT: stwcx. r5, 0, r4 +; PPC64-NEXT: .LBB9_2: # %cmpxchg.failure ; PPC64-NEXT: lwsync ; PPC64-NEXT: blr %val = cmpxchg weak ptr %mem, i16 0, i16 1 acquire acquire @@ -264,24 +260,24 @@ define i16 @cas_weak_i16_acquire_acquire(ptr %mem) { } define i32 @cas_strong_i32_acqrel_acquire(ptr %mem) { ; CHECK-LABEL: cas_strong_i32_acqrel_acquire: -; CHECK: # %bb.0: -; CHECK-NEXT: mr r4, r3 +; CHECK: # %bb.0: # %cmpxchg.start +; CHECK-NEXT: mr r4, r3 ; CHECK-NEXT: lwarx r3, 0, r3 -; CHECK-NEXT: cmplwi r3, 0 -; CHECK-NEXT: bne cr0, .LBB10_4 -; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore +; CHECK-NEXT: cmplwi r3, 0 +; CHECK-NEXT: bne- cr0, .LBB10_4 +; CHECK-NEXT: # %bb.1: # %cmpxchg.fencedstore ; CHECK-NEXT: li r5, 1 ; CHECK-NEXT: lwsync -; CHECK-NEXT: .LBB10_2: # %cmpxchg.trystore -; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB10_2: # %cmpxchg.trystore +; CHECK-NEXT: # ; CHECK-NEXT: stwcx. r5, 0, r4 -; CHECK-NEXT: beq cr0, .LBB10_4 -; CHECK-NEXT: # %bb.3: # %cmpxchg.releasedload -; CHECK-NEXT: # in Loop: Header=BB10_2 Depth=1 +; CHECK-NEXT: beq+ cr0, .LBB10_4 +; CHECK-NEXT: # %bb.3: # %cmpxchg.releasedload +; CHECK-NEXT: # ; CHECK-NEXT: lwarx r3, 0, r4 -; CHECK-NEXT: cmplwi r3, 0 -; CHECK-NEXT: beq cr0, .LBB10_2 -; CHECK-NEXT: .LBB10_4: # %cmpxchg.nostore +; CHECK-NEXT: cmplwi r3, 0 +; CHECK-NEXT: beq+ cr0, .LBB10_2 +; CHECK-NEXT: .LBB10_4: # %cmpxchg.nostore ; CHECK-NEXT: lwsync ; CHECK-NEXT: blr %val = cmpxchg ptr %mem, i32 0, i32 1 acq_rel acquire @@ -313,12 +309,12 @@ define i64 @cas_weak_i64_release_monotonic(ptr %mem) { ; PPC32-NEXT: blr ; ; PPC64-LABEL: cas_weak_i64_release_monotonic: -; PPC64: # %bb.0: -; PPC64-NEXT: mr r4, r3 +; PPC64: # %bb.0: # %cmpxchg.start +; PPC64-NEXT: mr r4, r3 ; PPC64-NEXT: ldarx r3, 0, r3 -; PPC64-NEXT: cmpldi r3, 0 -; PPC64-NEXT: bnelr cr0 -; PPC64-NEXT: # %bb.1: # %cmpxchg.fencedstore +; PPC64-NEXT: cmpldi r3, 0 +; PPC64-NEXT: bnelr- cr0 +; PPC64-NEXT: # %bb.1: # %cmpxchg.fencedstore ; PPC64-NEXT: li r5, 1 ; PPC64-NEXT: lwsync ; PPC64-NEXT: stdcx. r5, 0, r4 diff --git a/llvm/test/CodeGen/PowerPC/check-zero-vector.ll b/llvm/test/CodeGen/PowerPC/check-zero-vector.ll index d8e66d6500f5..0f7e0c76f8e2 100644 --- a/llvm/test/CodeGen/PowerPC/check-zero-vector.ll +++ b/llvm/test/CodeGen/PowerPC/check-zero-vector.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ -; RUN: < %s | FileCheck %s --check-prefix=POWERPC_64LE +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64LE ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \ -; RUN: < %s | FileCheck %s --check-prefix=POWERPC_64 +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc-ibm-aix \ -; RUN: < %s | FileCheck %s --check-prefix=POWERPC_32 +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_32 define i32 @test_Greater_than(ptr %colauths) { ; This testcase is for the special case of zero-vector comparisons. @@ -14,71 +14,71 @@ define i32 @test_Greater_than(ptr %colauths) { ; This pattern is expected to be optimized in a future patch. ; POWERPC_64LE-LABEL: test_Greater_than: ; POWERPC_64LE: # %bb.0: # %entry -; POWERPC_64LE-NEXT: lfd 0, 0(3) -; POWERPC_64LE-NEXT: xxlxor 35, 35, 35 -; POWERPC_64LE-NEXT: li 4, 0 -; POWERPC_64LE-NEXT: li 3, 4 -; POWERPC_64LE-NEXT: xxswapd 34, 0 -; POWERPC_64LE-NEXT: vcmpequh 2, 2, 3 -; POWERPC_64LE-NEXT: xxlnor 34, 34, 34 -; POWERPC_64LE-NEXT: vmrglh 3, 2, 2 -; POWERPC_64LE-NEXT: vextuwrx 4, 4, 2 -; POWERPC_64LE-NEXT: vextuwrx 3, 3, 3 -; POWERPC_64LE-NEXT: clrlwi 4, 4, 31 -; POWERPC_64LE-NEXT: rlwimi 4, 3, 1, 30, 30 -; POWERPC_64LE-NEXT: mfvsrwz 3, 35 -; POWERPC_64LE-NEXT: rlwimi 4, 3, 2, 29, 29 -; POWERPC_64LE-NEXT: li 3, 12 -; POWERPC_64LE-NEXT: vextuwrx 3, 3, 3 -; POWERPC_64LE-NEXT: rlwimi 4, 3, 3, 28, 28 -; POWERPC_64LE-NEXT: stb 4, -1(1) -; POWERPC_64LE-NEXT: lbz 3, -1(1) -; POWERPC_64LE-NEXT: popcntd 3, 3 +; POWERPC_64LE-NEXT: lfd f0, 0(r3) +; POWERPC_64LE-NEXT: xxlxor v3, v3, v3 +; POWERPC_64LE-NEXT: li r4, 0 +; POWERPC_64LE-NEXT: li r3, 4 +; POWERPC_64LE-NEXT: xxswapd v2, f0 +; POWERPC_64LE-NEXT: vcmpequh v2, v2, v3 +; POWERPC_64LE-NEXT: xxlnor v2, v2, v2 +; POWERPC_64LE-NEXT: vmrglh v3, v2, v2 +; POWERPC_64LE-NEXT: vextuwrx r4, r4, v2 +; POWERPC_64LE-NEXT: vextuwrx r3, r3, v3 +; POWERPC_64LE-NEXT: clrlwi r4, r4, 31 +; POWERPC_64LE-NEXT: rlwimi r4, r3, 1, 30, 30 +; POWERPC_64LE-NEXT: mfvsrwz r3, v3 +; POWERPC_64LE-NEXT: rlwimi r4, r3, 2, 29, 29 +; POWERPC_64LE-NEXT: li r3, 12 +; POWERPC_64LE-NEXT: vextuwrx r3, r3, v3 +; POWERPC_64LE-NEXT: rlwimi r4, r3, 3, 28, 28 +; POWERPC_64LE-NEXT: stb r4, -1(r1) +; POWERPC_64LE-NEXT: lbz r3, -1(r1) +; POWERPC_64LE-NEXT: popcntd r3, r3 ; POWERPC_64LE-NEXT: blr ; ; POWERPC_64-LABEL: test_Greater_than: ; POWERPC_64: # %bb.0: # %entry -; POWERPC_64-NEXT: lxsd 2, 0(3) -; POWERPC_64-NEXT: xxlxor 35, 35, 35 -; POWERPC_64-NEXT: li 4, 12 -; POWERPC_64-NEXT: li 3, 8 -; POWERPC_64-NEXT: vcmpequh 2, 2, 3 -; POWERPC_64-NEXT: xxlnor 34, 34, 34 -; POWERPC_64-NEXT: vmrghh 2, 2, 2 -; POWERPC_64-NEXT: vextuwlx 4, 4, 2 -; POWERPC_64-NEXT: vextuwlx 3, 3, 2 -; POWERPC_64-NEXT: clrlwi 4, 4, 31 -; POWERPC_64-NEXT: rlwimi 4, 3, 1, 30, 30 -; POWERPC_64-NEXT: mfvsrwz 3, 34 -; POWERPC_64-NEXT: rlwimi 4, 3, 2, 29, 29 -; POWERPC_64-NEXT: li 3, 0 -; POWERPC_64-NEXT: vextuwlx 3, 3, 2 -; POWERPC_64-NEXT: rlwimi 4, 3, 3, 28, 28 -; POWERPC_64-NEXT: stb 4, -1(1) -; POWERPC_64-NEXT: lbz 3, -1(1) -; POWERPC_64-NEXT: popcntd 3, 3 +; POWERPC_64-NEXT: lxsd v2, 0(r3) +; POWERPC_64-NEXT: xxlxor v3, v3, v3 +; POWERPC_64-NEXT: li r4, 12 +; POWERPC_64-NEXT: li r3, 8 +; POWERPC_64-NEXT: vcmpequh v2, v2, v3 +; POWERPC_64-NEXT: xxlnor v2, v2, v2 +; POWERPC_64-NEXT: vmrghh v2, v2, v2 +; POWERPC_64-NEXT: vextuwlx r4, r4, v2 +; POWERPC_64-NEXT: vextuwlx r3, r3, v2 +; POWERPC_64-NEXT: clrlwi r4, r4, 31 +; POWERPC_64-NEXT: rlwimi r4, r3, 1, 30, 30 +; POWERPC_64-NEXT: mfvsrwz r3, v2 +; POWERPC_64-NEXT: rlwimi r4, r3, 2, 29, 29 +; POWERPC_64-NEXT: li r3, 0 +; POWERPC_64-NEXT: vextuwlx r3, r3, v2 +; POWERPC_64-NEXT: rlwimi r4, r3, 3, 28, 28 +; POWERPC_64-NEXT: stb r4, -1(r1) +; POWERPC_64-NEXT: lbz r3, -1(r1) +; POWERPC_64-NEXT: popcntd r3, r3 ; POWERPC_64-NEXT: blr ; ; POWERPC_32-LABEL: test_Greater_than: ; POWERPC_32: # %bb.0: # %entry -; POWERPC_32-NEXT: li 4, 4 -; POWERPC_32-NEXT: lxvwsx 1, 0, 3 -; POWERPC_32-NEXT: xxlxor 35, 35, 35 -; POWERPC_32-NEXT: lxvwsx 0, 3, 4 -; POWERPC_32-NEXT: xxmrghw 34, 1, 0 -; POWERPC_32-NEXT: vcmpequh 2, 2, 3 -; POWERPC_32-NEXT: xxlnor 34, 34, 34 -; POWERPC_32-NEXT: vmrghh 2, 2, 2 -; POWERPC_32-NEXT: stxv 34, -32(1) -; POWERPC_32-NEXT: lwz 3, -20(1) -; POWERPC_32-NEXT: lwz 4, -24(1) -; POWERPC_32-NEXT: clrlwi 3, 3, 31 -; POWERPC_32-NEXT: rlwimi 3, 4, 1, 30, 30 -; POWERPC_32-NEXT: lwz 4, -28(1) -; POWERPC_32-NEXT: rlwimi 3, 4, 2, 29, 29 -; POWERPC_32-NEXT: lwz 4, -32(1) -; POWERPC_32-NEXT: rlwimi 3, 4, 3, 28, 28 -; POWERPC_32-NEXT: popcntw 3, 3 +; POWERPC_32-NEXT: li r4, 4 +; POWERPC_32-NEXT: lxvwsx vs1, 0, r3 +; POWERPC_32-NEXT: xxlxor v3, v3, v3 +; POWERPC_32-NEXT: lxvwsx vs0, r3, r4 +; POWERPC_32-NEXT: xxmrghw v2, vs1, vs0 +; POWERPC_32-NEXT: vcmpequh v2, v2, v3 +; POWERPC_32-NEXT: xxlnor v2, v2, v2 +; POWERPC_32-NEXT: vmrghh v2, v2, v2 +; POWERPC_32-NEXT: stxv v2, -32(r1) +; POWERPC_32-NEXT: lwz r3, -20(r1) +; POWERPC_32-NEXT: lwz r4, -24(r1) +; POWERPC_32-NEXT: clrlwi r3, r3, 31 +; POWERPC_32-NEXT: rlwimi r3, r4, 1, 30, 30 +; POWERPC_32-NEXT: lwz r4, -28(r1) +; POWERPC_32-NEXT: rlwimi r3, r4, 2, 29, 29 +; POWERPC_32-NEXT: lwz r4, -32(r1) +; POWERPC_32-NEXT: rlwimi r3, r4, 3, 28, 28 +; POWERPC_32-NEXT: popcntw r3, r3 ; POWERPC_32-NEXT: blr entry: %0 = load <4 x i16>, ptr %colauths, align 2, !tbaa !5 diff --git a/llvm/test/CodeGen/PowerPC/common-chain.ll b/llvm/test/CodeGen/PowerPC/common-chain.ll index b71a360d1be1..8283e7bac345 100644 --- a/llvm/test/CodeGen/PowerPC/common-chain.ll +++ b/llvm/test/CodeGen/PowerPC/common-chain.ll @@ -721,6 +721,13 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64 ; CHECK-LABEL: spill_reduce_succ: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: cmpdi r6, 0 +; CHECK-NEXT: ble cr0, .LBB7_9 +; CHECK-NEXT: # %bb.1: # %for.body.preheader +; CHECK-NEXT: sldi r6, r6, 2 +; CHECK-NEXT: li r11, 1 +; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill +; CHECK-NEXT: mr r26, r10 +; CHECK-NEXT: cmpdi r6, 1 ; CHECK-NEXT: std r14, -144(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r15, -136(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r16, -128(r1) # 8-byte Folded Spill @@ -733,231 +740,232 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64 ; CHECK-NEXT: std r23, -72(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r24, -64(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r25, -56(r1) # 8-byte Folded Spill -; CHECK-NEXT: std r26, -48(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r27, -40(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r28, -32(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r31, -8(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r2, -152(r1) # 8-byte Folded Spill -; CHECK-NEXT: std r9, -184(r1) # 8-byte Folded Spill -; CHECK-NEXT: std r8, -176(r1) # 8-byte Folded Spill -; CHECK-NEXT: std r7, -168(r1) # 8-byte Folded Spill -; CHECK-NEXT: std r3, -160(r1) # 8-byte Folded Spill -; CHECK-NEXT: ble cr0, .LBB7_7 -; CHECK-NEXT: # %bb.1: # %for.body.preheader -; CHECK-NEXT: sldi r6, r6, 2 -; CHECK-NEXT: li r7, 1 -; CHECK-NEXT: mr r30, r10 -; CHECK-NEXT: cmpdi r6, 1 -; CHECK-NEXT: iselgt r7, r6, r7 -; CHECK-NEXT: addi r8, r7, -1 -; CHECK-NEXT: clrldi r6, r7, 63 -; CHECK-NEXT: cmpldi r8, 3 -; CHECK-NEXT: blt cr0, .LBB7_4 +; CHECK-NEXT: iselgt r11, r6, r11 +; CHECK-NEXT: addi r12, r11, -1 +; CHECK-NEXT: cmpldi r12, 3 +; CHECK-NEXT: clrldi r6, r11, 63 +; CHECK-NEXT: blt cr0, .LBB7_5 ; CHECK-NEXT: # %bb.2: # %for.body.preheader.new -; CHECK-NEXT: ld r14, -168(r1) # 8-byte Folded Reload -; CHECK-NEXT: mulli r24, r30, 24 -; CHECK-NEXT: ld r16, -184(r1) # 8-byte Folded Reload -; CHECK-NEXT: ld r15, -176(r1) # 8-byte Folded Reload -; CHECK-NEXT: ld r3, -160(r1) # 8-byte Folded Reload -; CHECK-NEXT: rldicl r0, r7, 62, 2 -; CHECK-NEXT: sldi r11, r30, 5 -; CHECK-NEXT: sldi r19, r30, 4 -; CHECK-NEXT: sldi r7, r14, 3 -; CHECK-NEXT: add r14, r30, r14 -; CHECK-NEXT: sldi r10, r16, 3 -; CHECK-NEXT: sldi r12, r15, 3 -; CHECK-NEXT: add r16, r30, r16 -; CHECK-NEXT: add r15, r30, r15 -; CHECK-NEXT: add r27, r11, r7 -; CHECK-NEXT: add r22, r24, r7 -; CHECK-NEXT: add r17, r19, r7 -; CHECK-NEXT: sldi r2, r14, 3 -; CHECK-NEXT: add r26, r24, r10 -; CHECK-NEXT: add r25, r24, r12 -; CHECK-NEXT: add r21, r19, r10 -; CHECK-NEXT: add r20, r19, r12 -; CHECK-NEXT: add r8, r11, r10 -; CHECK-NEXT: sldi r16, r16, 3 -; CHECK-NEXT: add r29, r5, r27 -; CHECK-NEXT: add r28, r4, r27 -; CHECK-NEXT: add r27, r3, r27 -; CHECK-NEXT: add r24, r5, r22 -; CHECK-NEXT: add r23, r4, r22 -; CHECK-NEXT: add r22, r3, r22 -; CHECK-NEXT: add r19, r5, r17 -; CHECK-NEXT: add r18, r4, r17 -; CHECK-NEXT: add r17, r3, r17 -; CHECK-NEXT: add r14, r5, r2 -; CHECK-NEXT: add r31, r4, r2 -; CHECK-NEXT: add r2, r3, r2 -; CHECK-NEXT: add r9, r5, r8 -; CHECK-NEXT: add r8, r11, r12 +; CHECK-NEXT: rldicl r11, r11, 62, 2 +; CHECK-NEXT: sldi r20, r8, 3 +; CHECK-NEXT: mr r14, r7 +; CHECK-NEXT: sldi r7, r7, 3 +; CHECK-NEXT: sldi r21, r9, 3 +; CHECK-NEXT: std r3, -160(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r9, -208(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r8, -184(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r5, -200(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r4, -168(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r11, -192(r1) # 8-byte Folded Spill +; CHECK-NEXT: sldi r11, r10, 5 +; CHECK-NEXT: add r0, r11, r20 +; CHECK-NEXT: add r12, r11, r21 +; CHECK-NEXT: add r30, r5, r0 +; CHECK-NEXT: add r0, r11, r7 +; CHECK-NEXT: std r21, -216(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r20, -224(r1) # 8-byte Folded Spill +; CHECK-NEXT: add r12, r5, r12 +; CHECK-NEXT: add r29, r5, r0 +; CHECK-NEXT: add r28, r4, r0 +; CHECK-NEXT: add r27, r3, r0 +; CHECK-NEXT: mulli r0, r10, 24 +; CHECK-NEXT: std r14, -176(r1) # 8-byte Folded Spill +; CHECK-NEXT: add r26, r0, r21 +; CHECK-NEXT: add r25, r0, r20 +; CHECK-NEXT: add r0, r0, r7 +; CHECK-NEXT: add r24, r5, r0 +; CHECK-NEXT: add r23, r4, r0 +; CHECK-NEXT: add r22, r3, r0 +; CHECK-NEXT: sldi r0, r10, 4 ; CHECK-NEXT: add r26, r5, r26 ; CHECK-NEXT: add r25, r5, r25 +; CHECK-NEXT: add r21, r0, r21 +; CHECK-NEXT: add r20, r0, r20 +; CHECK-NEXT: add r0, r0, r7 +; CHECK-NEXT: add r19, r5, r0 +; CHECK-NEXT: add r18, r4, r0 +; CHECK-NEXT: add r17, r3, r0 +; CHECK-NEXT: add r0, r10, r9 ; CHECK-NEXT: add r21, r5, r21 ; CHECK-NEXT: add r20, r5, r20 -; CHECK-NEXT: add r16, r5, r16 -; CHECK-NEXT: add r8, r5, r8 -; CHECK-NEXT: rldicl r3, r0, 2, 1 -; CHECK-NEXT: addi r3, r3, -4 -; CHECK-NEXT: sub r0, r12, r7 -; CHECK-NEXT: sub r12, r10, r7 -; CHECK-NEXT: li r7, 0 -; CHECK-NEXT: mr r10, r30 -; CHECK-NEXT: sldi r15, r15, 3 -; CHECK-NEXT: add r15, r5, r15 -; CHECK-NEXT: rldicl r3, r3, 62, 2 -; CHECK-NEXT: addi r3, r3, 1 -; CHECK-NEXT: mtctr r3 +; CHECK-NEXT: sldi r0, r0, 3 +; CHECK-NEXT: add r16, r5, r0 +; CHECK-NEXT: add r0, r10, r8 +; CHECK-NEXT: sldi r0, r0, 3 +; CHECK-NEXT: add r15, r5, r0 +; CHECK-NEXT: add r0, r10, r14 +; CHECK-NEXT: sldi r0, r0, 3 +; CHECK-NEXT: add r2, r3, r0 +; CHECK-NEXT: ld r3, -224(r1) # 8-byte Folded Reload +; CHECK-NEXT: add r14, r5, r0 +; CHECK-NEXT: add r31, r4, r0 +; CHECK-NEXT: sub r0, r3, r7 +; CHECK-NEXT: ld r3, -192(r1) # 8-byte Folded Reload +; CHECK-NEXT: rldicl r9, r3, 2, 1 +; CHECK-NEXT: ld r3, -216(r1) # 8-byte Folded Reload +; CHECK-NEXT: addi r8, r9, -4 +; CHECK-NEXT: rldicl r8, r8, 62, 2 +; CHECK-NEXT: sub r7, r3, r7 +; CHECK-NEXT: ori r3, r9, 1 +; CHECK-NEXT: addi r8, r8, 1 +; CHECK-NEXT: mulld r3, r10, r3 +; CHECK-NEXT: mtctr r8 +; CHECK-NEXT: li r8, 0 +; CHECK-NEXT: std r10, -192(r1) # 8-byte Folded Spill +; CHECK-NEXT: std r3, -216(r1) # 8-byte Folded Spill ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB7_3: # %for.body ; CHECK-NEXT: # ; CHECK-NEXT: lfd f0, 0(r2) ; CHECK-NEXT: lfd f1, 0(r31) -; CHECK-NEXT: add r3, r10, r30 -; CHECK-NEXT: add r3, r3, r30 ; CHECK-NEXT: xsmuldp f0, f0, f1 ; CHECK-NEXT: lfd f1, 0(r14) -; CHECK-NEXT: add r3, r3, r30 -; CHECK-NEXT: add r10, r3, r30 ; CHECK-NEXT: xsadddp f0, f1, f0 ; CHECK-NEXT: stfd f0, 0(r14) ; CHECK-NEXT: add r14, r14, r11 ; CHECK-NEXT: lfdx f0, r2, r0 ; CHECK-NEXT: lfdx f1, r31, r0 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r15, r7 +; CHECK-NEXT: lfdx f1, r15, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r15, r7 -; CHECK-NEXT: lfdx f0, r2, r12 -; CHECK-NEXT: lfdx f1, r31, r12 +; CHECK-NEXT: stfdx f0, r15, r8 +; CHECK-NEXT: lfdx f0, r2, r7 +; CHECK-NEXT: lfdx f1, r31, r7 ; CHECK-NEXT: add r2, r2, r11 ; CHECK-NEXT: add r31, r31, r11 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r16, r7 +; CHECK-NEXT: lfdx f1, r16, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r16, r7 +; CHECK-NEXT: stfdx f0, r16, r8 ; CHECK-NEXT: lfd f0, 0(r17) ; CHECK-NEXT: lfd f1, 0(r18) ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r19, r7 +; CHECK-NEXT: lfdx f1, r19, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r19, r7 +; CHECK-NEXT: stfdx f0, r19, r8 ; CHECK-NEXT: lfdx f0, r17, r0 ; CHECK-NEXT: lfdx f1, r18, r0 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r20, r7 +; CHECK-NEXT: lfdx f1, r20, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r20, r7 -; CHECK-NEXT: lfdx f0, r17, r12 -; CHECK-NEXT: lfdx f1, r18, r12 +; CHECK-NEXT: stfdx f0, r20, r8 +; CHECK-NEXT: lfdx f0, r17, r7 +; CHECK-NEXT: lfdx f1, r18, r7 ; CHECK-NEXT: add r17, r17, r11 ; CHECK-NEXT: add r18, r18, r11 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r21, r7 +; CHECK-NEXT: lfdx f1, r21, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r21, r7 +; CHECK-NEXT: stfdx f0, r21, r8 ; CHECK-NEXT: lfd f0, 0(r22) ; CHECK-NEXT: lfd f1, 0(r23) ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r24, r7 +; CHECK-NEXT: lfdx f1, r24, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r24, r7 +; CHECK-NEXT: stfdx f0, r24, r8 ; CHECK-NEXT: lfdx f0, r22, r0 ; CHECK-NEXT: lfdx f1, r23, r0 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r25, r7 +; CHECK-NEXT: lfdx f1, r25, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r25, r7 -; CHECK-NEXT: lfdx f0, r22, r12 -; CHECK-NEXT: lfdx f1, r23, r12 +; CHECK-NEXT: stfdx f0, r25, r8 +; CHECK-NEXT: lfdx f0, r22, r7 +; CHECK-NEXT: lfdx f1, r23, r7 ; CHECK-NEXT: add r22, r22, r11 ; CHECK-NEXT: add r23, r23, r11 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r26, r7 +; CHECK-NEXT: lfdx f1, r26, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r26, r7 +; CHECK-NEXT: stfdx f0, r26, r8 ; CHECK-NEXT: lfd f0, 0(r27) ; CHECK-NEXT: lfd f1, 0(r28) ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r29, r7 +; CHECK-NEXT: lfdx f1, r29, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r29, r7 +; CHECK-NEXT: stfdx f0, r29, r8 ; CHECK-NEXT: lfdx f0, r27, r0 ; CHECK-NEXT: lfdx f1, r28, r0 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r8, r7 +; CHECK-NEXT: lfdx f1, r30, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r8, r7 -; CHECK-NEXT: lfdx f0, r27, r12 -; CHECK-NEXT: lfdx f1, r28, r12 +; CHECK-NEXT: stfdx f0, r30, r8 +; CHECK-NEXT: lfdx f0, r27, r7 +; CHECK-NEXT: lfdx f1, r28, r7 ; CHECK-NEXT: add r27, r27, r11 ; CHECK-NEXT: add r28, r28, r11 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r9, r7 +; CHECK-NEXT: lfdx f1, r12, r8 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r9, r7 -; CHECK-NEXT: add r7, r7, r11 +; CHECK-NEXT: stfdx f0, r12, r8 +; CHECK-NEXT: add r8, r8, r11 ; CHECK-NEXT: bdnz .LBB7_3 -; CHECK-NEXT: .LBB7_4: # %for.cond.cleanup.loopexit.unr-lcssa +; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: ld r3, -160(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r4, -168(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r7, -176(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r8, -184(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r10, -192(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r5, -200(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r9, -208(r1) # 8-byte Folded Reload +; CHECK-NEXT: ld r26, -216(r1) # 8-byte Folded Reload +; CHECK-NEXT: .LBB7_5: # %for.cond.cleanup.loopexit.unr-lcssa ; CHECK-NEXT: cmpldi r6, 0 -; CHECK-NEXT: beq cr0, .LBB7_7 -; CHECK-NEXT: # %bb.5: # %for.body.epil.preheader -; CHECK-NEXT: ld r3, -184(r1) # 8-byte Folded Reload -; CHECK-NEXT: ld r0, -160(r1) # 8-byte Folded Reload -; CHECK-NEXT: sldi r8, r30, 3 -; CHECK-NEXT: add r3, r10, r3 -; CHECK-NEXT: sldi r3, r3, 3 -; CHECK-NEXT: add r7, r5, r3 -; CHECK-NEXT: add r9, r4, r3 -; CHECK-NEXT: add r11, r0, r3 -; CHECK-NEXT: ld r3, -176(r1) # 8-byte Folded Reload -; CHECK-NEXT: add r3, r10, r3 -; CHECK-NEXT: sldi r3, r3, 3 -; CHECK-NEXT: add r12, r5, r3 -; CHECK-NEXT: add r30, r4, r3 -; CHECK-NEXT: add r29, r0, r3 -; CHECK-NEXT: ld r3, -168(r1) # 8-byte Folded Reload -; CHECK-NEXT: add r3, r10, r3 -; CHECK-NEXT: li r10, 0 -; CHECK-NEXT: sldi r3, r3, 3 -; CHECK-NEXT: add r5, r5, r3 -; CHECK-NEXT: add r4, r4, r3 -; CHECK-NEXT: add r3, r0, r3 +; CHECK-NEXT: beq cr0, .LBB7_8 +; CHECK-NEXT: # %bb.6: # %for.body.epil.preheader +; CHECK-NEXT: add r11, r26, r9 +; CHECK-NEXT: add r12, r26, r8 +; CHECK-NEXT: add r9, r26, r7 +; CHECK-NEXT: sldi r27, r10, 3 +; CHECK-NEXT: sldi r11, r11, 3 +; CHECK-NEXT: sldi r0, r12, 3 +; CHECK-NEXT: sldi r9, r9, 3 +; CHECK-NEXT: add r28, r5, r11 +; CHECK-NEXT: add r10, r4, r11 +; CHECK-NEXT: add r11, r3, r11 +; CHECK-NEXT: add r12, r5, r0 +; CHECK-NEXT: add r30, r4, r0 +; CHECK-NEXT: add r29, r3, r0 +; CHECK-NEXT: add r5, r5, r9 +; CHECK-NEXT: add r4, r4, r9 +; CHECK-NEXT: add r3, r3, r9 +; CHECK-NEXT: li r9, 0 ; CHECK-NEXT: .p2align 4 -; CHECK-NEXT: .LBB7_6: # %for.body.epil +; CHECK-NEXT: .LBB7_7: # %for.body.epil ; CHECK-NEXT: # -; CHECK-NEXT: lfdx f0, r3, r10 -; CHECK-NEXT: lfdx f1, r4, r10 +; CHECK-NEXT: lfdx f0, r3, r9 +; CHECK-NEXT: lfdx f1, r4, r9 ; CHECK-NEXT: addi r6, r6, -1 ; CHECK-NEXT: cmpldi r6, 0 ; CHECK-NEXT: xsmuldp f0, f0, f1 ; CHECK-NEXT: lfd f1, 0(r5) ; CHECK-NEXT: xsadddp f0, f1, f0 ; CHECK-NEXT: stfd f0, 0(r5) -; CHECK-NEXT: add r5, r5, r8 -; CHECK-NEXT: lfdx f0, r29, r10 -; CHECK-NEXT: lfdx f1, r30, r10 +; CHECK-NEXT: add r5, r5, r27 +; CHECK-NEXT: lfdx f0, r29, r9 +; CHECK-NEXT: lfdx f1, r30, r9 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r12, r10 +; CHECK-NEXT: lfdx f1, r12, r9 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r12, r10 -; CHECK-NEXT: lfdx f0, r11, r10 -; CHECK-NEXT: lfdx f1, r9, r10 +; CHECK-NEXT: stfdx f0, r12, r9 +; CHECK-NEXT: lfdx f0, r11, r9 +; CHECK-NEXT: lfdx f1, r10, r9 ; CHECK-NEXT: xsmuldp f0, f0, f1 -; CHECK-NEXT: lfdx f1, r7, r10 +; CHECK-NEXT: lfdx f1, r28, r9 ; CHECK-NEXT: xsadddp f0, f1, f0 -; CHECK-NEXT: stfdx f0, r7, r10 -; CHECK-NEXT: add r10, r10, r8 -; CHECK-NEXT: bne cr0, .LBB7_6 -; CHECK-NEXT: .LBB7_7: # %for.cond.cleanup +; CHECK-NEXT: stfdx f0, r28, r9 +; CHECK-NEXT: add r9, r9, r27 +; CHECK-NEXT: bne cr0, .LBB7_7 +; CHECK-NEXT: .LBB7_8: ; CHECK-NEXT: ld r2, -152(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload @@ -973,6 +981,8 @@ define signext i32 @spill_reduce_succ(ptr %input1, ptr %input2, ptr %output, i64 ; CHECK-NEXT: ld r16, -128(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r14, -144(r1) # 8-byte Folded Reload +; CHECK-NEXT: .LBB7_9: # %for.cond.cleanup +; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: blr entry: %cmp49 = icmp sgt i64 %m, 0 diff --git a/llvm/test/CodeGen/PowerPC/dmr-copy.ll b/llvm/test/CodeGen/PowerPC/dmr-copy.ll new file mode 100644 index 000000000000..d5a24309f94d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/dmr-copy.ll @@ -0,0 +1,245 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=future -ppc-asm-full-reg-names \ +; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix \ +; RUN: -mcpu=future -ppc-asm-full-reg-names \ +; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE + +define void @test_wacc_copy(ptr noundef %vdmrp, ptr noundef %vpp, <16 x i8> noundef %vc, ptr noundef %resp) #0 { +; CHECK-LABEL: test_wacc_copy: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: std r31, -8(r1) +; CHECK-NEXT: std r30, -16(r1) +; CHECK-NEXT: mr r30, r1 +; CHECK-NEXT: clrldi r0, r1, 57 +; CHECK-NEXT: subfic r0, r0, -384 +; CHECK-NEXT: stdux r1, r1, r0 +; CHECK-NEXT: .cfi_def_cfa_register r30 +; CHECK-NEXT: .cfi_offset r31, -8 +; CHECK-NEXT: .cfi_offset r30, -16 +; CHECK-NEXT: mr r31, r1 +; CHECK-NEXT: std r3, 360(r31) +; CHECK-NEXT: std r4, 352(r31) +; CHECK-NEXT: stxv v2, 336(r31) +; CHECK-NEXT: std r7, 328(r31) +; CHECK-NEXT: ld r3, 360(r31) +; CHECK-NEXT: lxvp vsp34, 0(r3) +; CHECK-NEXT: lxvp vsp36, 32(r3) +; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 +; CHECK-NEXT: lxvp vsp34, 64(r3) +; CHECK-NEXT: lxvp vsp36, 96(r3) +; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-NEXT: stxvp vsp34, 224(r31) +; CHECK-NEXT: stxvp vsp36, 192(r31) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-NEXT: stxvp vsp34, 160(r31) +; CHECK-NEXT: stxvp vsp36, 128(r31) +; CHECK-NEXT: ld r3, 352(r31) +; CHECK-NEXT: lxv v2, 16(r3) +; CHECK-NEXT: lxv v3, 0(r3) +; CHECK-NEXT: stxv v2, 112(r31) +; CHECK-NEXT: stxv v3, 96(r31) +; CHECK-NEXT: lxv v2, 112(r31) +; CHECK-NEXT: lxv v3, 96(r31) +; CHECK-NEXT: lxv vs0, 336(r31) +; CHECK-NEXT: dmxvi8gerx4 dmr0, vsp34, vs0 +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-NEXT: stxvp vsp34, 224(r31) +; CHECK-NEXT: stxvp vsp36, 192(r31) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-NEXT: stxvp vsp34, 160(r31) +; CHECK-NEXT: stxvp vsp36, 128(r31) +; CHECK-NEXT: lxvp vsp34, 128(r31) +; CHECK-NEXT: lxvp vsp36, 160(r31) +; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 +; CHECK-NEXT: lxvp vsp34, 192(r31) +; CHECK-NEXT: lxvp vsp36, 224(r31) +; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 +; CHECK-NEXT: ld r3, 328(r31) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-NEXT: stxvp vsp34, 96(r3) +; CHECK-NEXT: stxvp vsp36, 64(r3) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-NEXT: stxvp vsp34, 32(r3) +; CHECK-NEXT: stxvp vsp36, 0(r3) +; CHECK-NEXT: mr r1, r30 +; CHECK-NEXT: ld r31, -8(r1) +; CHECK-NEXT: ld r30, -16(r1) +; CHECK-NEXT: blr +; +; CHECK-BE-LABEL: test_wacc_copy: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: std r31, -8(r1) +; CHECK-BE-NEXT: std r30, -16(r1) +; CHECK-BE-NEXT: mr r30, r1 +; CHECK-BE-NEXT: clrldi r0, r1, 57 +; CHECK-BE-NEXT: subfic r0, r0, -384 +; CHECK-BE-NEXT: stdux r1, r1, r0 +; CHECK-BE-NEXT: mr r31, r1 +; CHECK-BE-NEXT: std r3, 360(r31) +; CHECK-BE-NEXT: std r4, 352(r31) +; CHECK-BE-NEXT: stxv v2, 336(r31) +; CHECK-BE-NEXT: std r5, 328(r31) +; CHECK-BE-NEXT: ld r3, 360(r31) +; CHECK-BE-NEXT: lxvp vsp34, 96(r3) +; CHECK-BE-NEXT: lxvp vsp36, 64(r3) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 +; CHECK-BE-NEXT: lxvp vsp34, 32(r3) +; CHECK-BE-NEXT: lxvp vsp36, 0(r3) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-BE-NEXT: stxvp vsp36, 224(r31) +; CHECK-BE-NEXT: stxvp vsp34, 192(r31) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-BE-NEXT: stxvp vsp36, 160(r31) +; CHECK-BE-NEXT: stxvp vsp34, 128(r31) +; CHECK-BE-NEXT: ld r3, 352(r31) +; CHECK-BE-NEXT: lxv v2, 0(r3) +; CHECK-BE-NEXT: lxv v3, 16(r3) +; CHECK-BE-NEXT: stxv v3, 112(r31) +; CHECK-BE-NEXT: stxv v2, 96(r31) +; CHECK-BE-NEXT: lxv v2, 96(r31) +; CHECK-BE-NEXT: lxv v3, 112(r31) +; CHECK-BE-NEXT: lxv vs0, 336(r31) +; CHECK-BE-NEXT: dmxvi8gerx4 dmr0, vsp34, vs0 +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-BE-NEXT: stxvp vsp36, 224(r31) +; CHECK-BE-NEXT: stxvp vsp34, 192(r31) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-BE-NEXT: stxvp vsp36, 160(r31) +; CHECK-BE-NEXT: stxvp vsp34, 128(r31) +; CHECK-BE-NEXT: lxvp vsp34, 224(r31) +; CHECK-BE-NEXT: lxvp vsp36, 192(r31) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 +; CHECK-BE-NEXT: lxvp vsp34, 160(r31) +; CHECK-BE-NEXT: lxvp vsp36, 128(r31) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 +; CHECK-BE-NEXT: ld r3, 328(r31) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-BE-NEXT: stxvp vsp36, 96(r3) +; CHECK-BE-NEXT: stxvp vsp34, 64(r3) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-BE-NEXT: stxvp vsp36, 32(r3) +; CHECK-BE-NEXT: stxvp vsp34, 0(r3) +; CHECK-BE-NEXT: mr r1, r30 +; CHECK-BE-NEXT: ld r31, -8(r1) +; CHECK-BE-NEXT: ld r30, -16(r1) +; CHECK-BE-NEXT: blr +entry: + %vdmrp.addr = alloca ptr, align 8 + %vpp.addr = alloca ptr, align 8 + %vc.addr = alloca <16 x i8>, align 16 + %resp.addr = alloca ptr, align 8 + %vdmr = alloca <1024 x i1>, align 128 + %vp = alloca <256 x i1>, align 32 + store ptr %vdmrp, ptr %vdmrp.addr, align 8 + store ptr %vpp, ptr %vpp.addr, align 8 + store <16 x i8> %vc, ptr %vc.addr, align 16 + store ptr %resp, ptr %resp.addr, align 8 + %0 = load ptr, ptr %vdmrp.addr, align 8 + %1 = load <1024 x i1>, ptr %0, align 128 + store <1024 x i1> %1, ptr %vdmr, align 128 + %2 = load ptr, ptr %vpp.addr, align 8 + %3 = load <256 x i1>, ptr %2, align 32 + store <256 x i1> %3, ptr %vp, align 32 + %4 = load <256 x i1>, ptr %vp, align 32 + %5 = load <16 x i8>, ptr %vc.addr, align 16 + %6 = call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> %4, <16 x i8> %5) + store <1024 x i1> %6, ptr %vdmr, align 128 + %7 = load <1024 x i1>, ptr %vdmr, align 128 + %8 = load ptr, ptr %resp.addr, align 8 + store <1024 x i1> %7, ptr %8, align 128 + ret void +} + +define void @foo(ptr noundef readonly captures(none) %p1, ptr noundef readonly captures(none) %p2, ptr noundef writeonly captures(none) initializes((0, 128)) %res1, ptr noundef writeonly captures(none) initializes((0, 128)) %res2) local_unnamed_addr #0 { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: dmsetdmrz dmr0 +; CHECK-NEXT: lxvp vsp34, 0(r3) +; CHECK-NEXT: lxvp vsp36, 32(r3) +; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1 +; CHECK-NEXT: lxvp vsp34, 64(r3) +; CHECK-NEXT: lxvp vsp36, 96(r3) +; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0 +; CHECK-NEXT: dmmr dmr2, dmr0 +; CHECK-NEXT: dmxor dmr2, dmr1 +; CHECK-NEXT: lxvp vsp34, 0(r4) +; CHECK-NEXT: lxvp vsp36, 32(r4) +; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1 +; CHECK-NEXT: lxvp vsp34, 64(r4) +; CHECK-NEXT: lxvp vsp36, 96(r4) +; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0 +; CHECK-NEXT: dmxor dmr0, dmr1 +; CHECK-NEXT: dmmr dmr1, dmr2 +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0 +; CHECK-NEXT: stxvp vsp34, 96(r5) +; CHECK-NEXT: stxvp vsp36, 64(r5) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1 +; CHECK-NEXT: stxvp vsp34, 32(r5) +; CHECK-NEXT: stxvp vsp36, 0(r5) +; CHECK-NEXT: dmmr dmr0, dmr0 +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-NEXT: stxvp vsp34, 96(r6) +; CHECK-NEXT: stxvp vsp36, 64(r6) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-NEXT: stxvp vsp34, 32(r6) +; CHECK-NEXT: stxvp vsp36, 0(r6) +; CHECK-NEXT: blr +; +; CHECK-BE-LABEL: foo: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: dmsetdmrz dmr0 +; CHECK-BE-NEXT: lxvp vsp34, 96(r3) +; CHECK-BE-NEXT: lxvp vsp36, 64(r3) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1 +; CHECK-BE-NEXT: lxvp vsp34, 32(r3) +; CHECK-BE-NEXT: lxvp vsp36, 0(r3) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0 +; CHECK-BE-NEXT: dmmr dmr2, dmr0 +; CHECK-BE-NEXT: dmxor dmr2, dmr1 +; CHECK-BE-NEXT: lxvp vsp34, 96(r4) +; CHECK-BE-NEXT: lxvp vsp36, 64(r4) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1 +; CHECK-BE-NEXT: lxvp vsp34, 32(r4) +; CHECK-BE-NEXT: lxvp vsp36, 0(r4) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0 +; CHECK-BE-NEXT: dmxor dmr0, dmr1 +; CHECK-BE-NEXT: dmmr dmr1, dmr2 +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1 +; CHECK-BE-NEXT: stxvp vsp36, 96(r5) +; CHECK-BE-NEXT: stxvp vsp34, 64(r5) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0 +; CHECK-BE-NEXT: stxvp vsp36, 32(r5) +; CHECK-BE-NEXT: stxvp vsp34, 0(r5) +; CHECK-BE-NEXT: dmmr dmr0, dmr0 +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-BE-NEXT: stxvp vsp36, 96(r6) +; CHECK-BE-NEXT: stxvp vsp34, 64(r6) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-BE-NEXT: stxvp vsp36, 32(r6) +; CHECK-BE-NEXT: stxvp vsp34, 0(r6) +; CHECK-BE-NEXT: blr +entry: + %0 = tail call <1024 x i1> @llvm.ppc.mma.dmsetdmrz() + %1 = load <1024 x i1>, ptr %p1, align 128 + %2 = tail call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> %0, <1024 x i1> %1) + %3 = load <1024 x i1>, ptr %p2, align 128 + %4 = tail call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> %0, <1024 x i1> %3) + %5 = tail call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> %2) + store <1024 x i1> %5, ptr %res1, align 128 + %6 = tail call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> %4) + store <1024 x i1> %6, ptr %res2, align 128 + ret void +} + +declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz() +declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>) +declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>) +declare <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1>, <16 x i8>) + +attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="future" "target-features"="+64bit,+allow-unaligned-fp-access,+altivec,+bpermd,+cmpb,+crbits,+crypto,+direct-move,+extdiv,+fast-MFLR,+fcpsgn,+fpcvt,+fprnd,+fpu,+fre,+fres,+frsqrte,+frsqrtes,+fsqrt,+fuse-add-logical,+fuse-arith-add,+fuse-logical,+fuse-logical-add,+fuse-sha3,+fuse-store,+fusion,+hard-float,+icbt,+isa-future-instructions,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+isa-v31-instructions,+isel,+ldbrx,+lfiwax,+mfocrf,+mma,+paired-vector-memops,+partword-atomics,+pcrelative-memops,+popcntd,+power10-vector,+power8-altivec,+power8-vector,+power9-altivec,+power9-vector,+ppc-postra-sched,+ppc-prera-sched,+predictable-select-expensive,+prefix-instrs,+quadword-atomics,+recipprec,+stfiwx,+two-const-nr,+vsx" } + + diff --git a/llvm/test/CodeGen/PowerPC/dmr-enable.ll b/llvm/test/CodeGen/PowerPC/dmr-enable.ll index 1e3014405ac4..a505ac4c2434 100644 --- a/llvm/test/CodeGen/PowerPC/dmr-enable.ll +++ b/llvm/test/CodeGen/PowerPC/dmr-enable.ll @@ -367,6 +367,69 @@ entry: ret void } +define void @tbuild(ptr %p1, ptr %p2, ptr %res1, ptr %res2, ptr %v) { +; CHECK-LABEL: tbuild: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lxv v3, 0(r7) +; CHECK-NEXT: vmr v2, v3 +; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp34, 1 +; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0 +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-NEXT: stxvp vsp34, 96(r6) +; CHECK-NEXT: stxvp vsp36, 64(r6) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-NEXT: stxvp vsp34, 32(r6) +; CHECK-NEXT: stxvp vsp36, 0(r6) +; CHECK-NEXT: lxvp vsp34, 0(r3) +; CHECK-NEXT: lxvp vsp36, 32(r3) +; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 +; CHECK-NEXT: lxvp vsp34, 64(r3) +; CHECK-NEXT: lxvp vsp36, 96(r3) +; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-NEXT: stxvp vsp34, 96(r5) +; CHECK-NEXT: stxvp vsp36, 64(r5) +; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-NEXT: stxvp vsp34, 32(r5) +; CHECK-NEXT: stxvp vsp36, 0(r5) +; CHECK-NEXT: blr +; +; CHECK-BE-LABEL: tbuild: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: lxv v3, 0(r7) +; CHECK-BE-NEXT: vmr v2, v3 +; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp34, 1 +; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0 +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-BE-NEXT: stxvp vsp36, 96(r6) +; CHECK-BE-NEXT: stxvp vsp34, 64(r6) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-BE-NEXT: stxvp vsp36, 32(r6) +; CHECK-BE-NEXT: stxvp vsp34, 0(r6) +; CHECK-BE-NEXT: lxvp vsp34, 96(r3) +; CHECK-BE-NEXT: lxvp vsp36, 64(r3) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1 +; CHECK-BE-NEXT: lxvp vsp34, 32(r3) +; CHECK-BE-NEXT: lxvp vsp36, 0(r3) +; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0 +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1 +; CHECK-BE-NEXT: stxvp vsp36, 96(r5) +; CHECK-BE-NEXT: stxvp vsp34, 64(r5) +; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0 +; CHECK-BE-NEXT: stxvp vsp36, 32(r5) +; CHECK-BE-NEXT: stxvp vsp34, 0(r5) +; CHECK-BE-NEXT: blr +entry: + %0 = load <16 x i8>, ptr %v, align 16 + %1 = tail call <1024 x i1> @llvm.ppc.mma.build.dmr(<16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0) + store <1024 x i1> %1, ptr %res2, align 128 + %2 = load <1024 x i1>, ptr %p1, align 128 + tail call void @llvm.ppc.mma.disassemble.dmr(ptr %res1, <1024 x i1> %2) + ret void +} + +declare <1024 x i1> @llvm.ppc.mma.build.dmr(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>) +declare void @llvm.ppc.mma.disassemble.dmr(ptr, <1024 x i1>) declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz() declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>) declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>) diff --git a/llvm/test/CodeGen/PowerPC/half.ll b/llvm/test/CodeGen/PowerPC/half.ll new file mode 100644 index 000000000000..903ea691ae6b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/half.ll @@ -0,0 +1,2547 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=powerpc-unknown-unknown \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefix=PPC32 +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,P8 +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefixes=CHECK,P9 +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -mattr=-hard-float \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefix=SOFT +; RUN: llc -mtriple=powerpc64-unknown-unknown \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ +; RUN: --check-prefix=BE + +; Tests for various operations on half precison float. Much of the test is +; copied from test/CodeGen/X86/half.ll. + +define void @store(half %x, ptr %p) nounwind { +; PPC32-LABEL: store: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: sth r3, 0(r30) +; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: store: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: mr r30, r4 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 0(r30) +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: store: +; P9: # %bb.0: +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: stxsihx f0, 0, r4 +; P9-NEXT: blr +; +; SOFT-LABEL: store: +; SOFT: # %bb.0: +; SOFT-NEXT: sth r3, 0(r4) +; SOFT-NEXT: blr +; +; BE-LABEL: store: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r4 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r3, 0(r30) +; BE-NEXT: ld r30, 112(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + store half %x, ptr %p + ret void +} + +define half @return(ptr %p) nounwind { +; PPC32-LABEL: return: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: return: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: lhz r3, 0(r3) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: return: +; P9: # %bb.0: +; P9-NEXT: lxsihzx f0, 0, r3 +; P9-NEXT: xscvhpdp f1, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: return: +; SOFT: # %bb.0: +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: blr +; +; BE-LABEL: return: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %r = load half, ptr %p + ret half %r +} + +define dso_local double @loadd(ptr nocapture readonly %a) local_unnamed_addr nounwind { +; PPC32-LABEL: loadd: +; PPC32: # %bb.0: # %entry +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: lhz r3, 2(r3) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: loadd: +; P8: # %bb.0: # %entry +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: lhz r3, 2(r3) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: loadd: +; P9: # %bb.0: # %entry +; P9-NEXT: addi r3, r3, 2 +; P9-NEXT: lxsihzx f0, 0, r3 +; P9-NEXT: xscvhpdp f1, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: loadd: +; SOFT: # %bb.0: # %entry +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: stdu r1, -32(r1) +; SOFT-NEXT: std r0, 48(r1) +; SOFT-NEXT: lhz r3, 2(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __extendsfdf2 +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 32 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: loadd: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: lhz r3, 2(r3) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +entry: + %arrayidx = getelementptr inbounds i16, ptr %a, i64 1 + %0 = load i16, ptr %arrayidx, align 2 + %1 = tail call double @llvm.convert.from.fp16.f64(i16 %0) + ret double %1 +} + +declare double @llvm.convert.from.fp16.f64(i16) + +define dso_local float @loadf(ptr nocapture readonly %a) local_unnamed_addr nounwind { +; PPC32-LABEL: loadf: +; PPC32: # %bb.0: # %entry +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: lhz r3, 2(r3) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: loadf: +; P8: # %bb.0: # %entry +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: lhz r3, 2(r3) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: loadf: +; P9: # %bb.0: # %entry +; P9-NEXT: addi r3, r3, 2 +; P9-NEXT: lxsihzx f0, 0, r3 +; P9-NEXT: xscvhpdp f1, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: loadf: +; SOFT: # %bb.0: # %entry +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: stdu r1, -32(r1) +; SOFT-NEXT: std r0, 48(r1) +; SOFT-NEXT: lhz r3, 2(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 32 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: loadf: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: lhz r3, 2(r3) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +entry: + %arrayidx = getelementptr inbounds i16, ptr %a, i64 1 + %0 = load i16, ptr %arrayidx, align 2 + %1 = tail call float @llvm.convert.from.fp16.f32(i16 %0) + ret float %1 +} + +declare float @llvm.convert.from.fp16.f32(i16) + +define dso_local void @stored(ptr nocapture %a, double %b) local_unnamed_addr nounwind { +; PPC32-LABEL: stored: +; PPC32: # %bb.0: # %entry +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: bl __truncdfhf2 +; PPC32-NEXT: sth r3, 0(r30) +; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: stored: +; P8: # %bb.0: # %entry +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: mr r30, r3 +; P8-NEXT: bl __truncdfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 0(r30) +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: stored: +; P9: # %bb.0: # %entry +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: stxsihx f0, 0, r3 +; P9-NEXT: blr +; +; SOFT-LABEL: stored: +; SOFT: # %bb.0: # %entry +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: mr r30, r3 +; SOFT-NEXT: mr r3, r4 +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: bl __truncdfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: stored: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r3 +; BE-NEXT: bl __truncdfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r3, 0(r30) +; BE-NEXT: ld r30, 112(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +entry: + %0 = tail call i16 @llvm.convert.to.fp16.f64(double %b) + store i16 %0, ptr %a, align 2 + ret void +} + +declare i16 @llvm.convert.to.fp16.f64(double) + +define dso_local void @storef(ptr nocapture %a, float %b) local_unnamed_addr nounwind { +; PPC32-LABEL: storef: +; PPC32: # %bb.0: # %entry +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: sth r3, 0(r30) +; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: storef: +; P8: # %bb.0: # %entry +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: mr r30, r3 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 0(r30) +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: storef: +; P9: # %bb.0: # %entry +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: stxsihx f0, 0, r3 +; P9-NEXT: blr +; +; SOFT-LABEL: storef: +; SOFT: # %bb.0: # %entry +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: mr r30, r3 +; SOFT-NEXT: clrldi r3, r4, 32 +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: storef: +; BE: # %bb.0: # %entry +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r3 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r3, 0(r30) +; BE-NEXT: ld r30, 112(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr +entry: + %0 = tail call i16 @llvm.convert.to.fp16.f32(float %b) + store i16 %0, ptr %a, align 2 + ret void +} + +declare i16 @llvm.convert.to.fp16.f32(float) +define void @test_load_store(ptr %in, ptr %out) nounwind { +; PPC32-LABEL: test_load_store: +; PPC32: # %bb.0: +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: sth r3, 0(r4) +; PPC32-NEXT: blr +; +; CHECK-LABEL: test_load_store: +; CHECK: # %bb.0: +; CHECK-NEXT: lhz r3, 0(r3) +; CHECK-NEXT: sth r3, 0(r4) +; CHECK-NEXT: blr +; +; SOFT-LABEL: test_load_store: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: mr r30, r4 +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_load_store: +; BE: # %bb.0: +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: sth r3, 0(r4) +; BE-NEXT: blr + %val = load half, ptr %in + store half %val, ptr %out + ret void +} +define i16 @test_bitcast_from_half(ptr %addr) nounwind { +; PPC32-LABEL: test_bitcast_from_half: +; PPC32: # %bb.0: +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: blr +; +; CHECK-LABEL: test_bitcast_from_half: +; CHECK: # %bb.0: +; CHECK-NEXT: lhz r3, 0(r3) +; CHECK-NEXT: blr +; +; SOFT-LABEL: test_bitcast_from_half: +; SOFT: # %bb.0: +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: blr +; +; BE-LABEL: test_bitcast_from_half: +; BE: # %bb.0: +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: blr + %val = load half, ptr %addr + %val_int = bitcast half %val to i16 + ret i16 %val_int +} +define void @test_bitcast_to_half(ptr %addr, i16 %in) nounwind { +; PPC32-LABEL: test_bitcast_to_half: +; PPC32: # %bb.0: +; PPC32-NEXT: sth r4, 0(r3) +; PPC32-NEXT: blr +; +; CHECK-LABEL: test_bitcast_to_half: +; CHECK: # %bb.0: +; CHECK-NEXT: sth r4, 0(r3) +; CHECK-NEXT: blr +; +; SOFT-LABEL: test_bitcast_to_half: +; SOFT: # %bb.0: +; SOFT-NEXT: sth r4, 0(r3) +; SOFT-NEXT: blr +; +; BE-LABEL: test_bitcast_to_half: +; BE: # %bb.0: +; BE-NEXT: sth r4, 0(r3) +; BE-NEXT: blr + %val_fp = bitcast i16 %in to half + store half %val_fp, ptr %addr + ret void +} + + +; Checks for https://github.com/llvm/llvm-project/issues/97981 +define half @from_bits(i16 %x) nounwind { +; PPC32-LABEL: from_bits: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: clrlwi r3, r3, 16 +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: from_bits: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: clrldi r3, r3, 48 +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: from_bits: +; P9: # %bb.0: +; P9-NEXT: clrlwi r3, r3, 16 +; P9-NEXT: mtfprwz f0, r3 +; P9-NEXT: xscvhpdp f1, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: from_bits: +; SOFT: # %bb.0: +; SOFT-NEXT: blr +; +; BE-LABEL: from_bits: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: clrldi r3, r3, 48 +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %res = bitcast i16 %x to half + ret half %res +} + +define i16 @to_bits(half %x) nounwind { +; PPC32-LABEL: to_bits: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: clrlwi r3, r3, 16 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: to_bits: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: clrldi r3, r3, 48 +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: to_bits: +; P9: # %bb.0: +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: clrlwi r3, r3, 16 +; P9-NEXT: blr +; +; SOFT-LABEL: to_bits: +; SOFT: # %bb.0: +; SOFT-NEXT: blr +; +; BE-LABEL: to_bits: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: clrldi r3, r3, 48 +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %res = bitcast half %x to i16 + ret i16 %res +} + +define float @test_extend32(ptr %addr) nounwind { +; PPC32-LABEL: test_extend32: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_extend32: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: lhz r3, 0(r3) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_extend32: +; P9: # %bb.0: +; P9-NEXT: lxsihzx f0, 0, r3 +; P9-NEXT: xscvhpdp f1, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: test_extend32: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: stdu r1, -32(r1) +; SOFT-NEXT: std r0, 48(r1) +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 32 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_extend32: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %val16 = load half, ptr %addr + %val32 = fpext half %val16 to float + ret float %val32 +} +define double @test_extend64(ptr %addr) nounwind { +; PPC32-LABEL: test_extend64: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_extend64: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: lhz r3, 0(r3) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_extend64: +; P9: # %bb.0: +; P9-NEXT: lxsihzx f0, 0, r3 +; P9-NEXT: xscvhpdp f1, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: test_extend64: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: stdu r1, -32(r1) +; SOFT-NEXT: std r0, 48(r1) +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __extendsfdf2 +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 32 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_extend64: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %val16 = load half, ptr %addr + %val32 = fpext half %val16 to double + ret double %val32 +} +define void @test_trunc32(float %in, ptr %addr) nounwind { +; PPC32-LABEL: test_trunc32: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: sth r3, 0(r30) +; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_trunc32: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: mr r30, r4 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 0(r30) +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_trunc32: +; P9: # %bb.0: +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: stxsihx f0, 0, r4 +; P9-NEXT: blr +; +; SOFT-LABEL: test_trunc32: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: clrldi r3, r3, 32 +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: mr r30, r4 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_trunc32: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r4 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r3, 0(r30) +; BE-NEXT: ld r30, 112(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %val16 = fptrunc float %in to half + store half %val16, ptr %addr + ret void +} +define void @test_trunc64(double %in, ptr %addr) nounwind { +; PPC32-LABEL: test_trunc64: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: bl __truncdfhf2 +; PPC32-NEXT: sth r3, 0(r30) +; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_trunc64: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: mr r30, r4 +; P8-NEXT: bl __truncdfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 0(r30) +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_trunc64: +; P9: # %bb.0: +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: stxsihx f0, 0, r4 +; P9-NEXT: blr +; +; SOFT-LABEL: test_trunc64: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: mr r30, r4 +; SOFT-NEXT: bl __truncdfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_trunc64: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: std r30, 112(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r4 +; BE-NEXT: bl __truncdfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r3, 0(r30) +; BE-NEXT: ld r30, 112(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %val16 = fptrunc double %in to half + store half %val16, ptr %addr + ret void +} +define i64 @test_fptosi_i64(ptr %p) nounwind { +; PPC32-LABEL: test_fptosi_i64: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: bl __fixsfdi +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_fptosi_i64: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: lhz r3, 0(r3) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: xscvdpsxds f0, f1 +; P8-NEXT: mffprd r3, f0 +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_fptosi_i64: +; P9: # %bb.0: +; P9-NEXT: lhz r3, 0(r3) +; P9-NEXT: mtfprwz f0, r3 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: xscvdpsxds f0, f0 +; P9-NEXT: mffprd r3, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: test_fptosi_i64: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: stdu r1, -32(r1) +; SOFT-NEXT: std r0, 48(r1) +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __fixsfdi +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 32 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_fptosi_i64: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: fctidz f0, f1 +; BE-NEXT: stfd f0, 120(r1) +; BE-NEXT: ld r3, 120(r1) +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %a = load half, ptr %p, align 2 + %r = fptosi half %a to i64 + ret i64 %r +} +define void @test_sitofp_i64(i64 %a, ptr %p) nounwind { +; PPC32-LABEL: test_sitofp_i64: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r5 +; PPC32-NEXT: bl __floatdisf +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: sth r3, 0(r30) +; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_sitofp_i64: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: mtfprd f0, r3 +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: mr r30, r4 +; P8-NEXT: xscvsxdsp f1, f0 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 0(r30) +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_sitofp_i64: +; P9: # %bb.0: +; P9-NEXT: mtfprd f0, r3 +; P9-NEXT: xscvsxdsp f0, f0 +; P9-NEXT: xscvdphp f0, f0 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: sth r3, 0(r4) +; P9-NEXT: blr +; +; SOFT-LABEL: test_sitofp_i64: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: mr r30, r4 +; SOFT-NEXT: bl __floatdisf +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 32 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_sitofp_i64: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -144(r1) +; BE-NEXT: sradi r5, r3, 53 +; BE-NEXT: std r0, 160(r1) +; BE-NEXT: addi r5, r5, 1 +; BE-NEXT: cmpldi r5, 1 +; BE-NEXT: std r30, 128(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r4 +; BE-NEXT: ble cr0, .LBB16_2 +; BE-NEXT: # %bb.1: +; BE-NEXT: clrldi r4, r3, 53 +; BE-NEXT: addi r4, r4, 2047 +; BE-NEXT: or r3, r4, r3 +; BE-NEXT: rldicr r3, r3, 0, 52 +; BE-NEXT: .LBB16_2: +; BE-NEXT: std r3, 120(r1) +; BE-NEXT: lfd f0, 120(r1) +; BE-NEXT: fcfid f0, f0 +; BE-NEXT: frsp f1, f0 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r3, 0(r30) +; BE-NEXT: ld r30, 128(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 144 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %r = sitofp i64 %a to half + store half %r, ptr %p + ret void +} +define i64 @test_fptoui_i64(ptr %p) nounwind { +; PPC32-LABEL: test_fptoui_i64: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: bl __fixunssfdi +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_fptoui_i64: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: lhz r3, 0(r3) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: xscvdpuxds f0, f1 +; P8-NEXT: mffprd r3, f0 +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_fptoui_i64: +; P9: # %bb.0: +; P9-NEXT: lhz r3, 0(r3) +; P9-NEXT: mtfprwz f0, r3 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: xscvdpuxds f0, f0 +; P9-NEXT: mffprd r3, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: test_fptoui_i64: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: stdu r1, -32(r1) +; SOFT-NEXT: std r0, 48(r1) +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __fixunssfdi +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 32 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_fptoui_i64: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha +; BE-NEXT: lfs f0, .LCPI17_0@toc@l(r3) +; BE-NEXT: fsubs f2, f1, f0 +; BE-NEXT: fcmpu cr0, f1, f0 +; BE-NEXT: fctidz f2, f2 +; BE-NEXT: stfd f2, 120(r1) +; BE-NEXT: fctidz f2, f1 +; BE-NEXT: stfd f2, 112(r1) +; BE-NEXT: blt cr0, .LBB17_2 +; BE-NEXT: # %bb.1: +; BE-NEXT: ld r3, 120(r1) +; BE-NEXT: li r4, 1 +; BE-NEXT: rldic r4, r4, 63, 0 +; BE-NEXT: xor r3, r3, r4 +; BE-NEXT: b .LBB17_3 +; BE-NEXT: .LBB17_2: +; BE-NEXT: ld r3, 112(r1) +; BE-NEXT: .LBB17_3: +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %a = load half, ptr %p, align 2 + %r = fptoui half %a to i64 + ret i64 %r +} +define void @test_uitofp_i64(i64 %a, ptr %p) nounwind { +; PPC32-LABEL: test_uitofp_i64: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: stw r30, 8(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r5 +; PPC32-NEXT: bl __floatundisf +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: sth r3, 0(r30) +; PPC32-NEXT: lwz r30, 8(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_uitofp_i64: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: mtfprd f0, r3 +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: mr r30, r4 +; P8-NEXT: xscvuxdsp f1, f0 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 0(r30) +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_uitofp_i64: +; P9: # %bb.0: +; P9-NEXT: mtfprd f0, r3 +; P9-NEXT: xscvuxdsp f0, f0 +; P9-NEXT: xscvdphp f0, f0 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: sth r3, 0(r4) +; P9-NEXT: blr +; +; SOFT-LABEL: test_uitofp_i64: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: mr r30, r4 +; SOFT-NEXT: bl __floatundisf +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_uitofp_i64: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -144(r1) +; BE-NEXT: sradi r5, r3, 53 +; BE-NEXT: std r0, 160(r1) +; BE-NEXT: addi r5, r5, 1 +; BE-NEXT: cmpldi r5, 1 +; BE-NEXT: std r30, 128(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r4 +; BE-NEXT: bgt cr0, .LBB18_2 +; BE-NEXT: # %bb.1: +; BE-NEXT: mr r4, r3 +; BE-NEXT: b .LBB18_3 +; BE-NEXT: .LBB18_2: +; BE-NEXT: clrldi r4, r3, 53 +; BE-NEXT: addi r4, r4, 2047 +; BE-NEXT: or r4, r4, r3 +; BE-NEXT: rldicr r4, r4, 0, 52 +; BE-NEXT: .LBB18_3: +; BE-NEXT: rldicl r5, r3, 10, 54 +; BE-NEXT: clrldi r6, r3, 63 +; BE-NEXT: std r4, 112(r1) +; BE-NEXT: addi r5, r5, 1 +; BE-NEXT: cmpldi r5, 1 +; BE-NEXT: rldicl r5, r3, 63, 1 +; BE-NEXT: or r4, r6, r5 +; BE-NEXT: ble cr0, .LBB18_5 +; BE-NEXT: # %bb.4: +; BE-NEXT: clrldi r4, r4, 53 +; BE-NEXT: addi r4, r4, 2047 +; BE-NEXT: or r4, r4, r5 +; BE-NEXT: rldicl r4, r4, 53, 11 +; BE-NEXT: rldicl r4, r4, 11, 1 +; BE-NEXT: .LBB18_5: +; BE-NEXT: cmpdi r3, 0 +; BE-NEXT: std r4, 120(r1) +; BE-NEXT: bc 12, lt, .LBB18_7 +; BE-NEXT: # %bb.6: +; BE-NEXT: lfd f0, 112(r1) +; BE-NEXT: fcfid f0, f0 +; BE-NEXT: frsp f1, f0 +; BE-NEXT: b .LBB18_8 +; BE-NEXT: .LBB18_7: +; BE-NEXT: lfd f0, 120(r1) +; BE-NEXT: fcfid f0, f0 +; BE-NEXT: frsp f0, f0 +; BE-NEXT: fadds f1, f0, f0 +; BE-NEXT: .LBB18_8: +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r3, 0(r30) +; BE-NEXT: ld r30, 128(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 144 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %r = uitofp i64 %a to half + store half %r, ptr %p + ret void +} +define <4 x float> @test_extend32_vec4(ptr %p) nounwind { +; PPC32-LABEL: test_extend32_vec4: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -48(r1) +; PPC32-NEXT: stw r0, 52(r1) +; PPC32-NEXT: stw r30, 16(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: stfd f29, 24(r1) # 8-byte Folded Spill +; PPC32-NEXT: stfd f30, 32(r1) # 8-byte Folded Spill +; PPC32-NEXT: stfd f31, 40(r1) # 8-byte Folded Spill +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lhz r3, 2(r30) +; PPC32-NEXT: fmr f31, f1 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lhz r3, 4(r30) +; PPC32-NEXT: fmr f30, f1 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lhz r3, 6(r30) +; PPC32-NEXT: fmr f29, f1 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: fmr f4, f1 +; PPC32-NEXT: fmr f1, f31 +; PPC32-NEXT: fmr f2, f30 +; PPC32-NEXT: fmr f3, f29 +; PPC32-NEXT: lfd f31, 40(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f30, 32(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f29, 24(r1) # 8-byte Folded Reload +; PPC32-NEXT: lwz r30, 16(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 52(r1) +; PPC32-NEXT: addi r1, r1, 48 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_extend32_vec4: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -112(r1) +; P8-NEXT: li r4, 48 +; P8-NEXT: std r0, 128(r1) +; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill +; P8-NEXT: mr r30, r3 +; P8-NEXT: lhz r3, 6(r3) +; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill +; P8-NEXT: li r4, 64 +; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill +; P8-NEXT: li r4, 80 +; P8-NEXT: stxvd2x vs63, r1, r4 # 16-byte Folded Spill +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: lhz r3, 2(r30) +; P8-NEXT: xxlor vs63, f1, f1 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: lhz r3, 4(r30) +; P8-NEXT: xxlor vs62, f1, f1 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: lhz r3, 0(r30) +; P8-NEXT: xxlor vs61, f1, f1 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: li r3, 80 +; P8-NEXT: xxmrghd vs0, vs61, vs1 +; P8-NEXT: xxmrghd vs1, vs63, vs62 +; P8-NEXT: ld r30, 96(r1) # 8-byte Folded Reload +; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload +; P8-NEXT: li r3, 64 +; P8-NEXT: xvcvdpsp vs34, vs0 +; P8-NEXT: xvcvdpsp vs35, vs1 +; P8-NEXT: lxvd2x vs62, r1, r3 # 16-byte Folded Reload +; P8-NEXT: li r3, 48 +; P8-NEXT: lxvd2x vs61, r1, r3 # 16-byte Folded Reload +; P8-NEXT: vmrgew v2, v3, v2 +; P8-NEXT: addi r1, r1, 112 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_extend32_vec4: +; P9: # %bb.0: +; P9-NEXT: lhz r4, 6(r3) +; P9-NEXT: mtfprwz f0, r4 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: lhz r4, 2(r3) +; P9-NEXT: mtfprwz f1, r4 +; P9-NEXT: xscvhpdp f1, f1 +; P9-NEXT: lhz r4, 4(r3) +; P9-NEXT: mtfprwz f2, r4 +; P9-NEXT: xscvhpdp f2, f2 +; P9-NEXT: lhz r3, 0(r3) +; P9-NEXT: xxmrghd vs0, vs0, vs1 +; P9-NEXT: mtfprwz f3, r3 +; P9-NEXT: xvcvdpsp vs35, vs0 +; P9-NEXT: xscvhpdp f3, f3 +; P9-NEXT: xxmrghd vs2, vs2, vs3 +; P9-NEXT: xvcvdpsp vs34, vs2 +; P9-NEXT: vmrgew v2, v3, v2 +; P9-NEXT: blr +; +; SOFT-LABEL: test_extend32_vec4: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -80(r1) +; SOFT-NEXT: std r0, 96(r1) +; SOFT-NEXT: mr r30, r3 +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r29, r3 +; SOFT-NEXT: lhz r3, 2(r30) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r28, r3 +; SOFT-NEXT: lhz r3, 4(r30) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r27, r3 +; SOFT-NEXT: lhz r3, 6(r30) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r6, r3 +; SOFT-NEXT: mr r3, r29 +; SOFT-NEXT: mr r4, r28 +; SOFT-NEXT: mr r5, r27 +; SOFT-NEXT: addi r1, r1, 80 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload +; SOFT-NEXT: blr +; +; BE-LABEL: test_extend32_vec4: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -176(r1) +; BE-NEXT: std r0, 192(r1) +; BE-NEXT: std r30, 136(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r3 +; BE-NEXT: lhz r3, 0(r3) +; BE-NEXT: stfd f29, 152(r1) # 8-byte Folded Spill +; BE-NEXT: stfd f30, 160(r1) # 8-byte Folded Spill +; BE-NEXT: stfd f31, 168(r1) # 8-byte Folded Spill +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: lhz r3, 2(r30) +; BE-NEXT: fmr f31, f1 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: lhz r3, 4(r30) +; BE-NEXT: fmr f30, f1 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: lhz r3, 6(r30) +; BE-NEXT: fmr f29, f1 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: stfs f29, 120(r1) +; BE-NEXT: addi r3, r1, 112 +; BE-NEXT: stfs f30, 116(r1) +; BE-NEXT: stfs f31, 112(r1) +; BE-NEXT: stfs f1, 124(r1) +; BE-NEXT: lvx v2, 0, r3 +; BE-NEXT: lfd f31, 168(r1) # 8-byte Folded Reload +; BE-NEXT: lfd f30, 160(r1) # 8-byte Folded Reload +; BE-NEXT: lfd f29, 152(r1) # 8-byte Folded Reload +; BE-NEXT: ld r30, 136(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 176 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %a = load <4 x half>, ptr %p, align 8 + %b = fpext <4 x half> %a to <4 x float> + ret <4 x float> %b +} +define <4 x double> @test_extend64_vec4(ptr %p) nounwind { +; PPC32-LABEL: test_extend64_vec4: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -48(r1) +; PPC32-NEXT: stw r0, 52(r1) +; PPC32-NEXT: stw r30, 16(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: lhz r3, 0(r3) +; PPC32-NEXT: stfd f29, 24(r1) # 8-byte Folded Spill +; PPC32-NEXT: stfd f30, 32(r1) # 8-byte Folded Spill +; PPC32-NEXT: stfd f31, 40(r1) # 8-byte Folded Spill +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lhz r3, 2(r30) +; PPC32-NEXT: fmr f31, f1 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lhz r3, 4(r30) +; PPC32-NEXT: fmr f30, f1 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lhz r3, 6(r30) +; PPC32-NEXT: fmr f29, f1 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: fmr f4, f1 +; PPC32-NEXT: fmr f1, f31 +; PPC32-NEXT: fmr f2, f30 +; PPC32-NEXT: fmr f3, f29 +; PPC32-NEXT: lfd f31, 40(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f30, 32(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f29, 24(r1) # 8-byte Folded Reload +; PPC32-NEXT: lwz r30, 16(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 52(r1) +; PPC32-NEXT: addi r1, r1, 48 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_extend64_vec4: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -112(r1) +; P8-NEXT: li r4, 48 +; P8-NEXT: std r0, 128(r1) +; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill +; P8-NEXT: mr r30, r3 +; P8-NEXT: lhz r3, 6(r3) +; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill +; P8-NEXT: li r4, 64 +; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill +; P8-NEXT: li r4, 80 +; P8-NEXT: stxvd2x vs63, r1, r4 # 16-byte Folded Spill +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: lhz r3, 4(r30) +; P8-NEXT: xxlor vs63, f1, f1 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: lhz r3, 2(r30) +; P8-NEXT: xxlor vs62, f1, f1 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: lhz r3, 0(r30) +; P8-NEXT: xxlor vs61, f1, f1 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: li r3, 80 +; P8-NEXT: xxmrghd vs35, vs63, vs62 +; P8-NEXT: xxmrghd vs34, vs61, vs1 +; P8-NEXT: ld r30, 96(r1) # 8-byte Folded Reload +; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload +; P8-NEXT: li r3, 64 +; P8-NEXT: lxvd2x vs62, r1, r3 # 16-byte Folded Reload +; P8-NEXT: li r3, 48 +; P8-NEXT: lxvd2x vs61, r1, r3 # 16-byte Folded Reload +; P8-NEXT: addi r1, r1, 112 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_extend64_vec4: +; P9: # %bb.0: +; P9-NEXT: lhz r4, 6(r3) +; P9-NEXT: lhz r5, 4(r3) +; P9-NEXT: lhz r6, 2(r3) +; P9-NEXT: lhz r3, 0(r3) +; P9-NEXT: mtfprwz f0, r3 +; P9-NEXT: mtfprwz f1, r6 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: xscvhpdp f1, f1 +; P9-NEXT: xxmrghd vs34, vs1, vs0 +; P9-NEXT: mtfprwz f0, r5 +; P9-NEXT: mtfprwz f1, r4 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: xscvhpdp f1, f1 +; P9-NEXT: xxmrghd vs35, vs1, vs0 +; P9-NEXT: blr +; +; SOFT-LABEL: test_extend64_vec4: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -80(r1) +; SOFT-NEXT: std r0, 96(r1) +; SOFT-NEXT: mr r30, r3 +; SOFT-NEXT: lhz r3, 0(r3) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __extendsfdf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r29, r3 +; SOFT-NEXT: lhz r3, 2(r30) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __extendsfdf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r28, r3 +; SOFT-NEXT: lhz r3, 4(r30) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __extendsfdf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r27, r3 +; SOFT-NEXT: lhz r3, 6(r30) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __extendsfdf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r6, r3 +; SOFT-NEXT: mr r3, r29 +; SOFT-NEXT: mr r4, r28 +; SOFT-NEXT: mr r5, r27 +; SOFT-NEXT: addi r1, r1, 80 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload +; SOFT-NEXT: blr +; +; BE-LABEL: test_extend64_vec4: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -160(r1) +; BE-NEXT: std r0, 176(r1) +; BE-NEXT: std r30, 120(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r3 +; BE-NEXT: lhz r3, 6(r3) +; BE-NEXT: stfd f29, 136(r1) # 8-byte Folded Spill +; BE-NEXT: stfd f30, 144(r1) # 8-byte Folded Spill +; BE-NEXT: stfd f31, 152(r1) # 8-byte Folded Spill +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: lhz r3, 4(r30) +; BE-NEXT: fmr f31, f1 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: lhz r3, 2(r30) +; BE-NEXT: fmr f30, f1 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: lhz r3, 0(r30) +; BE-NEXT: fmr f29, f1 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: fmr f2, f29 +; BE-NEXT: fmr f3, f30 +; BE-NEXT: lfd f30, 144(r1) # 8-byte Folded Reload +; BE-NEXT: lfd f29, 136(r1) # 8-byte Folded Reload +; BE-NEXT: fmr f4, f31 +; BE-NEXT: lfd f31, 152(r1) # 8-byte Folded Reload +; BE-NEXT: ld r30, 120(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 160 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %a = load <4 x half>, ptr %p, align 8 + %b = fpext <4 x half> %a to <4 x double> + ret <4 x double> %b +} +define void @test_trunc32_vec4(<4 x float> %a, ptr %p) nounwind { +; PPC32-LABEL: test_trunc32_vec4: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -64(r1) +; PPC32-NEXT: stw r0, 68(r1) +; PPC32-NEXT: stw r27, 20(r1) # 4-byte Folded Spill +; PPC32-NEXT: stw r28, 24(r1) # 4-byte Folded Spill +; PPC32-NEXT: stw r29, 28(r1) # 4-byte Folded Spill +; PPC32-NEXT: stw r30, 32(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: stfd f29, 40(r1) # 8-byte Folded Spill +; PPC32-NEXT: fmr f29, f2 +; PPC32-NEXT: stfd f30, 48(r1) # 8-byte Folded Spill +; PPC32-NEXT: fmr f30, f3 +; PPC32-NEXT: stfd f31, 56(r1) # 8-byte Folded Spill +; PPC32-NEXT: fmr f31, f4 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: fmr f1, f29 +; PPC32-NEXT: mr r29, r3 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: fmr f1, f30 +; PPC32-NEXT: mr r28, r3 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: fmr f1, f31 +; PPC32-NEXT: mr r27, r3 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: sth r27, 4(r30) +; PPC32-NEXT: sth r28, 2(r30) +; PPC32-NEXT: sth r3, 6(r30) +; PPC32-NEXT: sth r29, 0(r30) +; PPC32-NEXT: lfd f31, 56(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f30, 48(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f29, 40(r1) # 8-byte Folded Reload +; PPC32-NEXT: lwz r30, 32(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r29, 28(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r28, 24(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r27, 20(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 68(r1) +; PPC32-NEXT: addi r1, r1, 64 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_trunc32_vec4: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -112(r1) +; P8-NEXT: xxsldwi vs0, vs34, vs34, 3 +; P8-NEXT: li r3, 48 +; P8-NEXT: std r0, 128(r1) +; P8-NEXT: std r27, 72(r1) # 8-byte Folded Spill +; P8-NEXT: std r28, 80(r1) # 8-byte Folded Spill +; P8-NEXT: std r29, 88(r1) # 8-byte Folded Spill +; P8-NEXT: xscvspdpn f1, vs0 +; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill +; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill +; P8-NEXT: mr r30, r5 +; P8-NEXT: vmr v31, v2 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: xxswapd vs0, vs63 +; P8-NEXT: mr r29, r3 +; P8-NEXT: xscvspdpn f1, vs0 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: xxsldwi vs0, vs63, vs63, 1 +; P8-NEXT: mr r28, r3 +; P8-NEXT: xscvspdpn f1, vs0 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: xscvspdpn f1, vs63 +; P8-NEXT: mr r27, r3 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 6(r30) +; P8-NEXT: li r3, 48 +; P8-NEXT: sth r27, 4(r30) +; P8-NEXT: ld r27, 72(r1) # 8-byte Folded Reload +; P8-NEXT: sth r28, 2(r30) +; P8-NEXT: sth r29, 0(r30) +; P8-NEXT: ld r30, 96(r1) # 8-byte Folded Reload +; P8-NEXT: ld r29, 88(r1) # 8-byte Folded Reload +; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload +; P8-NEXT: ld r28, 80(r1) # 8-byte Folded Reload +; P8-NEXT: addi r1, r1, 112 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_trunc32_vec4: +; P9: # %bb.0: +; P9-NEXT: xxsldwi vs0, vs34, vs34, 3 +; P9-NEXT: xxsldwi vs1, vs34, vs34, 1 +; P9-NEXT: xscvspdpn f0, vs0 +; P9-NEXT: xscvspdpn f1, vs1 +; P9-NEXT: xscvdphp f0, f0 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: xxswapd vs0, vs34 +; P9-NEXT: xscvspdpn f0, vs0 +; P9-NEXT: xscvdphp f0, f0 +; P9-NEXT: xscvdphp f1, f1 +; P9-NEXT: mffprwz r4, f1 +; P9-NEXT: xscvspdpn f1, vs34 +; P9-NEXT: xscvdphp f1, f1 +; P9-NEXT: sth r4, 4(r5) +; P9-NEXT: mffprwz r4, f0 +; P9-NEXT: sth r3, 0(r5) +; P9-NEXT: sth r4, 2(r5) +; P9-NEXT: mffprwz r6, f1 +; P9-NEXT: sth r6, 6(r5) +; P9-NEXT: blr +; +; SOFT-LABEL: test_trunc32_vec4: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -80(r1) +; SOFT-NEXT: mr r27, r3 +; SOFT-NEXT: clrldi r3, r6, 32 +; SOFT-NEXT: std r0, 96(r1) +; SOFT-NEXT: mr r30, r7 +; SOFT-NEXT: mr r29, r5 +; SOFT-NEXT: mr r28, r4 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r26, r3 +; SOFT-NEXT: clrldi r3, r29, 32 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r29, r3 +; SOFT-NEXT: clrldi r3, r28, 32 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r28, r3 +; SOFT-NEXT: clrldi r3, r27, 32 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r27, r3 +; SOFT-NEXT: clrldi r3, r28, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r28, r3 +; SOFT-NEXT: clrldi r3, r29, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r29, r3 +; SOFT-NEXT: clrldi r3, r26, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 6(r30) +; SOFT-NEXT: mr r3, r29 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 4(r30) +; SOFT-NEXT: mr r3, r28 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 2(r30) +; SOFT-NEXT: mr r3, r27 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 80 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r26, -48(r1) # 8-byte Folded Reload +; SOFT-NEXT: blr +; +; BE-LABEL: test_trunc32_vec4: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -176(r1) +; BE-NEXT: addi r3, r1, 112 +; BE-NEXT: std r0, 192(r1) +; BE-NEXT: std r27, 136(r1) # 8-byte Folded Spill +; BE-NEXT: std r28, 144(r1) # 8-byte Folded Spill +; BE-NEXT: std r29, 152(r1) # 8-byte Folded Spill +; BE-NEXT: std r30, 160(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r5 +; BE-NEXT: stvx v2, 0, r3 +; BE-NEXT: lfs f1, 112(r1) +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: lfs f1, 116(r1) +; BE-NEXT: mr r29, r3 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: lfs f1, 120(r1) +; BE-NEXT: mr r28, r3 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: lfs f1, 124(r1) +; BE-NEXT: mr r27, r3 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r27, 4(r30) +; BE-NEXT: sth r28, 2(r30) +; BE-NEXT: sth r3, 6(r30) +; BE-NEXT: sth r29, 0(r30) +; BE-NEXT: ld r30, 160(r1) # 8-byte Folded Reload +; BE-NEXT: ld r29, 152(r1) # 8-byte Folded Reload +; BE-NEXT: ld r28, 144(r1) # 8-byte Folded Reload +; BE-NEXT: ld r27, 136(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 176 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %v = fptrunc <4 x float> %a to <4 x half> + store <4 x half> %v, ptr %p + ret void +} +define void @test_trunc64_vec4(<4 x double> %a, ptr %p) nounwind { +; PPC32-LABEL: test_trunc64_vec4: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -64(r1) +; PPC32-NEXT: stw r0, 68(r1) +; PPC32-NEXT: stw r27, 20(r1) # 4-byte Folded Spill +; PPC32-NEXT: stw r28, 24(r1) # 4-byte Folded Spill +; PPC32-NEXT: stw r29, 28(r1) # 4-byte Folded Spill +; PPC32-NEXT: stw r30, 32(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: stfd f29, 40(r1) # 8-byte Folded Spill +; PPC32-NEXT: fmr f29, f2 +; PPC32-NEXT: stfd f30, 48(r1) # 8-byte Folded Spill +; PPC32-NEXT: fmr f30, f3 +; PPC32-NEXT: stfd f31, 56(r1) # 8-byte Folded Spill +; PPC32-NEXT: fmr f31, f4 +; PPC32-NEXT: bl __truncdfhf2 +; PPC32-NEXT: fmr f1, f29 +; PPC32-NEXT: mr r29, r3 +; PPC32-NEXT: bl __truncdfhf2 +; PPC32-NEXT: fmr f1, f30 +; PPC32-NEXT: mr r28, r3 +; PPC32-NEXT: bl __truncdfhf2 +; PPC32-NEXT: fmr f1, f31 +; PPC32-NEXT: mr r27, r3 +; PPC32-NEXT: bl __truncdfhf2 +; PPC32-NEXT: sth r27, 4(r30) +; PPC32-NEXT: sth r28, 2(r30) +; PPC32-NEXT: sth r3, 6(r30) +; PPC32-NEXT: sth r29, 0(r30) +; PPC32-NEXT: lfd f31, 56(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f30, 48(r1) # 8-byte Folded Reload +; PPC32-NEXT: lfd f29, 40(r1) # 8-byte Folded Reload +; PPC32-NEXT: lwz r30, 32(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r29, 28(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r28, 24(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r27, 20(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 68(r1) +; PPC32-NEXT: addi r1, r1, 64 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_trunc64_vec4: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -128(r1) +; P8-NEXT: li r3, 48 +; P8-NEXT: std r0, 144(r1) +; P8-NEXT: xxswapd vs1, vs34 +; P8-NEXT: std r27, 88(r1) # 8-byte Folded Spill +; P8-NEXT: std r28, 96(r1) # 8-byte Folded Spill +; P8-NEXT: std r29, 104(r1) # 8-byte Folded Spill +; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill +; P8-NEXT: mr r30, r7 +; P8-NEXT: stxvd2x vs62, r1, r3 # 16-byte Folded Spill +; P8-NEXT: li r3, 64 +; P8-NEXT: vmr v30, v2 +; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill +; P8-NEXT: vmr v31, v3 +; P8-NEXT: bl __truncdfhf2 +; P8-NEXT: nop +; P8-NEXT: xxswapd vs1, vs63 +; P8-NEXT: mr r29, r3 +; P8-NEXT: bl __truncdfhf2 +; P8-NEXT: nop +; P8-NEXT: xxlor f1, vs62, vs62 +; P8-NEXT: mr r28, r3 +; P8-NEXT: bl __truncdfhf2 +; P8-NEXT: nop +; P8-NEXT: xxlor f1, vs63, vs63 +; P8-NEXT: mr r27, r3 +; P8-NEXT: bl __truncdfhf2 +; P8-NEXT: nop +; P8-NEXT: sth r3, 6(r30) +; P8-NEXT: li r3, 64 +; P8-NEXT: sth r27, 2(r30) +; P8-NEXT: ld r27, 88(r1) # 8-byte Folded Reload +; P8-NEXT: sth r28, 4(r30) +; P8-NEXT: sth r29, 0(r30) +; P8-NEXT: ld r30, 112(r1) # 8-byte Folded Reload +; P8-NEXT: ld r29, 104(r1) # 8-byte Folded Reload +; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload +; P8-NEXT: li r3, 48 +; P8-NEXT: ld r28, 96(r1) # 8-byte Folded Reload +; P8-NEXT: lxvd2x vs62, r1, r3 # 16-byte Folded Reload +; P8-NEXT: addi r1, r1, 128 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_trunc64_vec4: +; P9: # %bb.0: +; P9-NEXT: xxswapd vs0, vs34 +; P9-NEXT: xscvdphp f0, f0 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: xxswapd vs0, vs35 +; P9-NEXT: xscvdphp f0, f0 +; P9-NEXT: xscvdphp f1, vs34 +; P9-NEXT: mffprwz r4, f1 +; P9-NEXT: xscvdphp f1, vs35 +; P9-NEXT: sth r3, 0(r7) +; P9-NEXT: sth r4, 2(r7) +; P9-NEXT: mffprwz r4, f0 +; P9-NEXT: sth r4, 4(r7) +; P9-NEXT: mffprwz r5, f1 +; P9-NEXT: sth r5, 6(r7) +; P9-NEXT: blr +; +; SOFT-LABEL: test_trunc64_vec4: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -80(r1) +; SOFT-NEXT: mr r27, r3 +; SOFT-NEXT: mr r3, r6 +; SOFT-NEXT: std r0, 96(r1) +; SOFT-NEXT: mr r30, r7 +; SOFT-NEXT: mr r29, r5 +; SOFT-NEXT: mr r28, r4 +; SOFT-NEXT: bl __truncdfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r26, r3 +; SOFT-NEXT: mr r3, r29 +; SOFT-NEXT: bl __truncdfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r29, r3 +; SOFT-NEXT: mr r3, r28 +; SOFT-NEXT: bl __truncdfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r28, r3 +; SOFT-NEXT: mr r3, r27 +; SOFT-NEXT: bl __truncdfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r27, r3 +; SOFT-NEXT: clrldi r3, r28, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r28, r3 +; SOFT-NEXT: clrldi r3, r29, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r29, r3 +; SOFT-NEXT: clrldi r3, r26, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 6(r30) +; SOFT-NEXT: mr r3, r29 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 4(r30) +; SOFT-NEXT: mr r3, r28 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 2(r30) +; SOFT-NEXT: mr r3, r27 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: sth r3, 0(r30) +; SOFT-NEXT: addi r1, r1, 80 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r26, -48(r1) # 8-byte Folded Reload +; SOFT-NEXT: blr +; +; BE-LABEL: test_trunc64_vec4: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -176(r1) +; BE-NEXT: std r0, 192(r1) +; BE-NEXT: std r27, 112(r1) # 8-byte Folded Spill +; BE-NEXT: std r28, 120(r1) # 8-byte Folded Spill +; BE-NEXT: std r29, 128(r1) # 8-byte Folded Spill +; BE-NEXT: std r30, 136(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r7 +; BE-NEXT: stfd f29, 152(r1) # 8-byte Folded Spill +; BE-NEXT: fmr f29, f2 +; BE-NEXT: stfd f30, 160(r1) # 8-byte Folded Spill +; BE-NEXT: fmr f30, f3 +; BE-NEXT: stfd f31, 168(r1) # 8-byte Folded Spill +; BE-NEXT: fmr f31, f4 +; BE-NEXT: bl __truncdfhf2 +; BE-NEXT: nop +; BE-NEXT: fmr f1, f29 +; BE-NEXT: mr r29, r3 +; BE-NEXT: bl __truncdfhf2 +; BE-NEXT: nop +; BE-NEXT: fmr f1, f30 +; BE-NEXT: mr r28, r3 +; BE-NEXT: bl __truncdfhf2 +; BE-NEXT: nop +; BE-NEXT: fmr f1, f31 +; BE-NEXT: mr r27, r3 +; BE-NEXT: bl __truncdfhf2 +; BE-NEXT: nop +; BE-NEXT: sth r27, 4(r30) +; BE-NEXT: sth r28, 2(r30) +; BE-NEXT: sth r3, 6(r30) +; BE-NEXT: sth r29, 0(r30) +; BE-NEXT: lfd f31, 168(r1) # 8-byte Folded Reload +; BE-NEXT: lfd f30, 160(r1) # 8-byte Folded Reload +; BE-NEXT: lfd f29, 152(r1) # 8-byte Folded Reload +; BE-NEXT: ld r30, 136(r1) # 8-byte Folded Reload +; BE-NEXT: ld r29, 128(r1) # 8-byte Folded Reload +; BE-NEXT: ld r28, 120(r1) # 8-byte Folded Reload +; BE-NEXT: ld r27, 112(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 176 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %v = fptrunc <4 x double> %a to <4 x half> + store <4 x half> %v, ptr %p + ret void +} +define float @test_sitofp_fadd_i32(i32 %a, ptr %b) nounwind { +; PPC32-LABEL: test_sitofp_fadd_i32: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -32(r1) +; PPC32-NEXT: stw r0, 36(r1) +; PPC32-NEXT: stw r30, 16(r1) # 4-byte Folded Spill +; PPC32-NEXT: mr r30, r3 +; PPC32-NEXT: lhz r3, 0(r4) +; PPC32-NEXT: stfd f31, 24(r1) # 8-byte Folded Spill +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lis r3, 17200 +; PPC32-NEXT: stw r3, 8(r1) +; PPC32-NEXT: xoris r3, r30, 32768 +; PPC32-NEXT: stw r3, 12(r1) +; PPC32-NEXT: lis r3, .LCPI23_0@ha +; PPC32-NEXT: fmr f31, f1 +; PPC32-NEXT: lfd f0, 8(r1) +; PPC32-NEXT: lfs f1, .LCPI23_0@l(r3) +; PPC32-NEXT: fsub f0, f0, f1 +; PPC32-NEXT: frsp f1, f0 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: clrlwi r3, r3, 16 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: fadds f1, f31, f1 +; PPC32-NEXT: lfd f31, 24(r1) # 8-byte Folded Reload +; PPC32-NEXT: lwz r30, 16(r1) # 4-byte Folded Reload +; PPC32-NEXT: lwz r0, 36(r1) +; PPC32-NEXT: addi r1, r1, 32 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: test_sitofp_fadd_i32: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: std r30, -24(r1) # 8-byte Folded Spill +; P8-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -64(r1) +; P8-NEXT: std r0, 80(r1) +; P8-NEXT: mr r30, r3 +; P8-NEXT: lhz r3, 0(r4) +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: mtfprwa f0, r30 +; P8-NEXT: fmr f31, f1 +; P8-NEXT: xscvsxdsp f1, f0 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: clrldi r3, r3, 48 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: xsaddsp f1, f31, f1 +; P8-NEXT: addi r1, r1, 64 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload +; P8-NEXT: ld r30, -24(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: test_sitofp_fadd_i32: +; P9: # %bb.0: +; P9-NEXT: mtfprwa f1, r3 +; P9-NEXT: lhz r4, 0(r4) +; P9-NEXT: xscvsxdsp f1, f1 +; P9-NEXT: mtfprwz f0, r4 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: xscvdphp f1, f1 +; P9-NEXT: mffprwz r3, f1 +; P9-NEXT: clrlwi r3, r3, 16 +; P9-NEXT: mtfprwz f1, r3 +; P9-NEXT: xscvhpdp f1, f1 +; P9-NEXT: xsaddsp f1, f0, f1 +; P9-NEXT: blr +; +; SOFT-LABEL: test_sitofp_fadd_i32: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -64(r1) +; SOFT-NEXT: std r0, 80(r1) +; SOFT-NEXT: mr r30, r3 +; SOFT-NEXT: lhz r3, 0(r4) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r29, r3 +; SOFT-NEXT: extsw r3, r30 +; SOFT-NEXT: bl __floatsisf +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 32 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: mr r4, r3 +; SOFT-NEXT: mr r3, r29 +; SOFT-NEXT: bl __addsf3 +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 64 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: test_sitofp_fadd_i32: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -144(r1) +; BE-NEXT: std r0, 160(r1) +; BE-NEXT: std r30, 120(r1) # 8-byte Folded Spill +; BE-NEXT: mr r30, r3 +; BE-NEXT: lhz r3, 0(r4) +; BE-NEXT: stfd f31, 136(r1) # 8-byte Folded Spill +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: extsw r3, r30 +; BE-NEXT: fmr f31, f1 +; BE-NEXT: std r3, 112(r1) +; BE-NEXT: lfd f0, 112(r1) +; BE-NEXT: fcfid f0, f0 +; BE-NEXT: frsp f1, f0 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: clrldi r3, r3, 48 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: fadds f1, f31, f1 +; BE-NEXT: lfd f31, 136(r1) # 8-byte Folded Reload +; BE-NEXT: ld r30, 120(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 144 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %tmp0 = load half, ptr %b + %tmp1 = sitofp i32 %a to half + %tmp2 = fadd half %tmp0, %tmp1 + %tmp3 = fpext half %tmp2 to float + ret float %tmp3 +} +define half @PR40273(half) nounwind { +; PPC32-LABEL: PR40273: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: clrlwi r3, r3, 16 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: lis r3, .LCPI24_0@ha +; PPC32-NEXT: lfs f0, .LCPI24_0@l(r3) +; PPC32-NEXT: li r3, 0 +; PPC32-NEXT: fcmpu cr0, f1, f0 +; PPC32-NEXT: bc 12, eq, .LBB24_2 +; PPC32-NEXT: # %bb.1: +; PPC32-NEXT: li r3, 4 +; PPC32-NEXT: .LBB24_2: +; PPC32-NEXT: li r4, .LCPI24_1@l +; PPC32-NEXT: addis r4, r4, .LCPI24_1@ha +; PPC32-NEXT: lfsx f1, r4, r3 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: PR40273: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: clrldi r3, r3, 48 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: fmr f0, f1 +; P8-NEXT: xxlxor f1, f1, f1 +; P8-NEXT: fcmpu cr0, f0, f1 +; P8-NEXT: beq cr0, .LBB24_2 +; P8-NEXT: # %bb.1: +; P8-NEXT: vspltisw v2, 1 +; P8-NEXT: xvcvsxwdp vs1, vs34 +; P8-NEXT: .LBB24_2: +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: PR40273: +; P9: # %bb.0: +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: xxlxor f1, f1, f1 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: clrlwi r3, r3, 16 +; P9-NEXT: mtfprwz f0, r3 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: fcmpu cr0, f0, f1 +; P9-NEXT: beqlr cr0 +; P9-NEXT: # %bb.1: +; P9-NEXT: vspltisw v2, 1 +; P9-NEXT: xvcvsxwdp vs1, vs34 +; P9-NEXT: blr +; +; SOFT-LABEL: PR40273: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: stdu r1, -32(r1) +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: std r0, 48(r1) +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: li r4, 0 +; SOFT-NEXT: bl __nesf2 +; SOFT-NEXT: nop +; SOFT-NEXT: cmplwi r3, 0 +; SOFT-NEXT: lis r3, 16256 +; SOFT-NEXT: iseleq r3, 0, r3 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 32 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: PR40273: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: clrldi r3, r3, 48 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: addis r3, r2, .LCPI24_0@toc@ha +; BE-NEXT: lfs f0, .LCPI24_0@toc@l(r3) +; BE-NEXT: li r3, 0 +; BE-NEXT: fcmpu cr0, f1, f0 +; BE-NEXT: bc 12, eq, .LBB24_2 +; BE-NEXT: # %bb.1: +; BE-NEXT: li r3, 4 +; BE-NEXT: .LBB24_2: +; BE-NEXT: addis r4, r2, .LCPI24_1@toc@ha +; BE-NEXT: addi r4, r4, .LCPI24_1@toc@l +; BE-NEXT: lfsx f1, r4, r3 +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %2 = fcmp une half %0, 0xH0000 + %3 = uitofp i1 %2 to half + ret half %3 +} + +; Trivial operations shouldn't need a libcall + +define half @fabs(half %x) nounwind { +; PPC32-LABEL: fabs: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -16(r1) +; PPC32-NEXT: stw r0, 20(r1) +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: clrlwi r3, r3, 16 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: fabs f1, f1 +; PPC32-NEXT: lwz r0, 20(r1) +; PPC32-NEXT: addi r1, r1, 16 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: fabs: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stdu r1, -32(r1) +; P8-NEXT: std r0, 48(r1) +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: clrldi r3, r3, 48 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: xsabsdp f1, f1 +; P8-NEXT: addi r1, r1, 32 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: fabs: +; P9: # %bb.0: +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: clrlwi r3, r3, 16 +; P9-NEXT: mtfprwz f0, r3 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: xsabsdp f1, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: fabs: +; SOFT: # %bb.0: +; SOFT-NEXT: clrldi r3, r3, 49 +; SOFT-NEXT: blr +; +; BE-LABEL: fabs: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -112(r1) +; BE-NEXT: std r0, 128(r1) +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: clrldi r3, r3, 48 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: fabs f1, f1 +; BE-NEXT: addi r1, r1, 112 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %a = call half @llvm.fabs.f16(half %x) + ret half %a +} + +define half @fcopysign(half %x, half %y) nounwind { +; PPC32-LABEL: fcopysign: +; PPC32: # %bb.0: +; PPC32-NEXT: mflr r0 +; PPC32-NEXT: stwu r1, -32(r1) +; PPC32-NEXT: stw r0, 36(r1) +; PPC32-NEXT: stfd f31, 24(r1) # 8-byte Folded Spill +; PPC32-NEXT: fmr f31, f2 +; PPC32-NEXT: bl __truncsfhf2 +; PPC32-NEXT: clrlwi r3, r3, 16 +; PPC32-NEXT: bl __extendhfsf2 +; PPC32-NEXT: stfs f31, 20(r1) +; PPC32-NEXT: lwz r3, 20(r1) +; PPC32-NEXT: srwi r3, r3, 31 +; PPC32-NEXT: andi. r3, r3, 1 +; PPC32-NEXT: bc 12, gt, .LBB26_2 +; PPC32-NEXT: # %bb.1: +; PPC32-NEXT: fabs f1, f1 +; PPC32-NEXT: b .LBB26_3 +; PPC32-NEXT: .LBB26_2: +; PPC32-NEXT: fnabs f1, f1 +; PPC32-NEXT: .LBB26_3: +; PPC32-NEXT: lfd f31, 24(r1) # 8-byte Folded Reload +; PPC32-NEXT: lwz r0, 36(r1) +; PPC32-NEXT: addi r1, r1, 32 +; PPC32-NEXT: mtlr r0 +; PPC32-NEXT: blr +; +; P8-LABEL: fcopysign: +; P8: # %bb.0: +; P8-NEXT: mflr r0 +; P8-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill +; P8-NEXT: stdu r1, -48(r1) +; P8-NEXT: std r0, 64(r1) +; P8-NEXT: fmr f31, f2 +; P8-NEXT: bl __truncsfhf2 +; P8-NEXT: nop +; P8-NEXT: clrldi r3, r3, 48 +; P8-NEXT: bl __extendhfsf2 +; P8-NEXT: nop +; P8-NEXT: fcpsgn f1, f31, f1 +; P8-NEXT: addi r1, r1, 48 +; P8-NEXT: ld r0, 16(r1) +; P8-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload +; P8-NEXT: mtlr r0 +; P8-NEXT: blr +; +; P9-LABEL: fcopysign: +; P9: # %bb.0: +; P9-NEXT: xscvdphp f0, f1 +; P9-NEXT: mffprwz r3, f0 +; P9-NEXT: clrlwi r3, r3, 16 +; P9-NEXT: mtfprwz f0, r3 +; P9-NEXT: xscvhpdp f0, f0 +; P9-NEXT: fcpsgn f1, f2, f0 +; P9-NEXT: blr +; +; SOFT-LABEL: fcopysign: +; SOFT: # %bb.0: +; SOFT-NEXT: mflr r0 +; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill +; SOFT-NEXT: stdu r1, -48(r1) +; SOFT-NEXT: clrldi r3, r3, 48 +; SOFT-NEXT: std r0, 64(r1) +; SOFT-NEXT: mr r30, r4 +; SOFT-NEXT: bl __extendhfsf2 +; SOFT-NEXT: nop +; SOFT-NEXT: rlwimi r3, r30, 16, 0, 0 +; SOFT-NEXT: clrldi r3, r3, 32 +; SOFT-NEXT: bl __truncsfhf2 +; SOFT-NEXT: nop +; SOFT-NEXT: addi r1, r1, 48 +; SOFT-NEXT: ld r0, 16(r1) +; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; SOFT-NEXT: mtlr r0 +; SOFT-NEXT: blr +; +; BE-LABEL: fcopysign: +; BE: # %bb.0: +; BE-NEXT: mflr r0 +; BE-NEXT: stdu r1, -128(r1) +; BE-NEXT: std r0, 144(r1) +; BE-NEXT: stfd f31, 120(r1) # 8-byte Folded Spill +; BE-NEXT: fmr f31, f2 +; BE-NEXT: bl __truncsfhf2 +; BE-NEXT: nop +; BE-NEXT: clrldi r3, r3, 48 +; BE-NEXT: bl __extendhfsf2 +; BE-NEXT: nop +; BE-NEXT: stfs f31, 116(r1) +; BE-NEXT: lwz r3, 116(r1) +; BE-NEXT: srwi r3, r3, 31 +; BE-NEXT: andi. r3, r3, 1 +; BE-NEXT: bc 12, gt, .LBB26_2 +; BE-NEXT: # %bb.1: +; BE-NEXT: fabs f1, f1 +; BE-NEXT: b .LBB26_3 +; BE-NEXT: .LBB26_2: +; BE-NEXT: fnabs f1, f1 +; BE-NEXT: .LBB26_3: +; BE-NEXT: lfd f31, 120(r1) # 8-byte Folded Reload +; BE-NEXT: addi r1, r1, 128 +; BE-NEXT: ld r0, 16(r1) +; BE-NEXT: mtlr r0 +; BE-NEXT: blr + %a = call half @llvm.copysign.f16(half %x, half %y) + ret half %a +} diff --git a/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll b/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll deleted file mode 100644 index 50f05cca8045..000000000000 --- a/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll +++ /dev/null @@ -1,1281 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ -; RUN: --check-prefix=P8 -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s -; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -mattr=-hard-float \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s \ -; RUN: --check-prefix=SOFT - -; Tests for various operations on half precison float. Much of the test is -; copied from test/CodeGen/X86/half.ll. -define dso_local double @loadd(ptr nocapture readonly %a) local_unnamed_addr #0 { -; P8-LABEL: loadd: -; P8: # %bb.0: # %entry -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -32(r1) -; P8-NEXT: std r0, 48(r1) -; P8-NEXT: lhz r3, 2(r3) -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: addi r1, r1, 32 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: loadd: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi r3, r3, 2 -; CHECK-NEXT: lxsihzx f0, 0, r3 -; CHECK-NEXT: xscvhpdp f1, f0 -; CHECK-NEXT: blr -; -; SOFT-LABEL: loadd: -; SOFT: # %bb.0: # %entry -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: stdu r1, -32(r1) -; SOFT-NEXT: std r0, 48(r1) -; SOFT-NEXT: lhz r3, 2(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __extendsfdf2 -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 32 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr -entry: - %arrayidx = getelementptr inbounds i16, ptr %a, i64 1 - %0 = load i16, ptr %arrayidx, align 2 - %1 = tail call double @llvm.convert.from.fp16.f64(i16 %0) - ret double %1 -} - -declare double @llvm.convert.from.fp16.f64(i16) - -define dso_local float @loadf(ptr nocapture readonly %a) local_unnamed_addr #0 { -; P8-LABEL: loadf: -; P8: # %bb.0: # %entry -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -32(r1) -; P8-NEXT: std r0, 48(r1) -; P8-NEXT: lhz r3, 2(r3) -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: addi r1, r1, 32 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: loadf: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: addi r3, r3, 2 -; CHECK-NEXT: lxsihzx f0, 0, r3 -; CHECK-NEXT: xscvhpdp f1, f0 -; CHECK-NEXT: blr -; -; SOFT-LABEL: loadf: -; SOFT: # %bb.0: # %entry -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: stdu r1, -32(r1) -; SOFT-NEXT: std r0, 48(r1) -; SOFT-NEXT: lhz r3, 2(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 32 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr -entry: - %arrayidx = getelementptr inbounds i16, ptr %a, i64 1 - %0 = load i16, ptr %arrayidx, align 2 - %1 = tail call float @llvm.convert.from.fp16.f32(i16 %0) - ret float %1 -} - -declare float @llvm.convert.from.fp16.f32(i16) - -define dso_local void @stored(ptr nocapture %a, double %b) local_unnamed_addr #0 { -; P8-LABEL: stored: -; P8: # %bb.0: # %entry -; P8-NEXT: mflr r0 -; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; P8-NEXT: stdu r1, -48(r1) -; P8-NEXT: std r0, 64(r1) -; P8-NEXT: mr r30, r3 -; P8-NEXT: bl __truncdfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 0(r30) -; P8-NEXT: addi r1, r1, 48 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: stored: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvdphp f0, f1 -; CHECK-NEXT: stxsihx f0, 0, r3 -; CHECK-NEXT: blr -; -; SOFT-LABEL: stored: -; SOFT: # %bb.0: # %entry -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -48(r1) -; SOFT-NEXT: mr r30, r3 -; SOFT-NEXT: mr r3, r4 -; SOFT-NEXT: std r0, 64(r1) -; SOFT-NEXT: bl __truncdfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 48 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr -entry: - %0 = tail call i16 @llvm.convert.to.fp16.f64(double %b) - store i16 %0, ptr %a, align 2 - ret void -} - -declare i16 @llvm.convert.to.fp16.f64(double) - -define dso_local void @storef(ptr nocapture %a, float %b) local_unnamed_addr #0 { -; P8-LABEL: storef: -; P8: # %bb.0: # %entry -; P8-NEXT: mflr r0 -; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; P8-NEXT: stdu r1, -48(r1) -; P8-NEXT: std r0, 64(r1) -; P8-NEXT: mr r30, r3 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 0(r30) -; P8-NEXT: addi r1, r1, 48 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: storef: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xscvdphp f0, f1 -; CHECK-NEXT: stxsihx f0, 0, r3 -; CHECK-NEXT: blr -; -; SOFT-LABEL: storef: -; SOFT: # %bb.0: # %entry -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -48(r1) -; SOFT-NEXT: mr r30, r3 -; SOFT-NEXT: clrldi r3, r4, 32 -; SOFT-NEXT: std r0, 64(r1) -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 48 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr -entry: - %0 = tail call i16 @llvm.convert.to.fp16.f32(float %b) - store i16 %0, ptr %a, align 2 - ret void -} - -declare i16 @llvm.convert.to.fp16.f32(float) -define void @test_load_store(ptr %in, ptr %out) #0 { -; P8-LABEL: test_load_store: -; P8: # %bb.0: -; P8-NEXT: lhz r3, 0(r3) -; P8-NEXT: sth r3, 0(r4) -; P8-NEXT: blr -; -; CHECK-LABEL: test_load_store: -; CHECK: # %bb.0: -; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: sth r3, 0(r4) -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_load_store: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -48(r1) -; SOFT-NEXT: std r0, 64(r1) -; SOFT-NEXT: mr r30, r4 -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 48 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %val = load half, ptr %in - store half %val, ptr %out - ret void -} -define i16 @test_bitcast_from_half(ptr %addr) #0 { -; P8-LABEL: test_bitcast_from_half: -; P8: # %bb.0: -; P8-NEXT: lhz r3, 0(r3) -; P8-NEXT: blr -; -; CHECK-LABEL: test_bitcast_from_half: -; CHECK: # %bb.0: -; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_bitcast_from_half: -; SOFT: # %bb.0: -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: blr - %val = load half, ptr %addr - %val_int = bitcast half %val to i16 - ret i16 %val_int -} -define void @test_bitcast_to_half(ptr %addr, i16 %in) #0 { -; P8-LABEL: test_bitcast_to_half: -; P8: # %bb.0: -; P8-NEXT: sth r4, 0(r3) -; P8-NEXT: blr -; -; CHECK-LABEL: test_bitcast_to_half: -; CHECK: # %bb.0: -; CHECK-NEXT: sth r4, 0(r3) -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_bitcast_to_half: -; SOFT: # %bb.0: -; SOFT-NEXT: sth r4, 0(r3) -; SOFT-NEXT: blr - %val_fp = bitcast i16 %in to half - store half %val_fp, ptr %addr - ret void -} -define float @test_extend32(ptr %addr) #0 { -; P8-LABEL: test_extend32: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -32(r1) -; P8-NEXT: std r0, 48(r1) -; P8-NEXT: lhz r3, 0(r3) -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: addi r1, r1, 32 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_extend32: -; CHECK: # %bb.0: -; CHECK-NEXT: lxsihzx f0, 0, r3 -; CHECK-NEXT: xscvhpdp f1, f0 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_extend32: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: stdu r1, -32(r1) -; SOFT-NEXT: std r0, 48(r1) -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 32 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %val16 = load half, ptr %addr - %val32 = fpext half %val16 to float - ret float %val32 -} -define double @test_extend64(ptr %addr) #0 { -; P8-LABEL: test_extend64: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -32(r1) -; P8-NEXT: std r0, 48(r1) -; P8-NEXT: lhz r3, 0(r3) -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: addi r1, r1, 32 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_extend64: -; CHECK: # %bb.0: -; CHECK-NEXT: lxsihzx f0, 0, r3 -; CHECK-NEXT: xscvhpdp f1, f0 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_extend64: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: stdu r1, -32(r1) -; SOFT-NEXT: std r0, 48(r1) -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __extendsfdf2 -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 32 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %val16 = load half, ptr %addr - %val32 = fpext half %val16 to double - ret double %val32 -} -define void @test_trunc32(float %in, ptr %addr) #0 { -; P8-LABEL: test_trunc32: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; P8-NEXT: stdu r1, -48(r1) -; P8-NEXT: std r0, 64(r1) -; P8-NEXT: mr r30, r4 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 0(r30) -; P8-NEXT: addi r1, r1, 48 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_trunc32: -; CHECK: # %bb.0: -; CHECK-NEXT: xscvdphp f0, f1 -; CHECK-NEXT: stxsihx f0, 0, r4 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_trunc32: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -48(r1) -; SOFT-NEXT: clrldi r3, r3, 32 -; SOFT-NEXT: std r0, 64(r1) -; SOFT-NEXT: mr r30, r4 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 48 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %val16 = fptrunc float %in to half - store half %val16, ptr %addr - ret void -} -define void @test_trunc64(double %in, ptr %addr) #0 { -; P8-LABEL: test_trunc64: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; P8-NEXT: stdu r1, -48(r1) -; P8-NEXT: std r0, 64(r1) -; P8-NEXT: mr r30, r4 -; P8-NEXT: bl __truncdfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 0(r30) -; P8-NEXT: addi r1, r1, 48 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_trunc64: -; CHECK: # %bb.0: -; CHECK-NEXT: xscvdphp f0, f1 -; CHECK-NEXT: stxsihx f0, 0, r4 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_trunc64: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -48(r1) -; SOFT-NEXT: std r0, 64(r1) -; SOFT-NEXT: mr r30, r4 -; SOFT-NEXT: bl __truncdfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 48 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %val16 = fptrunc double %in to half - store half %val16, ptr %addr - ret void -} -define i64 @test_fptosi_i64(ptr %p) #0 { -; P8-LABEL: test_fptosi_i64: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -32(r1) -; P8-NEXT: std r0, 48(r1) -; P8-NEXT: lhz r3, 0(r3) -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: xscvdpsxds f0, f1 -; P8-NEXT: mffprd r3, f0 -; P8-NEXT: addi r1, r1, 32 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_fptosi_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: mtfprwz f0, r3 -; CHECK-NEXT: xscvhpdp f0, f0 -; CHECK-NEXT: xscvdpsxds f0, f0 -; CHECK-NEXT: mffprd r3, f0 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_fptosi_i64: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: stdu r1, -32(r1) -; SOFT-NEXT: std r0, 48(r1) -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __fixsfdi -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 32 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %a = load half, ptr %p, align 2 - %r = fptosi half %a to i64 - ret i64 %r -} -define void @test_sitofp_i64(i64 %a, ptr %p) #0 { -; P8-LABEL: test_sitofp_i64: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; P8-NEXT: stdu r1, -48(r1) -; P8-NEXT: mtfprd f0, r3 -; P8-NEXT: std r0, 64(r1) -; P8-NEXT: mr r30, r4 -; P8-NEXT: xscvsxdsp f1, f0 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 0(r30) -; P8-NEXT: addi r1, r1, 48 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_sitofp_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: mtfprd f0, r3 -; CHECK-NEXT: xscvsxdsp f0, f0 -; CHECK-NEXT: xscvdphp f0, f0 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: sth r3, 0(r4) -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_sitofp_i64: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -48(r1) -; SOFT-NEXT: std r0, 64(r1) -; SOFT-NEXT: mr r30, r4 -; SOFT-NEXT: bl __floatdisf -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 32 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 48 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %r = sitofp i64 %a to half - store half %r, ptr %p - ret void -} -define i64 @test_fptoui_i64(ptr %p) #0 { -; P8-LABEL: test_fptoui_i64: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -32(r1) -; P8-NEXT: std r0, 48(r1) -; P8-NEXT: lhz r3, 0(r3) -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: xscvdpuxds f0, f1 -; P8-NEXT: mffprd r3, f0 -; P8-NEXT: addi r1, r1, 32 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_fptoui_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: mtfprwz f0, r3 -; CHECK-NEXT: xscvhpdp f0, f0 -; CHECK-NEXT: xscvdpuxds f0, f0 -; CHECK-NEXT: mffprd r3, f0 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_fptoui_i64: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: stdu r1, -32(r1) -; SOFT-NEXT: std r0, 48(r1) -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __fixunssfdi -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 32 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %a = load half, ptr %p, align 2 - %r = fptoui half %a to i64 - ret i64 %r -} -define void @test_uitofp_i64(i64 %a, ptr %p) #0 { -; P8-LABEL: test_uitofp_i64: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; P8-NEXT: stdu r1, -48(r1) -; P8-NEXT: mtfprd f0, r3 -; P8-NEXT: std r0, 64(r1) -; P8-NEXT: mr r30, r4 -; P8-NEXT: xscvuxdsp f1, f0 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 0(r30) -; P8-NEXT: addi r1, r1, 48 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_uitofp_i64: -; CHECK: # %bb.0: -; CHECK-NEXT: mtfprd f0, r3 -; CHECK-NEXT: xscvuxdsp f0, f0 -; CHECK-NEXT: xscvdphp f0, f0 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: sth r3, 0(r4) -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_uitofp_i64: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -48(r1) -; SOFT-NEXT: std r0, 64(r1) -; SOFT-NEXT: mr r30, r4 -; SOFT-NEXT: bl __floatundisf -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 48 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %r = uitofp i64 %a to half - store half %r, ptr %p - ret void -} -define <4 x float> @test_extend32_vec4(ptr %p) #0 { -; P8-LABEL: test_extend32_vec4: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -112(r1) -; P8-NEXT: li r4, 48 -; P8-NEXT: std r0, 128(r1) -; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill -; P8-NEXT: mr r30, r3 -; P8-NEXT: lhz r3, 6(r3) -; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill -; P8-NEXT: li r4, 64 -; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill -; P8-NEXT: li r4, 80 -; P8-NEXT: stxvd2x vs63, r1, r4 # 16-byte Folded Spill -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: lhz r3, 2(r30) -; P8-NEXT: xxlor vs63, f1, f1 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: lhz r3, 4(r30) -; P8-NEXT: xxlor vs62, f1, f1 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: lhz r3, 0(r30) -; P8-NEXT: xxlor vs61, f1, f1 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: li r3, 80 -; P8-NEXT: xxmrghd vs0, vs61, vs1 -; P8-NEXT: xxmrghd vs1, vs63, vs62 -; P8-NEXT: ld r30, 96(r1) # 8-byte Folded Reload -; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload -; P8-NEXT: li r3, 64 -; P8-NEXT: xvcvdpsp vs34, vs0 -; P8-NEXT: xvcvdpsp vs35, vs1 -; P8-NEXT: lxvd2x vs62, r1, r3 # 16-byte Folded Reload -; P8-NEXT: li r3, 48 -; P8-NEXT: lxvd2x vs61, r1, r3 # 16-byte Folded Reload -; P8-NEXT: vmrgew v2, v3, v2 -; P8-NEXT: addi r1, r1, 112 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_extend32_vec4: -; CHECK: # %bb.0: -; CHECK-NEXT: lhz r4, 6(r3) -; CHECK-NEXT: mtfprwz f0, r4 -; CHECK-NEXT: xscvhpdp f0, f0 -; CHECK-NEXT: lhz r4, 2(r3) -; CHECK-NEXT: mtfprwz f1, r4 -; CHECK-NEXT: xscvhpdp f1, f1 -; CHECK-NEXT: lhz r4, 4(r3) -; CHECK-NEXT: mtfprwz f2, r4 -; CHECK-NEXT: xscvhpdp f2, f2 -; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: xxmrghd vs0, vs0, vs1 -; CHECK-NEXT: mtfprwz f3, r3 -; CHECK-NEXT: xvcvdpsp vs35, vs0 -; CHECK-NEXT: xscvhpdp f3, f3 -; CHECK-NEXT: xxmrghd vs2, vs2, vs3 -; CHECK-NEXT: xvcvdpsp vs34, vs2 -; CHECK-NEXT: vmrgew v2, v3, v2 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_extend32_vec4: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -80(r1) -; SOFT-NEXT: std r0, 96(r1) -; SOFT-NEXT: mr r30, r3 -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r29, r3 -; SOFT-NEXT: lhz r3, 2(r30) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r28, r3 -; SOFT-NEXT: lhz r3, 4(r30) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r27, r3 -; SOFT-NEXT: lhz r3, 6(r30) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r6, r3 -; SOFT-NEXT: mr r3, r29 -; SOFT-NEXT: mr r4, r28 -; SOFT-NEXT: mr r5, r27 -; SOFT-NEXT: addi r1, r1, 80 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; SOFT-NEXT: blr - %a = load <4 x half>, ptr %p, align 8 - %b = fpext <4 x half> %a to <4 x float> - ret <4 x float> %b -} -define <4 x double> @test_extend64_vec4(ptr %p) #0 { -; P8-LABEL: test_extend64_vec4: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -112(r1) -; P8-NEXT: li r4, 48 -; P8-NEXT: std r0, 128(r1) -; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill -; P8-NEXT: mr r30, r3 -; P8-NEXT: lhz r3, 6(r3) -; P8-NEXT: stxvd2x vs61, r1, r4 # 16-byte Folded Spill -; P8-NEXT: li r4, 64 -; P8-NEXT: stxvd2x vs62, r1, r4 # 16-byte Folded Spill -; P8-NEXT: li r4, 80 -; P8-NEXT: stxvd2x vs63, r1, r4 # 16-byte Folded Spill -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: lhz r3, 4(r30) -; P8-NEXT: xxlor vs63, f1, f1 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: lhz r3, 2(r30) -; P8-NEXT: xxlor vs62, f1, f1 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: lhz r3, 0(r30) -; P8-NEXT: xxlor vs61, f1, f1 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: li r3, 80 -; P8-NEXT: xxmrghd vs35, vs63, vs62 -; P8-NEXT: xxmrghd vs34, vs61, vs1 -; P8-NEXT: ld r30, 96(r1) # 8-byte Folded Reload -; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload -; P8-NEXT: li r3, 64 -; P8-NEXT: lxvd2x vs62, r1, r3 # 16-byte Folded Reload -; P8-NEXT: li r3, 48 -; P8-NEXT: lxvd2x vs61, r1, r3 # 16-byte Folded Reload -; P8-NEXT: addi r1, r1, 112 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_extend64_vec4: -; CHECK: # %bb.0: -; CHECK-NEXT: lhz r4, 6(r3) -; CHECK-NEXT: lhz r5, 4(r3) -; CHECK-NEXT: lhz r6, 2(r3) -; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: mtfprwz f0, r3 -; CHECK-NEXT: mtfprwz f1, r6 -; CHECK-NEXT: xscvhpdp f0, f0 -; CHECK-NEXT: xscvhpdp f1, f1 -; CHECK-NEXT: xxmrghd vs34, vs1, vs0 -; CHECK-NEXT: mtfprwz f0, r5 -; CHECK-NEXT: mtfprwz f1, r4 -; CHECK-NEXT: xscvhpdp f0, f0 -; CHECK-NEXT: xscvhpdp f1, f1 -; CHECK-NEXT: xxmrghd vs35, vs1, vs0 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_extend64_vec4: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -80(r1) -; SOFT-NEXT: std r0, 96(r1) -; SOFT-NEXT: mr r30, r3 -; SOFT-NEXT: lhz r3, 0(r3) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __extendsfdf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r29, r3 -; SOFT-NEXT: lhz r3, 2(r30) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __extendsfdf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r28, r3 -; SOFT-NEXT: lhz r3, 4(r30) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __extendsfdf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r27, r3 -; SOFT-NEXT: lhz r3, 6(r30) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __extendsfdf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r6, r3 -; SOFT-NEXT: mr r3, r29 -; SOFT-NEXT: mr r4, r28 -; SOFT-NEXT: mr r5, r27 -; SOFT-NEXT: addi r1, r1, 80 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; SOFT-NEXT: blr - %a = load <4 x half>, ptr %p, align 8 - %b = fpext <4 x half> %a to <4 x double> - ret <4 x double> %b -} -define void @test_trunc32_vec4(<4 x float> %a, ptr %p) #0 { -; P8-LABEL: test_trunc32_vec4: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -112(r1) -; P8-NEXT: xxsldwi vs0, vs34, vs34, 3 -; P8-NEXT: li r3, 48 -; P8-NEXT: std r0, 128(r1) -; P8-NEXT: std r27, 72(r1) # 8-byte Folded Spill -; P8-NEXT: std r28, 80(r1) # 8-byte Folded Spill -; P8-NEXT: std r29, 88(r1) # 8-byte Folded Spill -; P8-NEXT: xscvspdpn f1, vs0 -; P8-NEXT: std r30, 96(r1) # 8-byte Folded Spill -; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill -; P8-NEXT: mr r30, r5 -; P8-NEXT: vmr v31, v2 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: xxswapd vs0, vs63 -; P8-NEXT: mr r29, r3 -; P8-NEXT: xscvspdpn f1, vs0 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: xxsldwi vs0, vs63, vs63, 1 -; P8-NEXT: mr r28, r3 -; P8-NEXT: xscvspdpn f1, vs0 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: xscvspdpn f1, vs63 -; P8-NEXT: mr r27, r3 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 6(r30) -; P8-NEXT: li r3, 48 -; P8-NEXT: sth r27, 4(r30) -; P8-NEXT: ld r27, 72(r1) # 8-byte Folded Reload -; P8-NEXT: sth r28, 2(r30) -; P8-NEXT: sth r29, 0(r30) -; P8-NEXT: ld r30, 96(r1) # 8-byte Folded Reload -; P8-NEXT: ld r29, 88(r1) # 8-byte Folded Reload -; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload -; P8-NEXT: ld r28, 80(r1) # 8-byte Folded Reload -; P8-NEXT: addi r1, r1, 112 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_trunc32_vec4: -; CHECK: # %bb.0: -; CHECK-NEXT: xxsldwi vs0, vs34, vs34, 3 -; CHECK-NEXT: xxsldwi vs1, vs34, vs34, 1 -; CHECK-NEXT: xscvspdpn f0, vs0 -; CHECK-NEXT: xscvspdpn f1, vs1 -; CHECK-NEXT: xscvdphp f0, f0 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: xxswapd vs0, vs34 -; CHECK-NEXT: xscvspdpn f0, vs0 -; CHECK-NEXT: xscvdphp f0, f0 -; CHECK-NEXT: xscvdphp f1, f1 -; CHECK-NEXT: mffprwz r4, f1 -; CHECK-NEXT: xscvspdpn f1, vs34 -; CHECK-NEXT: xscvdphp f1, f1 -; CHECK-NEXT: sth r4, 4(r5) -; CHECK-NEXT: mffprwz r4, f0 -; CHECK-NEXT: sth r3, 0(r5) -; CHECK-NEXT: sth r4, 2(r5) -; CHECK-NEXT: mffprwz r6, f1 -; CHECK-NEXT: sth r6, 6(r5) -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_trunc32_vec4: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -80(r1) -; SOFT-NEXT: mr r27, r3 -; SOFT-NEXT: clrldi r3, r6, 32 -; SOFT-NEXT: std r0, 96(r1) -; SOFT-NEXT: mr r30, r7 -; SOFT-NEXT: mr r29, r5 -; SOFT-NEXT: mr r28, r4 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r26, r3 -; SOFT-NEXT: clrldi r3, r29, 32 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r29, r3 -; SOFT-NEXT: clrldi r3, r28, 32 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r28, r3 -; SOFT-NEXT: clrldi r3, r27, 32 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r27, r3 -; SOFT-NEXT: clrldi r3, r28, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r28, r3 -; SOFT-NEXT: clrldi r3, r29, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r29, r3 -; SOFT-NEXT: clrldi r3, r26, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 6(r30) -; SOFT-NEXT: mr r3, r29 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 4(r30) -; SOFT-NEXT: mr r3, r28 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 2(r30) -; SOFT-NEXT: mr r3, r27 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 80 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; SOFT-NEXT: blr - %v = fptrunc <4 x float> %a to <4 x half> - store <4 x half> %v, ptr %p - ret void -} -define void @test_trunc64_vec4(<4 x double> %a, ptr %p) #0 { -; P8-LABEL: test_trunc64_vec4: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -128(r1) -; P8-NEXT: li r3, 48 -; P8-NEXT: std r0, 144(r1) -; P8-NEXT: xxswapd vs1, vs34 -; P8-NEXT: std r27, 88(r1) # 8-byte Folded Spill -; P8-NEXT: std r28, 96(r1) # 8-byte Folded Spill -; P8-NEXT: std r29, 104(r1) # 8-byte Folded Spill -; P8-NEXT: std r30, 112(r1) # 8-byte Folded Spill -; P8-NEXT: mr r30, r7 -; P8-NEXT: stxvd2x vs62, r1, r3 # 16-byte Folded Spill -; P8-NEXT: li r3, 64 -; P8-NEXT: vmr v30, v2 -; P8-NEXT: stxvd2x vs63, r1, r3 # 16-byte Folded Spill -; P8-NEXT: vmr v31, v3 -; P8-NEXT: bl __truncdfhf2 -; P8-NEXT: nop -; P8-NEXT: xxswapd vs1, vs63 -; P8-NEXT: mr r29, r3 -; P8-NEXT: bl __truncdfhf2 -; P8-NEXT: nop -; P8-NEXT: xxlor f1, vs62, vs62 -; P8-NEXT: mr r28, r3 -; P8-NEXT: bl __truncdfhf2 -; P8-NEXT: nop -; P8-NEXT: xxlor f1, vs63, vs63 -; P8-NEXT: mr r27, r3 -; P8-NEXT: bl __truncdfhf2 -; P8-NEXT: nop -; P8-NEXT: sth r3, 6(r30) -; P8-NEXT: li r3, 64 -; P8-NEXT: sth r27, 2(r30) -; P8-NEXT: ld r27, 88(r1) # 8-byte Folded Reload -; P8-NEXT: sth r28, 4(r30) -; P8-NEXT: sth r29, 0(r30) -; P8-NEXT: ld r30, 112(r1) # 8-byte Folded Reload -; P8-NEXT: ld r29, 104(r1) # 8-byte Folded Reload -; P8-NEXT: lxvd2x vs63, r1, r3 # 16-byte Folded Reload -; P8-NEXT: li r3, 48 -; P8-NEXT: ld r28, 96(r1) # 8-byte Folded Reload -; P8-NEXT: lxvd2x vs62, r1, r3 # 16-byte Folded Reload -; P8-NEXT: addi r1, r1, 128 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_trunc64_vec4: -; CHECK: # %bb.0: -; CHECK-NEXT: xxswapd vs0, vs34 -; CHECK-NEXT: xscvdphp f0, f0 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: xxswapd vs0, vs35 -; CHECK-NEXT: xscvdphp f0, f0 -; CHECK-NEXT: xscvdphp f1, vs34 -; CHECK-NEXT: mffprwz r4, f1 -; CHECK-NEXT: xscvdphp f1, vs35 -; CHECK-NEXT: sth r3, 0(r7) -; CHECK-NEXT: sth r4, 2(r7) -; CHECK-NEXT: mffprwz r4, f0 -; CHECK-NEXT: sth r4, 4(r7) -; CHECK-NEXT: mffprwz r5, f1 -; CHECK-NEXT: sth r5, 6(r7) -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_trunc64_vec4: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r26, -48(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -80(r1) -; SOFT-NEXT: mr r27, r3 -; SOFT-NEXT: mr r3, r6 -; SOFT-NEXT: std r0, 96(r1) -; SOFT-NEXT: mr r30, r7 -; SOFT-NEXT: mr r29, r5 -; SOFT-NEXT: mr r28, r4 -; SOFT-NEXT: bl __truncdfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r26, r3 -; SOFT-NEXT: mr r3, r29 -; SOFT-NEXT: bl __truncdfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r29, r3 -; SOFT-NEXT: mr r3, r28 -; SOFT-NEXT: bl __truncdfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r28, r3 -; SOFT-NEXT: mr r3, r27 -; SOFT-NEXT: bl __truncdfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r27, r3 -; SOFT-NEXT: clrldi r3, r28, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r28, r3 -; SOFT-NEXT: clrldi r3, r29, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r29, r3 -; SOFT-NEXT: clrldi r3, r26, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 6(r30) -; SOFT-NEXT: mr r3, r29 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 4(r30) -; SOFT-NEXT: mr r3, r28 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 2(r30) -; SOFT-NEXT: mr r3, r27 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: sth r3, 0(r30) -; SOFT-NEXT: addi r1, r1, 80 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; SOFT-NEXT: blr - %v = fptrunc <4 x double> %a to <4 x half> - store <4 x half> %v, ptr %p - ret void -} -define float @test_sitofp_fadd_i32(i32 %a, ptr %b) #0 { -; P8-LABEL: test_sitofp_fadd_i32: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: std r30, -24(r1) # 8-byte Folded Spill -; P8-NEXT: stfd f31, -8(r1) # 8-byte Folded Spill -; P8-NEXT: stdu r1, -64(r1) -; P8-NEXT: std r0, 80(r1) -; P8-NEXT: mr r30, r3 -; P8-NEXT: lhz r3, 0(r4) -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: mtfprwa f0, r30 -; P8-NEXT: fmr f31, f1 -; P8-NEXT: xscvsxdsp f1, f0 -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: clrldi r3, r3, 48 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: xsaddsp f1, f31, f1 -; P8-NEXT: addi r1, r1, 64 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: lfd f31, -8(r1) # 8-byte Folded Reload -; P8-NEXT: ld r30, -24(r1) # 8-byte Folded Reload -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: test_sitofp_fadd_i32: -; CHECK: # %bb.0: -; CHECK-NEXT: mtfprwa f1, r3 -; CHECK-NEXT: lhz r4, 0(r4) -; CHECK-NEXT: xscvsxdsp f1, f1 -; CHECK-NEXT: mtfprwz f0, r4 -; CHECK-NEXT: xscvhpdp f0, f0 -; CHECK-NEXT: xscvdphp f1, f1 -; CHECK-NEXT: mffprwz r3, f1 -; CHECK-NEXT: clrlwi r3, r3, 16 -; CHECK-NEXT: mtfprwz f1, r3 -; CHECK-NEXT: xscvhpdp f1, f1 -; CHECK-NEXT: xsaddsp f1, f0, f1 -; CHECK-NEXT: blr -; -; SOFT-LABEL: test_sitofp_fadd_i32: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; SOFT-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; SOFT-NEXT: stdu r1, -64(r1) -; SOFT-NEXT: std r0, 80(r1) -; SOFT-NEXT: mr r30, r3 -; SOFT-NEXT: lhz r3, 0(r4) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r29, r3 -; SOFT-NEXT: extsw r3, r30 -; SOFT-NEXT: bl __floatsisf -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 32 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: mr r4, r3 -; SOFT-NEXT: mr r3, r29 -; SOFT-NEXT: bl __addsf3 -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 64 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; SOFT-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %tmp0 = load half, ptr %b - %tmp1 = sitofp i32 %a to half - %tmp2 = fadd half %tmp0, %tmp1 - %tmp3 = fpext half %tmp2 to float - ret float %tmp3 -} -define half @PR40273(half) #0 { -; P8-LABEL: PR40273: -; P8: # %bb.0: -; P8-NEXT: mflr r0 -; P8-NEXT: stdu r1, -32(r1) -; P8-NEXT: std r0, 48(r1) -; P8-NEXT: bl __truncsfhf2 -; P8-NEXT: nop -; P8-NEXT: clrldi r3, r3, 48 -; P8-NEXT: bl __extendhfsf2 -; P8-NEXT: nop -; P8-NEXT: fmr f0, f1 -; P8-NEXT: xxlxor f1, f1, f1 -; P8-NEXT: fcmpu cr0, f0, f1 -; P8-NEXT: beq cr0, .LBB20_2 -; P8-NEXT: # %bb.1: -; P8-NEXT: vspltisw v2, 1 -; P8-NEXT: xvcvsxwdp vs1, vs34 -; P8-NEXT: .LBB20_2: -; P8-NEXT: addi r1, r1, 32 -; P8-NEXT: ld r0, 16(r1) -; P8-NEXT: mtlr r0 -; P8-NEXT: blr -; -; CHECK-LABEL: PR40273: -; CHECK: # %bb.0: -; CHECK-NEXT: xscvdphp f0, f1 -; CHECK-NEXT: xxlxor f1, f1, f1 -; CHECK-NEXT: mffprwz r3, f0 -; CHECK-NEXT: clrlwi r3, r3, 16 -; CHECK-NEXT: mtfprwz f0, r3 -; CHECK-NEXT: xscvhpdp f0, f0 -; CHECK-NEXT: fcmpu cr0, f0, f1 -; CHECK-NEXT: beqlr cr0 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: vspltisw v2, 1 -; CHECK-NEXT: xvcvsxwdp vs1, vs34 -; CHECK-NEXT: blr -; -; SOFT-LABEL: PR40273: -; SOFT: # %bb.0: -; SOFT-NEXT: mflr r0 -; SOFT-NEXT: stdu r1, -32(r1) -; SOFT-NEXT: clrldi r3, r3, 48 -; SOFT-NEXT: std r0, 48(r1) -; SOFT-NEXT: bl __extendhfsf2 -; SOFT-NEXT: nop -; SOFT-NEXT: li r4, 0 -; SOFT-NEXT: bl __nesf2 -; SOFT-NEXT: nop -; SOFT-NEXT: cmplwi r3, 0 -; SOFT-NEXT: lis r3, 16256 -; SOFT-NEXT: iseleq r3, 0, r3 -; SOFT-NEXT: bl __truncsfhf2 -; SOFT-NEXT: nop -; SOFT-NEXT: addi r1, r1, 32 -; SOFT-NEXT: ld r0, 16(r1) -; SOFT-NEXT: mtlr r0 -; SOFT-NEXT: blr - %2 = fcmp une half %0, 0xH0000 - %3 = uitofp i1 %2 to half - ret half %3 -} -attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/loop-comment.ll b/llvm/test/CodeGen/PowerPC/loop-comment.ll index 530e67b4804f..b4ceb3676890 100644 --- a/llvm/test/CodeGen/PowerPC/loop-comment.ll +++ b/llvm/test/CodeGen/PowerPC/loop-comment.ll @@ -6,16 +6,15 @@ define void @test(ptr %ptr, i8 %cmp, i8 %val) { ; PPC64LE: # %bb.0: ; PPC64LE-NEXT: clrlwi 5, 5, 24 ; PPC64LE-NEXT: clrlwi 4, 4, 24 -; PPC64LE-NEXT: .p2align 5 ; PPC64LE-NEXT: .LBB0_1: # %cmpxchg.start ; PPC64LE-NEXT: # ; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: cmplw 6, 4 -; PPC64LE-NEXT: bnelr 0 +; PPC64LE-NEXT: bnelr- 0 ; PPC64LE-NEXT: # %bb.2: # %cmpxchg.fencedstore ; PPC64LE-NEXT: # ; PPC64LE-NEXT: stbcx. 5, 0, 3 -; PPC64LE-NEXT: bne 0, .LBB0_1 +; PPC64LE-NEXT: bne- 0, .LBB0_1 ; PPC64LE-NEXT: # %bb.3: # %cmpxchg.end ; PPC64LE-NEXT: blr %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic diff --git a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll index 018fbe99ce49..f3085ccc85c8 100644 --- a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll +++ b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll @@ -81,7 +81,7 @@ declare double @__log10_finite (double); declare double @__pow_finite (double, double); declare double @__sinh_finite (double); -define float @acosf_f32(float %a) #0 { +define float @acosf_f32(float %a) { ; CHECK-LABEL: acosf_f32 ; CHECK: __xl_acosf ; CHECK: blr @@ -90,7 +90,7 @@ entry: ret float %call } -define float @acoshf_f32(float %a) #0 { +define float @acoshf_f32(float %a) { ; CHECK-LABEL: acoshf_f32 ; CHECK: __xl_acoshf ; CHECK: blr @@ -99,7 +99,7 @@ entry: ret float %call } -define float @asinf_f32(float %a) #0 { +define float @asinf_f32(float %a) { ; CHECK-LABEL: asinf_f32 ; CHECK: __xl_asinf ; CHECK: blr @@ -108,7 +108,7 @@ entry: ret float %call } -define float @asinhf_f32(float %a) #0 { +define float @asinhf_f32(float %a) { ; CHECK-LABEL: asinhf_f32 ; CHECK: __xl_asinhf ; CHECK: blr @@ -117,7 +117,7 @@ entry: ret float %call } -define float @atan2f_f32(float %a, float %b) #0 { +define float @atan2f_f32(float %a, float %b) { ; CHECK-LABEL: atan2f_f32 ; CHECK: __xl_atan2f ; CHECK: blr @@ -126,7 +126,7 @@ entry: ret float %call } -define float @atanf_f32(float %a) #0 { +define float @atanf_f32(float %a) { ; CHECK-LABEL: atanf_f32 ; CHECK: __xl_atanf ; CHECK: blr @@ -135,7 +135,7 @@ entry: ret float %call } -define float @atanhf_f32(float %a) #0 { +define float @atanhf_f32(float %a) { ; CHECK-LABEL: atanhf_f32 ; CHECK: __xl_atanhf ; CHECK: blr @@ -144,7 +144,7 @@ entry: ret float %call } -define float @cbrtf_f32(float %a) #0 { +define float @cbrtf_f32(float %a) { ; CHECK-LABEL: cbrtf_f32 ; CHECK: __xl_cbrtf ; CHECK: blr @@ -153,7 +153,7 @@ entry: ret float %call } -define float @copysignf_f32(float %a, float %b) #0 { +define float @copysignf_f32(float %a, float %b) { ; CHECK-LABEL: copysignf_f32 ; CHECK: copysignf ; CHECK: blr @@ -162,7 +162,7 @@ entry: ret float %call } -define float @cosf_f32(float %a) #0 { +define float @cosf_f32(float %a) { ; CHECK-LABEL: cosf_f32 ; CHECK: __xl_cosf ; CHECK: blr @@ -171,7 +171,7 @@ entry: ret float %call } -define float @coshf_f32(float %a) #0 { +define float @coshf_f32(float %a) { ; CHECK-LABEL: coshf_f32 ; CHECK: __xl_coshf ; CHECK: blr @@ -180,7 +180,7 @@ entry: ret float %call } -define float @erfcf_f32(float %a) #0 { +define float @erfcf_f32(float %a) { ; CHECK-LABEL: erfcf_f32 ; CHECK: __xl_erfcf ; CHECK: blr @@ -189,7 +189,7 @@ entry: ret float %call } -define float @erff_f32(float %a) #0 { +define float @erff_f32(float %a) { ; CHECK-LABEL: erff_f32 ; CHECK: __xl_erff ; CHECK: blr @@ -198,7 +198,7 @@ entry: ret float %call } -define float @expf_f32(float %a) #0 { +define float @expf_f32(float %a) { ; CHECK-LABEL: expf_f32 ; CHECK: __xl_expf ; CHECK: blr @@ -207,7 +207,7 @@ entry: ret float %call } -define float @expm1f_f32(float %a) #0 { +define float @expm1f_f32(float %a) { ; CHECK-LABEL: expm1f_f32 ; CHECK: __xl_expm1f ; CHECK: blr @@ -216,7 +216,7 @@ entry: ret float %call } -define float @hypotf_f32(float %a, float %b) #0 { +define float @hypotf_f32(float %a, float %b) { ; CHECK-LABEL: hypotf_f32 ; CHECK: __xl_hypotf ; CHECK: blr @@ -225,7 +225,7 @@ entry: ret float %call } -define float @lgammaf_f32(float %a) #0 { +define float @lgammaf_f32(float %a) { ; CHECK-LABEL: lgammaf_f32 ; CHECK: __xl_lgammaf ; CHECK: blr @@ -234,7 +234,7 @@ entry: ret float %call } -define float @log10f_f32(float %a) #0 { +define float @log10f_f32(float %a) { ; CHECK-LABEL: log10f_f32 ; CHECK: __xl_log10f ; CHECK: blr @@ -243,7 +243,7 @@ entry: ret float %call } -define float @log1pf_f32(float %a) #0 { +define float @log1pf_f32(float %a) { ; CHECK-LABEL: log1pf_f32 ; CHECK: __xl_log1pf ; CHECK: blr @@ -252,7 +252,7 @@ entry: ret float %call } -define float @logf_f32(float %a) #0 { +define float @logf_f32(float %a) { ; CHECK-LABEL: logf_f32 ; CHECK: __xl_logf ; CHECK: blr @@ -261,7 +261,7 @@ entry: ret float %call } -define float @powf_f32(float %a, float %b) #0 { +define float @powf_f32(float %a, float %b) { ; CHECK-LABEL: powf_f32 ; CHECK: __xl_powf ; CHECK: blr @@ -270,7 +270,7 @@ entry: ret float %call } -define float @rintf_f32(float %a) #0 { +define float @rintf_f32(float %a) { ; CHECK-LABEL: rintf_f32 ; CHECK-NOT: __xl_rintf ; CHECK: blr @@ -279,7 +279,7 @@ entry: ret float %call } -define float @sinf_f32(float %a) #0 { +define float @sinf_f32(float %a) { ; CHECK-LABEL: sinf_f32 ; CHECK: __xl_sinf ; CHECK: blr @@ -288,7 +288,7 @@ entry: ret float %call } -define float @sinhf_f32(float %a) #0 { +define float @sinhf_f32(float %a) { ; CHECK-LABEL: sinhf_f32 ; CHECK: __xl_sinhf ; CHECK: blr @@ -297,7 +297,7 @@ entry: ret float %call } -define float @tanf_f32(float %a) #0 { +define float @tanf_f32(float %a) { ; CHECK-LABEL: tanf_f32 ; CHECK: __xl_tanf ; CHECK: blr @@ -306,7 +306,7 @@ entry: ret float %call } -define float @tanhf_f32(float %a) #0 { +define float @tanhf_f32(float %a) { ; CHECK-LABEL: tanhf_f32 ; CHECK: __xl_tanhf ; CHECK: blr @@ -315,7 +315,7 @@ entry: ret float %call } -define double @acos_f64(double %a) #0 { +define double @acos_f64(double %a) { ; CHECK-LABEL: acos_f64 ; CHECK: __xl_acos ; CHECK: blr @@ -324,7 +324,7 @@ entry: ret double %call } -define double @acosh_f64(double %a) #0 { +define double @acosh_f64(double %a) { ; CHECK-LABEL: acosh_f64 ; CHECK: __xl_acosh ; CHECK: blr @@ -333,7 +333,7 @@ entry: ret double %call } -define double @anint_f64(double %a) #0 { +define double @anint_f64(double %a) { ; CHECK-LABEL: anint_f64 ; CHECK-NOT: __xl_anint ; CHECK: blr @@ -342,7 +342,7 @@ entry: ret double %call } -define double @asin_f64(double %a) #0 { +define double @asin_f64(double %a) { ; CHECK-LABEL: asin_f64 ; CHECK: __xl_asin ; CHECK: blr @@ -351,7 +351,7 @@ entry: ret double %call } -define double @asinh_f64(double %a) #0 { +define double @asinh_f64(double %a) { ; CHECK-LABEL: asinh_f64 ; CHECK: __xl_asinh ; CHECK: blr @@ -360,7 +360,7 @@ entry: ret double %call } -define double @atan_f64(double %a) #0 { +define double @atan_f64(double %a) { ; CHECK-LABEL: atan_f64 ; CHECK: __xl_atan ; CHECK: blr @@ -369,7 +369,7 @@ entry: ret double %call } -define double @atan2_f64(double %a, double %b) #0 { +define double @atan2_f64(double %a, double %b) { ; CHECK-LABEL: atan2_f64 ; CHECK: __xl_atan2 ; CHECK: blr @@ -378,7 +378,7 @@ entry: ret double %call } -define double @atanh_f64(double %a) #0 { +define double @atanh_f64(double %a) { ; CHECK-LABEL: atanh_f64 ; CHECK: __xl_atanh ; CHECK: blr @@ -387,7 +387,7 @@ entry: ret double %call } -define double @cbrt_f64(double %a) #0 { +define double @cbrt_f64(double %a) { ; CHECK-LABEL: cbrt_f64 ; CHECK: __xl_cbrt ; CHECK: blr @@ -396,7 +396,7 @@ entry: ret double %call } -define double @copysign_f64(double %a, double %b) #0 { +define double @copysign_f64(double %a, double %b) { ; CHECK-LABEL: copysign_f64 ; CHECK: copysign ; CHECK: blr @@ -405,7 +405,7 @@ entry: ret double %call } -define double @cos_f64(double %a) #0 { +define double @cos_f64(double %a) { ; CHECK-LABEL: cos_f64 ; CHECK: __xl_cos ; CHECK: blr @@ -414,7 +414,7 @@ entry: ret double %call } -define double @cosh_f64(double %a) #0 { +define double @cosh_f64(double %a) { ; CHECK-LABEL: cosh_f64 ; CHECK: __xl_cosh ; CHECK: blr @@ -423,7 +423,7 @@ entry: ret double %call } -define double @cosisin_f64(double %a) #0 { +define double @cosisin_f64(double %a) { ; CHECK-LABEL: cosisin_f64 ; CHECK-NOT: __xl_cosisin ; CHECK: blr @@ -432,7 +432,7 @@ entry: ret double %call } -define double @dnint_f64(double %a) #0 { +define double @dnint_f64(double %a) { ; CHECK-LABEL: dnint_f64 ; CHECK-NOT: __xl_dnint ; CHECK: blr @@ -441,7 +441,7 @@ entry: ret double %call } -define double @erf_f64(double %a) #0 { +define double @erf_f64(double %a) { ; CHECK-LABEL: erf_f64 ; CHECK: __xl_erf ; CHECK: blr @@ -450,7 +450,7 @@ entry: ret double %call } -define double @erfc_f64(double %a) #0 { +define double @erfc_f64(double %a) { ; CHECK-LABEL: erfc_f64 ; CHECK: __xl_erfc ; CHECK: blr @@ -459,7 +459,7 @@ entry: ret double %call } -define double @exp_f64(double %a) #0 { +define double @exp_f64(double %a) { ; CHECK-LABEL: exp_f64 ; CHECK: __xl_exp ; CHECK: blr @@ -468,7 +468,7 @@ entry: ret double %call } -define double @expm1_f64(double %a) #0 { +define double @expm1_f64(double %a) { ; CHECK-LABEL: expm1_f64 ; CHECK: __xl_expm1 ; CHECK: blr @@ -477,7 +477,7 @@ entry: ret double %call } -define double @hypot_f64(double %a, double %b) #0 { +define double @hypot_f64(double %a, double %b) { ; CHECK-LABEL: hypot_f64 ; CHECK: __xl_hypot ; CHECK: blr @@ -486,7 +486,7 @@ entry: ret double %call } -define double @lgamma_f64(double %a) #0 { +define double @lgamma_f64(double %a) { ; CHECK-LABEL: lgamma_f64 ; CHECK: __xl_lgamma ; CHECK: blr @@ -495,7 +495,7 @@ entry: ret double %call } -define double @log_f64(double %a) #0 { +define double @log_f64(double %a) { ; CHECK-LABEL: log_f64 ; CHECK: __xl_log ; CHECK: blr @@ -504,7 +504,7 @@ entry: ret double %call } -define double @log10_f64(double %a) #0 { +define double @log10_f64(double %a) { ; CHECK-LABEL: log10_f64 ; CHECK: __xl_log10 ; CHECK: blr @@ -513,7 +513,7 @@ entry: ret double %call } -define double @log1p_f64(double %a) #0 { +define double @log1p_f64(double %a) { ; CHECK-LABEL: log1p_f64 ; CHECK: __xl_log1p ; CHECK: blr @@ -522,7 +522,7 @@ entry: ret double %call } -define double @pow_f64(double %a, double %b) #0 { +define double @pow_f64(double %a, double %b) { ; CHECK-LABEL: pow_f64 ; CHECK: __xl_pow ; CHECK: blr @@ -531,7 +531,7 @@ entry: ret double %call } -define double @rsqrt_f64(double %a) #0 { +define double @rsqrt_f64(double %a) { ; CHECK-LABEL: rsqrt_f64 ; CHECK: __xl_rsqrt ; CHECK: blr @@ -540,7 +540,7 @@ entry: ret double %call } -define double @sin_f64(double %a) #0 { +define double @sin_f64(double %a) { ; CHECK-LABEL: sin_f64 ; CHECK: __xl_sin ; CHECK: blr @@ -549,7 +549,7 @@ entry: ret double %call } -define double @sincos_f64(double %a) #0 { +define double @sincos_f64(double %a) { ; CHECK-LABEL: sincos_f64 ; CHECK-NOT: __xl_sincos ; CHECK: blr @@ -558,7 +558,7 @@ entry: ret double %call } -define double @sinh_f64(double %a) #0 { +define double @sinh_f64(double %a) { ; CHECK-LABEL: sinh_f64 ; CHECK: __xl_sinh ; CHECK: blr @@ -567,7 +567,7 @@ entry: ret double %call } -define double @sqrt_f64(double %a) #0 { +define double @sqrt_f64(double %a) { ; CHECK-LABEL: sqrt_f64 ; CHECK: __xl_sqrt ; CHECK: blr @@ -576,7 +576,7 @@ entry: ret double %call } -define double @tan_f64(double %a) #0 { +define double @tan_f64(double %a) { ; CHECK-LABEL: tan_f64 ; CHECK: __xl_tan ; CHECK: blr @@ -585,7 +585,7 @@ entry: ret double %call } -define double @tanh_f64(double %a) #0 { +define double @tanh_f64(double %a) { ; CHECK-LABEL: tanh_f64 ; CHECK: __xl_tanh ; CHECK: blr @@ -594,7 +594,7 @@ entry: ret double %call } -define float @__acosf_finite_f32(float %a) #0 { +define float @__acosf_finite_f32(float %a) { ; CHECK-LABEL: __acosf_finite_f32 ; CHECK: __xl_acosf ; CHECK: blr @@ -603,7 +603,7 @@ entry: ret float %call } -define float @__acoshf_finite_f32(float %a) #0 { +define float @__acoshf_finite_f32(float %a) { ; CHECK-LABEL: __acoshf_finite_f32 ; CHECK: __xl_acoshf ; CHECK: blr @@ -612,7 +612,7 @@ entry: ret float %call } -define float @__asinf_finite_f32(float %a) #0 { +define float @__asinf_finite_f32(float %a) { ; CHECK-LABEL: __asinf_finite_f32 ; CHECK: __xl_asinf ; CHECK: blr @@ -621,7 +621,7 @@ entry: ret float %call } -define float @__atan2f_finite_f32(float %a, float %b) #0 { +define float @__atan2f_finite_f32(float %a, float %b) { ; CHECK-LABEL: __atan2f_finite_f32 ; CHECK: __xl_atan2f ; CHECK: blr @@ -630,7 +630,7 @@ entry: ret float %call } -define float @__atanhf_finite_f32(float %a) #0 { +define float @__atanhf_finite_f32(float %a) { ; CHECK-LABEL: __atanhf_finite_f32 ; CHECK: __xl_atanhf ; CHECK: blr @@ -639,7 +639,7 @@ entry: ret float %call } -define float @__coshf_finite_f32(float %a) #0 { +define float @__coshf_finite_f32(float %a) { ; CHECK-LABEL: __coshf_finite_f32 ; CHECK: __xl_coshf ; CHECK: blr @@ -647,7 +647,7 @@ entry: %call = tail call afn float @__coshf_finite(float %a) ret float %call } -define float @__expf_finite_f32(float %a) #0 { +define float @__expf_finite_f32(float %a) { ; CHECK-LABEL: __expf_finite_f32 ; CHECK: __xl_expf ; CHECK: blr @@ -655,7 +655,7 @@ entry: %call = tail call afn float @__expf_finite(float %a) ret float %call } -define float @__logf_finite_f32(float %a) #0 { +define float @__logf_finite_f32(float %a) { ; CHECK-LABEL: __logf_finite_f32 ; CHECK: __xl_logf ; CHECK: blr @@ -663,7 +663,7 @@ entry: %call = tail call afn float @__logf_finite(float %a) ret float %call } -define float @__log10f_finite_f32(float %a) #0 { +define float @__log10f_finite_f32(float %a) { ; CHECK-LABEL: __log10f_finite_f32 ; CHECK: __xl_log10f ; CHECK: blr @@ -671,7 +671,7 @@ entry: %call = tail call afn float @__log10f_finite(float %a) ret float %call } -define float @__powf_finite_f32(float %a, float %b) #0 { +define float @__powf_finite_f32(float %a, float %b) { ; CHECK-LABEL: __powf_finite_f32 ; CHECK: __xl_powf ; CHECK: blr @@ -679,7 +679,7 @@ entry: %call = tail call afn float @__powf_finite(float %a, float %b) ret float %call } -define float @__sinhf_finite_f32(float %a) #0 { +define float @__sinhf_finite_f32(float %a) { ; CHECK-LABEL: __sinhf_finite_f32 ; CHECK: __xl_sinhf ; CHECK: blr @@ -688,7 +688,7 @@ entry: ret float %call } -define double @__acos_finite_f64(double %a) #0 { +define double @__acos_finite_f64(double %a) { ; CHECK-LABEL: __acos_finite_f64 ; CHECK: __xl_acos ; CHECK: blr @@ -697,7 +697,7 @@ entry: ret double %call } -define double @__acosh_finite_f64(double %a) #0 { +define double @__acosh_finite_f64(double %a) { ; CHECK-LABEL: __acosh_finite_f64 ; CHECK: __xl_acosh ; CHECK: blr @@ -706,7 +706,7 @@ entry: ret double %call } -define double @__asin_finite_f64(double %a) #0 { +define double @__asin_finite_f64(double %a) { ; CHECK-LABEL: __asin_finite_f64 ; CHECK: __xl_asin ; CHECK: blr @@ -715,7 +715,7 @@ entry: ret double %call } -define double @__atan2_finite_f64(double %a, double %b) #0 { +define double @__atan2_finite_f64(double %a, double %b) { ; CHECK-LABEL: __atan2_finite_f64 ; CHECK: __xl_atan2 ; CHECK: blr @@ -724,7 +724,7 @@ entry: ret double %call } -define double @__atanh_finite_f64(double %a) #0 { +define double @__atanh_finite_f64(double %a) { ; CHECK-LABEL: __atanh_finite_f64 ; CHECK: __xl_atanh ; CHECK: blr @@ -733,7 +733,7 @@ entry: ret double %call } -define double @__cosh_finite_f64(double %a) #0 { +define double @__cosh_finite_f64(double %a) { ; CHECK-LABEL: __cosh_finite_f64 ; CHECK: __xl_cosh ; CHECK: blr @@ -742,7 +742,7 @@ entry: ret double %call } -define double @__exp_finite_f64(double %a) #0 { +define double @__exp_finite_f64(double %a) { ; CHECK-LABEL: __exp_finite_f64 ; CHECK: __xl_exp ; CHECK: blr @@ -751,7 +751,7 @@ entry: ret double %call } -define double @__log_finite_f64(double %a) #0 { +define double @__log_finite_f64(double %a) { ; CHECK-LABEL: __log_finite_f64 ; CHECK: __xl_log ; CHECK: blr @@ -760,7 +760,7 @@ entry: ret double %call } -define double @__log10_finite_f64(double %a) #0 { +define double @__log10_finite_f64(double %a) { ; CHECK-LABEL: __log10_finite_f64 ; CHECK: __xl_log10 ; CHECK: blr @@ -769,7 +769,7 @@ entry: ret double %call } -define double @__pow_finite_f64(double %a, double %b) #0 { +define double @__pow_finite_f64(double %a, double %b) { ; CHECK-LABEL: __pow_finite_f64 ; CHECK: __xl_pow ; CHECK: blr @@ -778,7 +778,7 @@ entry: ret double %call } -define double @__sinh_finite_f64(double %a) #0 { +define double @__sinh_finite_f64(double %a) { ; CHECK-LABEL: __sinh_finite_f64 ; CHECK: __xl_sinh ; CHECK: blr @@ -786,5 +786,3 @@ entry: %call = tail call afn double @__sinh_finite(double %a) ret double %call } - -attributes #0 = { "approx-func-fp-math"="true" } diff --git a/llvm/test/CodeGen/PowerPC/patchable-function-entry.ll b/llvm/test/CodeGen/PowerPC/patchable-function-entry.ll index 0c2d2829a6d4..f5977543784f 100644 --- a/llvm/test/CodeGen/PowerPC/patchable-function-entry.ll +++ b/llvm/test/CodeGen/PowerPC/patchable-function-entry.ll @@ -1,5 +1,6 @@ ; RUN: llc -mtriple=powerpc %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32 ; RUN: llc -mtriple=powerpc64 %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64 +; RUN: llc -mtriple=powerpc64le %s -o - | FileCheck %s --check-prefix=PPC64LE @a = global i32 0, align 4 @@ -9,6 +10,12 @@ define void @f0() { ; CHECK: # %bb.0: ; CHECK-NEXT: blr ; CHECK-NOT: .section __patchable_function_entries +; +; PPC64LE-LABEL: f0: +; PPC64LE-NOT: nop +; PPC64LE: # %bb.0: +; PPC64LE-NEXT: blr +; PPC64LE-NOT: .section __patchable_function_entries ret void } @@ -18,6 +25,22 @@ define void @f1() "patchable-function-entry"="0" { ; CHECK: # %bb.0: ; CHECK-NEXT: blr ; CHECK-NOT: .section __patchable_function_entries +; +; PPC64LE-LABEL: f1: +; PPC64LE: # %bb.0: +; PPC64LE-NEXT: .Ltmp0: +; PPC64LE-NEXT: b .Ltmp1 +; PPC64LE-NEXT: nop +; PPC64LE-NEXT: std 0, -8(1) +; PPC64LE-NEXT: mflr 0 +; PPC64LE-NEXT: bl __xray_FunctionEntry +; PPC64LE-NEXT: nop +; PPC64LE-NEXT: mtlr 0 +; PPC64LE-NEXT: .Ltmp1: +; PPC64LE-NEXT: blr +; PPC64LE-NOT: .section __patchable_function_entries +; PPC64LE: .section xray_instr_map +; PPC64LE: .section xray_fn_idx ret void } @@ -32,6 +55,17 @@ define void @f2() "patchable-function-entry"="1" { ; PPC64: .p2align 3, 0x0 ; PPC32-NEXT: .long .Lfunc_begin2 ; PPC64-NEXT: .quad .Lfunc_begin2 +; +; PPC64LE-LABEL: f2: +; PPC64LE-LABEL-NEXT: .Lfunc_begin2: +; PPC64LE: # %bb.0: +; PPC64LE-NEXT: nop +; PPC64LE-NEXT: blr +; PPC64LE: .section __patchable_function_entries +; PPC64LE: .p2align 3, 0x0 +; PPC64LE-NEXT: .quad .Lfunc_begin2 +; PPC64LE-NOT: .section xray_instr_map +; PPC64LE-NOT: .section xray_fn_idx ret void } @@ -52,6 +86,21 @@ define i32 @f3() "patchable-function-entry"="1" "patchable-function-prefix"="2" ; PPC64: .p2align 3, 0x0 ; PPC32-NEXT: .long .Ltmp0 ; PPC64-NEXT: .quad .Ltmp0 +; +; PC64LE-LABEL: .Ltmp3: +; PC64LE-COUNT-2: nop +; PC64LE-LABEL: f3: +; PC64LE: # %bb.0: +; PC64LE-NEXT: nop +; PC64LE: addis 3, 2, .LC0@toc@ha +; PC64LE-NEXT: ld 3, .LC0@toc@l(3) +; PC64LE-NEXT: lwz 3, 0(3) +; PC64LE: blr +; PC64LE: .section __patchable_function_entries +; PPC64LE: .p2align 3, 0x0 +; PPC64LE-NEXT: .quad .Ltmp3 +; PC64LE-NOT: .section xray_instr_map +; PC64LE-NOT: .section xray_fn_idx entry: %0 = load i32, ptr @a, align 4 ret i32 %0 diff --git a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll index 58e228a5a0cc..ff8c7ffa272d 100644 --- a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll +++ b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll @@ -309,4 +309,4 @@ entry: %call = tail call nnan ninf afn nsz double @llvm.pow.f64(double %a, double 5.000000e-01) ret double %call } -attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "approx-func-fp-math"="true" } +attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } diff --git a/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll b/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll index c43bccc3f239..3e0cdb03d386 100644 --- a/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll +++ b/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll @@ -453,4 +453,4 @@ entry: ret double %call } -attributes #1 = { "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } +attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" } diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll index b540948b20f7..eaab932c41df 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll @@ -190,1000 +190,25 @@ entry: ret <8 x i16> %6 } -; FIXME: This does not produce ISD::ABS. This does not even vectorize correctly! -; This function should look like sub_absv_32 and sub_absv_16 except that the type is v16i8. -; Function Attrs: norecurse nounwind readnone define <16 x i8> @sub_absv_8_ext(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr { -; CHECK-PWR9-LE-LABEL: sub_absv_8_ext: -; CHECK-PWR9-LE: # %bb.0: # %entry -; CHECK-PWR9-LE-NEXT: li r3, 0 -; CHECK-PWR9-LE-NEXT: li r5, 2 -; CHECK-PWR9-LE-NEXT: li r4, 1 -; CHECK-PWR9-LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-PWR9-LE-NEXT: vextubrx r6, r3, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r3, r3, v3 -; CHECK-PWR9-LE-NEXT: vextubrx r8, r5, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r5, r5, v3 -; CHECK-PWR9-LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-PWR9-LE-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-PWR9-LE-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; CHECK-PWR9-LE-NEXT: std r26, -48(r1) # 8-byte Folded Spill -; CHECK-PWR9-LE-NEXT: std r25, -56(r1) # 8-byte Folded Spill -; CHECK-PWR9-LE-NEXT: clrlwi r6, r6, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r3, r3, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r5, r5, 24 -; CHECK-PWR9-LE-NEXT: vextubrx r7, r4, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r4, r4, v3 -; CHECK-PWR9-LE-NEXT: sub r3, r6, r3 -; CHECK-PWR9-LE-NEXT: sub r6, r8, r5 -; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r4, r4, 24 -; CHECK-PWR9-LE-NEXT: sub r4, r7, r4 -; CHECK-PWR9-LE-NEXT: srawi r5, r3, 31 -; CHECK-PWR9-LE-NEXT: srawi r7, r4, 31 -; CHECK-PWR9-LE-NEXT: xor r3, r3, r5 -; CHECK-PWR9-LE-NEXT: xor r4, r4, r7 -; CHECK-PWR9-LE-NEXT: sub r5, r3, r5 -; CHECK-PWR9-LE-NEXT: srawi r3, r6, 31 -; CHECK-PWR9-LE-NEXT: sub r4, r4, r7 -; CHECK-PWR9-LE-NEXT: xor r6, r6, r3 -; CHECK-PWR9-LE-NEXT: sub r3, r6, r3 -; CHECK-PWR9-LE-NEXT: li r6, 3 -; CHECK-PWR9-LE-NEXT: vextubrx r7, r6, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r6, r6, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r6, r6, 24 -; CHECK-PWR9-LE-NEXT: sub r6, r7, r6 -; CHECK-PWR9-LE-NEXT: srawi r7, r6, 31 -; CHECK-PWR9-LE-NEXT: xor r6, r6, r7 -; CHECK-PWR9-LE-NEXT: sub r6, r6, r7 -; CHECK-PWR9-LE-NEXT: li r7, 4 -; CHECK-PWR9-LE-NEXT: vextubrx r8, r7, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r7, r7, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v4, r6 -; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24 -; CHECK-PWR9-LE-NEXT: sub r7, r8, r7 -; CHECK-PWR9-LE-NEXT: srawi r8, r7, 31 -; CHECK-PWR9-LE-NEXT: xor r7, r7, r8 -; CHECK-PWR9-LE-NEXT: sub r7, r7, r8 -; CHECK-PWR9-LE-NEXT: li r8, 5 -; CHECK-PWR9-LE-NEXT: vextubrx r9, r8, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r8, r8, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24 -; CHECK-PWR9-LE-NEXT: sub r8, r9, r8 -; CHECK-PWR9-LE-NEXT: srawi r9, r8, 31 -; CHECK-PWR9-LE-NEXT: xor r8, r8, r9 -; CHECK-PWR9-LE-NEXT: sub r8, r8, r9 -; CHECK-PWR9-LE-NEXT: li r9, 6 -; CHECK-PWR9-LE-NEXT: vextubrx r10, r9, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r9, r9, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24 -; CHECK-PWR9-LE-NEXT: sub r9, r10, r9 -; CHECK-PWR9-LE-NEXT: srawi r10, r9, 31 -; CHECK-PWR9-LE-NEXT: xor r9, r9, r10 -; CHECK-PWR9-LE-NEXT: sub r9, r9, r10 -; CHECK-PWR9-LE-NEXT: li r10, 7 -; CHECK-PWR9-LE-NEXT: vextubrx r11, r10, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r10, r10, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24 -; CHECK-PWR9-LE-NEXT: sub r10, r11, r10 -; CHECK-PWR9-LE-NEXT: srawi r11, r10, 31 -; CHECK-PWR9-LE-NEXT: xor r10, r10, r11 -; CHECK-PWR9-LE-NEXT: sub r10, r10, r11 -; CHECK-PWR9-LE-NEXT: li r11, 8 -; CHECK-PWR9-LE-NEXT: vextubrx r12, r11, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r11, r11, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v5, r10 -; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24 -; CHECK-PWR9-LE-NEXT: sub r11, r12, r11 -; CHECK-PWR9-LE-NEXT: srawi r12, r11, 31 -; CHECK-PWR9-LE-NEXT: xor r11, r11, r12 -; CHECK-PWR9-LE-NEXT: sub r11, r11, r12 -; CHECK-PWR9-LE-NEXT: li r12, 9 -; CHECK-PWR9-LE-NEXT: vextubrx r0, r12, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r12, r12, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24 -; CHECK-PWR9-LE-NEXT: sub r12, r0, r12 -; CHECK-PWR9-LE-NEXT: srawi r0, r12, 31 -; CHECK-PWR9-LE-NEXT: xor r12, r12, r0 -; CHECK-PWR9-LE-NEXT: sub r12, r12, r0 -; CHECK-PWR9-LE-NEXT: li r0, 10 -; CHECK-PWR9-LE-NEXT: vextubrx r30, r0, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r0, r0, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24 -; CHECK-PWR9-LE-NEXT: sub r0, r30, r0 -; CHECK-PWR9-LE-NEXT: srawi r30, r0, 31 -; CHECK-PWR9-LE-NEXT: xor r0, r0, r30 -; CHECK-PWR9-LE-NEXT: sub r0, r0, r30 -; CHECK-PWR9-LE-NEXT: li r30, 11 -; CHECK-PWR9-LE-NEXT: vextubrx r29, r30, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r30, r30, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24 -; CHECK-PWR9-LE-NEXT: sub r30, r29, r30 -; CHECK-PWR9-LE-NEXT: srawi r29, r30, 31 -; CHECK-PWR9-LE-NEXT: xor r30, r30, r29 -; CHECK-PWR9-LE-NEXT: sub r30, r30, r29 -; CHECK-PWR9-LE-NEXT: li r29, 12 -; CHECK-PWR9-LE-NEXT: vextubrx r28, r29, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r29, r29, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24 -; CHECK-PWR9-LE-NEXT: sub r29, r28, r29 -; CHECK-PWR9-LE-NEXT: srawi r28, r29, 31 -; CHECK-PWR9-LE-NEXT: xor r29, r29, r28 -; CHECK-PWR9-LE-NEXT: sub r29, r29, r28 -; CHECK-PWR9-LE-NEXT: li r28, 13 -; CHECK-PWR9-LE-NEXT: vextubrx r27, r28, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r28, r28, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24 -; CHECK-PWR9-LE-NEXT: sub r28, r27, r28 -; CHECK-PWR9-LE-NEXT: srawi r27, r28, 31 -; CHECK-PWR9-LE-NEXT: xor r28, r28, r27 -; CHECK-PWR9-LE-NEXT: sub r28, r28, r27 -; CHECK-PWR9-LE-NEXT: li r27, 14 -; CHECK-PWR9-LE-NEXT: vextubrx r26, r27, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r27, r27, v3 -; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24 -; CHECK-PWR9-LE-NEXT: sub r27, r26, r27 -; CHECK-PWR9-LE-NEXT: srawi r26, r27, 31 -; CHECK-PWR9-LE-NEXT: xor r27, r27, r26 -; CHECK-PWR9-LE-NEXT: sub r27, r27, r26 -; CHECK-PWR9-LE-NEXT: li r26, 15 -; CHECK-PWR9-LE-NEXT: vextubrx r25, r26, v2 -; CHECK-PWR9-LE-NEXT: vextubrx r26, r26, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v2, r5 -; CHECK-PWR9-LE-NEXT: mtvsrd v3, r4 -; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2 -; CHECK-PWR9-LE-NEXT: mtvsrd v3, r3 -; CHECK-PWR9-LE-NEXT: clrlwi r25, r25, 24 -; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24 -; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v4, r8 -; CHECK-PWR9-LE-NEXT: sub r26, r25, r26 -; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2 -; CHECK-PWR9-LE-NEXT: mtvsrd v3, r7 -; CHECK-PWR9-LE-NEXT: srawi r25, r26, 31 -; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v4, r9 -; CHECK-PWR9-LE-NEXT: xor r26, r26, r25 -; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4 -; CHECK-PWR9-LE-NEXT: sub r26, r26, r25 -; CHECK-PWR9-LE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload -; CHECK-PWR9-LE-NEXT: mtvsrd v5, r26 -; CHECK-PWR9-LE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v4, r30 -; CHECK-PWR9-LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-PWR9-LE-NEXT: xxmrglw vs0, v3, v2 -; CHECK-PWR9-LE-NEXT: mtvsrd v2, r11 -; CHECK-PWR9-LE-NEXT: mtvsrd v3, r12 -; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2 -; CHECK-PWR9-LE-NEXT: mtvsrd v3, r0 -; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v4, r28 -; CHECK-PWR9-LE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2 -; CHECK-PWR9-LE-NEXT: mtvsrd v3, r29 -; CHECK-PWR9-LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR9-LE-NEXT: mtvsrd v4, r27 -; CHECK-PWR9-LE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4 -; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3 -; CHECK-PWR9-LE-NEXT: xxmrglw vs1, v3, v2 -; CHECK-PWR9-LE-NEXT: xxmrgld v2, vs1, vs0 -; CHECK-PWR9-LE-NEXT: blr -; -; CHECK-PWR9-BE-LABEL: sub_absv_8_ext: -; CHECK-PWR9-BE: # %bb.0: # %entry -; CHECK-PWR9-BE-NEXT: li r3, 0 -; CHECK-PWR9-BE-NEXT: li r4, 1 -; CHECK-PWR9-BE-NEXT: li r5, 2 -; CHECK-PWR9-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-PWR9-BE-NEXT: vextublx r6, r3, v2 -; CHECK-PWR9-BE-NEXT: vextublx r3, r3, v3 -; CHECK-PWR9-BE-NEXT: vextublx r7, r4, v2 -; CHECK-PWR9-BE-NEXT: vextublx r4, r4, v3 -; CHECK-PWR9-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-PWR9-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-PWR9-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; CHECK-PWR9-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill -; CHECK-PWR9-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill -; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r3, r3, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r4, r4, 24 -; CHECK-PWR9-BE-NEXT: vextublx r8, r5, v2 -; CHECK-PWR9-BE-NEXT: vextublx r5, r5, v3 -; CHECK-PWR9-BE-NEXT: sub r3, r6, r3 -; CHECK-PWR9-BE-NEXT: sub r4, r7, r4 -; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r5, r5, 24 -; CHECK-PWR9-BE-NEXT: sub r5, r8, r5 -; CHECK-PWR9-BE-NEXT: srawi r6, r3, 31 -; CHECK-PWR9-BE-NEXT: srawi r7, r4, 31 -; CHECK-PWR9-BE-NEXT: srawi r8, r5, 31 -; CHECK-PWR9-BE-NEXT: xor r3, r3, r6 -; CHECK-PWR9-BE-NEXT: xor r4, r4, r7 -; CHECK-PWR9-BE-NEXT: xor r5, r5, r8 -; CHECK-PWR9-BE-NEXT: sub r3, r3, r6 -; CHECK-PWR9-BE-NEXT: li r6, 3 -; CHECK-PWR9-BE-NEXT: sub r4, r4, r7 -; CHECK-PWR9-BE-NEXT: sub r5, r5, r8 -; CHECK-PWR9-BE-NEXT: vextublx r7, r6, v2 -; CHECK-PWR9-BE-NEXT: vextublx r6, r6, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24 -; CHECK-PWR9-BE-NEXT: sub r6, r7, r6 -; CHECK-PWR9-BE-NEXT: srawi r7, r6, 31 -; CHECK-PWR9-BE-NEXT: xor r6, r6, r7 -; CHECK-PWR9-BE-NEXT: sub r6, r6, r7 -; CHECK-PWR9-BE-NEXT: li r7, 4 -; CHECK-PWR9-BE-NEXT: vextublx r8, r7, v2 -; CHECK-PWR9-BE-NEXT: vextublx r7, r7, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24 -; CHECK-PWR9-BE-NEXT: sub r7, r8, r7 -; CHECK-PWR9-BE-NEXT: srawi r8, r7, 31 -; CHECK-PWR9-BE-NEXT: xor r7, r7, r8 -; CHECK-PWR9-BE-NEXT: sub r7, r7, r8 -; CHECK-PWR9-BE-NEXT: li r8, 5 -; CHECK-PWR9-BE-NEXT: vextublx r9, r8, v2 -; CHECK-PWR9-BE-NEXT: vextublx r8, r8, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24 -; CHECK-PWR9-BE-NEXT: sub r8, r9, r8 -; CHECK-PWR9-BE-NEXT: srawi r9, r8, 31 -; CHECK-PWR9-BE-NEXT: xor r8, r8, r9 -; CHECK-PWR9-BE-NEXT: sub r8, r8, r9 -; CHECK-PWR9-BE-NEXT: li r9, 6 -; CHECK-PWR9-BE-NEXT: vextublx r10, r9, v2 -; CHECK-PWR9-BE-NEXT: vextublx r9, r9, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24 -; CHECK-PWR9-BE-NEXT: sub r9, r10, r9 -; CHECK-PWR9-BE-NEXT: srawi r10, r9, 31 -; CHECK-PWR9-BE-NEXT: xor r9, r9, r10 -; CHECK-PWR9-BE-NEXT: sub r9, r9, r10 -; CHECK-PWR9-BE-NEXT: li r10, 7 -; CHECK-PWR9-BE-NEXT: vextublx r11, r10, v2 -; CHECK-PWR9-BE-NEXT: vextublx r10, r10, v3 -; CHECK-PWR9-BE-NEXT: mtfprwz f2, r9 -; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24 -; CHECK-PWR9-BE-NEXT: sub r10, r11, r10 -; CHECK-PWR9-BE-NEXT: srawi r11, r10, 31 -; CHECK-PWR9-BE-NEXT: xor r10, r10, r11 -; CHECK-PWR9-BE-NEXT: sub r10, r10, r11 -; CHECK-PWR9-BE-NEXT: li r11, 8 -; CHECK-PWR9-BE-NEXT: vextublx r12, r11, v2 -; CHECK-PWR9-BE-NEXT: vextublx r11, r11, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24 -; CHECK-PWR9-BE-NEXT: sub r11, r12, r11 -; CHECK-PWR9-BE-NEXT: srawi r12, r11, 31 -; CHECK-PWR9-BE-NEXT: xor r11, r11, r12 -; CHECK-PWR9-BE-NEXT: sub r11, r11, r12 -; CHECK-PWR9-BE-NEXT: li r12, 9 -; CHECK-PWR9-BE-NEXT: vextublx r0, r12, v2 -; CHECK-PWR9-BE-NEXT: vextublx r12, r12, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24 -; CHECK-PWR9-BE-NEXT: sub r12, r0, r12 -; CHECK-PWR9-BE-NEXT: srawi r0, r12, 31 -; CHECK-PWR9-BE-NEXT: xor r12, r12, r0 -; CHECK-PWR9-BE-NEXT: sub r12, r12, r0 -; CHECK-PWR9-BE-NEXT: li r0, 10 -; CHECK-PWR9-BE-NEXT: vextublx r30, r0, v2 -; CHECK-PWR9-BE-NEXT: vextublx r0, r0, v3 -; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r12 -; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24 -; CHECK-PWR9-BE-NEXT: sub r0, r30, r0 -; CHECK-PWR9-BE-NEXT: srawi r30, r0, 31 -; CHECK-PWR9-BE-NEXT: xor r0, r0, r30 -; CHECK-PWR9-BE-NEXT: sub r0, r0, r30 -; CHECK-PWR9-BE-NEXT: li r30, 11 -; CHECK-PWR9-BE-NEXT: vextublx r29, r30, v2 -; CHECK-PWR9-BE-NEXT: vextublx r30, r30, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24 -; CHECK-PWR9-BE-NEXT: sub r30, r29, r30 -; CHECK-PWR9-BE-NEXT: srawi r29, r30, 31 -; CHECK-PWR9-BE-NEXT: xor r30, r30, r29 -; CHECK-PWR9-BE-NEXT: sub r30, r30, r29 -; CHECK-PWR9-BE-NEXT: li r29, 12 -; CHECK-PWR9-BE-NEXT: vextublx r28, r29, v2 -; CHECK-PWR9-BE-NEXT: vextublx r29, r29, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24 -; CHECK-PWR9-BE-NEXT: sub r29, r28, r29 -; CHECK-PWR9-BE-NEXT: srawi r28, r29, 31 -; CHECK-PWR9-BE-NEXT: xor r29, r29, r28 -; CHECK-PWR9-BE-NEXT: sub r29, r29, r28 -; CHECK-PWR9-BE-NEXT: li r28, 13 -; CHECK-PWR9-BE-NEXT: vextublx r27, r28, v2 -; CHECK-PWR9-BE-NEXT: vextublx r28, r28, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24 -; CHECK-PWR9-BE-NEXT: sub r28, r27, r28 -; CHECK-PWR9-BE-NEXT: srawi r27, r28, 31 -; CHECK-PWR9-BE-NEXT: xor r28, r28, r27 -; CHECK-PWR9-BE-NEXT: sub r28, r28, r27 -; CHECK-PWR9-BE-NEXT: li r27, 14 -; CHECK-PWR9-BE-NEXT: vextublx r26, r27, v2 -; CHECK-PWR9-BE-NEXT: vextublx r27, r27, v3 -; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24 -; CHECK-PWR9-BE-NEXT: sub r27, r26, r27 -; CHECK-PWR9-BE-NEXT: srawi r26, r27, 31 -; CHECK-PWR9-BE-NEXT: xor r27, r27, r26 -; CHECK-PWR9-BE-NEXT: sub r27, r27, r26 -; CHECK-PWR9-BE-NEXT: li r26, 15 -; CHECK-PWR9-BE-NEXT: vextublx r25, r26, v2 -; CHECK-PWR9-BE-NEXT: vextublx r26, r26, v3 -; CHECK-PWR9-BE-NEXT: mtfprwz f0, r27 -; CHECK-PWR9-BE-NEXT: addis r27, r2, .LCPI9_0@toc@ha -; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r28 -; CHECK-PWR9-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: addi r27, r27, .LCPI9_0@toc@l -; CHECK-PWR9-BE-NEXT: clrlwi r25, r25, 24 -; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24 -; CHECK-PWR9-BE-NEXT: lxv vs1, 0(r27) -; CHECK-PWR9-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: sub r26, r25, r26 -; CHECK-PWR9-BE-NEXT: srawi r25, r26, 31 -; CHECK-PWR9-BE-NEXT: xor r26, r26, r25 -; CHECK-PWR9-BE-NEXT: sub r26, r26, r25 -; CHECK-PWR9-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r26 -; CHECK-PWR9-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: xxperm v2, vs0, vs1 -; CHECK-PWR9-BE-NEXT: mtfprwz f0, r29 -; CHECK-PWR9-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1 -; CHECK-PWR9-BE-NEXT: mtfprwz f0, r0 -; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2 -; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r30 -; CHECK-PWR9-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1 -; CHECK-PWR9-BE-NEXT: mtfprwz f0, r11 -; CHECK-PWR9-BE-NEXT: xxperm v4, vs0, vs1 -; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r4 -; CHECK-PWR9-BE-NEXT: xxmrghw vs0, v3, v2 -; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r10 -; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r8 -; CHECK-PWR9-BE-NEXT: xxperm v2, vs2, vs1 -; CHECK-PWR9-BE-NEXT: mtfprwz f2, r7 -; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1 -; CHECK-PWR9-BE-NEXT: mtfprwz f2, r5 -; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2 -; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r6 -; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1 -; CHECK-PWR9-BE-NEXT: mtfprwz f2, r3 -; CHECK-PWR9-BE-NEXT: xxperm v4, vs2, vs1 -; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-PWR9-BE-NEXT: xxmrghw vs1, v3, v2 -; CHECK-PWR9-BE-NEXT: xxmrghd v2, vs1, vs0 -; CHECK-PWR9-BE-NEXT: blr -; -; CHECK-PWR8-LABEL: sub_absv_8_ext: -; CHECK-PWR8: # %bb.0: # %entry -; CHECK-PWR8-NEXT: xxswapd vs0, v2 -; CHECK-PWR8-NEXT: xxswapd vs1, v3 -; CHECK-PWR8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-PWR8-NEXT: std r28, -32(r1) # 8-byte Folded Spill -; CHECK-PWR8-NEXT: std r29, -24(r1) # 8-byte Folded Spill -; CHECK-PWR8-NEXT: std r26, -48(r1) # 8-byte Folded Spill -; CHECK-PWR8-NEXT: mffprd r11, f0 -; CHECK-PWR8-NEXT: mffprd r8, f1 -; CHECK-PWR8-NEXT: std r27, -40(r1) # 8-byte Folded Spill -; CHECK-PWR8-NEXT: std r25, -56(r1) # 8-byte Folded Spill -; CHECK-PWR8-NEXT: clrldi r3, r11, 56 -; CHECK-PWR8-NEXT: clrldi r4, r8, 56 -; CHECK-PWR8-NEXT: rldicl r5, r11, 56, 56 -; CHECK-PWR8-NEXT: rldicl r6, r8, 56, 56 -; CHECK-PWR8-NEXT: rldicl r7, r11, 48, 56 -; CHECK-PWR8-NEXT: rldicl r9, r8, 48, 56 -; CHECK-PWR8-NEXT: rldicl r0, r11, 32, 56 -; CHECK-PWR8-NEXT: rldicl r30, r8, 32, 56 -; CHECK-PWR8-NEXT: rldicl r29, r11, 24, 56 -; CHECK-PWR8-NEXT: rldicl r28, r8, 24, 56 -; CHECK-PWR8-NEXT: rldicl r10, r11, 40, 56 -; CHECK-PWR8-NEXT: rldicl r12, r8, 40, 56 -; CHECK-PWR8-NEXT: rldicl r27, r11, 16, 56 -; CHECK-PWR8-NEXT: rldicl r11, r11, 8, 56 -; CHECK-PWR8-NEXT: std r24, -64(r1) # 8-byte Folded Spill -; CHECK-PWR8-NEXT: clrlwi r3, r3, 24 -; CHECK-PWR8-NEXT: clrlwi r4, r4, 24 -; CHECK-PWR8-NEXT: clrlwi r5, r5, 24 -; CHECK-PWR8-NEXT: clrlwi r6, r6, 24 -; CHECK-PWR8-NEXT: clrlwi r7, r7, 24 -; CHECK-PWR8-NEXT: clrlwi r9, r9, 24 -; CHECK-PWR8-NEXT: sub r3, r3, r4 -; CHECK-PWR8-NEXT: clrlwi r0, r0, 24 -; CHECK-PWR8-NEXT: clrlwi r30, r30, 24 -; CHECK-PWR8-NEXT: sub r4, r5, r6 -; CHECK-PWR8-NEXT: sub r5, r7, r9 -; CHECK-PWR8-NEXT: clrlwi r29, r29, 24 -; CHECK-PWR8-NEXT: clrlwi r28, r28, 24 -; CHECK-PWR8-NEXT: sub r7, r0, r30 -; CHECK-PWR8-NEXT: sub r9, r29, r28 -; CHECK-PWR8-NEXT: clrlwi r10, r10, 24 -; CHECK-PWR8-NEXT: clrlwi r12, r12, 24 -; CHECK-PWR8-NEXT: sub r6, r10, r12 -; CHECK-PWR8-NEXT: clrlwi r27, r27, 24 -; CHECK-PWR8-NEXT: clrlwi r11, r11, 24 -; CHECK-PWR8-NEXT: srawi r0, r5, 31 -; CHECK-PWR8-NEXT: srawi r29, r7, 31 -; CHECK-PWR8-NEXT: srawi r12, r4, 31 -; CHECK-PWR8-NEXT: srawi r28, r9, 31 -; CHECK-PWR8-NEXT: srawi r30, r6, 31 -; CHECK-PWR8-NEXT: srawi r10, r3, 31 -; CHECK-PWR8-NEXT: xor r5, r5, r0 -; CHECK-PWR8-NEXT: xor r26, r7, r29 -; CHECK-PWR8-NEXT: sub r7, r5, r0 -; CHECK-PWR8-NEXT: rldicl r5, r8, 16, 56 -; CHECK-PWR8-NEXT: rldicl r8, r8, 8, 56 -; CHECK-PWR8-NEXT: xor r4, r4, r12 -; CHECK-PWR8-NEXT: xor r25, r9, r28 -; CHECK-PWR8-NEXT: sub r9, r4, r12 -; CHECK-PWR8-NEXT: sub r4, r26, r29 -; CHECK-PWR8-NEXT: mtvsrd v1, r9 -; CHECK-PWR8-NEXT: clrlwi r5, r5, 24 -; CHECK-PWR8-NEXT: sub r5, r27, r5 -; CHECK-PWR8-NEXT: clrlwi r8, r8, 24 -; CHECK-PWR8-NEXT: sub r8, r11, r8 -; CHECK-PWR8-NEXT: xor r6, r6, r30 -; CHECK-PWR8-NEXT: sub r6, r6, r30 -; CHECK-PWR8-NEXT: xor r3, r3, r10 -; CHECK-PWR8-NEXT: sub r10, r3, r10 -; CHECK-PWR8-NEXT: sub r3, r25, r28 -; CHECK-PWR8-NEXT: mtvsrd v6, r6 -; CHECK-PWR8-NEXT: mtvsrd v7, r3 -; CHECK-PWR8-NEXT: srawi r12, r5, 31 -; CHECK-PWR8-NEXT: srawi r11, r8, 31 -; CHECK-PWR8-NEXT: xor r5, r5, r12 -; CHECK-PWR8-NEXT: xor r8, r8, r11 -; CHECK-PWR8-NEXT: sub r5, r5, r12 -; CHECK-PWR8-NEXT: sub r8, r8, r11 -; CHECK-PWR8-NEXT: mfvsrd r11, v2 -; CHECK-PWR8-NEXT: mfvsrd r12, v3 -; CHECK-PWR8-NEXT: mtvsrd v8, r8 -; CHECK-PWR8-NEXT: clrldi r0, r11, 56 -; CHECK-PWR8-NEXT: clrldi r30, r12, 56 -; CHECK-PWR8-NEXT: rldicl r29, r12, 56, 56 -; CHECK-PWR8-NEXT: rldicl r28, r12, 48, 56 -; CHECK-PWR8-NEXT: rldicl r27, r12, 40, 56 -; CHECK-PWR8-NEXT: rldicl r26, r12, 32, 56 -; CHECK-PWR8-NEXT: rldicl r25, r12, 24, 56 -; CHECK-PWR8-NEXT: rldicl r24, r12, 16, 56 -; CHECK-PWR8-NEXT: rldicl r12, r12, 8, 56 -; CHECK-PWR8-NEXT: clrlwi r0, r0, 24 -; CHECK-PWR8-NEXT: clrlwi r30, r30, 24 -; CHECK-PWR8-NEXT: clrlwi r29, r29, 24 -; CHECK-PWR8-NEXT: clrlwi r28, r28, 24 -; CHECK-PWR8-NEXT: clrlwi r27, r27, 24 -; CHECK-PWR8-NEXT: clrlwi r26, r26, 24 -; CHECK-PWR8-NEXT: clrlwi r25, r25, 24 -; CHECK-PWR8-NEXT: clrlwi r24, r24, 24 -; CHECK-PWR8-NEXT: clrlwi r12, r12, 24 -; CHECK-PWR8-NEXT: sub r0, r0, r30 -; CHECK-PWR8-NEXT: srawi r30, r0, 31 -; CHECK-PWR8-NEXT: xor r0, r0, r30 -; CHECK-PWR8-NEXT: sub r0, r0, r30 -; CHECK-PWR8-NEXT: rldicl r30, r11, 56, 56 -; CHECK-PWR8-NEXT: clrlwi r30, r30, 24 -; CHECK-PWR8-NEXT: mtvsrd v2, r0 -; CHECK-PWR8-NEXT: sub r30, r30, r29 -; CHECK-PWR8-NEXT: srawi r29, r30, 31 -; CHECK-PWR8-NEXT: xor r30, r30, r29 -; CHECK-PWR8-NEXT: sub r30, r30, r29 -; CHECK-PWR8-NEXT: rldicl r29, r11, 48, 56 -; CHECK-PWR8-NEXT: clrlwi r29, r29, 24 -; CHECK-PWR8-NEXT: mtvsrd v3, r30 -; CHECK-PWR8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-PWR8-NEXT: sub r29, r29, r28 -; CHECK-PWR8-NEXT: srawi r28, r29, 31 -; CHECK-PWR8-NEXT: xor r29, r29, r28 -; CHECK-PWR8-NEXT: sub r29, r29, r28 -; CHECK-PWR8-NEXT: rldicl r28, r11, 40, 56 -; CHECK-PWR8-NEXT: clrlwi r28, r28, 24 -; CHECK-PWR8-NEXT: sub r28, r28, r27 -; CHECK-PWR8-NEXT: srawi r27, r28, 31 -; CHECK-PWR8-NEXT: xor r28, r28, r27 -; CHECK-PWR8-NEXT: sub r28, r28, r27 -; CHECK-PWR8-NEXT: rldicl r27, r11, 32, 56 -; CHECK-PWR8-NEXT: clrlwi r27, r27, 24 -; CHECK-PWR8-NEXT: mtvsrd v4, r28 -; CHECK-PWR8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; CHECK-PWR8-NEXT: sub r27, r27, r26 -; CHECK-PWR8-NEXT: srawi r26, r27, 31 -; CHECK-PWR8-NEXT: xor r27, r27, r26 -; CHECK-PWR8-NEXT: sub r27, r27, r26 -; CHECK-PWR8-NEXT: rldicl r26, r11, 24, 56 -; CHECK-PWR8-NEXT: clrlwi r26, r26, 24 -; CHECK-PWR8-NEXT: sub r26, r26, r25 -; CHECK-PWR8-NEXT: srawi r25, r26, 31 -; CHECK-PWR8-NEXT: xor r26, r26, r25 -; CHECK-PWR8-NEXT: sub r26, r26, r25 -; CHECK-PWR8-NEXT: rldicl r25, r11, 16, 56 -; CHECK-PWR8-NEXT: rldicl r11, r11, 8, 56 -; CHECK-PWR8-NEXT: clrlwi r25, r25, 24 -; CHECK-PWR8-NEXT: clrlwi r11, r11, 24 -; CHECK-PWR8-NEXT: mtvsrd v5, r26 -; CHECK-PWR8-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; CHECK-PWR8-NEXT: sub r25, r25, r24 -; CHECK-PWR8-NEXT: sub r11, r11, r12 -; CHECK-PWR8-NEXT: srawi r24, r25, 31 -; CHECK-PWR8-NEXT: srawi r12, r11, 31 -; CHECK-PWR8-NEXT: xor r25, r25, r24 -; CHECK-PWR8-NEXT: xor r11, r11, r12 -; CHECK-PWR8-NEXT: sub r25, r25, r24 -; CHECK-PWR8-NEXT: sub r11, r11, r12 -; CHECK-PWR8-NEXT: ld r24, -64(r1) # 8-byte Folded Reload -; CHECK-PWR8-NEXT: mtvsrd v0, r11 -; CHECK-PWR8-NEXT: vmrghb v2, v3, v2 -; CHECK-PWR8-NEXT: mtvsrd v3, r29 -; CHECK-PWR8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload -; CHECK-PWR8-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR8-NEXT: mtvsrd v4, r27 -; CHECK-PWR8-NEXT: ld r27, -40(r1) # 8-byte Folded Reload -; CHECK-PWR8-NEXT: vmrglh v2, v3, v2 -; CHECK-PWR8-NEXT: vmrghb v4, v5, v4 -; CHECK-PWR8-NEXT: mtvsrd v5, r25 -; CHECK-PWR8-NEXT: ld r25, -56(r1) # 8-byte Folded Reload -; CHECK-PWR8-NEXT: vmrghb v5, v0, v5 -; CHECK-PWR8-NEXT: mtvsrd v0, r10 -; CHECK-PWR8-NEXT: vmrglh v3, v5, v4 -; CHECK-PWR8-NEXT: xxmrglw vs0, v3, v2 -; CHECK-PWR8-NEXT: vmrghb v0, v1, v0 -; CHECK-PWR8-NEXT: mtvsrd v1, r7 -; CHECK-PWR8-NEXT: vmrghb v1, v6, v1 -; CHECK-PWR8-NEXT: mtvsrd v6, r4 -; CHECK-PWR8-NEXT: vmrglh v4, v1, v0 -; CHECK-PWR8-NEXT: vmrghb v6, v7, v6 -; CHECK-PWR8-NEXT: mtvsrd v7, r5 -; CHECK-PWR8-NEXT: vmrghb v7, v8, v7 -; CHECK-PWR8-NEXT: vmrglh v5, v7, v6 -; CHECK-PWR8-NEXT: xxmrglw vs1, v5, v4 -; CHECK-PWR8-NEXT: xxmrgld v2, vs0, vs1 -; CHECK-PWR8-NEXT: blr +; CHECK-PWR9-LABEL: sub_absv_8_ext: +; CHECK-PWR9: # %bb.0: # %entry +; CHECK-PWR9-NEXT: vabsdub v2, v2, v3 +; CHECK-PWR9-NEXT: blr ; -; CHECK-PWR7-LABEL: sub_absv_8_ext: -; CHECK-PWR7: # %bb.0: # %entry -; CHECK-PWR7-NEXT: stdu r1, -512(r1) -; CHECK-PWR7-NEXT: .cfi_def_cfa_offset 512 -; CHECK-PWR7-NEXT: .cfi_offset r14, -144 -; CHECK-PWR7-NEXT: .cfi_offset r15, -136 -; CHECK-PWR7-NEXT: .cfi_offset r16, -128 -; CHECK-PWR7-NEXT: .cfi_offset r17, -120 -; CHECK-PWR7-NEXT: .cfi_offset r18, -112 -; CHECK-PWR7-NEXT: .cfi_offset r19, -104 -; CHECK-PWR7-NEXT: .cfi_offset r20, -96 -; CHECK-PWR7-NEXT: .cfi_offset r21, -88 -; CHECK-PWR7-NEXT: .cfi_offset r22, -80 -; CHECK-PWR7-NEXT: .cfi_offset r23, -72 -; CHECK-PWR7-NEXT: .cfi_offset r24, -64 -; CHECK-PWR7-NEXT: .cfi_offset r25, -56 -; CHECK-PWR7-NEXT: .cfi_offset r26, -48 -; CHECK-PWR7-NEXT: .cfi_offset r27, -40 -; CHECK-PWR7-NEXT: .cfi_offset r28, -32 -; CHECK-PWR7-NEXT: .cfi_offset r29, -24 -; CHECK-PWR7-NEXT: .cfi_offset r30, -16 -; CHECK-PWR7-NEXT: .cfi_offset r31, -8 -; CHECK-PWR7-NEXT: .cfi_offset r2, -152 -; CHECK-PWR7-NEXT: addi r3, r1, 320 -; CHECK-PWR7-NEXT: std r14, 368(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r15, 376(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r16, 384(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r17, 392(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r18, 400(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r19, 408(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r20, 416(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r21, 424(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r22, 432(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r23, 440(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r24, 448(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r25, 456(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r26, 464(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r27, 472(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r28, 480(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r29, 488(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r30, 496(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r31, 504(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: std r2, 360(r1) # 8-byte Folded Spill -; CHECK-PWR7-NEXT: stxvw4x v2, 0, r3 -; CHECK-PWR7-NEXT: lbz r3, 320(r1) -; CHECK-PWR7-NEXT: addi r4, r1, 336 -; CHECK-PWR7-NEXT: stw r3, 60(r1) # 4-byte Folded Spill -; CHECK-PWR7-NEXT: stxvw4x v3, 0, r4 -; CHECK-PWR7-NEXT: lbz r15, 334(r1) -; CHECK-PWR7-NEXT: lbz r14, 350(r1) -; CHECK-PWR7-NEXT: lbz r31, 335(r1) -; CHECK-PWR7-NEXT: lbz r2, 351(r1) -; CHECK-PWR7-NEXT: sub r15, r15, r14 -; CHECK-PWR7-NEXT: sub r14, r31, r2 -; CHECK-PWR7-NEXT: srawi r2, r14, 31 -; CHECK-PWR7-NEXT: xor r14, r14, r2 -; CHECK-PWR7-NEXT: lbz r3, 333(r1) -; CHECK-PWR7-NEXT: lbz r19, 331(r1) -; CHECK-PWR7-NEXT: lbz r18, 347(r1) -; CHECK-PWR7-NEXT: sub r19, r19, r18 -; CHECK-PWR7-NEXT: lbz r17, 332(r1) -; CHECK-PWR7-NEXT: lbz r16, 348(r1) -; CHECK-PWR7-NEXT: sub r17, r17, r16 -; CHECK-PWR7-NEXT: lbz r23, 329(r1) -; CHECK-PWR7-NEXT: sub r14, r14, r2 -; CHECK-PWR7-NEXT: lbz r2, 349(r1) -; CHECK-PWR7-NEXT: lbz r22, 345(r1) -; CHECK-PWR7-NEXT: lbz r4, 336(r1) -; CHECK-PWR7-NEXT: lbz r5, 321(r1) -; CHECK-PWR7-NEXT: lbz r6, 337(r1) -; CHECK-PWR7-NEXT: lbz r7, 322(r1) -; CHECK-PWR7-NEXT: lbz r8, 338(r1) -; CHECK-PWR7-NEXT: lbz r9, 323(r1) -; CHECK-PWR7-NEXT: lbz r10, 339(r1) -; CHECK-PWR7-NEXT: lbz r11, 324(r1) -; CHECK-PWR7-NEXT: lbz r12, 340(r1) -; CHECK-PWR7-NEXT: lbz r0, 325(r1) -; CHECK-PWR7-NEXT: lbz r30, 341(r1) -; CHECK-PWR7-NEXT: lbz r29, 326(r1) -; CHECK-PWR7-NEXT: lbz r28, 342(r1) -; CHECK-PWR7-NEXT: lbz r27, 327(r1) -; CHECK-PWR7-NEXT: lbz r26, 343(r1) -; CHECK-PWR7-NEXT: sub r3, r3, r2 -; CHECK-PWR7-NEXT: lbz r25, 328(r1) -; CHECK-PWR7-NEXT: lbz r24, 344(r1) -; CHECK-PWR7-NEXT: lbz r21, 330(r1) -; CHECK-PWR7-NEXT: lbz r20, 346(r1) -; CHECK-PWR7-NEXT: sub r5, r5, r6 -; CHECK-PWR7-NEXT: srawi r18, r3, 31 -; CHECK-PWR7-NEXT: sub r7, r7, r8 -; CHECK-PWR7-NEXT: sub r9, r9, r10 -; CHECK-PWR7-NEXT: sub r11, r11, r12 -; CHECK-PWR7-NEXT: sub r0, r0, r30 -; CHECK-PWR7-NEXT: sub r29, r29, r28 -; CHECK-PWR7-NEXT: sub r27, r27, r26 -; CHECK-PWR7-NEXT: sub r25, r25, r24 -; CHECK-PWR7-NEXT: srawi r31, r15, 31 -; CHECK-PWR7-NEXT: ld r2, 360(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: xor r3, r3, r18 -; CHECK-PWR7-NEXT: srawi r6, r5, 31 -; CHECK-PWR7-NEXT: srawi r8, r7, 31 -; CHECK-PWR7-NEXT: srawi r10, r9, 31 -; CHECK-PWR7-NEXT: srawi r12, r11, 31 -; CHECK-PWR7-NEXT: srawi r30, r0, 31 -; CHECK-PWR7-NEXT: sub r3, r3, r18 -; CHECK-PWR7-NEXT: srawi r18, r19, 31 -; CHECK-PWR7-NEXT: srawi r28, r29, 31 -; CHECK-PWR7-NEXT: ld r16, 384(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: sldi r3, r3, 56 -; CHECK-PWR7-NEXT: srawi r26, r27, 31 -; CHECK-PWR7-NEXT: srawi r24, r25, 31 -; CHECK-PWR7-NEXT: xor r19, r19, r18 -; CHECK-PWR7-NEXT: xor r15, r15, r31 -; CHECK-PWR7-NEXT: xor r5, r5, r6 -; CHECK-PWR7-NEXT: std r3, 272(r1) -; CHECK-PWR7-NEXT: std r3, 280(r1) -; CHECK-PWR7-NEXT: srawi r3, r17, 31 -; CHECK-PWR7-NEXT: sub r19, r19, r18 -; CHECK-PWR7-NEXT: xor r7, r7, r8 -; CHECK-PWR7-NEXT: sub r15, r15, r31 -; CHECK-PWR7-NEXT: xor r17, r17, r3 -; CHECK-PWR7-NEXT: xor r9, r9, r10 -; CHECK-PWR7-NEXT: xor r11, r11, r12 -; CHECK-PWR7-NEXT: xor r0, r0, r30 -; CHECK-PWR7-NEXT: xor r29, r29, r28 -; CHECK-PWR7-NEXT: xor r27, r27, r26 -; CHECK-PWR7-NEXT: sub r3, r17, r3 -; CHECK-PWR7-NEXT: xor r25, r25, r24 -; CHECK-PWR7-NEXT: sub r25, r25, r24 -; CHECK-PWR7-NEXT: sub r27, r27, r26 -; CHECK-PWR7-NEXT: sub r29, r29, r28 -; CHECK-PWR7-NEXT: sldi r3, r3, 56 -; CHECK-PWR7-NEXT: sub r0, r0, r30 -; CHECK-PWR7-NEXT: sub r11, r11, r12 -; CHECK-PWR7-NEXT: sub r9, r9, r10 -; CHECK-PWR7-NEXT: sub r7, r7, r8 -; CHECK-PWR7-NEXT: sub r5, r5, r6 -; CHECK-PWR7-NEXT: sldi r14, r14, 56 -; CHECK-PWR7-NEXT: sldi r15, r15, 56 -; CHECK-PWR7-NEXT: ld r31, 504(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: std r3, 256(r1) -; CHECK-PWR7-NEXT: std r3, 264(r1) -; CHECK-PWR7-NEXT: sldi r3, r19, 56 -; CHECK-PWR7-NEXT: sldi r25, r25, 56 -; CHECK-PWR7-NEXT: sldi r27, r27, 56 -; CHECK-PWR7-NEXT: std r3, 240(r1) -; CHECK-PWR7-NEXT: std r3, 248(r1) -; CHECK-PWR7-NEXT: sub r3, r23, r22 -; CHECK-PWR7-NEXT: srawi r23, r3, 31 -; CHECK-PWR7-NEXT: sub r22, r21, r20 -; CHECK-PWR7-NEXT: srawi r21, r22, 31 -; CHECK-PWR7-NEXT: sldi r29, r29, 56 -; CHECK-PWR7-NEXT: sldi r0, r0, 56 -; CHECK-PWR7-NEXT: sldi r11, r11, 56 -; CHECK-PWR7-NEXT: xor r3, r3, r23 -; CHECK-PWR7-NEXT: xor r22, r22, r21 -; CHECK-PWR7-NEXT: sldi r9, r9, 56 -; CHECK-PWR7-NEXT: sldi r7, r7, 56 -; CHECK-PWR7-NEXT: sldi r5, r5, 56 -; CHECK-PWR7-NEXT: ld r30, 496(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: ld r28, 480(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: sub r3, r3, r23 -; CHECK-PWR7-NEXT: sub r22, r22, r21 -; CHECK-PWR7-NEXT: std r14, 304(r1) -; CHECK-PWR7-NEXT: ld r26, 464(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: sldi r3, r3, 56 -; CHECK-PWR7-NEXT: sldi r22, r22, 56 -; CHECK-PWR7-NEXT: ld r24, 448(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: ld r23, 440(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: std r14, 312(r1) -; CHECK-PWR7-NEXT: std r15, 288(r1) -; CHECK-PWR7-NEXT: std r3, 208(r1) -; CHECK-PWR7-NEXT: std r3, 216(r1) -; CHECK-PWR7-NEXT: lwz r3, 60(r1) # 4-byte Folded Reload -; CHECK-PWR7-NEXT: std r15, 296(r1) -; CHECK-PWR7-NEXT: ld r21, 424(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: ld r20, 416(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: std r22, 224(r1) -; CHECK-PWR7-NEXT: std r22, 232(r1) -; CHECK-PWR7-NEXT: sub r4, r3, r4 -; CHECK-PWR7-NEXT: std r25, 192(r1) -; CHECK-PWR7-NEXT: ld r22, 432(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: ld r19, 408(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: srawi r3, r4, 31 -; CHECK-PWR7-NEXT: std r25, 200(r1) -; CHECK-PWR7-NEXT: ld r25, 456(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: std r27, 176(r1) -; CHECK-PWR7-NEXT: std r27, 184(r1) -; CHECK-PWR7-NEXT: xor r4, r4, r3 -; CHECK-PWR7-NEXT: std r29, 160(r1) -; CHECK-PWR7-NEXT: ld r27, 472(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: std r29, 168(r1) -; CHECK-PWR7-NEXT: std r0, 144(r1) -; CHECK-PWR7-NEXT: sub r3, r4, r3 -; CHECK-PWR7-NEXT: std r0, 152(r1) -; CHECK-PWR7-NEXT: ld r29, 488(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: ld r18, 400(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: sldi r3, r3, 56 -; CHECK-PWR7-NEXT: std r11, 128(r1) -; CHECK-PWR7-NEXT: ld r17, 392(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: std r11, 136(r1) -; CHECK-PWR7-NEXT: std r9, 112(r1) -; CHECK-PWR7-NEXT: std r3, 64(r1) -; CHECK-PWR7-NEXT: std r3, 72(r1) -; CHECK-PWR7-NEXT: addi r3, r1, 304 -; CHECK-PWR7-NEXT: std r9, 120(r1) -; CHECK-PWR7-NEXT: ld r15, 376(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: std r7, 96(r1) -; CHECK-PWR7-NEXT: std r7, 104(r1) -; CHECK-PWR7-NEXT: std r5, 80(r1) -; CHECK-PWR7-NEXT: std r5, 88(r1) -; CHECK-PWR7-NEXT: lxvw4x v2, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 288 -; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 272 -; CHECK-PWR7-NEXT: ld r14, 368(r1) # 8-byte Folded Reload -; CHECK-PWR7-NEXT: vmrghb v2, v3, v2 -; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 256 -; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 240 -; CHECK-PWR7-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR7-NEXT: vmrghh v2, v3, v2 -; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 224 -; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 208 -; CHECK-PWR7-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 192 -; CHECK-PWR7-NEXT: lxvw4x v5, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 176 -; CHECK-PWR7-NEXT: vmrghb v4, v5, v4 -; CHECK-PWR7-NEXT: vmrghh v3, v4, v3 -; CHECK-PWR7-NEXT: xxmrghw vs0, v3, v2 -; CHECK-PWR7-NEXT: lxvw4x v2, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 160 -; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 144 -; CHECK-PWR7-NEXT: vmrghb v2, v3, v2 -; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 128 -; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3 -; CHECK-PWR7-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR7-NEXT: addi r3, r1, 112 -; CHECK-PWR7-NEXT: vmrghh v2, v3, v2 -; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 96 -; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 80 -; CHECK-PWR7-NEXT: vmrghb v3, v4, v3 -; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3 -; CHECK-PWR7-NEXT: addi r3, r1, 64 -; CHECK-PWR7-NEXT: lxvw4x v5, 0, r3 -; CHECK-PWR7-NEXT: vmrghb v4, v5, v4 -; CHECK-PWR7-NEXT: vmrghh v3, v4, v3 -; CHECK-PWR7-NEXT: xxmrghw vs1, v3, v2 -; CHECK-PWR7-NEXT: xxmrghd v2, vs1, vs0 -; CHECK-PWR7-NEXT: addi r1, r1, 512 -; CHECK-PWR7-NEXT: blr +; CHECK-PWR78-LABEL: sub_absv_8_ext: +; CHECK-PWR78: # %bb.0: # %entry +; CHECK-PWR78-NEXT: vminub v4, v2, v3 +; CHECK-PWR78-NEXT: vmaxub v2, v2, v3 +; CHECK-PWR78-NEXT: vsububm v2, v2, v4 +; CHECK-PWR78-NEXT: blr entry: - %vecext = extractelement <16 x i8> %a, i32 0 - %conv = zext i8 %vecext to i32 - %vecext1 = extractelement <16 x i8> %b, i32 0 - %conv2 = zext i8 %vecext1 to i32 - %sub = sub nsw i32 %conv, %conv2 - %ispos = icmp sgt i32 %sub, -1 - %neg = sub nsw i32 0, %sub - %0 = select i1 %ispos, i32 %sub, i32 %neg - %conv3 = trunc i32 %0 to i8 - %vecins = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv3, i32 0 - %vecext4 = extractelement <16 x i8> %a, i32 1 - %conv5 = zext i8 %vecext4 to i32 - %vecext6 = extractelement <16 x i8> %b, i32 1 - %conv7 = zext i8 %vecext6 to i32 - %sub8 = sub nsw i32 %conv5, %conv7 - %ispos171 = icmp sgt i32 %sub8, -1 - %neg172 = sub nsw i32 0, %sub8 - %1 = select i1 %ispos171, i32 %sub8, i32 %neg172 - %conv10 = trunc i32 %1 to i8 - %vecins11 = insertelement <16 x i8> %vecins, i8 %conv10, i32 1 - %vecext12 = extractelement <16 x i8> %a, i32 2 - %conv13 = zext i8 %vecext12 to i32 - %vecext14 = extractelement <16 x i8> %b, i32 2 - %conv15 = zext i8 %vecext14 to i32 - %sub16 = sub nsw i32 %conv13, %conv15 - %ispos173 = icmp sgt i32 %sub16, -1 - %neg174 = sub nsw i32 0, %sub16 - %2 = select i1 %ispos173, i32 %sub16, i32 %neg174 - %conv18 = trunc i32 %2 to i8 - %vecins19 = insertelement <16 x i8> %vecins11, i8 %conv18, i32 2 - %vecext20 = extractelement <16 x i8> %a, i32 3 - %conv21 = zext i8 %vecext20 to i32 - %vecext22 = extractelement <16 x i8> %b, i32 3 - %conv23 = zext i8 %vecext22 to i32 - %sub24 = sub nsw i32 %conv21, %conv23 - %ispos175 = icmp sgt i32 %sub24, -1 - %neg176 = sub nsw i32 0, %sub24 - %3 = select i1 %ispos175, i32 %sub24, i32 %neg176 - %conv26 = trunc i32 %3 to i8 - %vecins27 = insertelement <16 x i8> %vecins19, i8 %conv26, i32 3 - %vecext28 = extractelement <16 x i8> %a, i32 4 - %conv29 = zext i8 %vecext28 to i32 - %vecext30 = extractelement <16 x i8> %b, i32 4 - %conv31 = zext i8 %vecext30 to i32 - %sub32 = sub nsw i32 %conv29, %conv31 - %ispos177 = icmp sgt i32 %sub32, -1 - %neg178 = sub nsw i32 0, %sub32 - %4 = select i1 %ispos177, i32 %sub32, i32 %neg178 - %conv34 = trunc i32 %4 to i8 - %vecins35 = insertelement <16 x i8> %vecins27, i8 %conv34, i32 4 - %vecext36 = extractelement <16 x i8> %a, i32 5 - %conv37 = zext i8 %vecext36 to i32 - %vecext38 = extractelement <16 x i8> %b, i32 5 - %conv39 = zext i8 %vecext38 to i32 - %sub40 = sub nsw i32 %conv37, %conv39 - %ispos179 = icmp sgt i32 %sub40, -1 - %neg180 = sub nsw i32 0, %sub40 - %5 = select i1 %ispos179, i32 %sub40, i32 %neg180 - %conv42 = trunc i32 %5 to i8 - %vecins43 = insertelement <16 x i8> %vecins35, i8 %conv42, i32 5 - %vecext44 = extractelement <16 x i8> %a, i32 6 - %conv45 = zext i8 %vecext44 to i32 - %vecext46 = extractelement <16 x i8> %b, i32 6 - %conv47 = zext i8 %vecext46 to i32 - %sub48 = sub nsw i32 %conv45, %conv47 - %ispos181 = icmp sgt i32 %sub48, -1 - %neg182 = sub nsw i32 0, %sub48 - %6 = select i1 %ispos181, i32 %sub48, i32 %neg182 - %conv50 = trunc i32 %6 to i8 - %vecins51 = insertelement <16 x i8> %vecins43, i8 %conv50, i32 6 - %vecext52 = extractelement <16 x i8> %a, i32 7 - %conv53 = zext i8 %vecext52 to i32 - %vecext54 = extractelement <16 x i8> %b, i32 7 - %conv55 = zext i8 %vecext54 to i32 - %sub56 = sub nsw i32 %conv53, %conv55 - %ispos183 = icmp sgt i32 %sub56, -1 - %neg184 = sub nsw i32 0, %sub56 - %7 = select i1 %ispos183, i32 %sub56, i32 %neg184 - %conv58 = trunc i32 %7 to i8 - %vecins59 = insertelement <16 x i8> %vecins51, i8 %conv58, i32 7 - %vecext60 = extractelement <16 x i8> %a, i32 8 - %conv61 = zext i8 %vecext60 to i32 - %vecext62 = extractelement <16 x i8> %b, i32 8 - %conv63 = zext i8 %vecext62 to i32 - %sub64 = sub nsw i32 %conv61, %conv63 - %ispos185 = icmp sgt i32 %sub64, -1 - %neg186 = sub nsw i32 0, %sub64 - %8 = select i1 %ispos185, i32 %sub64, i32 %neg186 - %conv66 = trunc i32 %8 to i8 - %vecins67 = insertelement <16 x i8> %vecins59, i8 %conv66, i32 8 - %vecext68 = extractelement <16 x i8> %a, i32 9 - %conv69 = zext i8 %vecext68 to i32 - %vecext70 = extractelement <16 x i8> %b, i32 9 - %conv71 = zext i8 %vecext70 to i32 - %sub72 = sub nsw i32 %conv69, %conv71 - %ispos187 = icmp sgt i32 %sub72, -1 - %neg188 = sub nsw i32 0, %sub72 - %9 = select i1 %ispos187, i32 %sub72, i32 %neg188 - %conv74 = trunc i32 %9 to i8 - %vecins75 = insertelement <16 x i8> %vecins67, i8 %conv74, i32 9 - %vecext76 = extractelement <16 x i8> %a, i32 10 - %conv77 = zext i8 %vecext76 to i32 - %vecext78 = extractelement <16 x i8> %b, i32 10 - %conv79 = zext i8 %vecext78 to i32 - %sub80 = sub nsw i32 %conv77, %conv79 - %ispos189 = icmp sgt i32 %sub80, -1 - %neg190 = sub nsw i32 0, %sub80 - %10 = select i1 %ispos189, i32 %sub80, i32 %neg190 - %conv82 = trunc i32 %10 to i8 - %vecins83 = insertelement <16 x i8> %vecins75, i8 %conv82, i32 10 - %vecext84 = extractelement <16 x i8> %a, i32 11 - %conv85 = zext i8 %vecext84 to i32 - %vecext86 = extractelement <16 x i8> %b, i32 11 - %conv87 = zext i8 %vecext86 to i32 - %sub88 = sub nsw i32 %conv85, %conv87 - %ispos191 = icmp sgt i32 %sub88, -1 - %neg192 = sub nsw i32 0, %sub88 - %11 = select i1 %ispos191, i32 %sub88, i32 %neg192 - %conv90 = trunc i32 %11 to i8 - %vecins91 = insertelement <16 x i8> %vecins83, i8 %conv90, i32 11 - %vecext92 = extractelement <16 x i8> %a, i32 12 - %conv93 = zext i8 %vecext92 to i32 - %vecext94 = extractelement <16 x i8> %b, i32 12 - %conv95 = zext i8 %vecext94 to i32 - %sub96 = sub nsw i32 %conv93, %conv95 - %ispos193 = icmp sgt i32 %sub96, -1 - %neg194 = sub nsw i32 0, %sub96 - %12 = select i1 %ispos193, i32 %sub96, i32 %neg194 - %conv98 = trunc i32 %12 to i8 - %vecins99 = insertelement <16 x i8> %vecins91, i8 %conv98, i32 12 - %vecext100 = extractelement <16 x i8> %a, i32 13 - %conv101 = zext i8 %vecext100 to i32 - %vecext102 = extractelement <16 x i8> %b, i32 13 - %conv103 = zext i8 %vecext102 to i32 - %sub104 = sub nsw i32 %conv101, %conv103 - %ispos195 = icmp sgt i32 %sub104, -1 - %neg196 = sub nsw i32 0, %sub104 - %13 = select i1 %ispos195, i32 %sub104, i32 %neg196 - %conv106 = trunc i32 %13 to i8 - %vecins107 = insertelement <16 x i8> %vecins99, i8 %conv106, i32 13 - %vecext108 = extractelement <16 x i8> %a, i32 14 - %conv109 = zext i8 %vecext108 to i32 - %vecext110 = extractelement <16 x i8> %b, i32 14 - %conv111 = zext i8 %vecext110 to i32 - %sub112 = sub nsw i32 %conv109, %conv111 - %ispos197 = icmp sgt i32 %sub112, -1 - %neg198 = sub nsw i32 0, %sub112 - %14 = select i1 %ispos197, i32 %sub112, i32 %neg198 - %conv114 = trunc i32 %14 to i8 - %vecins115 = insertelement <16 x i8> %vecins107, i8 %conv114, i32 14 - %vecext116 = extractelement <16 x i8> %a, i32 15 - %conv117 = zext i8 %vecext116 to i32 - %vecext118 = extractelement <16 x i8> %b, i32 15 - %conv119 = zext i8 %vecext118 to i32 - %sub120 = sub nsw i32 %conv117, %conv119 - %ispos199 = icmp sgt i32 %sub120, -1 - %neg200 = sub nsw i32 0, %sub120 - %15 = select i1 %ispos199, i32 %sub120, i32 %neg200 - %conv122 = trunc i32 %15 to i8 - %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15 - ret <16 x i8> %vecins123 + %0 = zext <16 x i8> %a to <16 x i32> + %1 = zext <16 x i8> %b to <16 x i32> + %2 = sub nsw <16 x i32> %0, %1 + %3 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %2, i1 true) + %4 = trunc <16 x i32> %3 to <16 x i8> + ret <16 x i8> %4 } define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr { diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll index 2598a410b876..4bf572bb0294 100644 --- a/llvm/test/CodeGen/PowerPC/recipest.ll +++ b/llvm/test/CodeGen/PowerPC/recipest.ll @@ -1,7 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck --check-prefix=CHECK-P7 %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck --check-prefix=CHECK-P8 %s -; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 | FileCheck --check-prefix=CHECK-P9 %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr | FileCheck --check-prefix=CHECK-P7 %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr | FileCheck --check-prefix=CHECK-P8 %s +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr | FileCheck --check-prefix=CHECK-P9 %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" @@ -14,58 +17,58 @@ declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) define double @foo_fmf(double %a, double %b) nounwind { ; CHECK-P7-LABEL: foo_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: frsqrte 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI0_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI0_1@toc@ha -; CHECK-P7-NEXT: lfs 5, .LCPI0_1@toc@l(3) -; CHECK-P7-NEXT: fmul 3, 2, 0 -; CHECK-P7-NEXT: fmadd 3, 3, 0, 4 -; CHECK-P7-NEXT: fmul 0, 0, 5 -; CHECK-P7-NEXT: fmul 0, 0, 3 -; CHECK-P7-NEXT: fmul 2, 2, 0 -; CHECK-P7-NEXT: fmadd 2, 2, 0, 4 -; CHECK-P7-NEXT: fmul 0, 0, 5 -; CHECK-P7-NEXT: fmul 0, 0, 2 -; CHECK-P7-NEXT: fmul 1, 1, 0 +; CHECK-P7-NEXT: frsqrte f0, f2 +; CHECK-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-P7-NEXT: lfs f4, .LCPI0_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI0_1@toc@ha +; CHECK-P7-NEXT: lfs f5, .LCPI0_1@toc@l(r3) +; CHECK-P7-NEXT: fmul f3, f2, f0 +; CHECK-P7-NEXT: fmadd f3, f3, f0, f4 +; CHECK-P7-NEXT: fmul f0, f0, f5 +; CHECK-P7-NEXT: fmul f0, f0, f3 +; CHECK-P7-NEXT: fmul f2, f2, f0 +; CHECK-P7-NEXT: fmadd f2, f2, f0, f4 +; CHECK-P7-NEXT: fmul f0, f0, f5 +; CHECK-P7-NEXT: fmul f0, f0, f2 +; CHECK-P7-NEXT: fmul f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: xsrsqrtedp 0, 2 -; CHECK-P8-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 4, 34 -; CHECK-P8-NEXT: xsmuldp 3, 2, 0 -; CHECK-P8-NEXT: fmr 5, 4 -; CHECK-P8-NEXT: xsmaddadp 5, 3, 0 -; CHECK-P8-NEXT: lfs 3, .LCPI0_0@toc@l(3) -; CHECK-P8-NEXT: xsmuldp 0, 0, 3 -; CHECK-P8-NEXT: xsmuldp 0, 0, 5 -; CHECK-P8-NEXT: xsmuldp 2, 2, 0 -; CHECK-P8-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P8-NEXT: xsmuldp 0, 0, 3 -; CHECK-P8-NEXT: xsmuldp 0, 0, 4 -; CHECK-P8-NEXT: xsmuldp 1, 1, 0 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: xsrsqrtedp f0, f2 +; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs4, v2 +; CHECK-P8-NEXT: xsmuldp f3, f2, f0 +; CHECK-P8-NEXT: fmr f5, f4 +; CHECK-P8-NEXT: xsmaddadp f5, f3, f0 +; CHECK-P8-NEXT: lfs f3, .LCPI0_0@toc@l(r3) +; CHECK-P8-NEXT: xsmuldp f0, f0, f3 +; CHECK-P8-NEXT: xsmuldp f0, f0, f5 +; CHECK-P8-NEXT: xsmuldp f2, f2, f0 +; CHECK-P8-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P8-NEXT: xsmuldp f0, f0, f3 +; CHECK-P8-NEXT: xsmuldp f0, f0, f4 +; CHECK-P8-NEXT: xsmuldp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsrsqrtedp 0, 2 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; CHECK-P9-NEXT: xsmuldp 3, 2, 0 -; CHECK-P9-NEXT: xvcvsxwdp 4, 34 -; CHECK-P9-NEXT: fmr 5, 4 -; CHECK-P9-NEXT: xsmaddadp 5, 3, 0 -; CHECK-P9-NEXT: lfs 3, .LCPI0_0@toc@l(3) -; CHECK-P9-NEXT: xsmuldp 0, 0, 3 -; CHECK-P9-NEXT: xsmuldp 0, 0, 5 -; CHECK-P9-NEXT: xsmuldp 2, 2, 0 -; CHECK-P9-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P9-NEXT: xsmuldp 0, 0, 3 -; CHECK-P9-NEXT: xsmuldp 0, 0, 4 -; CHECK-P9-NEXT: xsmuldp 1, 1, 0 +; CHECK-P9-NEXT: xsrsqrtedp f0, f2 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha +; CHECK-P9-NEXT: xsmuldp f3, f2, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs4, v2 +; CHECK-P9-NEXT: fmr f5, f4 +; CHECK-P9-NEXT: xsmaddadp f5, f3, f0 +; CHECK-P9-NEXT: lfs f3, .LCPI0_0@toc@l(r3) +; CHECK-P9-NEXT: xsmuldp f0, f0, f3 +; CHECK-P9-NEXT: xsmuldp f0, f0, f5 +; CHECK-P9-NEXT: xsmuldp f2, f2, f0 +; CHECK-P9-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P9-NEXT: xsmuldp f0, f0, f3 +; CHECK-P9-NEXT: xsmuldp f0, f0, f4 +; CHECK-P9-NEXT: xsmuldp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call arcp contract reassoc double @llvm.sqrt.f64(double %b) %r = fdiv arcp contract reassoc double %a, %x @@ -75,20 +78,20 @@ define double @foo_fmf(double %a, double %b) nounwind { define double @foo_safe(double %a, double %b) nounwind { ; CHECK-P7-LABEL: foo_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrt 0, 2 -; CHECK-P7-NEXT: fdiv 1, 1, 0 +; CHECK-P7-NEXT: fsqrt f0, f2 +; CHECK-P7-NEXT: fdiv f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xssqrtdp 0, 2 -; CHECK-P8-NEXT: xsdivdp 1, 1, 0 +; CHECK-P8-NEXT: xssqrtdp f0, f2 +; CHECK-P8-NEXT: xsdivdp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtdp 0, 2 -; CHECK-P9-NEXT: xsdivdp 1, 1, 0 +; CHECK-P9-NEXT: xssqrtdp f0, f2 +; CHECK-P9-NEXT: xsdivdp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call double @llvm.sqrt.f64(double %b) %r = fdiv double %a, %x @@ -98,20 +101,20 @@ define double @foo_safe(double %a, double %b) nounwind { define double @no_estimate_refinement_f64(double %a, double %b) #0 { ; CHECK-P7-LABEL: no_estimate_refinement_f64: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: frsqrte 0, 2 -; CHECK-P7-NEXT: fmul 1, 1, 0 +; CHECK-P7-NEXT: frsqrte f0, f2 +; CHECK-P7-NEXT: fmul f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: no_estimate_refinement_f64: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsrsqrtedp 0, 2 -; CHECK-P8-NEXT: xsmuldp 1, 1, 0 +; CHECK-P8-NEXT: xsrsqrtedp f0, f2 +; CHECK-P8-NEXT: xsmuldp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: no_estimate_refinement_f64: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsrsqrtedp 0, 2 -; CHECK-P9-NEXT: xsmuldp 1, 1, 0 +; CHECK-P9-NEXT: xsrsqrtedp f0, f2 +; CHECK-P9-NEXT: xsmuldp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call arcp reassoc double @llvm.sqrt.f64(double %b) %r = fdiv arcp reassoc double %a, %x @@ -121,44 +124,44 @@ define double @no_estimate_refinement_f64(double %a, double %b) #0 { define double @foof_fmf(double %a, float %b) nounwind { ; CHECK-P7-LABEL: foof_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: frsqrtes 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI3_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; CHECK-P7-NEXT: fmuls 2, 2, 0 -; CHECK-P7-NEXT: fmadds 2, 2, 0, 3 -; CHECK-P7-NEXT: lfs 3, .LCPI3_1@toc@l(3) -; CHECK-P7-NEXT: fmuls 0, 0, 3 -; CHECK-P7-NEXT: fmuls 0, 0, 2 -; CHECK-P7-NEXT: fmul 1, 1, 0 +; CHECK-P7-NEXT: frsqrtes f0, f2 +; CHECK-P7-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; CHECK-P7-NEXT: lfs f3, .LCPI3_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI3_1@toc@ha +; CHECK-P7-NEXT: fmuls f2, f2, f0 +; CHECK-P7-NEXT: fmadds f2, f2, f0, f3 +; CHECK-P7-NEXT: lfs f3, .LCPI3_1@toc@l(r3) +; CHECK-P7-NEXT: fmuls f0, f0, f3 +; CHECK-P7-NEXT: fmuls f0, f0, f2 +; CHECK-P7-NEXT: fmul f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foof_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsrsqrtesp 0, 2 -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 3, 34 -; CHECK-P8-NEXT: xsmulsp 2, 2, 0 -; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P8-NEXT: lfs 2, .LCPI3_0@toc@l(3) -; CHECK-P8-NEXT: xsmulsp 0, 0, 2 -; CHECK-P8-NEXT: xsmulsp 0, 0, 3 -; CHECK-P8-NEXT: xsmuldp 1, 1, 0 +; CHECK-P8-NEXT: xsrsqrtesp f0, f2 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P8-NEXT: xsmulsp f2, f2, f0 +; CHECK-P8-NEXT: xsmaddasp f3, f2, f0 +; CHECK-P8-NEXT: lfs f2, .LCPI3_0@toc@l(r3) +; CHECK-P8-NEXT: xsmulsp f0, f0, f2 +; CHECK-P8-NEXT: xsmulsp f0, f0, f3 +; CHECK-P8-NEXT: xsmuldp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foof_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsrsqrtesp 0, 2 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; CHECK-P9-NEXT: xsmulsp 2, 2, 0 -; CHECK-P9-NEXT: xvcvsxwdp 3, 34 -; CHECK-P9-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI3_0@toc@l(3) -; CHECK-P9-NEXT: xsmulsp 0, 0, 2 -; CHECK-P9-NEXT: xsmulsp 0, 0, 3 -; CHECK-P9-NEXT: xsmuldp 1, 1, 0 +; CHECK-P9-NEXT: xsrsqrtesp f0, f2 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; CHECK-P9-NEXT: xsmulsp f2, f2, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P9-NEXT: xsmaddasp f3, f2, f0 +; CHECK-P9-NEXT: lfs f2, .LCPI3_0@toc@l(r3) +; CHECK-P9-NEXT: xsmulsp f0, f0, f2 +; CHECK-P9-NEXT: xsmulsp f0, f0, f3 +; CHECK-P9-NEXT: xsmuldp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call contract reassoc arcp float @llvm.sqrt.f32(float %b) %y = fpext float %x to double @@ -169,20 +172,20 @@ define double @foof_fmf(double %a, float %b) nounwind { define double @foof_safe(double %a, float %b) nounwind { ; CHECK-P7-LABEL: foof_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrts 0, 2 -; CHECK-P7-NEXT: fdiv 1, 1, 0 +; CHECK-P7-NEXT: fsqrts f0, f2 +; CHECK-P7-NEXT: fdiv f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foof_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xssqrtsp 0, 2 -; CHECK-P8-NEXT: xsdivdp 1, 1, 0 +; CHECK-P8-NEXT: xssqrtsp f0, f2 +; CHECK-P8-NEXT: xsdivdp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foof_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtsp 0, 2 -; CHECK-P9-NEXT: xsdivdp 1, 1, 0 +; CHECK-P9-NEXT: xssqrtsp f0, f2 +; CHECK-P9-NEXT: xsdivdp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call float @llvm.sqrt.f32(float %b) %y = fpext float %x to double @@ -193,61 +196,61 @@ define double @foof_safe(double %a, float %b) nounwind { define float @food_fmf(float %a, double %b) nounwind { ; CHECK-P7-LABEL: food_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: frsqrte 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI5_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; CHECK-P7-NEXT: lfs 5, .LCPI5_1@toc@l(3) -; CHECK-P7-NEXT: fmul 3, 2, 0 -; CHECK-P7-NEXT: fmadd 3, 3, 0, 4 -; CHECK-P7-NEXT: fmul 0, 0, 5 -; CHECK-P7-NEXT: fmul 0, 0, 3 -; CHECK-P7-NEXT: fmul 2, 2, 0 -; CHECK-P7-NEXT: fmadd 2, 2, 0, 4 -; CHECK-P7-NEXT: fmul 0, 0, 5 -; CHECK-P7-NEXT: fmul 0, 0, 2 -; CHECK-P7-NEXT: frsp 0, 0 -; CHECK-P7-NEXT: fmuls 1, 1, 0 +; CHECK-P7-NEXT: frsqrte f0, f2 +; CHECK-P7-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; CHECK-P7-NEXT: lfs f4, .LCPI5_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI5_1@toc@ha +; CHECK-P7-NEXT: lfs f5, .LCPI5_1@toc@l(r3) +; CHECK-P7-NEXT: fmul f3, f2, f0 +; CHECK-P7-NEXT: fmadd f3, f3, f0, f4 +; CHECK-P7-NEXT: fmul f0, f0, f5 +; CHECK-P7-NEXT: fmul f0, f0, f3 +; CHECK-P7-NEXT: fmul f2, f2, f0 +; CHECK-P7-NEXT: fmadd f2, f2, f0, f4 +; CHECK-P7-NEXT: fmul f0, f0, f5 +; CHECK-P7-NEXT: fmul f0, f0, f2 +; CHECK-P7-NEXT: frsp f0, f0 +; CHECK-P7-NEXT: fmuls f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: food_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: xsrsqrtedp 0, 2 -; CHECK-P8-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 4, 34 -; CHECK-P8-NEXT: xsmuldp 3, 2, 0 -; CHECK-P8-NEXT: fmr 5, 4 -; CHECK-P8-NEXT: xsmaddadp 5, 3, 0 -; CHECK-P8-NEXT: lfs 3, .LCPI5_0@toc@l(3) -; CHECK-P8-NEXT: xsmuldp 0, 0, 3 -; CHECK-P8-NEXT: xsmuldp 0, 0, 5 -; CHECK-P8-NEXT: xsmuldp 2, 2, 0 -; CHECK-P8-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P8-NEXT: xsmuldp 0, 0, 3 -; CHECK-P8-NEXT: xsmuldp 0, 0, 4 -; CHECK-P8-NEXT: xsrsp 0, 0 -; CHECK-P8-NEXT: xsmulsp 1, 1, 0 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: xsrsqrtedp f0, f2 +; CHECK-P8-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs4, v2 +; CHECK-P8-NEXT: xsmuldp f3, f2, f0 +; CHECK-P8-NEXT: fmr f5, f4 +; CHECK-P8-NEXT: xsmaddadp f5, f3, f0 +; CHECK-P8-NEXT: lfs f3, .LCPI5_0@toc@l(r3) +; CHECK-P8-NEXT: xsmuldp f0, f0, f3 +; CHECK-P8-NEXT: xsmuldp f0, f0, f5 +; CHECK-P8-NEXT: xsmuldp f2, f2, f0 +; CHECK-P8-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P8-NEXT: xsmuldp f0, f0, f3 +; CHECK-P8-NEXT: xsmuldp f0, f0, f4 +; CHECK-P8-NEXT: xsrsp f0, f0 +; CHECK-P8-NEXT: xsmulsp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: food_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsrsqrtedp 0, 2 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; CHECK-P9-NEXT: xsmuldp 3, 2, 0 -; CHECK-P9-NEXT: xvcvsxwdp 4, 34 -; CHECK-P9-NEXT: fmr 5, 4 -; CHECK-P9-NEXT: xsmaddadp 5, 3, 0 -; CHECK-P9-NEXT: lfs 3, .LCPI5_0@toc@l(3) -; CHECK-P9-NEXT: xsmuldp 0, 0, 3 -; CHECK-P9-NEXT: xsmuldp 0, 0, 5 -; CHECK-P9-NEXT: xsmuldp 2, 2, 0 -; CHECK-P9-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P9-NEXT: xsmuldp 0, 0, 3 -; CHECK-P9-NEXT: xsmuldp 0, 0, 4 -; CHECK-P9-NEXT: xsrsp 0, 0 -; CHECK-P9-NEXT: xsmulsp 1, 1, 0 +; CHECK-P9-NEXT: xsrsqrtedp f0, f2 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; CHECK-P9-NEXT: xsmuldp f3, f2, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs4, v2 +; CHECK-P9-NEXT: fmr f5, f4 +; CHECK-P9-NEXT: xsmaddadp f5, f3, f0 +; CHECK-P9-NEXT: lfs f3, .LCPI5_0@toc@l(r3) +; CHECK-P9-NEXT: xsmuldp f0, f0, f3 +; CHECK-P9-NEXT: xsmuldp f0, f0, f5 +; CHECK-P9-NEXT: xsmuldp f2, f2, f0 +; CHECK-P9-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P9-NEXT: xsmuldp f0, f0, f3 +; CHECK-P9-NEXT: xsmuldp f0, f0, f4 +; CHECK-P9-NEXT: xsrsp f0, f0 +; CHECK-P9-NEXT: xsmulsp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call contract reassoc arcp double @llvm.sqrt.f64(double %b) %y = fptrunc double %x to float @@ -258,23 +261,23 @@ define float @food_fmf(float %a, double %b) nounwind { define float @food_safe(float %a, double %b) nounwind { ; CHECK-P7-LABEL: food_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrt 0, 2 -; CHECK-P7-NEXT: frsp 0, 0 -; CHECK-P7-NEXT: fdivs 1, 1, 0 +; CHECK-P7-NEXT: fsqrt f0, f2 +; CHECK-P7-NEXT: frsp f0, f0 +; CHECK-P7-NEXT: fdivs f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: food_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xssqrtdp 0, 2 -; CHECK-P8-NEXT: xsrsp 0, 0 -; CHECK-P8-NEXT: xsdivsp 1, 1, 0 +; CHECK-P8-NEXT: xssqrtdp f0, f2 +; CHECK-P8-NEXT: xsrsp f0, f0 +; CHECK-P8-NEXT: xsdivsp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: food_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtdp 0, 2 -; CHECK-P9-NEXT: xsrsp 0, 0 -; CHECK-P9-NEXT: xsdivsp 1, 1, 0 +; CHECK-P9-NEXT: xssqrtdp f0, f2 +; CHECK-P9-NEXT: xsrsp f0, f0 +; CHECK-P9-NEXT: xsdivsp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call double @llvm.sqrt.f64(double %b) %y = fptrunc double %x to float @@ -285,44 +288,44 @@ define float @food_safe(float %a, double %b) nounwind { define float @goo_fmf(float %a, float %b) nounwind { ; CHECK-P7-LABEL: goo_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: frsqrtes 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI7_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; CHECK-P7-NEXT: fmuls 2, 2, 0 -; CHECK-P7-NEXT: fmadds 2, 2, 0, 3 -; CHECK-P7-NEXT: lfs 3, .LCPI7_1@toc@l(3) -; CHECK-P7-NEXT: fmuls 0, 0, 3 -; CHECK-P7-NEXT: fmuls 0, 0, 2 -; CHECK-P7-NEXT: fmuls 1, 1, 0 +; CHECK-P7-NEXT: frsqrtes f0, f2 +; CHECK-P7-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; CHECK-P7-NEXT: lfs f3, .LCPI7_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI7_1@toc@ha +; CHECK-P7-NEXT: fmuls f2, f2, f0 +; CHECK-P7-NEXT: fmadds f2, f2, f0, f3 +; CHECK-P7-NEXT: lfs f3, .LCPI7_1@toc@l(r3) +; CHECK-P7-NEXT: fmuls f0, f0, f3 +; CHECK-P7-NEXT: fmuls f0, f0, f2 +; CHECK-P7-NEXT: fmuls f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: goo_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsrsqrtesp 0, 2 -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 3, 34 -; CHECK-P8-NEXT: xsmulsp 2, 2, 0 -; CHECK-P8-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P8-NEXT: lfs 2, .LCPI7_0@toc@l(3) -; CHECK-P8-NEXT: xsmulsp 0, 0, 2 -; CHECK-P8-NEXT: xsmulsp 0, 0, 3 -; CHECK-P8-NEXT: xsmulsp 1, 1, 0 +; CHECK-P8-NEXT: xsrsqrtesp f0, f2 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P8-NEXT: xsmulsp f2, f2, f0 +; CHECK-P8-NEXT: xsmaddasp f3, f2, f0 +; CHECK-P8-NEXT: lfs f2, .LCPI7_0@toc@l(r3) +; CHECK-P8-NEXT: xsmulsp f0, f0, f2 +; CHECK-P8-NEXT: xsmulsp f0, f0, f3 +; CHECK-P8-NEXT: xsmulsp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: goo_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsrsqrtesp 0, 2 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; CHECK-P9-NEXT: xsmulsp 2, 2, 0 -; CHECK-P9-NEXT: xvcvsxwdp 3, 34 -; CHECK-P9-NEXT: xsmaddasp 3, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI7_0@toc@l(3) -; CHECK-P9-NEXT: xsmulsp 0, 0, 2 -; CHECK-P9-NEXT: xsmulsp 0, 0, 3 -; CHECK-P9-NEXT: xsmulsp 1, 1, 0 +; CHECK-P9-NEXT: xsrsqrtesp f0, f2 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; CHECK-P9-NEXT: xsmulsp f2, f2, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P9-NEXT: xsmaddasp f3, f2, f0 +; CHECK-P9-NEXT: lfs f2, .LCPI7_0@toc@l(r3) +; CHECK-P9-NEXT: xsmulsp f0, f0, f2 +; CHECK-P9-NEXT: xsmulsp f0, f0, f3 +; CHECK-P9-NEXT: xsmulsp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call contract reassoc arcp float @llvm.sqrt.f32(float %b) %r = fdiv contract reassoc arcp float %a, %x @@ -332,20 +335,20 @@ define float @goo_fmf(float %a, float %b) nounwind { define float @goo_safe(float %a, float %b) nounwind { ; CHECK-P7-LABEL: goo_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrts 0, 2 -; CHECK-P7-NEXT: fdivs 1, 1, 0 +; CHECK-P7-NEXT: fsqrts f0, f2 +; CHECK-P7-NEXT: fdivs f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: goo_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xssqrtsp 0, 2 -; CHECK-P8-NEXT: xsdivsp 1, 1, 0 +; CHECK-P8-NEXT: xssqrtsp f0, f2 +; CHECK-P8-NEXT: xsdivsp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: goo_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtsp 0, 2 -; CHECK-P9-NEXT: xsdivsp 1, 1, 0 +; CHECK-P9-NEXT: xssqrtsp f0, f2 +; CHECK-P9-NEXT: xsdivsp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call float @llvm.sqrt.f32(float %b) %r = fdiv float %a, %x @@ -355,20 +358,20 @@ define float @goo_safe(float %a, float %b) nounwind { define float @no_estimate_refinement_f32(float %a, float %b) #0 { ; CHECK-P7-LABEL: no_estimate_refinement_f32: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: frsqrtes 0, 2 -; CHECK-P7-NEXT: fmuls 1, 1, 0 +; CHECK-P7-NEXT: frsqrtes f0, f2 +; CHECK-P7-NEXT: fmuls f1, f1, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: no_estimate_refinement_f32: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsrsqrtesp 0, 2 -; CHECK-P8-NEXT: xsmulsp 1, 1, 0 +; CHECK-P8-NEXT: xsrsqrtesp f0, f2 +; CHECK-P8-NEXT: xsmulsp f1, f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: no_estimate_refinement_f32: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsrsqrtesp 0, 2 -; CHECK-P9-NEXT: xsmulsp 1, 1, 0 +; CHECK-P9-NEXT: xsrsqrtesp f0, f2 +; CHECK-P9-NEXT: xsmulsp f1, f1, f0 ; CHECK-P9-NEXT: blr %x = call reassoc arcp float @llvm.sqrt.f32(float %b) %r = fdiv reassoc arcp float %a, %x @@ -378,56 +381,56 @@ define float @no_estimate_refinement_f32(float %a, float %b) #0 { define float @rsqrt_fmul_fmf(float %a, float %b, float %c) { ; CHECK-P7-LABEL: rsqrt_fmul_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: frsqrtes 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI10_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; CHECK-P7-NEXT: fmuls 1, 1, 0 -; CHECK-P7-NEXT: fmadds 1, 1, 0, 4 -; CHECK-P7-NEXT: lfs 4, .LCPI10_1@toc@l(3) -; CHECK-P7-NEXT: fmuls 0, 0, 4 -; CHECK-P7-NEXT: fmuls 0, 0, 1 -; CHECK-P7-NEXT: fres 1, 2 -; CHECK-P7-NEXT: fmuls 4, 0, 1 -; CHECK-P7-NEXT: fnmsubs 0, 2, 4, 0 -; CHECK-P7-NEXT: fmadds 0, 1, 0, 4 -; CHECK-P7-NEXT: fmuls 1, 3, 0 +; CHECK-P7-NEXT: frsqrtes f0, f1 +; CHECK-P7-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; CHECK-P7-NEXT: lfs f4, .LCPI10_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI10_1@toc@ha +; CHECK-P7-NEXT: fmuls f1, f1, f0 +; CHECK-P7-NEXT: fmadds f1, f1, f0, f4 +; CHECK-P7-NEXT: lfs f4, .LCPI10_1@toc@l(r3) +; CHECK-P7-NEXT: fmuls f0, f0, f4 +; CHECK-P7-NEXT: fmuls f0, f0, f1 +; CHECK-P7-NEXT: fres f1, f2 +; CHECK-P7-NEXT: fmuls f4, f0, f1 +; CHECK-P7-NEXT: fnmsubs f0, f2, f4, f0 +; CHECK-P7-NEXT: fmadds f0, f1, f0, f4 +; CHECK-P7-NEXT: fmuls f1, f3, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: rsqrt_fmul_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsrsqrtesp 0, 1 -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 4, 34 -; CHECK-P8-NEXT: xsmulsp 1, 1, 0 -; CHECK-P8-NEXT: xsmaddasp 4, 1, 0 -; CHECK-P8-NEXT: lfs 1, .LCPI10_0@toc@l(3) -; CHECK-P8-NEXT: xsmulsp 0, 0, 1 -; CHECK-P8-NEXT: xsresp 1, 2 -; CHECK-P8-NEXT: xsmulsp 0, 0, 4 -; CHECK-P8-NEXT: xsmulsp 4, 0, 1 -; CHECK-P8-NEXT: xsnmsubasp 0, 2, 4 -; CHECK-P8-NEXT: xsmaddasp 4, 1, 0 -; CHECK-P8-NEXT: xsmulsp 1, 3, 4 +; CHECK-P8-NEXT: xsrsqrtesp f0, f1 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs4, v2 +; CHECK-P8-NEXT: xsmulsp f1, f1, f0 +; CHECK-P8-NEXT: xsmaddasp f4, f1, f0 +; CHECK-P8-NEXT: lfs f1, .LCPI10_0@toc@l(r3) +; CHECK-P8-NEXT: xsmulsp f0, f0, f1 +; CHECK-P8-NEXT: xsresp f1, f2 +; CHECK-P8-NEXT: xsmulsp f0, f0, f4 +; CHECK-P8-NEXT: xsmulsp f4, f0, f1 +; CHECK-P8-NEXT: xsnmsubasp f0, f2, f4 +; CHECK-P8-NEXT: xsmaddasp f4, f1, f0 +; CHECK-P8-NEXT: xsmulsp f1, f3, f4 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: rsqrt_fmul_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsrsqrtesp 0, 1 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; CHECK-P9-NEXT: xsmulsp 1, 1, 0 -; CHECK-P9-NEXT: xvcvsxwdp 4, 34 -; CHECK-P9-NEXT: xsmaddasp 4, 1, 0 -; CHECK-P9-NEXT: lfs 1, .LCPI10_0@toc@l(3) -; CHECK-P9-NEXT: xsmulsp 0, 0, 1 -; CHECK-P9-NEXT: xsresp 1, 2 -; CHECK-P9-NEXT: xsmulsp 0, 0, 4 -; CHECK-P9-NEXT: xsmulsp 4, 0, 1 -; CHECK-P9-NEXT: xsnmsubasp 0, 2, 4 -; CHECK-P9-NEXT: xsmaddasp 4, 1, 0 -; CHECK-P9-NEXT: xsmulsp 1, 3, 4 +; CHECK-P9-NEXT: xsrsqrtesp f0, f1 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; CHECK-P9-NEXT: xsmulsp f1, f1, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs4, v2 +; CHECK-P9-NEXT: xsmaddasp f4, f1, f0 +; CHECK-P9-NEXT: lfs f1, .LCPI10_0@toc@l(r3) +; CHECK-P9-NEXT: xsmulsp f0, f0, f1 +; CHECK-P9-NEXT: xsresp f1, f2 +; CHECK-P9-NEXT: xsmulsp f0, f0, f4 +; CHECK-P9-NEXT: xsmulsp f4, f0, f1 +; CHECK-P9-NEXT: xsnmsubasp f0, f2, f4 +; CHECK-P9-NEXT: xsmaddasp f4, f1, f0 +; CHECK-P9-NEXT: xsmulsp f1, f3, f4 ; CHECK-P9-NEXT: blr %x = call contract reassoc arcp nsz float @llvm.sqrt.f32(float %a) %y = fmul contract reassoc nsz float %x, %b @@ -438,23 +441,23 @@ define float @rsqrt_fmul_fmf(float %a, float %b, float %c) { define float @rsqrt_fmul_safe(float %a, float %b, float %c) { ; CHECK-P7-LABEL: rsqrt_fmul_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrts 0, 1 -; CHECK-P7-NEXT: fmuls 0, 0, 2 -; CHECK-P7-NEXT: fdivs 1, 3, 0 +; CHECK-P7-NEXT: fsqrts f0, f1 +; CHECK-P7-NEXT: fmuls f0, f0, f2 +; CHECK-P7-NEXT: fdivs f1, f3, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: rsqrt_fmul_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xssqrtsp 0, 1 -; CHECK-P8-NEXT: xsmulsp 0, 0, 2 -; CHECK-P8-NEXT: xsdivsp 1, 3, 0 +; CHECK-P8-NEXT: xssqrtsp f0, f1 +; CHECK-P8-NEXT: xsmulsp f0, f0, f2 +; CHECK-P8-NEXT: xsdivsp f1, f3, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: rsqrt_fmul_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtsp 0, 1 -; CHECK-P9-NEXT: xsmulsp 0, 0, 2 -; CHECK-P9-NEXT: xsdivsp 1, 3, 0 +; CHECK-P9-NEXT: xssqrtsp f0, f1 +; CHECK-P9-NEXT: xsmulsp f0, f0, f2 +; CHECK-P9-NEXT: xsdivsp f1, f3, f0 ; CHECK-P9-NEXT: blr %x = call float @llvm.sqrt.f32(float %a) %y = fmul float %x, %b @@ -465,52 +468,52 @@ define float @rsqrt_fmul_safe(float %a, float %b, float %c) { define <4 x float> @hoo_fmf(<4 x float> %a, <4 x float> %b) nounwind { ; CHECK-P7-LABEL: hoo_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; CHECK-P7-NEXT: vspltisw 4, -1 -; CHECK-P7-NEXT: vrsqrtefp 5, 3 -; CHECK-P7-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P7-NEXT: vslw 4, 4, 4 -; CHECK-P7-NEXT: lvx 0, 0, 3 -; CHECK-P7-NEXT: addis 3, 2, .LCPI12_1@toc@ha -; CHECK-P7-NEXT: vmaddfp 3, 3, 5, 4 -; CHECK-P7-NEXT: addi 3, 3, .LCPI12_1@toc@l -; CHECK-P7-NEXT: vmaddfp 3, 3, 5, 0 -; CHECK-P7-NEXT: lvx 0, 0, 3 -; CHECK-P7-NEXT: vmaddfp 5, 5, 0, 4 -; CHECK-P7-NEXT: vmaddfp 3, 5, 3, 4 -; CHECK-P7-NEXT: vmaddfp 2, 2, 3, 4 +; CHECK-P7-NEXT: addis r3, r2, .LCPI12_0@toc@ha +; CHECK-P7-NEXT: vspltisw v4, -1 +; CHECK-P7-NEXT: vrsqrtefp v5, v3 +; CHECK-P7-NEXT: addi r3, r3, .LCPI12_0@toc@l +; CHECK-P7-NEXT: vslw v4, v4, v4 +; CHECK-P7-NEXT: lvx v0, 0, r3 +; CHECK-P7-NEXT: addis r3, r2, .LCPI12_1@toc@ha +; CHECK-P7-NEXT: vmaddfp v3, v3, v5, v4 +; CHECK-P7-NEXT: addi r3, r3, .LCPI12_1@toc@l +; CHECK-P7-NEXT: vmaddfp v3, v3, v5, v0 +; CHECK-P7-NEXT: lvx v0, 0, r3 +; CHECK-P7-NEXT: vmaddfp v5, v5, v0, v4 +; CHECK-P7-NEXT: vmaddfp v3, v5, v3, v4 +; CHECK-P7-NEXT: vmaddfp v2, v2, v3, v4 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvrsqrtesp 0, 35 -; CHECK-P8-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P8-NEXT: lxvd2x 2, 0, 3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI12_1@toc@ha -; CHECK-P8-NEXT: xvmulsp 1, 35, 0 -; CHECK-P8-NEXT: addi 3, 3, .LCPI12_1@toc@l -; CHECK-P8-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P8-NEXT: lxvd2x 1, 0, 3 -; CHECK-P8-NEXT: xvmulsp 0, 0, 1 -; CHECK-P8-NEXT: xvmulsp 0, 0, 2 -; CHECK-P8-NEXT: xvmulsp 34, 34, 0 +; CHECK-P8-NEXT: xvrsqrtesp vs0, v3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI12_0@toc@ha +; CHECK-P8-NEXT: addi r3, r3, .LCPI12_0@toc@l +; CHECK-P8-NEXT: lxvd2x vs2, 0, r3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI12_1@toc@ha +; CHECK-P8-NEXT: xvmulsp vs1, v3, vs0 +; CHECK-P8-NEXT: addi r3, r3, .LCPI12_1@toc@l +; CHECK-P8-NEXT: xvmaddasp vs2, vs1, vs0 +; CHECK-P8-NEXT: lxvd2x vs1, 0, r3 +; CHECK-P8-NEXT: xvmulsp vs0, vs0, vs1 +; CHECK-P8-NEXT: xvmulsp vs0, vs0, vs2 +; CHECK-P8-NEXT: xvmulsp v2, v2, vs0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvrsqrtesp 0, 35 -; CHECK-P9-NEXT: addis 3, 2, .LCPI12_0@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI12_0@toc@l -; CHECK-P9-NEXT: lxv 2, 0(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI12_1@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI12_1@toc@l -; CHECK-P9-NEXT: xvmulsp 1, 35, 0 -; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lxv 1, 0(3) -; CHECK-P9-NEXT: xvmulsp 0, 0, 1 -; CHECK-P9-NEXT: xvmulsp 0, 0, 2 -; CHECK-P9-NEXT: xvmulsp 34, 34, 0 +; CHECK-P9-NEXT: xvrsqrtesp vs0, v3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI12_0@toc@ha +; CHECK-P9-NEXT: addi r3, r3, .LCPI12_0@toc@l +; CHECK-P9-NEXT: lxv vs2, 0(r3) +; CHECK-P9-NEXT: addis r3, r2, .LCPI12_1@toc@ha +; CHECK-P9-NEXT: addi r3, r3, .LCPI12_1@toc@l +; CHECK-P9-NEXT: xvmulsp vs1, v3, vs0 +; CHECK-P9-NEXT: xvmaddasp vs2, vs1, vs0 +; CHECK-P9-NEXT: lxv vs1, 0(r3) +; CHECK-P9-NEXT: xvmulsp vs0, vs0, vs1 +; CHECK-P9-NEXT: xvmulsp vs0, vs0, vs2 +; CHECK-P9-NEXT: xvmulsp v2, v2, vs0 ; CHECK-P9-NEXT: blr %x = call contract reassoc arcp <4 x float> @llvm.sqrt.v4f32(<4 x float> %b) %r = fdiv contract reassoc arcp <4 x float> %a, %x @@ -520,44 +523,44 @@ define <4 x float> @hoo_fmf(<4 x float> %a, <4 x float> %b) nounwind { define <4 x float> @hoo_safe(<4 x float> %a, <4 x float> %b) nounwind { ; CHECK-P7-LABEL: hoo_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: addi 3, 1, -32 -; CHECK-P7-NEXT: stvx 3, 0, 3 -; CHECK-P7-NEXT: addi 3, 1, -48 -; CHECK-P7-NEXT: lfs 3, -20(1) -; CHECK-P7-NEXT: lfs 2, -24(1) -; CHECK-P7-NEXT: lfs 0, -32(1) -; CHECK-P7-NEXT: lfs 1, -28(1) -; CHECK-P7-NEXT: fsqrts 3, 3 -; CHECK-P7-NEXT: stvx 2, 0, 3 -; CHECK-P7-NEXT: lfs 4, -36(1) -; CHECK-P7-NEXT: fsqrts 2, 2 -; CHECK-P7-NEXT: fsqrts 1, 1 -; CHECK-P7-NEXT: fsqrts 0, 0 -; CHECK-P7-NEXT: addi 3, 1, -16 -; CHECK-P7-NEXT: fdivs 3, 4, 3 -; CHECK-P7-NEXT: stfs 3, -4(1) -; CHECK-P7-NEXT: lfs 3, -40(1) -; CHECK-P7-NEXT: fdivs 2, 3, 2 -; CHECK-P7-NEXT: stfs 2, -8(1) -; CHECK-P7-NEXT: lfs 2, -44(1) -; CHECK-P7-NEXT: fdivs 1, 2, 1 -; CHECK-P7-NEXT: stfs 1, -12(1) -; CHECK-P7-NEXT: lfs 1, -48(1) -; CHECK-P7-NEXT: fdivs 0, 1, 0 -; CHECK-P7-NEXT: stfs 0, -16(1) -; CHECK-P7-NEXT: lvx 2, 0, 3 +; CHECK-P7-NEXT: addi r3, r1, -32 +; CHECK-P7-NEXT: stvx v3, 0, r3 +; CHECK-P7-NEXT: addi r3, r1, -48 +; CHECK-P7-NEXT: lfs f3, -20(r1) +; CHECK-P7-NEXT: lfs f2, -24(r1) +; CHECK-P7-NEXT: lfs f0, -32(r1) +; CHECK-P7-NEXT: lfs f1, -28(r1) +; CHECK-P7-NEXT: fsqrts f3, f3 +; CHECK-P7-NEXT: stvx v2, 0, r3 +; CHECK-P7-NEXT: lfs f4, -36(r1) +; CHECK-P7-NEXT: fsqrts f2, f2 +; CHECK-P7-NEXT: fsqrts f1, f1 +; CHECK-P7-NEXT: fsqrts f0, f0 +; CHECK-P7-NEXT: addi r3, r1, -16 +; CHECK-P7-NEXT: fdivs f3, f4, f3 +; CHECK-P7-NEXT: stfs f3, -4(r1) +; CHECK-P7-NEXT: lfs f3, -40(r1) +; CHECK-P7-NEXT: fdivs f2, f3, f2 +; CHECK-P7-NEXT: stfs f2, -8(r1) +; CHECK-P7-NEXT: lfs f2, -44(r1) +; CHECK-P7-NEXT: fdivs f1, f2, f1 +; CHECK-P7-NEXT: stfs f1, -12(r1) +; CHECK-P7-NEXT: lfs f1, -48(r1) +; CHECK-P7-NEXT: fdivs f0, f1, f0 +; CHECK-P7-NEXT: stfs f0, -16(r1) +; CHECK-P7-NEXT: lvx v2, 0, r3 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvsqrtsp 0, 35 -; CHECK-P8-NEXT: xvdivsp 34, 34, 0 +; CHECK-P8-NEXT: xvsqrtsp vs0, v3 +; CHECK-P8-NEXT: xvdivsp v2, v2, vs0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvsqrtsp 0, 35 -; CHECK-P9-NEXT: xvdivsp 34, 34, 0 +; CHECK-P9-NEXT: xvsqrtsp vs0, v3 +; CHECK-P9-NEXT: xvdivsp v2, v2, vs0 ; CHECK-P9-NEXT: blr %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b) %r = fdiv <4 x float> %a, %x @@ -567,40 +570,40 @@ define <4 x float> @hoo_safe(<4 x float> %a, <4 x float> %b) nounwind { define double @foo2_fmf(double %a, double %b) nounwind { ; CHECK-P7-LABEL: foo2_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fre 0, 2 -; CHECK-P7-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI14_0@toc@l(3) -; CHECK-P7-NEXT: fmadd 3, 2, 0, 3 -; CHECK-P7-NEXT: fnmsub 0, 0, 3, 0 -; CHECK-P7-NEXT: fmul 3, 1, 0 -; CHECK-P7-NEXT: fnmsub 1, 2, 3, 1 -; CHECK-P7-NEXT: fmadd 1, 0, 1, 3 +; CHECK-P7-NEXT: fre f0, f2 +; CHECK-P7-NEXT: addis r3, r2, .LCPI14_0@toc@ha +; CHECK-P7-NEXT: lfs f3, .LCPI14_0@toc@l(r3) +; CHECK-P7-NEXT: fmadd f3, f2, f0, f3 +; CHECK-P7-NEXT: fnmsub f0, f0, f3, f0 +; CHECK-P7-NEXT: fmul f3, f1, f0 +; CHECK-P7-NEXT: fnmsub f1, f2, f3, f1 +; CHECK-P7-NEXT: fmadd f1, f0, f1, f3 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo2_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: vspltisw 2, -1 -; CHECK-P8-NEXT: xsredp 3, 2 -; CHECK-P8-NEXT: xvcvsxwdp 0, 34 -; CHECK-P8-NEXT: xsmaddadp 0, 2, 3 -; CHECK-P8-NEXT: xsnmsubadp 3, 3, 0 -; CHECK-P8-NEXT: xsmuldp 0, 1, 3 -; CHECK-P8-NEXT: xsnmsubadp 1, 2, 0 -; CHECK-P8-NEXT: xsmaddadp 0, 3, 1 -; CHECK-P8-NEXT: fmr 1, 0 +; CHECK-P8-NEXT: vspltisw v2, -1 +; CHECK-P8-NEXT: xsredp f3, f2 +; CHECK-P8-NEXT: xvcvsxwdp vs0, v2 +; CHECK-P8-NEXT: xsmaddadp f0, f2, f3 +; CHECK-P8-NEXT: xsnmsubadp f3, f3, f0 +; CHECK-P8-NEXT: xsmuldp f0, f1, f3 +; CHECK-P8-NEXT: xsnmsubadp f1, f2, f0 +; CHECK-P8-NEXT: xsmaddadp f0, f3, f1 +; CHECK-P8-NEXT: fmr f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo2_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: vspltisw 2, -1 -; CHECK-P9-NEXT: xsredp 3, 2 -; CHECK-P9-NEXT: xvcvsxwdp 0, 34 -; CHECK-P9-NEXT: xsmaddadp 0, 2, 3 -; CHECK-P9-NEXT: xsnmsubadp 3, 3, 0 -; CHECK-P9-NEXT: xsmuldp 0, 1, 3 -; CHECK-P9-NEXT: xsnmsubadp 1, 2, 0 -; CHECK-P9-NEXT: xsmaddadp 0, 3, 1 -; CHECK-P9-NEXT: fmr 1, 0 +; CHECK-P9-NEXT: vspltisw v2, -1 +; CHECK-P9-NEXT: xsredp f3, f2 +; CHECK-P9-NEXT: xvcvsxwdp vs0, v2 +; CHECK-P9-NEXT: xsmaddadp f0, f2, f3 +; CHECK-P9-NEXT: xsnmsubadp f3, f3, f0 +; CHECK-P9-NEXT: xsmuldp f0, f1, f3 +; CHECK-P9-NEXT: xsnmsubadp f1, f2, f0 +; CHECK-P9-NEXT: xsmaddadp f0, f3, f1 +; CHECK-P9-NEXT: fmr f1, f0 ; CHECK-P9-NEXT: blr %r = fdiv contract reassoc arcp nsz ninf double %a, %b ret double %r @@ -609,17 +612,17 @@ define double @foo2_fmf(double %a, double %b) nounwind { define double @foo2_safe(double %a, double %b) nounwind { ; CHECK-P7-LABEL: foo2_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fdiv 1, 1, 2 +; CHECK-P7-NEXT: fdiv f1, f1, f2 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo2_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsdivdp 1, 1, 2 +; CHECK-P8-NEXT: xsdivdp f1, f1, f2 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo2_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsdivdp 1, 1, 2 +; CHECK-P9-NEXT: xsdivdp f1, f1, f2 ; CHECK-P9-NEXT: blr %r = fdiv double %a, %b ret double %r @@ -628,28 +631,28 @@ define double @foo2_safe(double %a, double %b) nounwind { define float @goo2_fmf(float %a, float %b) nounwind { ; CHECK-P7-LABEL: goo2_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fres 0, 2 -; CHECK-P7-NEXT: fmuls 3, 1, 0 -; CHECK-P7-NEXT: fnmsubs 1, 2, 3, 1 -; CHECK-P7-NEXT: fmadds 1, 0, 1, 3 +; CHECK-P7-NEXT: fres f0, f2 +; CHECK-P7-NEXT: fmuls f3, f1, f0 +; CHECK-P7-NEXT: fnmsubs f1, f2, f3, f1 +; CHECK-P7-NEXT: fmadds f1, f0, f1, f3 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: goo2_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsresp 3, 2 -; CHECK-P8-NEXT: xsmulsp 0, 1, 3 -; CHECK-P8-NEXT: xsnmsubasp 1, 2, 0 -; CHECK-P8-NEXT: xsmaddasp 0, 3, 1 -; CHECK-P8-NEXT: fmr 1, 0 +; CHECK-P8-NEXT: xsresp f3, f2 +; CHECK-P8-NEXT: xsmulsp f0, f1, f3 +; CHECK-P8-NEXT: xsnmsubasp f1, f2, f0 +; CHECK-P8-NEXT: xsmaddasp f0, f3, f1 +; CHECK-P8-NEXT: fmr f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: goo2_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsresp 3, 2 -; CHECK-P9-NEXT: xsmulsp 0, 1, 3 -; CHECK-P9-NEXT: xsnmsubasp 1, 2, 0 -; CHECK-P9-NEXT: xsmaddasp 0, 3, 1 -; CHECK-P9-NEXT: fmr 1, 0 +; CHECK-P9-NEXT: xsresp f3, f2 +; CHECK-P9-NEXT: xsmulsp f0, f1, f3 +; CHECK-P9-NEXT: xsnmsubasp f1, f2, f0 +; CHECK-P9-NEXT: xsmaddasp f0, f3, f1 +; CHECK-P9-NEXT: fmr f1, f0 ; CHECK-P9-NEXT: blr %r = fdiv contract reassoc arcp nsz ninf float %a, %b ret float %r @@ -658,17 +661,17 @@ define float @goo2_fmf(float %a, float %b) nounwind { define float @goo2_safe(float %a, float %b) nounwind { ; CHECK-P7-LABEL: goo2_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fdivs 1, 1, 2 +; CHECK-P7-NEXT: fdivs f1, f1, f2 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: goo2_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xsdivsp 1, 1, 2 +; CHECK-P8-NEXT: xsdivsp f1, f1, f2 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: goo2_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xsdivsp 1, 1, 2 +; CHECK-P9-NEXT: xsdivsp f1, f1, f2 ; CHECK-P9-NEXT: blr %r = fdiv float %a, %b ret float %r @@ -677,30 +680,30 @@ define float @goo2_safe(float %a, float %b) nounwind { define <4 x float> @hoo2_fmf(<4 x float> %a, <4 x float> %b) nounwind { ; CHECK-P7-LABEL: hoo2_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: vspltisw 4, -1 -; CHECK-P7-NEXT: vrefp 5, 3 -; CHECK-P7-NEXT: vslw 4, 4, 4 -; CHECK-P7-NEXT: vmaddfp 4, 2, 5, 4 -; CHECK-P7-NEXT: vnmsubfp 2, 3, 4, 2 -; CHECK-P7-NEXT: vmaddfp 2, 5, 2, 4 +; CHECK-P7-NEXT: vspltisw v4, -1 +; CHECK-P7-NEXT: vrefp v5, v3 +; CHECK-P7-NEXT: vslw v4, v4, v4 +; CHECK-P7-NEXT: vmaddfp v4, v2, v5, v4 +; CHECK-P7-NEXT: vnmsubfp v2, v3, v4, v2 +; CHECK-P7-NEXT: vmaddfp v2, v5, v2, v4 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo2_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvresp 1, 35 -; CHECK-P8-NEXT: xvmulsp 0, 34, 1 -; CHECK-P8-NEXT: xvnmsubasp 34, 35, 0 -; CHECK-P8-NEXT: xvmaddasp 0, 1, 34 -; CHECK-P8-NEXT: xxlor 34, 0, 0 +; CHECK-P8-NEXT: xvresp vs1, v3 +; CHECK-P8-NEXT: xvmulsp vs0, v2, vs1 +; CHECK-P8-NEXT: xvnmsubasp v2, v3, vs0 +; CHECK-P8-NEXT: xvmaddasp vs0, vs1, v2 +; CHECK-P8-NEXT: xxlor v2, vs0, vs0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo2_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvresp 1, 35 -; CHECK-P9-NEXT: xvmulsp 0, 34, 1 -; CHECK-P9-NEXT: xvnmsubasp 34, 35, 0 -; CHECK-P9-NEXT: xvmaddasp 0, 1, 34 -; CHECK-P9-NEXT: xxlor 34, 0, 0 +; CHECK-P9-NEXT: xvresp vs1, v3 +; CHECK-P9-NEXT: xvmulsp vs0, v2, vs1 +; CHECK-P9-NEXT: xvnmsubasp v2, v3, vs0 +; CHECK-P9-NEXT: xvmaddasp vs0, vs1, v2 +; CHECK-P9-NEXT: xxlor v2, vs0, vs0 ; CHECK-P9-NEXT: blr %r = fdiv contract reassoc arcp nsz ninf <4 x float> %a, %b ret <4 x float> %r @@ -709,38 +712,38 @@ define <4 x float> @hoo2_fmf(<4 x float> %a, <4 x float> %b) nounwind { define <4 x float> @hoo2_safe(<4 x float> %a, <4 x float> %b) nounwind { ; CHECK-P7-LABEL: hoo2_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: addi 3, 1, -32 -; CHECK-P7-NEXT: stvx 3, 0, 3 -; CHECK-P7-NEXT: addi 3, 1, -48 -; CHECK-P7-NEXT: stvx 2, 0, 3 -; CHECK-P7-NEXT: addi 3, 1, -16 -; CHECK-P7-NEXT: lfs 0, -20(1) -; CHECK-P7-NEXT: lfs 1, -36(1) -; CHECK-P7-NEXT: fdivs 0, 1, 0 -; CHECK-P7-NEXT: lfs 1, -40(1) -; CHECK-P7-NEXT: stfs 0, -4(1) -; CHECK-P7-NEXT: lfs 0, -24(1) -; CHECK-P7-NEXT: fdivs 0, 1, 0 -; CHECK-P7-NEXT: lfs 1, -44(1) -; CHECK-P7-NEXT: stfs 0, -8(1) -; CHECK-P7-NEXT: lfs 0, -28(1) -; CHECK-P7-NEXT: fdivs 0, 1, 0 -; CHECK-P7-NEXT: lfs 1, -48(1) -; CHECK-P7-NEXT: stfs 0, -12(1) -; CHECK-P7-NEXT: lfs 0, -32(1) -; CHECK-P7-NEXT: fdivs 0, 1, 0 -; CHECK-P7-NEXT: stfs 0, -16(1) -; CHECK-P7-NEXT: lvx 2, 0, 3 +; CHECK-P7-NEXT: addi r3, r1, -32 +; CHECK-P7-NEXT: stvx v3, 0, r3 +; CHECK-P7-NEXT: addi r3, r1, -48 +; CHECK-P7-NEXT: stvx v2, 0, r3 +; CHECK-P7-NEXT: addi r3, r1, -16 +; CHECK-P7-NEXT: lfs f0, -20(r1) +; CHECK-P7-NEXT: lfs f1, -36(r1) +; CHECK-P7-NEXT: fdivs f0, f1, f0 +; CHECK-P7-NEXT: lfs f1, -40(r1) +; CHECK-P7-NEXT: stfs f0, -4(r1) +; CHECK-P7-NEXT: lfs f0, -24(r1) +; CHECK-P7-NEXT: fdivs f0, f1, f0 +; CHECK-P7-NEXT: lfs f1, -44(r1) +; CHECK-P7-NEXT: stfs f0, -8(r1) +; CHECK-P7-NEXT: lfs f0, -28(r1) +; CHECK-P7-NEXT: fdivs f0, f1, f0 +; CHECK-P7-NEXT: lfs f1, -48(r1) +; CHECK-P7-NEXT: stfs f0, -12(r1) +; CHECK-P7-NEXT: lfs f0, -32(r1) +; CHECK-P7-NEXT: fdivs f0, f1, f0 +; CHECK-P7-NEXT: stfs f0, -16(r1) +; CHECK-P7-NEXT: lvx v2, 0, r3 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo2_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvdivsp 34, 34, 35 +; CHECK-P8-NEXT: xvdivsp v2, v2, v3 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo2_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvdivsp 34, 34, 35 +; CHECK-P9-NEXT: xvdivsp v2, v2, v3 ; CHECK-P9-NEXT: blr %r = fdiv <4 x float> %a, %b ret <4 x float> %r @@ -749,73 +752,73 @@ define <4 x float> @hoo2_safe(<4 x float> %a, <4 x float> %b) nounwind { define double @foo3_fmf(double %a) nounwind { ; CHECK-P7-LABEL: foo3_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: ftsqrt 0, 1 -; CHECK-P7-NEXT: bc 12, 2, .LBB20_2 +; CHECK-P7-NEXT: ftsqrt cr0, f1 +; CHECK-P7-NEXT: bc 12, eq, .LBB20_2 ; CHECK-P7-NEXT: # %bb.1: -; CHECK-P7-NEXT: frsqrte 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI20_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI20_1@toc@l(3) -; CHECK-P7-NEXT: fmul 2, 1, 0 -; CHECK-P7-NEXT: fmadd 2, 2, 0, 3 -; CHECK-P7-NEXT: fmul 0, 0, 4 -; CHECK-P7-NEXT: fmul 0, 0, 2 -; CHECK-P7-NEXT: fmul 1, 1, 0 -; CHECK-P7-NEXT: fmadd 0, 1, 0, 3 -; CHECK-P7-NEXT: fmul 1, 1, 4 -; CHECK-P7-NEXT: fmul 1, 1, 0 +; CHECK-P7-NEXT: frsqrte f0, f1 +; CHECK-P7-NEXT: addis r3, r2, .LCPI20_0@toc@ha +; CHECK-P7-NEXT: lfs f3, .LCPI20_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI20_1@toc@ha +; CHECK-P7-NEXT: lfs f4, .LCPI20_1@toc@l(r3) +; CHECK-P7-NEXT: fmul f2, f1, f0 +; CHECK-P7-NEXT: fmadd f2, f2, f0, f3 +; CHECK-P7-NEXT: fmul f0, f0, f4 +; CHECK-P7-NEXT: fmul f0, f0, f2 +; CHECK-P7-NEXT: fmul f1, f1, f0 +; CHECK-P7-NEXT: fmadd f0, f1, f0, f3 +; CHECK-P7-NEXT: fmul f1, f1, f4 +; CHECK-P7-NEXT: fmul f1, f1, f0 ; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: .LBB20_2: -; CHECK-P7-NEXT: fsqrt 1, 1 +; CHECK-P7-NEXT: fsqrt f1, f1 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo3_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xstsqrtdp 0, 1 -; CHECK-P8-NEXT: bc 12, 2, .LBB20_2 +; CHECK-P8-NEXT: xstsqrtdp cr0, f1 +; CHECK-P8-NEXT: bc 12, eq, .LBB20_2 ; CHECK-P8-NEXT: # %bb.1: -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: xsrsqrtedp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 3, 34 -; CHECK-P8-NEXT: xsmuldp 2, 1, 0 -; CHECK-P8-NEXT: fmr 4, 3 -; CHECK-P8-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P8-NEXT: lfs 2, .LCPI20_0@toc@l(3) -; CHECK-P8-NEXT: xsmuldp 0, 0, 2 -; CHECK-P8-NEXT: xsmuldp 0, 0, 4 -; CHECK-P8-NEXT: xsmuldp 1, 1, 0 -; CHECK-P8-NEXT: xsmaddadp 3, 1, 0 -; CHECK-P8-NEXT: xsmuldp 0, 1, 2 -; CHECK-P8-NEXT: xsmuldp 1, 0, 3 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: xsrsqrtedp f0, f1 +; CHECK-P8-NEXT: addis r3, r2, .LCPI20_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P8-NEXT: xsmuldp f2, f1, f0 +; CHECK-P8-NEXT: fmr f4, f3 +; CHECK-P8-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P8-NEXT: lfs f2, .LCPI20_0@toc@l(r3) +; CHECK-P8-NEXT: xsmuldp f0, f0, f2 +; CHECK-P8-NEXT: xsmuldp f0, f0, f4 +; CHECK-P8-NEXT: xsmuldp f1, f1, f0 +; CHECK-P8-NEXT: xsmaddadp f3, f1, f0 +; CHECK-P8-NEXT: xsmuldp f0, f1, f2 +; CHECK-P8-NEXT: xsmuldp f1, f0, f3 ; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: .LBB20_2: -; CHECK-P8-NEXT: xssqrtdp 1, 1 +; CHECK-P8-NEXT: xssqrtdp f1, f1 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo3_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xstsqrtdp 0, 1 -; CHECK-P9-NEXT: bc 12, 2, .LBB20_2 +; CHECK-P9-NEXT: xstsqrtdp cr0, f1 +; CHECK-P9-NEXT: bc 12, eq, .LBB20_2 ; CHECK-P9-NEXT: # %bb.1: -; CHECK-P9-NEXT: xsrsqrtedp 0, 1 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; CHECK-P9-NEXT: xsmuldp 2, 1, 0 -; CHECK-P9-NEXT: xvcvsxwdp 3, 34 -; CHECK-P9-NEXT: fmr 4, 3 -; CHECK-P9-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI20_0@toc@l(3) -; CHECK-P9-NEXT: xsmuldp 0, 0, 2 -; CHECK-P9-NEXT: xsmuldp 0, 0, 4 -; CHECK-P9-NEXT: xsmuldp 1, 1, 0 -; CHECK-P9-NEXT: xsmaddadp 3, 1, 0 -; CHECK-P9-NEXT: xsmuldp 0, 1, 2 -; CHECK-P9-NEXT: xsmuldp 1, 0, 3 +; CHECK-P9-NEXT: xsrsqrtedp f0, f1 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI20_0@toc@ha +; CHECK-P9-NEXT: xsmuldp f2, f1, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P9-NEXT: fmr f4, f3 +; CHECK-P9-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P9-NEXT: lfs f2, .LCPI20_0@toc@l(r3) +; CHECK-P9-NEXT: xsmuldp f0, f0, f2 +; CHECK-P9-NEXT: xsmuldp f0, f0, f4 +; CHECK-P9-NEXT: xsmuldp f1, f1, f0 +; CHECK-P9-NEXT: xsmaddadp f3, f1, f0 +; CHECK-P9-NEXT: xsmuldp f0, f1, f2 +; CHECK-P9-NEXT: xsmuldp f1, f0, f3 ; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: .LBB20_2: -; CHECK-P9-NEXT: xssqrtdp 1, 1 +; CHECK-P9-NEXT: xssqrtdp f1, f1 ; CHECK-P9-NEXT: blr %r = call contract reassoc ninf afn double @llvm.sqrt.f64(double %a) ret double %r @@ -824,82 +827,82 @@ define double @foo3_fmf(double %a) nounwind { define double @foo3_fmf_crbits_off(double %a) #2 { ; CHECK-P7-LABEL: foo3_fmf_crbits_off: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fabs 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI21_2@toc@ha -; CHECK-P7-NEXT: lfd 2, .LCPI21_2@toc@l(3) -; CHECK-P7-NEXT: fcmpu 0, 0, 2 -; CHECK-P7-NEXT: blt 0, .LBB21_2 +; CHECK-P7-NEXT: fabs f0, f1 +; CHECK-P7-NEXT: addis r3, r2, .LCPI21_2@toc@ha +; CHECK-P7-NEXT: lfd f2, .LCPI21_2@toc@l(r3) +; CHECK-P7-NEXT: fcmpu cr0, f0, f2 +; CHECK-P7-NEXT: blt cr0, .LBB21_2 ; CHECK-P7-NEXT: # %bb.1: -; CHECK-P7-NEXT: frsqrte 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI21_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; CHECK-P7-NEXT: lfs 4, .LCPI21_1@toc@l(3) -; CHECK-P7-NEXT: fmul 2, 1, 0 -; CHECK-P7-NEXT: fmadd 2, 2, 0, 3 -; CHECK-P7-NEXT: fmul 0, 0, 4 -; CHECK-P7-NEXT: fmul 0, 0, 2 -; CHECK-P7-NEXT: fmul 1, 1, 0 -; CHECK-P7-NEXT: fmadd 0, 1, 0, 3 -; CHECK-P7-NEXT: fmul 1, 1, 4 -; CHECK-P7-NEXT: fmul 1, 1, 0 +; CHECK-P7-NEXT: frsqrte f0, f1 +; CHECK-P7-NEXT: addis r3, r2, .LCPI21_0@toc@ha +; CHECK-P7-NEXT: lfs f3, .LCPI21_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI21_1@toc@ha +; CHECK-P7-NEXT: lfs f4, .LCPI21_1@toc@l(r3) +; CHECK-P7-NEXT: fmul f2, f1, f0 +; CHECK-P7-NEXT: fmadd f2, f2, f0, f3 +; CHECK-P7-NEXT: fmul f0, f0, f4 +; CHECK-P7-NEXT: fmul f0, f0, f2 +; CHECK-P7-NEXT: fmul f1, f1, f0 +; CHECK-P7-NEXT: fmadd f0, f1, f0, f3 +; CHECK-P7-NEXT: fmul f1, f1, f4 +; CHECK-P7-NEXT: fmul f1, f1, f0 ; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: .LBB21_2: -; CHECK-P7-NEXT: fsqrt 1, 1 +; CHECK-P7-NEXT: fsqrt f1, f1 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo3_fmf_crbits_off: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; CHECK-P8-NEXT: xsabsdp 0, 1 -; CHECK-P8-NEXT: lfd 2, .LCPI21_1@toc@l(3) -; CHECK-P8-NEXT: xscmpudp 0, 0, 2 -; CHECK-P8-NEXT: blt 0, .LBB21_2 +; CHECK-P8-NEXT: addis r3, r2, .LCPI21_1@toc@ha +; CHECK-P8-NEXT: xsabsdp f0, f1 +; CHECK-P8-NEXT: lfd f2, .LCPI21_1@toc@l(r3) +; CHECK-P8-NEXT: xscmpudp cr0, f0, f2 +; CHECK-P8-NEXT: blt cr0, .LBB21_2 ; CHECK-P8-NEXT: # %bb.1: -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: xsrsqrtedp 0, 1 -; CHECK-P8-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 3, 34 -; CHECK-P8-NEXT: xsmuldp 2, 1, 0 -; CHECK-P8-NEXT: fmr 4, 3 -; CHECK-P8-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P8-NEXT: lfs 2, .LCPI21_0@toc@l(3) -; CHECK-P8-NEXT: xsmuldp 0, 0, 2 -; CHECK-P8-NEXT: xsmuldp 0, 0, 4 -; CHECK-P8-NEXT: xsmuldp 1, 1, 0 -; CHECK-P8-NEXT: xsmaddadp 3, 1, 0 -; CHECK-P8-NEXT: xsmuldp 0, 1, 2 -; CHECK-P8-NEXT: xsmuldp 1, 0, 3 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: xsrsqrtedp f0, f1 +; CHECK-P8-NEXT: addis r3, r2, .LCPI21_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P8-NEXT: xsmuldp f2, f1, f0 +; CHECK-P8-NEXT: fmr f4, f3 +; CHECK-P8-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P8-NEXT: lfs f2, .LCPI21_0@toc@l(r3) +; CHECK-P8-NEXT: xsmuldp f0, f0, f2 +; CHECK-P8-NEXT: xsmuldp f0, f0, f4 +; CHECK-P8-NEXT: xsmuldp f1, f1, f0 +; CHECK-P8-NEXT: xsmaddadp f3, f1, f0 +; CHECK-P8-NEXT: xsmuldp f0, f1, f2 +; CHECK-P8-NEXT: xsmuldp f1, f0, f3 ; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: .LBB21_2: -; CHECK-P8-NEXT: xssqrtdp 1, 1 +; CHECK-P8-NEXT: xssqrtdp f1, f1 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo3_fmf_crbits_off: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; CHECK-P9-NEXT: xsabsdp 0, 1 -; CHECK-P9-NEXT: lfd 2, .LCPI21_1@toc@l(3) -; CHECK-P9-NEXT: xscmpudp 0, 0, 2 -; CHECK-P9-NEXT: blt 0, .LBB21_2 +; CHECK-P9-NEXT: addis r3, r2, .LCPI21_1@toc@ha +; CHECK-P9-NEXT: xsabsdp f0, f1 +; CHECK-P9-NEXT: lfd f2, .LCPI21_1@toc@l(r3) +; CHECK-P9-NEXT: xscmpudp cr0, f0, f2 +; CHECK-P9-NEXT: blt cr0, .LBB21_2 ; CHECK-P9-NEXT: # %bb.1: -; CHECK-P9-NEXT: xsrsqrtedp 0, 1 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; CHECK-P9-NEXT: xsmuldp 2, 1, 0 -; CHECK-P9-NEXT: xvcvsxwdp 3, 34 -; CHECK-P9-NEXT: fmr 4, 3 -; CHECK-P9-NEXT: xsmaddadp 4, 2, 0 -; CHECK-P9-NEXT: lfs 2, .LCPI21_0@toc@l(3) -; CHECK-P9-NEXT: xsmuldp 0, 0, 2 -; CHECK-P9-NEXT: xsmuldp 0, 0, 4 -; CHECK-P9-NEXT: xsmuldp 1, 1, 0 -; CHECK-P9-NEXT: xsmaddadp 3, 1, 0 -; CHECK-P9-NEXT: xsmuldp 0, 1, 2 -; CHECK-P9-NEXT: xsmuldp 1, 0, 3 +; CHECK-P9-NEXT: xsrsqrtedp f0, f1 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI21_0@toc@ha +; CHECK-P9-NEXT: xsmuldp f2, f1, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs3, v2 +; CHECK-P9-NEXT: fmr f4, f3 +; CHECK-P9-NEXT: xsmaddadp f4, f2, f0 +; CHECK-P9-NEXT: lfs f2, .LCPI21_0@toc@l(r3) +; CHECK-P9-NEXT: xsmuldp f0, f0, f2 +; CHECK-P9-NEXT: xsmuldp f0, f0, f4 +; CHECK-P9-NEXT: xsmuldp f1, f1, f0 +; CHECK-P9-NEXT: xsmaddadp f3, f1, f0 +; CHECK-P9-NEXT: xsmuldp f0, f1, f2 +; CHECK-P9-NEXT: xsmuldp f1, f0, f3 ; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: .LBB21_2: -; CHECK-P9-NEXT: xssqrtdp 1, 1 +; CHECK-P9-NEXT: xssqrtdp f1, f1 ; CHECK-P9-NEXT: blr %r = call contract reassoc ninf afn double @llvm.sqrt.f64(double %a) ret double %r @@ -908,17 +911,17 @@ define double @foo3_fmf_crbits_off(double %a) #2 { define double @foo3_safe(double %a) nounwind { ; CHECK-P7-LABEL: foo3_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrt 1, 1 +; CHECK-P7-NEXT: fsqrt f1, f1 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: foo3_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xssqrtdp 1, 1 +; CHECK-P8-NEXT: xssqrtdp f1, f1 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: foo3_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtdp 1, 1 +; CHECK-P9-NEXT: xssqrtdp f1, f1 ; CHECK-P9-NEXT: blr %r = call double @llvm.sqrt.f64(double %a) ret double %r @@ -927,69 +930,69 @@ define double @foo3_safe(double %a) nounwind { define float @goo3_fmf(float %a) nounwind { ; CHECK-P7-LABEL: goo3_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fabs 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI23_2@toc@ha -; CHECK-P7-NEXT: lfs 2, .LCPI23_2@toc@l(3) -; CHECK-P7-NEXT: fcmpu 0, 0, 2 -; CHECK-P7-NEXT: blt 0, .LBB23_2 +; CHECK-P7-NEXT: fabs f0, f1 +; CHECK-P7-NEXT: addis r3, r2, .LCPI23_2@toc@ha +; CHECK-P7-NEXT: lfs f2, .LCPI23_2@toc@l(r3) +; CHECK-P7-NEXT: fcmpu cr0, f0, f2 +; CHECK-P7-NEXT: blt cr0, .LBB23_2 ; CHECK-P7-NEXT: # %bb.1: -; CHECK-P7-NEXT: frsqrtes 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-P7-NEXT: lfs 2, .LCPI23_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; CHECK-P7-NEXT: fmuls 1, 1, 0 -; CHECK-P7-NEXT: fmadds 0, 1, 0, 2 -; CHECK-P7-NEXT: lfs 2, .LCPI23_1@toc@l(3) -; CHECK-P7-NEXT: fmuls 1, 1, 2 -; CHECK-P7-NEXT: fmuls 1, 1, 0 +; CHECK-P7-NEXT: frsqrtes f0, f1 +; CHECK-P7-NEXT: addis r3, r2, .LCPI23_0@toc@ha +; CHECK-P7-NEXT: lfs f2, .LCPI23_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI23_1@toc@ha +; CHECK-P7-NEXT: fmuls f1, f1, f0 +; CHECK-P7-NEXT: fmadds f0, f1, f0, f2 +; CHECK-P7-NEXT: lfs f2, .LCPI23_1@toc@l(r3) +; CHECK-P7-NEXT: fmuls f1, f1, f2 +; CHECK-P7-NEXT: fmuls f1, f1, f0 ; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: .LBB23_2: -; CHECK-P7-NEXT: addis 3, 2, .LCPI23_3@toc@ha -; CHECK-P7-NEXT: lfs 1, .LCPI23_3@toc@l(3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI23_3@toc@ha +; CHECK-P7-NEXT: lfs f1, .LCPI23_3@toc@l(r3) ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: goo3_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; CHECK-P8-NEXT: xsabsdp 0, 1 -; CHECK-P8-NEXT: lfs 2, .LCPI23_1@toc@l(3) -; CHECK-P8-NEXT: fcmpu 0, 0, 2 -; CHECK-P8-NEXT: xxlxor 0, 0, 0 -; CHECK-P8-NEXT: blt 0, .LBB23_2 +; CHECK-P8-NEXT: addis r3, r2, .LCPI23_1@toc@ha +; CHECK-P8-NEXT: xsabsdp f0, f1 +; CHECK-P8-NEXT: lfs f2, .LCPI23_1@toc@l(r3) +; CHECK-P8-NEXT: fcmpu cr0, f0, f2 +; CHECK-P8-NEXT: xxlxor f0, f0, f0 +; CHECK-P8-NEXT: blt cr0, .LBB23_2 ; CHECK-P8-NEXT: # %bb.1: -; CHECK-P8-NEXT: xsrsqrtesp 0, 1 -; CHECK-P8-NEXT: vspltisw 2, -3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-P8-NEXT: xvcvsxwdp 2, 34 -; CHECK-P8-NEXT: xsmulsp 1, 1, 0 -; CHECK-P8-NEXT: xsmaddasp 2, 1, 0 -; CHECK-P8-NEXT: lfs 0, .LCPI23_0@toc@l(3) -; CHECK-P8-NEXT: xsmulsp 0, 1, 0 -; CHECK-P8-NEXT: xsmulsp 0, 0, 2 +; CHECK-P8-NEXT: xsrsqrtesp f0, f1 +; CHECK-P8-NEXT: vspltisw v2, -3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI23_0@toc@ha +; CHECK-P8-NEXT: xvcvsxwdp vs2, v2 +; CHECK-P8-NEXT: xsmulsp f1, f1, f0 +; CHECK-P8-NEXT: xsmaddasp f2, f1, f0 +; CHECK-P8-NEXT: lfs f0, .LCPI23_0@toc@l(r3) +; CHECK-P8-NEXT: xsmulsp f0, f1, f0 +; CHECK-P8-NEXT: xsmulsp f0, f0, f2 ; CHECK-P8-NEXT: .LBB23_2: -; CHECK-P8-NEXT: fmr 1, 0 +; CHECK-P8-NEXT: fmr f1, f0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: goo3_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; CHECK-P9-NEXT: xsabsdp 0, 1 -; CHECK-P9-NEXT: lfs 2, .LCPI23_1@toc@l(3) -; CHECK-P9-NEXT: fcmpu 0, 0, 2 -; CHECK-P9-NEXT: xxlxor 0, 0, 0 -; CHECK-P9-NEXT: blt 0, .LBB23_2 +; CHECK-P9-NEXT: addis r3, r2, .LCPI23_1@toc@ha +; CHECK-P9-NEXT: xsabsdp f0, f1 +; CHECK-P9-NEXT: lfs f2, .LCPI23_1@toc@l(r3) +; CHECK-P9-NEXT: fcmpu cr0, f0, f2 +; CHECK-P9-NEXT: xxlxor f0, f0, f0 +; CHECK-P9-NEXT: blt cr0, .LBB23_2 ; CHECK-P9-NEXT: # %bb.1: -; CHECK-P9-NEXT: xsrsqrtesp 0, 1 -; CHECK-P9-NEXT: vspltisw 2, -3 -; CHECK-P9-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; CHECK-P9-NEXT: xsmulsp 1, 1, 0 -; CHECK-P9-NEXT: xvcvsxwdp 2, 34 -; CHECK-P9-NEXT: xsmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lfs 0, .LCPI23_0@toc@l(3) -; CHECK-P9-NEXT: xsmulsp 0, 1, 0 -; CHECK-P9-NEXT: xsmulsp 0, 0, 2 +; CHECK-P9-NEXT: xsrsqrtesp f0, f1 +; CHECK-P9-NEXT: vspltisw v2, -3 +; CHECK-P9-NEXT: addis r3, r2, .LCPI23_0@toc@ha +; CHECK-P9-NEXT: xsmulsp f1, f1, f0 +; CHECK-P9-NEXT: xvcvsxwdp vs2, v2 +; CHECK-P9-NEXT: xsmaddasp f2, f1, f0 +; CHECK-P9-NEXT: lfs f0, .LCPI23_0@toc@l(r3) +; CHECK-P9-NEXT: xsmulsp f0, f1, f0 +; CHECK-P9-NEXT: xsmulsp f0, f0, f2 ; CHECK-P9-NEXT: .LBB23_2: -; CHECK-P9-NEXT: fmr 1, 0 +; CHECK-P9-NEXT: fmr f1, f0 ; CHECK-P9-NEXT: blr %r = call contract reassoc ninf afn float @llvm.sqrt.f32(float %a) ret float %r @@ -998,17 +1001,17 @@ define float @goo3_fmf(float %a) nounwind { define float @goo3_safe(float %a) nounwind { ; CHECK-P7-LABEL: goo3_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrts 1, 1 +; CHECK-P7-NEXT: fsqrts f1, f1 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: goo3_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xssqrtsp 1, 1 +; CHECK-P8-NEXT: xssqrtsp f1, f1 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: goo3_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtsp 1, 1 +; CHECK-P9-NEXT: xssqrtsp f1, f1 ; CHECK-P9-NEXT: blr %r = call float @llvm.sqrt.f32(float %a) ret float %r @@ -1017,65 +1020,65 @@ define float @goo3_safe(float %a) nounwind { define <4 x float> @hoo3_fmf(<4 x float> %a) #1 { ; CHECK-P7-LABEL: hoo3_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; CHECK-P7-NEXT: vspltisw 3, -1 -; CHECK-P7-NEXT: vrsqrtefp 4, 2 -; CHECK-P7-NEXT: addi 3, 3, .LCPI25_0@toc@l -; CHECK-P7-NEXT: vslw 3, 3, 3 -; CHECK-P7-NEXT: lvx 0, 0, 3 -; CHECK-P7-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; CHECK-P7-NEXT: vmaddfp 5, 2, 4, 3 -; CHECK-P7-NEXT: addi 3, 3, .LCPI25_1@toc@l -; CHECK-P7-NEXT: vmaddfp 4, 5, 4, 0 -; CHECK-P7-NEXT: lvx 0, 0, 3 -; CHECK-P7-NEXT: vmaddfp 5, 5, 0, 3 -; CHECK-P7-NEXT: vmaddfp 3, 5, 4, 3 -; CHECK-P7-NEXT: vxor 4, 4, 4 -; CHECK-P7-NEXT: vcmpeqfp 2, 2, 4 -; CHECK-P7-NEXT: vnot 2, 2 -; CHECK-P7-NEXT: vand 2, 2, 3 +; CHECK-P7-NEXT: addis r3, r2, .LCPI25_0@toc@ha +; CHECK-P7-NEXT: vspltisw v3, -1 +; CHECK-P7-NEXT: vrsqrtefp v4, v2 +; CHECK-P7-NEXT: addi r3, r3, .LCPI25_0@toc@l +; CHECK-P7-NEXT: vslw v3, v3, v3 +; CHECK-P7-NEXT: lvx v0, 0, r3 +; CHECK-P7-NEXT: addis r3, r2, .LCPI25_1@toc@ha +; CHECK-P7-NEXT: vmaddfp v5, v2, v4, v3 +; CHECK-P7-NEXT: addi r3, r3, .LCPI25_1@toc@l +; CHECK-P7-NEXT: vmaddfp v4, v5, v4, v0 +; CHECK-P7-NEXT: lvx v0, 0, r3 +; CHECK-P7-NEXT: vmaddfp v5, v5, v0, v3 +; CHECK-P7-NEXT: vmaddfp v3, v5, v4, v3 +; CHECK-P7-NEXT: vxor v4, v4, v4 +; CHECK-P7-NEXT: vcmpeqfp v2, v2, v4 +; CHECK-P7-NEXT: vnot v2, v2 +; CHECK-P7-NEXT: vand v2, v2, v3 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo3_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvtsqrtsp 0, 34 -; CHECK-P8-NEXT: bc 12, 2, .LBB25_2 +; CHECK-P8-NEXT: xvtsqrtsp cr0, v2 +; CHECK-P8-NEXT: bc 12, eq, .LBB25_2 ; CHECK-P8-NEXT: # %bb.1: -; CHECK-P8-NEXT: xvrsqrtesp 0, 34 -; CHECK-P8-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI25_0@toc@l -; CHECK-P8-NEXT: lxvd2x 2, 0, 3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; CHECK-P8-NEXT: xvmulsp 1, 34, 0 -; CHECK-P8-NEXT: addi 3, 3, .LCPI25_1@toc@l -; CHECK-P8-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P8-NEXT: lxvd2x 0, 0, 3 -; CHECK-P8-NEXT: xvmulsp 0, 1, 0 -; CHECK-P8-NEXT: xvmulsp 34, 0, 2 +; CHECK-P8-NEXT: xvrsqrtesp vs0, v2 +; CHECK-P8-NEXT: addis r3, r2, .LCPI25_0@toc@ha +; CHECK-P8-NEXT: addi r3, r3, .LCPI25_0@toc@l +; CHECK-P8-NEXT: lxvd2x vs2, 0, r3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI25_1@toc@ha +; CHECK-P8-NEXT: xvmulsp vs1, v2, vs0 +; CHECK-P8-NEXT: addi r3, r3, .LCPI25_1@toc@l +; CHECK-P8-NEXT: xvmaddasp vs2, vs1, vs0 +; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: xvmulsp vs0, vs1, vs0 +; CHECK-P8-NEXT: xvmulsp v2, vs0, vs2 ; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: .LBB25_2: -; CHECK-P8-NEXT: xvsqrtsp 34, 34 +; CHECK-P8-NEXT: xvsqrtsp v2, v2 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo3_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvtsqrtsp 0, 34 -; CHECK-P9-NEXT: bc 12, 2, .LBB25_2 +; CHECK-P9-NEXT: xvtsqrtsp cr0, v2 +; CHECK-P9-NEXT: bc 12, eq, .LBB25_2 ; CHECK-P9-NEXT: # %bb.1: -; CHECK-P9-NEXT: xvrsqrtesp 0, 34 -; CHECK-P9-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI25_0@toc@l -; CHECK-P9-NEXT: lxv 2, 0(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI25_1@toc@l -; CHECK-P9-NEXT: xvmulsp 1, 34, 0 -; CHECK-P9-NEXT: xvmaddasp 2, 1, 0 -; CHECK-P9-NEXT: lxv 0, 0(3) -; CHECK-P9-NEXT: xvmulsp 0, 1, 0 -; CHECK-P9-NEXT: xvmulsp 34, 0, 2 +; CHECK-P9-NEXT: xvrsqrtesp vs0, v2 +; CHECK-P9-NEXT: addis r3, r2, .LCPI25_0@toc@ha +; CHECK-P9-NEXT: addi r3, r3, .LCPI25_0@toc@l +; CHECK-P9-NEXT: lxv vs2, 0(r3) +; CHECK-P9-NEXT: addis r3, r2, .LCPI25_1@toc@ha +; CHECK-P9-NEXT: addi r3, r3, .LCPI25_1@toc@l +; CHECK-P9-NEXT: xvmulsp vs1, v2, vs0 +; CHECK-P9-NEXT: xvmaddasp vs2, vs1, vs0 +; CHECK-P9-NEXT: lxv vs0, 0(r3) +; CHECK-P9-NEXT: xvmulsp vs0, vs1, vs0 +; CHECK-P9-NEXT: xvmulsp v2, vs0, vs2 ; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: .LBB25_2: -; CHECK-P9-NEXT: xvsqrtsp 34, 34 +; CHECK-P9-NEXT: xvsqrtsp v2, v2 ; CHECK-P9-NEXT: blr %r = call contract reassoc ninf afn <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) ret <4 x float> %r @@ -1084,32 +1087,32 @@ define <4 x float> @hoo3_fmf(<4 x float> %a) #1 { define <4 x float> @hoo3_safe(<4 x float> %a) nounwind { ; CHECK-P7-LABEL: hoo3_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: addi 3, 1, -32 -; CHECK-P7-NEXT: stvx 2, 0, 3 -; CHECK-P7-NEXT: addi 3, 1, -16 -; CHECK-P7-NEXT: lfs 0, -20(1) -; CHECK-P7-NEXT: fsqrts 0, 0 -; CHECK-P7-NEXT: stfs 0, -4(1) -; CHECK-P7-NEXT: lfs 0, -24(1) -; CHECK-P7-NEXT: fsqrts 0, 0 -; CHECK-P7-NEXT: stfs 0, -8(1) -; CHECK-P7-NEXT: lfs 0, -28(1) -; CHECK-P7-NEXT: fsqrts 0, 0 -; CHECK-P7-NEXT: stfs 0, -12(1) -; CHECK-P7-NEXT: lfs 0, -32(1) -; CHECK-P7-NEXT: fsqrts 0, 0 -; CHECK-P7-NEXT: stfs 0, -16(1) -; CHECK-P7-NEXT: lvx 2, 0, 3 +; CHECK-P7-NEXT: addi r3, r1, -32 +; CHECK-P7-NEXT: stvx v2, 0, r3 +; CHECK-P7-NEXT: addi r3, r1, -16 +; CHECK-P7-NEXT: lfs f0, -20(r1) +; CHECK-P7-NEXT: fsqrts f0, f0 +; CHECK-P7-NEXT: stfs f0, -4(r1) +; CHECK-P7-NEXT: lfs f0, -24(r1) +; CHECK-P7-NEXT: fsqrts f0, f0 +; CHECK-P7-NEXT: stfs f0, -8(r1) +; CHECK-P7-NEXT: lfs f0, -28(r1) +; CHECK-P7-NEXT: fsqrts f0, f0 +; CHECK-P7-NEXT: stfs f0, -12(r1) +; CHECK-P7-NEXT: lfs f0, -32(r1) +; CHECK-P7-NEXT: fsqrts f0, f0 +; CHECK-P7-NEXT: stfs f0, -16(r1) +; CHECK-P7-NEXT: lvx v2, 0, r3 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo3_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvsqrtsp 34, 34 +; CHECK-P8-NEXT: xvsqrtsp v2, v2 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo3_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvsqrtsp 34, 34 +; CHECK-P9-NEXT: xvsqrtsp v2, v2 ; CHECK-P9-NEXT: blr %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) ret <4 x float> %r @@ -1118,93 +1121,93 @@ define <4 x float> @hoo3_safe(<4 x float> %a) nounwind { define <2 x double> @hoo4_fmf(<2 x double> %a) #1 { ; CHECK-P7-LABEL: hoo4_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: ftsqrt 0, 1 -; CHECK-P7-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; CHECK-P7-NEXT: lfs 0, .LCPI27_0@toc@l(3) -; CHECK-P7-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; CHECK-P7-NEXT: lfs 3, .LCPI27_1@toc@l(3) -; CHECK-P7-NEXT: bc 12, 2, .LBB27_3 +; CHECK-P7-NEXT: ftsqrt cr0, f1 +; CHECK-P7-NEXT: addis r3, r2, .LCPI27_0@toc@ha +; CHECK-P7-NEXT: lfs f0, .LCPI27_0@toc@l(r3) +; CHECK-P7-NEXT: addis r3, r2, .LCPI27_1@toc@ha +; CHECK-P7-NEXT: lfs f3, .LCPI27_1@toc@l(r3) +; CHECK-P7-NEXT: bc 12, eq, .LBB27_3 ; CHECK-P7-NEXT: # %bb.1: -; CHECK-P7-NEXT: frsqrte 4, 1 -; CHECK-P7-NEXT: fmul 5, 1, 4 -; CHECK-P7-NEXT: fmadd 5, 5, 4, 0 -; CHECK-P7-NEXT: fmul 4, 4, 3 -; CHECK-P7-NEXT: fmul 4, 4, 5 -; CHECK-P7-NEXT: fmul 1, 1, 4 -; CHECK-P7-NEXT: fmadd 4, 1, 4, 0 -; CHECK-P7-NEXT: fmul 1, 1, 3 -; CHECK-P7-NEXT: fmul 1, 1, 4 -; CHECK-P7-NEXT: ftsqrt 0, 2 -; CHECK-P7-NEXT: bc 4, 2, .LBB27_4 +; CHECK-P7-NEXT: frsqrte f4, f1 +; CHECK-P7-NEXT: fmul f5, f1, f4 +; CHECK-P7-NEXT: fmadd f5, f5, f4, f0 +; CHECK-P7-NEXT: fmul f4, f4, f3 +; CHECK-P7-NEXT: fmul f4, f4, f5 +; CHECK-P7-NEXT: fmul f1, f1, f4 +; CHECK-P7-NEXT: fmadd f4, f1, f4, f0 +; CHECK-P7-NEXT: fmul f1, f1, f3 +; CHECK-P7-NEXT: fmul f1, f1, f4 +; CHECK-P7-NEXT: ftsqrt cr0, f2 +; CHECK-P7-NEXT: bc 4, eq, .LBB27_4 ; CHECK-P7-NEXT: .LBB27_2: -; CHECK-P7-NEXT: fsqrt 2, 2 +; CHECK-P7-NEXT: fsqrt f2, f2 ; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: .LBB27_3: -; CHECK-P7-NEXT: fsqrt 1, 1 -; CHECK-P7-NEXT: ftsqrt 0, 2 -; CHECK-P7-NEXT: bc 12, 2, .LBB27_2 +; CHECK-P7-NEXT: fsqrt f1, f1 +; CHECK-P7-NEXT: ftsqrt cr0, f2 +; CHECK-P7-NEXT: bc 12, eq, .LBB27_2 ; CHECK-P7-NEXT: .LBB27_4: -; CHECK-P7-NEXT: frsqrte 4, 2 -; CHECK-P7-NEXT: fmul 5, 2, 4 -; CHECK-P7-NEXT: fmadd 5, 5, 4, 0 -; CHECK-P7-NEXT: fmul 4, 4, 3 -; CHECK-P7-NEXT: fmul 4, 4, 5 -; CHECK-P7-NEXT: fmul 2, 2, 4 -; CHECK-P7-NEXT: fmadd 0, 2, 4, 0 -; CHECK-P7-NEXT: fmul 2, 2, 3 -; CHECK-P7-NEXT: fmul 2, 2, 0 +; CHECK-P7-NEXT: frsqrte f4, f2 +; CHECK-P7-NEXT: fmul f5, f2, f4 +; CHECK-P7-NEXT: fmadd f5, f5, f4, f0 +; CHECK-P7-NEXT: fmul f4, f4, f3 +; CHECK-P7-NEXT: fmul f4, f4, f5 +; CHECK-P7-NEXT: fmul f2, f2, f4 +; CHECK-P7-NEXT: fmadd f0, f2, f4, f0 +; CHECK-P7-NEXT: fmul f2, f2, f3 +; CHECK-P7-NEXT: fmul f2, f2, f0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo4_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvtsqrtdp 0, 34 -; CHECK-P8-NEXT: bc 12, 2, .LBB27_2 +; CHECK-P8-NEXT: xvtsqrtdp cr0, v2 +; CHECK-P8-NEXT: bc 12, eq, .LBB27_2 ; CHECK-P8-NEXT: # %bb.1: -; CHECK-P8-NEXT: xvrsqrtedp 0, 34 -; CHECK-P8-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; CHECK-P8-NEXT: addi 3, 3, .LCPI27_0@toc@l -; CHECK-P8-NEXT: lxvd2x 2, 0, 3 -; CHECK-P8-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; CHECK-P8-NEXT: xvmuldp 1, 34, 0 -; CHECK-P8-NEXT: addi 3, 3, .LCPI27_1@toc@l -; CHECK-P8-NEXT: xxlor 3, 2, 2 -; CHECK-P8-NEXT: xvmaddadp 3, 1, 0 -; CHECK-P8-NEXT: lxvd2x 1, 0, 3 -; CHECK-P8-NEXT: xvmuldp 0, 0, 1 -; CHECK-P8-NEXT: xvmuldp 0, 0, 3 -; CHECK-P8-NEXT: xvmuldp 3, 34, 0 -; CHECK-P8-NEXT: xvmaddadp 2, 3, 0 -; CHECK-P8-NEXT: xvmuldp 0, 3, 1 -; CHECK-P8-NEXT: xvmuldp 34, 0, 2 +; CHECK-P8-NEXT: xvrsqrtedp vs0, v2 +; CHECK-P8-NEXT: addis r3, r2, .LCPI27_0@toc@ha +; CHECK-P8-NEXT: addi r3, r3, .LCPI27_0@toc@l +; CHECK-P8-NEXT: lxvd2x vs2, 0, r3 +; CHECK-P8-NEXT: addis r3, r2, .LCPI27_1@toc@ha +; CHECK-P8-NEXT: xvmuldp vs1, v2, vs0 +; CHECK-P8-NEXT: addi r3, r3, .LCPI27_1@toc@l +; CHECK-P8-NEXT: xxlor vs3, vs2, vs2 +; CHECK-P8-NEXT: xvmaddadp vs3, vs1, vs0 +; CHECK-P8-NEXT: lxvd2x vs1, 0, r3 +; CHECK-P8-NEXT: xvmuldp vs0, vs0, vs1 +; CHECK-P8-NEXT: xvmuldp vs0, vs0, vs3 +; CHECK-P8-NEXT: xvmuldp vs3, v2, vs0 +; CHECK-P8-NEXT: xvmaddadp vs2, vs3, vs0 +; CHECK-P8-NEXT: xvmuldp vs0, vs3, vs1 +; CHECK-P8-NEXT: xvmuldp v2, vs0, vs2 ; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: .LBB27_2: -; CHECK-P8-NEXT: xvsqrtdp 34, 34 +; CHECK-P8-NEXT: xvsqrtdp v2, v2 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo4_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvtsqrtdp 0, 34 -; CHECK-P9-NEXT: bc 12, 2, .LBB27_2 +; CHECK-P9-NEXT: xvtsqrtdp cr0, v2 +; CHECK-P9-NEXT: bc 12, eq, .LBB27_2 ; CHECK-P9-NEXT: # %bb.1: -; CHECK-P9-NEXT: xvrsqrtedp 0, 34 -; CHECK-P9-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI27_0@toc@l -; CHECK-P9-NEXT: lxv 2, 0(3) -; CHECK-P9-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; CHECK-P9-NEXT: addi 3, 3, .LCPI27_1@toc@l -; CHECK-P9-NEXT: xvmuldp 1, 34, 0 -; CHECK-P9-NEXT: xxlor 3, 2, 2 -; CHECK-P9-NEXT: xvmaddadp 3, 1, 0 -; CHECK-P9-NEXT: lxv 1, 0(3) -; CHECK-P9-NEXT: xvmuldp 0, 0, 1 -; CHECK-P9-NEXT: xvmuldp 0, 0, 3 -; CHECK-P9-NEXT: xvmuldp 3, 34, 0 -; CHECK-P9-NEXT: xvmaddadp 2, 3, 0 -; CHECK-P9-NEXT: xvmuldp 0, 3, 1 -; CHECK-P9-NEXT: xvmuldp 34, 0, 2 +; CHECK-P9-NEXT: xvrsqrtedp vs0, v2 +; CHECK-P9-NEXT: addis r3, r2, .LCPI27_0@toc@ha +; CHECK-P9-NEXT: addi r3, r3, .LCPI27_0@toc@l +; CHECK-P9-NEXT: lxv vs2, 0(r3) +; CHECK-P9-NEXT: addis r3, r2, .LCPI27_1@toc@ha +; CHECK-P9-NEXT: addi r3, r3, .LCPI27_1@toc@l +; CHECK-P9-NEXT: xvmuldp vs1, v2, vs0 +; CHECK-P9-NEXT: xxlor vs3, vs2, vs2 +; CHECK-P9-NEXT: xvmaddadp vs3, vs1, vs0 +; CHECK-P9-NEXT: lxv vs1, 0(r3) +; CHECK-P9-NEXT: xvmuldp vs0, vs0, vs1 +; CHECK-P9-NEXT: xvmuldp vs0, vs0, vs3 +; CHECK-P9-NEXT: xvmuldp vs3, v2, vs0 +; CHECK-P9-NEXT: xvmaddadp vs2, vs3, vs0 +; CHECK-P9-NEXT: xvmuldp vs0, vs3, vs1 +; CHECK-P9-NEXT: xvmuldp v2, vs0, vs2 ; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: .LBB27_2: -; CHECK-P9-NEXT: xvsqrtdp 34, 34 +; CHECK-P9-NEXT: xvsqrtdp v2, v2 ; CHECK-P9-NEXT: blr %r = call contract reassoc ninf afn <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) ret <2 x double> %r @@ -1213,18 +1216,18 @@ define <2 x double> @hoo4_fmf(<2 x double> %a) #1 { define <2 x double> @hoo4_safe(<2 x double> %a) #1 { ; CHECK-P7-LABEL: hoo4_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: fsqrt 1, 1 -; CHECK-P7-NEXT: fsqrt 2, 2 +; CHECK-P7-NEXT: fsqrt f1, f1 +; CHECK-P7-NEXT: fsqrt f2, f2 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo4_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: xvsqrtdp 34, 34 +; CHECK-P8-NEXT: xvsqrtdp v2, v2 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo4_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xvsqrtdp 34, 34 +; CHECK-P9-NEXT: xvsqrtdp v2, v2 ; CHECK-P9-NEXT: blr %r = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) ret <2 x double> %r @@ -1233,31 +1236,31 @@ define <2 x double> @hoo4_safe(<2 x double> %a) #1 { define fp128 @hoo5_fmf(fp128 %a) #1 { ; CHECK-P7-LABEL: hoo5_fmf: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: mflr 0 -; CHECK-P7-NEXT: stdu 1, -112(1) -; CHECK-P7-NEXT: std 0, 128(1) +; CHECK-P7-NEXT: mflr r0 +; CHECK-P7-NEXT: stdu r1, -112(r1) +; CHECK-P7-NEXT: std r0, 128(r1) ; CHECK-P7-NEXT: bl sqrtf128 ; CHECK-P7-NEXT: nop -; CHECK-P7-NEXT: addi 1, 1, 112 -; CHECK-P7-NEXT: ld 0, 16(1) -; CHECK-P7-NEXT: mtlr 0 +; CHECK-P7-NEXT: addi r1, r1, 112 +; CHECK-P7-NEXT: ld r0, 16(r1) +; CHECK-P7-NEXT: mtlr r0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo5_fmf: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: mflr 0 -; CHECK-P8-NEXT: stdu 1, -32(1) -; CHECK-P8-NEXT: std 0, 48(1) +; CHECK-P8-NEXT: mflr r0 +; CHECK-P8-NEXT: stdu r1, -32(r1) +; CHECK-P8-NEXT: std r0, 48(r1) ; CHECK-P8-NEXT: bl sqrtf128 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi 1, 1, 32 -; CHECK-P8-NEXT: ld 0, 16(1) -; CHECK-P8-NEXT: mtlr 0 +; CHECK-P8-NEXT: addi r1, r1, 32 +; CHECK-P8-NEXT: ld r0, 16(r1) +; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo5_fmf: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtqp 2, 2 +; CHECK-P9-NEXT: xssqrtqp v2, v2 ; CHECK-P9-NEXT: blr %r = call contract reassoc ninf afn fp128 @llvm.sqrt.f128(fp128 %a) ret fp128 %r @@ -1266,31 +1269,31 @@ define fp128 @hoo5_fmf(fp128 %a) #1 { define fp128 @hoo5_safe(fp128 %a) #1 { ; CHECK-P7-LABEL: hoo5_safe: ; CHECK-P7: # %bb.0: -; CHECK-P7-NEXT: mflr 0 -; CHECK-P7-NEXT: stdu 1, -112(1) -; CHECK-P7-NEXT: std 0, 128(1) +; CHECK-P7-NEXT: mflr r0 +; CHECK-P7-NEXT: stdu r1, -112(r1) +; CHECK-P7-NEXT: std r0, 128(r1) ; CHECK-P7-NEXT: bl sqrtf128 ; CHECK-P7-NEXT: nop -; CHECK-P7-NEXT: addi 1, 1, 112 -; CHECK-P7-NEXT: ld 0, 16(1) -; CHECK-P7-NEXT: mtlr 0 +; CHECK-P7-NEXT: addi r1, r1, 112 +; CHECK-P7-NEXT: ld r0, 16(r1) +; CHECK-P7-NEXT: mtlr r0 ; CHECK-P7-NEXT: blr ; ; CHECK-P8-LABEL: hoo5_safe: ; CHECK-P8: # %bb.0: -; CHECK-P8-NEXT: mflr 0 -; CHECK-P8-NEXT: stdu 1, -32(1) -; CHECK-P8-NEXT: std 0, 48(1) +; CHECK-P8-NEXT: mflr r0 +; CHECK-P8-NEXT: stdu r1, -32(r1) +; CHECK-P8-NEXT: std r0, 48(r1) ; CHECK-P8-NEXT: bl sqrtf128 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: addi 1, 1, 32 -; CHECK-P8-NEXT: ld 0, 16(1) -; CHECK-P8-NEXT: mtlr 0 +; CHECK-P8-NEXT: addi r1, r1, 32 +; CHECK-P8-NEXT: ld r0, 16(r1) +; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr ; ; CHECK-P9-LABEL: hoo5_safe: ; CHECK-P9: # %bb.0: -; CHECK-P9-NEXT: xssqrtqp 2, 2 +; CHECK-P9-NEXT: xssqrtqp v2, v2 ; CHECK-P9-NEXT: blr %r = call fp128 @llvm.sqrt.f128(fp128 %a) ret fp128 %r diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll index 1c3ac17666e2..5ebfec68695f 100644 --- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll +++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll @@ -1,12 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true | FileCheck %s +; RUN: llc < %s -ppc-gpr-icmps=all -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -ppc-convert-rr-to-ri=true \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr | FileCheck %s define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_clear: ; CHECK: # %bb.0: -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: srwi 3, 3, 5 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr %a = icmp eq i32 %P, 0 %b = icmp eq i32 %Q, 0 @@ -17,9 +18,9 @@ define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_clear: ; CHECK: # %bb.0: -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 -; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: rlwinm r3, r3, 1, 31, 31 +; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr %a = icmp sgt i32 %P, -1 %b = icmp sgt i32 %Q, -1 @@ -30,11 +31,11 @@ define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @all_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_set: ; CHECK: # %bb.0: -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: li 4, -1 -; CHECK-NEXT: xor 3, 3, 4 -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: srwi 3, 3, 5 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: li r4, -1 +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr %a = icmp eq i32 %P, -1 %b = icmp eq i32 %Q, -1 @@ -45,8 +46,8 @@ define zeroext i1 @all_bits_set(i32 %P, i32 %Q) { define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_set: ; CHECK: # %bb.0: -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: rlwinm r3, r3, 1, 31, 31 ; CHECK-NEXT: blr %a = icmp slt i32 %P, 0 %b = icmp slt i32 %Q, 0 @@ -57,10 +58,10 @@ define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_set: ; CHECK: # %bb.0: -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: srwi 3, 3, 5 -; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr %a = icmp ne i32 %P, 0 %b = icmp ne i32 %Q, 0 @@ -71,8 +72,8 @@ define zeroext i1 @any_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_set: ; CHECK: # %bb.0: -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: rlwinm r3, r3, 1, 31, 31 ; CHECK-NEXT: blr %a = icmp slt i32 %P, 0 %b = icmp slt i32 %Q, 0 @@ -83,12 +84,12 @@ define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) { define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_clear: ; CHECK: # %bb.0: -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: li 4, -1 -; CHECK-NEXT: xor 3, 3, 4 -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: srwi 3, 3, 5 -; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: li r4, -1 +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr %a = icmp ne i32 %P, -1 %b = icmp ne i32 %Q, -1 @@ -99,9 +100,9 @@ define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) { define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_clear: ; CHECK: # %bb.0: -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: rlwinm 3, 3, 1, 31, 31 -; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: rlwinm r3, r3, 1, 31, 31 +; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr %a = icmp sgt i32 %P, -1 %b = icmp sgt i32 %Q, -1 @@ -113,13 +114,13 @@ define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) { define i32 @all_bits_clear_branch(ptr %P, ptr %Q) { ; CHECK-LABEL: all_bits_clear_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: or. 3, 3, 4 -; CHECK-NEXT: bne 0, .LBB8_2 +; CHECK-NEXT: or. r3, r3, r4 +; CHECK-NEXT: bne cr0, .LBB8_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB8_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp eq ptr %P, null @@ -137,14 +138,14 @@ return: define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_clear_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: cmpwi 3, 0 -; CHECK-NEXT: blt 0, .LBB9_2 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: cmpwi r3, 0 +; CHECK-NEXT: blt cr0, .LBB9_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB9_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp sgt i32 %P, -1 @@ -162,14 +163,14 @@ return: define i32 @all_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_bits_set_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: bne 0, .LBB10_2 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: cmpwi r3, -1 +; CHECK-NEXT: bne cr0, .LBB10_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB10_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp eq i32 %P, -1 @@ -187,14 +188,14 @@ return: define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: all_sign_bits_set_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: bgt 0, .LBB11_2 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: cmpwi r3, -1 +; CHECK-NEXT: bgt cr0, .LBB11_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB11_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp slt i32 %P, 0 @@ -213,13 +214,13 @@ return: define i32 @any_bits_set_branch(ptr %P, ptr %Q) { ; CHECK-LABEL: any_bits_set_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: or. 3, 3, 4 -; CHECK-NEXT: beq 0, .LBB12_2 +; CHECK-NEXT: or. r3, r3, r4 +; CHECK-NEXT: beq cr0, .LBB12_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB12_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp ne ptr %P, null @@ -237,14 +238,14 @@ return: define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_set_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: bgt 0, .LBB13_2 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: cmpwi r3, -1 +; CHECK-NEXT: bgt cr0, .LBB13_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB13_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp slt i32 %P, 0 @@ -262,14 +263,14 @@ return: define i32 @any_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_bits_clear_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: beq 0, .LBB14_2 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: cmpwi r3, -1 +; CHECK-NEXT: beq cr0, .LBB14_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB14_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp ne i32 %P, -1 @@ -287,14 +288,14 @@ return: define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) { ; CHECK-LABEL: any_sign_bits_clear_branch: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: and 3, 3, 4 -; CHECK-NEXT: cmpwi 3, 0 -; CHECK-NEXT: blt 0, .LBB15_2 +; CHECK-NEXT: and r3, r3, r4 +; CHECK-NEXT: cmpwi r3, 0 +; CHECK-NEXT: blt cr0, .LBB15_2 ; CHECK-NEXT: # %bb.1: # %bb1 -; CHECK-NEXT: li 3, 4 +; CHECK-NEXT: li r3, 4 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB15_2: # %return -; CHECK-NEXT: li 3, 192 +; CHECK-NEXT: li r3, 192 ; CHECK-NEXT: blr entry: %a = icmp sgt i32 %P, -1 @@ -312,9 +313,9 @@ return: define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_bits_clear_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxlor 34, 34, 35 -; CHECK-NEXT: xxlxor 35, 35, 35 -; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: xxlor v2, v2, v3 +; CHECK-NEXT: xxlxor v3, v3, v3 +; CHECK-NEXT: vcmpequw v2, v2, v3 ; CHECK-NEXT: blr %a = icmp eq <4 x i32> %P, zeroinitializer %b = icmp eq <4 x i32> %Q, zeroinitializer @@ -325,9 +326,9 @@ define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_sign_bits_clear_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxlor 34, 34, 35 -; CHECK-NEXT: xxleqv 35, 35, 35 -; CHECK-NEXT: vcmpgtsw 2, 2, 3 +; CHECK-NEXT: xxlor v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vcmpgtsw v2, v2, v3 ; CHECK-NEXT: blr %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -338,9 +339,9 @@ define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_bits_set_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxland 34, 34, 35 -; CHECK-NEXT: xxleqv 35, 35, 35 -; CHECK-NEXT: vcmpequw 2, 2, 3 +; CHECK-NEXT: xxland v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vcmpequw v2, v2, v3 ; CHECK-NEXT: blr %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -351,9 +352,9 @@ define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: all_sign_bits_set_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxland 34, 34, 35 -; CHECK-NEXT: xxlxor 35, 35, 35 -; CHECK-NEXT: vcmpgtsw 2, 3, 2 +; CHECK-NEXT: xxland v2, v2, v3 +; CHECK-NEXT: xxlxor v3, v3, v3 +; CHECK-NEXT: vcmpgtsw v2, v3, v2 ; CHECK-NEXT: blr %a = icmp slt <4 x i32> %P, zeroinitializer %b = icmp slt <4 x i32> %Q, zeroinitializer @@ -364,10 +365,10 @@ define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_bits_set_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxlor 34, 34, 35 -; CHECK-NEXT: xxlxor 35, 35, 35 -; CHECK-NEXT: vcmpequw 2, 2, 3 -; CHECK-NEXT: xxlnor 34, 34, 34 +; CHECK-NEXT: xxlor v2, v2, v3 +; CHECK-NEXT: xxlxor v3, v3, v3 +; CHECK-NEXT: vcmpequw v2, v2, v3 +; CHECK-NEXT: xxlnor v2, v2, v2 ; CHECK-NEXT: blr %a = icmp ne <4 x i32> %P, zeroinitializer %b = icmp ne <4 x i32> %Q, zeroinitializer @@ -378,9 +379,9 @@ define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_sign_bits_set_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxlor 34, 34, 35 -; CHECK-NEXT: xxlxor 35, 35, 35 -; CHECK-NEXT: vcmpgtsw 2, 3, 2 +; CHECK-NEXT: xxlor v2, v2, v3 +; CHECK-NEXT: xxlxor v3, v3, v3 +; CHECK-NEXT: vcmpgtsw v2, v3, v2 ; CHECK-NEXT: blr %a = icmp slt <4 x i32> %P, zeroinitializer %b = icmp slt <4 x i32> %Q, zeroinitializer @@ -391,10 +392,10 @@ define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_bits_clear_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxland 34, 34, 35 -; CHECK-NEXT: xxleqv 35, 35, 35 -; CHECK-NEXT: vcmpequw 2, 2, 3 -; CHECK-NEXT: xxlnor 34, 34, 34 +; CHECK-NEXT: xxland v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vcmpequw v2, v2, v3 +; CHECK-NEXT: xxlnor v2, v2, v2 ; CHECK-NEXT: blr %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -405,9 +406,9 @@ define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { ; CHECK-LABEL: any_sign_bits_clear_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: xxland 34, 34, 35 -; CHECK-NEXT: xxleqv 35, 35, 35 -; CHECK-NEXT: vcmpgtsw 2, 2, 3 +; CHECK-NEXT: xxland v2, v2, v3 +; CHECK-NEXT: xxleqv v3, v3, v3 +; CHECK-NEXT: vcmpgtsw v2, v2, v3 ; CHECK-NEXT: blr %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1> %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -418,11 +419,11 @@ define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) { define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { ; CHECK-LABEL: ne_neg1_and_ne_zero: ; CHECK: # %bb.0: -; CHECK-NEXT: addi 3, 3, 1 -; CHECK-NEXT: li 4, 1 -; CHECK-NEXT: subfic 3, 3, 1 -; CHECK-NEXT: subfe 3, 4, 4 -; CHECK-NEXT: neg 3, 3 +; CHECK-NEXT: addi r3, r3, 1 +; CHECK-NEXT: li r4, 1 +; CHECK-NEXT: subfic r3, r3, 1 +; CHECK-NEXT: subfe r3, r4, r4 +; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: blr %cmp1 = icmp ne i64 %x, -1 %cmp2 = icmp ne i64 %x, 0 @@ -435,11 +436,11 @@ define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) { define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) { ; CHECK-LABEL: and_eq: ; CHECK: # %bb.0: -; CHECK-NEXT: xor 3, 3, 4 -; CHECK-NEXT: xor 4, 5, 6 -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: srwi 3, 3, 5 +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: xor r4, r5, r6 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 ; CHECK-NEXT: blr %cmp1 = icmp eq i16 %a, %b %cmp2 = icmp eq i16 %c, %d @@ -450,12 +451,12 @@ define zeroext i1 @and_eq(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 z define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: or_ne: ; CHECK: # %bb.0: -; CHECK-NEXT: xor 3, 3, 4 -; CHECK-NEXT: xor 4, 5, 6 -; CHECK-NEXT: or 3, 3, 4 -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: srwi 3, 3, 5 -; CHECK-NEXT: xori 3, 3, 1 +; CHECK-NEXT: xor r3, r3, r4 +; CHECK-NEXT: xor r4, r5, r6 +; CHECK-NEXT: or r3, r3, r4 +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: srwi r3, r3, 5 +; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: blr %cmp1 = icmp ne i32 %a, %b %cmp2 = icmp ne i32 %c, %d @@ -468,9 +469,9 @@ define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) { define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { ; CHECK-LABEL: and_eq_vec: ; CHECK: # %bb.0: -; CHECK-NEXT: vcmpequw 2, 2, 3 -; CHECK-NEXT: vcmpequw 3, 4, 5 -; CHECK-NEXT: xxland 34, 34, 35 +; CHECK-NEXT: vcmpequw v2, v2, v3 +; CHECK-NEXT: vcmpequw v3, v4, v5 +; CHECK-NEXT: xxland v2, v2, v3 ; CHECK-NEXT: blr %cmp1 = icmp eq <4 x i32> %a, %b %cmp2 = icmp eq <4 x i32> %c, %d @@ -481,11 +482,11 @@ define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> define i1 @or_icmps_const_1bit_diff(i64 %x) { ; CHECK-LABEL: or_icmps_const_1bit_diff: ; CHECK: # %bb.0: -; CHECK-NEXT: addi 3, 3, -13 -; CHECK-NEXT: rldicl 3, 3, 61, 1 -; CHECK-NEXT: rotldi 3, 3, 3 -; CHECK-NEXT: cntlzd 3, 3 -; CHECK-NEXT: rldicl 3, 3, 58, 63 +; CHECK-NEXT: addi r3, r3, -13 +; CHECK-NEXT: rldicl r3, r3, 61, 1 +; CHECK-NEXT: rotldi r3, r3, 3 +; CHECK-NEXT: cntlzd r3, r3 +; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: blr %a = icmp eq i64 %x, 17 %b = icmp eq i64 %x, 13 @@ -496,11 +497,11 @@ define i1 @or_icmps_const_1bit_diff(i64 %x) { define i1 @and_icmps_const_1bit_diff(i32 %x) { ; CHECK-LABEL: and_icmps_const_1bit_diff: ; CHECK: # %bb.0: -; CHECK-NEXT: addi 3, 3, -4625 -; CHECK-NEXT: rlwinm 3, 3, 0, 28, 26 -; CHECK-NEXT: cntlzw 3, 3 -; CHECK-NEXT: not 3, 3 -; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 +; CHECK-NEXT: addi r3, r3, -4625 +; CHECK-NEXT: rlwinm r3, r3, 0, 28, 26 +; CHECK-NEXT: cntlzw r3, r3 +; CHECK-NEXT: not r3, r3 +; CHECK-NEXT: rlwinm r3, r3, 27, 31, 31 ; CHECK-NEXT: blr %a = icmp ne i32 %x, 4625 %b = icmp ne i32 %x, 4641 diff --git a/llvm/test/CodeGen/PowerPC/tls-picgot.ll b/llvm/test/CodeGen/PowerPC/tls-picgot.ll new file mode 100644 index 000000000000..6562d864d1ba --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/tls-picgot.ll @@ -0,0 +1,31 @@ +; RUN: llc -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s + +target triple = "powerpc-unknown-linux-gnu" + +; Test that LR is preserved when PPC32PICGOT clobbers it with a local "bl". + +@TLS = external thread_local global i8 + +; CHECK-LABEL: tls_addr: +; CHECK: mflr [[SAVED_REG:[0-9]+]] + +; CHECK: bl [[JUMP:\.L[[:alnum:]_]+]] +; CHECK-NEXT: [[OFFSET:\.L[[:alnum:]_]+]]: +; CHECK-NEXT: .long _GLOBAL_OFFSET_TABLE_-[[OFFSET]] +; CHECK-NEXT: [[JUMP]] +; CHECK-NEXT: mflr {{[0-9]+}} + +; CHECK: mtlr [[SAVED_REG]] +; CHECK-NEXT: blr + +define ptr @tls_addr() unnamed_addr { + %1 = call ptr @llvm.threadlocal.address.p0(ptr @TLS) + ret ptr %1 +} + +declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 8, !"PIC Level", i32 2} +!1 = !{i32 7, !"PIE Level", i32 2} diff --git a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll index 43cbc62e0bb1..56382092dc8e 100644 --- a/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll +++ b/llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll @@ -1,54 +1,58 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 < %s | FileCheck %s --check-prefix=PWR5 -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 < %s | FileCheck %s --check-prefix=PWR6 -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=PWR7 -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix=PWR8 -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s --check-prefix=PWR9 - +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr5 \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=PWR5 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=PWR6 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=PWR7 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=PWR8 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 \ +; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=PWR9 define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_1_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vaddubm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequb 2, 2, 3 -; PWR5-NEXT: vnot 2, 2 +; PWR5-NEXT: vspltisb v3, -1 +; PWR5-NEXT: vaddubm v3, v2, v3 +; PWR5-NEXT: vand v2, v2, v3 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: vcmpequb v2, v2, v3 +; PWR5-NEXT: vnot v2, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_1_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: vspltisb 3, -1 -; PWR6-NEXT: vaddubm 3, 2, 3 -; PWR6-NEXT: vand 2, 2, 3 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: vcmpequb 2, 2, 3 -; PWR6-NEXT: vnot 2, 2 +; PWR6-NEXT: vspltisb v3, -1 +; PWR6-NEXT: vaddubm v3, v2, v3 +; PWR6-NEXT: vand v2, v2, v3 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: vcmpequb v2, v2, v3 +; PWR6-NEXT: vnot v2, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_1_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, -1 -; PWR7-NEXT: vaddubm 3, 2, 3 -; PWR7-NEXT: xxland 34, 34, 35 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: vcmpequb 2, 2, 3 -; PWR7-NEXT: xxlnor 34, 34, 34 +; PWR7-NEXT: vspltisb v3, -1 +; PWR7-NEXT: vaddubm v3, v2, v3 +; PWR7-NEXT: xxland v2, v2, v3 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: vcmpequb v2, v2, v3 +; PWR7-NEXT: xxlnor v2, v2, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_1_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 1 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 2, 3 +; PWR8-NEXT: vspltisb v3, 1 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_1_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 1 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 1 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ugt <16 x i8> %2, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> @@ -59,43 +63,43 @@ define <16 x i8> @ugt_1_v16i8(<16 x i8> %0) { define <16 x i8> @ult_2_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_2_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vaddubm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequb 2, 2, 3 +; PWR5-NEXT: vspltisb v3, -1 +; PWR5-NEXT: vaddubm v3, v2, v3 +; PWR5-NEXT: vand v2, v2, v3 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: vcmpequb v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_2_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: vspltisb 3, -1 -; PWR6-NEXT: vaddubm 3, 2, 3 -; PWR6-NEXT: vand 2, 2, 3 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: vcmpequb 2, 2, 3 +; PWR6-NEXT: vspltisb v3, -1 +; PWR6-NEXT: vaddubm v3, v2, v3 +; PWR6-NEXT: vand v2, v2, v3 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: vcmpequb v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_2_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, -1 -; PWR7-NEXT: vaddubm 3, 2, 3 -; PWR7-NEXT: xxland 34, 34, 35 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: vcmpequb 2, 2, 3 +; PWR7-NEXT: vspltisb v3, -1 +; PWR7-NEXT: vaddubm v3, v2, v3 +; PWR7-NEXT: xxland v2, v2, v3 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: vcmpequb v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_2_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 2 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 3, 2 +; PWR8-NEXT: vspltisb v3, 2 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_2_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 2 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 2 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ult <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> @@ -106,91 +110,91 @@ define <16 x i8> @ult_2_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_2_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI2_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI2_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 5 +; PWR5-NEXT: addis r3, r2, .LCPI2_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI2_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI2_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI2_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v2, v5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_2_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI2_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI2_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 2, 5 +; PWR6-NEXT: addis r3, r2, .LCPI2_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI2_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI2_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI2_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v2, v5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_2_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI2_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI2_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI2_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: xxland 35, 34, 0 -; PWR7-NEXT: vsrb 2, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: vaddubm 2, 3, 2 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 2, 4 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI2_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI2_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI2_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI2_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: xxland v3, v2, vs0 +; PWR7-NEXT: vsrb v2, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: vaddubm v2, v3, v2 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_2_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 2 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 2, 3 +; PWR8-NEXT: vspltisb v3, 2 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_2_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 2 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 2 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ugt <16 x i8> %2, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> @@ -201,94 +205,94 @@ define <16 x i8> @ugt_2_v16i8(<16 x i8> %0) { define <16 x i8> @ult_3_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_3_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI3_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI3_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 3 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI3_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI3_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI3_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 3 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_3_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI3_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI3_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 3 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI3_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI3_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI3_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 3 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_3_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI3_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI3_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI3_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 3 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 1, 2 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI3_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI3_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI3_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI3_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 3 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v1, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_3_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 3 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 3, 2 +; PWR8-NEXT: vspltisb v3, 3 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_3_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 3 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 3 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ult <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> @@ -299,94 +303,94 @@ define <16 x i8> @ult_3_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_3_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI4_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI4_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 3 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI4_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI4_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI4_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI4_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 3 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_3_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI4_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI4_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 3 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI4_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI4_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI4_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI4_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 3 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_3_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI4_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI4_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI4_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI4_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 3 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 2, 1 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI4_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI4_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI4_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI4_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 3 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v2, v1 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_3_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 3 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 2, 3 +; PWR8-NEXT: vspltisb v3, 3 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_3_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 3 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 3 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ugt <16 x i8> %2, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> @@ -397,91 +401,91 @@ define <16 x i8> @ugt_3_v16i8(<16 x i8> %0) { define <16 x i8> @ult_4_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_4_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI5_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI5_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vcmpgtub 2, 4, 2 +; PWR5-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI5_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI5_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI5_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vcmpgtub v2, v4, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_4_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI5_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI5_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vcmpgtub 2, 4, 2 +; PWR6-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI5_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI5_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI5_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vcmpgtub v2, v4, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_4_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI5_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI5_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI5_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI5_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 5, 2 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI5_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI5_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI5_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v5, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_4_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 4 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 3, 2 +; PWR8-NEXT: vspltisb v3, 4 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_4_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 4 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 4 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ult <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> @@ -492,91 +496,91 @@ define <16 x i8> @ult_4_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_4_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI6_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI6_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vcmpgtub 2, 2, 4 +; PWR5-NEXT: addis r3, r2, .LCPI6_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI6_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI6_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI6_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vcmpgtub v2, v2, v4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_4_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI6_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI6_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vcmpgtub 2, 2, 4 +; PWR6-NEXT: addis r3, r2, .LCPI6_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI6_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI6_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI6_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vcmpgtub v2, v2, v4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_4_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI6_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI6_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI6_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI6_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 2, 5 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI6_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI6_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI6_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI6_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v2, v5 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_4_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 4 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 2, 3 +; PWR8-NEXT: vspltisb v3, 4 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_4_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 4 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 4 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ugt <16 x i8> %2, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> @@ -587,94 +591,94 @@ define <16 x i8> @ugt_4_v16i8(<16 x i8> %0) { define <16 x i8> @ult_5_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_5_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI7_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI7_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI7_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI7_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI7_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_5_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI7_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI7_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI7_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI7_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI7_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_5_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI7_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI7_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI7_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 5 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 1, 2 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI7_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI7_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI7_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI7_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 5 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v1, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_5_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 5 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 3, 2 +; PWR8-NEXT: vspltisb v3, 5 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_5_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 5 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 5 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ult <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> @@ -685,94 +689,94 @@ define <16 x i8> @ult_5_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_5_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI8_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI8_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI8_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI8_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI8_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI8_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI8_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_5_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI8_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI8_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI8_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI8_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI8_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI8_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI8_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_5_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI8_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI8_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI8_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI8_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 5 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 2, 1 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI8_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI8_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI8_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI8_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 5 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v2, v1 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_5_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 5 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 2, 3 +; PWR8-NEXT: vspltisb v3, 5 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_5_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 5 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 5 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ugt <16 x i8> %2, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> @@ -783,94 +787,94 @@ define <16 x i8> @ugt_5_v16i8(<16 x i8> %0) { define <16 x i8> @ult_6_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_6_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI9_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI9_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 6 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI9_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI9_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI9_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI9_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 6 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_6_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI9_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI9_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 6 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI9_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI9_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI9_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI9_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 6 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_6_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI9_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI9_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI9_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI9_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 6 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 1, 2 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI9_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI9_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI9_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI9_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 6 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v1, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_6_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 6 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 3, 2 +; PWR8-NEXT: vspltisb v3, 6 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_6_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 6 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 6 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ult <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6> @@ -881,94 +885,94 @@ define <16 x i8> @ult_6_v16i8(<16 x i8> %0) { define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ugt_6_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI10_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI10_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 6 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI10_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI10_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI10_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 6 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_6_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI10_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI10_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 6 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI10_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI10_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI10_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 6 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_6_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI10_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI10_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI10_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI10_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 6 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 2, 1 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI10_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI10_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI10_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI10_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 6 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v2, v1 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_6_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 6 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 2, 3 +; PWR8-NEXT: vspltisb v3, 6 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_6_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 6 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 6 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ugt <16 x i8> %2, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6> @@ -979,94 +983,94 @@ define <16 x i8> @ugt_6_v16i8(<16 x i8> %0) { define <16 x i8> @ult_7_v16i8(<16 x i8> %0) { ; PWR5-LABEL: ult_7_v16i8: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI11_0@toc@ha -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI11_0@toc@l -; PWR5-NEXT: vsrb 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI11_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI11_1@toc@l -; PWR5-NEXT: vspltisb 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsububm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrb 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 4 -; PWR5-NEXT: vaddubm 2, 3, 2 -; PWR5-NEXT: vsrb 3, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vaddubm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 7 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vcmpgtub 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI11_0@toc@ha +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI11_0@toc@l +; PWR5-NEXT: vsrb v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI11_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI11_1@toc@l +; PWR5-NEXT: vspltisb v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsububm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrb v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 4 +; PWR5-NEXT: vaddubm v2, v3, v2 +; PWR5-NEXT: vsrb v3, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vaddubm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 7 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vcmpgtub v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_7_v16i8: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI11_0@toc@ha -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI11_0@toc@l -; PWR6-NEXT: vsrb 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI11_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI11_1@toc@l -; PWR6-NEXT: vspltisb 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsububm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrb 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 4 -; PWR6-NEXT: vaddubm 2, 3, 2 -; PWR6-NEXT: vsrb 3, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vaddubm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 7 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vcmpgtub 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI11_0@toc@ha +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI11_0@toc@l +; PWR6-NEXT: vsrb v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI11_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI11_1@toc@l +; PWR6-NEXT: vspltisb v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsububm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrb v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 4 +; PWR6-NEXT: vaddubm v2, v3, v2 +; PWR6-NEXT: vsrb v3, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vaddubm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 7 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vcmpgtub v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_7_v16i8: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI11_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI11_0@toc@l -; PWR7-NEXT: vspltisb 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI11_1@toc@ha -; PWR7-NEXT: vspltisb 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI11_1@toc@l -; PWR7-NEXT: vsrb 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 7 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsububm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: vsrb 3, 2, 5 -; PWR7-NEXT: vaddubm 2, 2, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vcmpgtub 2, 1, 2 +; PWR7-NEXT: vspltisb v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI11_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI11_0@toc@l +; PWR7-NEXT: vspltisb v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI11_1@toc@ha +; PWR7-NEXT: vspltisb v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI11_1@toc@l +; PWR7-NEXT: vsrb v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 7 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsububm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: vsrb v3, v2, v5 +; PWR7-NEXT: vaddubm v2, v2, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vcmpgtub v2, v1, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_7_v16i8: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisb 3, 7 -; PWR8-NEXT: vpopcntb 2, 2 -; PWR8-NEXT: vcmpgtub 2, 3, 2 +; PWR8-NEXT: vspltisb v3, 7 +; PWR8-NEXT: vpopcntb v2, v2 +; PWR8-NEXT: vcmpgtub v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_7_v16i8: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 7 -; PWR9-NEXT: vpopcntb 2, 2 -; PWR9-NEXT: vcmpgtub 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 7 +; PWR9-NEXT: vpopcntb v2, v2 +; PWR9-NEXT: vcmpgtub v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %0) %3 = icmp ult <16 x i8> %2, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> @@ -1077,46 +1081,46 @@ define <16 x i8> @ult_7_v16i8(<16 x i8> %0) { define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_1_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduhm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequh 2, 2, 3 -; PWR5-NEXT: vnot 2, 2 +; PWR5-NEXT: vspltisb v3, -1 +; PWR5-NEXT: vadduhm v3, v2, v3 +; PWR5-NEXT: vand v2, v2, v3 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: vcmpequh v2, v2, v3 +; PWR5-NEXT: vnot v2, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_1_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: vspltisb 3, -1 -; PWR6-NEXT: vadduhm 3, 2, 3 -; PWR6-NEXT: vand 2, 2, 3 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: vcmpequh 2, 2, 3 -; PWR6-NEXT: vnot 2, 2 +; PWR6-NEXT: vspltisb v3, -1 +; PWR6-NEXT: vadduhm v3, v2, v3 +; PWR6-NEXT: vand v2, v2, v3 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: vcmpequh v2, v2, v3 +; PWR6-NEXT: vnot v2, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_1_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, -1 -; PWR7-NEXT: vadduhm 3, 2, 3 -; PWR7-NEXT: xxland 34, 34, 35 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: vcmpequh 2, 2, 3 -; PWR7-NEXT: xxlnor 34, 34, 34 +; PWR7-NEXT: vspltisb v3, -1 +; PWR7-NEXT: vadduhm v3, v2, v3 +; PWR7-NEXT: xxland v2, v2, v3 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: vcmpequh v2, v2, v3 +; PWR7-NEXT: xxlnor v2, v2, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_1_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 1 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 1 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_1_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 1 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 1 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> @@ -1127,43 +1131,43 @@ define <8 x i16> @ugt_1_v8i16(<8 x i16> %0) { define <8 x i16> @ult_2_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_2_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduhm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequh 2, 2, 3 +; PWR5-NEXT: vspltisb v3, -1 +; PWR5-NEXT: vadduhm v3, v2, v3 +; PWR5-NEXT: vand v2, v2, v3 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: vcmpequh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_2_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: vspltisb 3, -1 -; PWR6-NEXT: vadduhm 3, 2, 3 -; PWR6-NEXT: vand 2, 2, 3 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: vcmpequh 2, 2, 3 +; PWR6-NEXT: vspltisb v3, -1 +; PWR6-NEXT: vadduhm v3, v2, v3 +; PWR6-NEXT: vand v2, v2, v3 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: vcmpequh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_2_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, -1 -; PWR7-NEXT: vadduhm 3, 2, 3 -; PWR7-NEXT: xxland 34, 34, 35 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: vcmpequh 2, 2, 3 +; PWR7-NEXT: vspltisb v3, -1 +; PWR7-NEXT: vadduhm v3, v2, v3 +; PWR7-NEXT: xxland v2, v2, v3 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: vcmpequh v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_2_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 2 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 2 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_2_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 2 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 2 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> @@ -1174,106 +1178,106 @@ define <8 x i16> @ult_2_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_2_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; PWR5-NEXT: vspltish 3, 1 -; PWR5-NEXT: addi 3, 3, .LCPI14_0@toc@l -; PWR5-NEXT: vsrh 3, 2, 3 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI14_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI14_1@toc@l -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vand 3, 3, 4 -; PWR5-NEXT: lvx 4, 0, 3 -; PWR5-NEXT: vsubuhm 2, 2, 3 -; PWR5-NEXT: vand 3, 2, 4 -; PWR5-NEXT: vsrh 2, 2, 5 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vadduhm 2, 3, 2 -; PWR5-NEXT: vspltish 3, 4 -; PWR5-NEXT: vsrh 3, 2, 3 -; PWR5-NEXT: vadduhm 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 15 -; PWR5-NEXT: vxor 4, 4, 4 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vspltisb 3, 1 -; PWR5-NEXT: vmladduhm 2, 2, 3, 4 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 5 +; PWR5-NEXT: addis r3, r2, .LCPI14_0@toc@ha +; PWR5-NEXT: vspltish v3, 1 +; PWR5-NEXT: addi r3, r3, .LCPI14_0@toc@l +; PWR5-NEXT: vsrh v3, v2, v3 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI14_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI14_1@toc@l +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vand v3, v3, v4 +; PWR5-NEXT: lvx v4, 0, r3 +; PWR5-NEXT: vsubuhm v2, v2, v3 +; PWR5-NEXT: vand v3, v2, v4 +; PWR5-NEXT: vsrh v2, v2, v5 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vadduhm v2, v3, v2 +; PWR5-NEXT: vspltish v3, 4 +; PWR5-NEXT: vsrh v3, v2, v3 +; PWR5-NEXT: vadduhm v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 15 +; PWR5-NEXT: vxor v4, v4, v4 +; PWR5-NEXT: vand v2, v2, v3 +; PWR5-NEXT: vspltisb v3, 1 +; PWR5-NEXT: vmladduhm v2, v2, v3, v4 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vcmpgtuh v2, v2, v5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_2_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; PWR6-NEXT: vspltish 3, 1 -; PWR6-NEXT: addi 3, 3, .LCPI14_0@toc@l -; PWR6-NEXT: vsrh 3, 2, 3 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI14_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI14_1@toc@l -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vand 3, 3, 4 -; PWR6-NEXT: lvx 4, 0, 3 -; PWR6-NEXT: vsubuhm 2, 2, 3 -; PWR6-NEXT: vand 3, 2, 4 -; PWR6-NEXT: vsrh 2, 2, 5 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vadduhm 2, 3, 2 -; PWR6-NEXT: vspltish 3, 4 -; PWR6-NEXT: vsrh 3, 2, 3 -; PWR6-NEXT: vadduhm 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 15 -; PWR6-NEXT: vxor 4, 4, 4 -; PWR6-NEXT: vand 2, 2, 3 -; PWR6-NEXT: vspltisb 3, 1 -; PWR6-NEXT: vmladduhm 2, 2, 3, 4 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vcmpgtuh 2, 2, 5 +; PWR6-NEXT: addis r3, r2, .LCPI14_0@toc@ha +; PWR6-NEXT: vspltish v3, 1 +; PWR6-NEXT: addi r3, r3, .LCPI14_0@toc@l +; PWR6-NEXT: vsrh v3, v2, v3 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI14_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI14_1@toc@l +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vand v3, v3, v4 +; PWR6-NEXT: lvx v4, 0, r3 +; PWR6-NEXT: vsubuhm v2, v2, v3 +; PWR6-NEXT: vand v3, v2, v4 +; PWR6-NEXT: vsrh v2, v2, v5 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vadduhm v2, v3, v2 +; PWR6-NEXT: vspltish v3, 4 +; PWR6-NEXT: vsrh v3, v2, v3 +; PWR6-NEXT: vadduhm v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 15 +; PWR6-NEXT: vxor v4, v4, v4 +; PWR6-NEXT: vand v2, v2, v3 +; PWR6-NEXT: vspltisb v3, 1 +; PWR6-NEXT: vmladduhm v2, v2, v3, v4 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vcmpgtuh v2, v2, v5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_2_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI14_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI14_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI14_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI14_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: xxland 35, 34, 0 -; PWR7-NEXT: vsrh 2, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: vadduhm 2, 3, 2 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 4 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI14_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI14_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI14_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI14_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: xxland v3, v2, vs0 +; PWR7-NEXT: vsrh v2, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: vadduhm v2, v3, v2 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_2_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 2 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 2 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_2_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 2 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 2 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> @@ -1284,109 +1288,109 @@ define <8 x i16> @ugt_2_v8i16(<8 x i16> %0) { define <8 x i16> @ult_3_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_3_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI15_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI15_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI15_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 3 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI15_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI15_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI15_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI15_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 3 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_3_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI15_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI15_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI15_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 3 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI15_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI15_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI15_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI15_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 3 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_3_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI15_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI15_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI15_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI15_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 3 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI15_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI15_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI15_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI15_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 3 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_3_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 3 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 3 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_3_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 3 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 3 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> @@ -1397,109 +1401,109 @@ define <8 x i16> @ult_3_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_3_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI16_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI16_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI16_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI16_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI16_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 3 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_3_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI16_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 3 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI16_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI16_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI16_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI16_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 3 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_3_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI16_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI16_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI16_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI16_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 3 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI16_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI16_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI16_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI16_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 3 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_3_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 3 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 3 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_3_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 3 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 3 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> @@ -1510,106 +1514,106 @@ define <8 x i16> @ugt_3_v8i16(<8 x i16> %0) { define <8 x i16> @ult_4_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_4_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI17_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI17_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI17_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 5, 2 +; PWR5-NEXT: addis r3, r2, .LCPI17_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI17_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI17_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI17_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vcmpgtuh v2, v5, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_4_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI17_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI17_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI17_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vcmpgtuh 2, 5, 2 +; PWR6-NEXT: addis r3, r2, .LCPI17_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI17_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI17_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI17_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vcmpgtuh v2, v5, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_4_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI17_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI17_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI17_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI17_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 5, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI17_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI17_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI17_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI17_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v5, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_4_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 4 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 4 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_4_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 4 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 4 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> @@ -1620,106 +1624,106 @@ define <8 x i16> @ult_4_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_4_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI18_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI18_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 15 -; PWR5-NEXT: vand 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 5 +; PWR5-NEXT: addis r3, r2, .LCPI18_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI18_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI18_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI18_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 15 +; PWR5-NEXT: vand v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vcmpgtuh v2, v2, v5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_4_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI18_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI18_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 15 -; PWR6-NEXT: vand 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vcmpgtuh 2, 2, 5 +; PWR6-NEXT: addis r3, r2, .LCPI18_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI18_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI18_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI18_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 15 +; PWR6-NEXT: vand v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vcmpgtuh v2, v2, v5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_4_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI18_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI18_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI18_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI18_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 5 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI18_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI18_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI18_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI18_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v5 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_4_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 4 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 4 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_4_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 4 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 4 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> @@ -1730,109 +1734,109 @@ define <8 x i16> @ugt_4_v8i16(<8 x i16> %0) { define <8 x i16> @ult_5_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_5_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI19_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 5 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI19_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI19_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI19_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI19_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 5 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_5_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI19_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 5 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI19_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI19_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI19_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI19_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 5 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_5_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI19_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI19_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI19_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI19_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 5 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI19_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI19_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI19_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI19_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 5 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_5_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 5 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 5 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_5_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 5 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 5 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> @@ -1843,109 +1847,109 @@ define <8 x i16> @ult_5_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_5_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI20_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI20_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 5 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI20_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI20_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI20_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI20_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 5 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_5_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI20_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI20_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 5 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI20_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI20_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI20_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI20_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 5 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_5_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI20_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI20_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI20_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI20_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 5 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI20_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI20_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI20_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI20_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 5 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_5_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 5 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 5 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_5_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 5 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 5 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> @@ -1956,109 +1960,109 @@ define <8 x i16> @ugt_5_v8i16(<8 x i16> %0) { define <8 x i16> @ult_6_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_6_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 6 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI21_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI21_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI21_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI21_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 6 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_6_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 6 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI21_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI21_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI21_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI21_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 6 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_6_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI21_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI21_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI21_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI21_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 6 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI21_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI21_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI21_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI21_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 6 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_6_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 6 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 6 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_6_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 6 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 6 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6> @@ -2069,109 +2073,109 @@ define <8 x i16> @ult_6_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_6_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI22_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI22_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI22_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 6 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI22_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI22_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI22_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI22_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 6 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_6_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI22_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI22_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI22_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 6 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI22_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI22_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI22_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI22_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 6 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_6_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI22_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI22_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI22_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI22_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 6 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI22_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI22_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI22_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI22_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 6 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_6_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 6 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 6 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_6_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 6 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 6 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6> @@ -2182,109 +2186,109 @@ define <8 x i16> @ugt_6_v8i16(<8 x i16> %0) { define <8 x i16> @ult_7_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_7_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI23_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI23_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 7 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI23_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI23_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI23_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI23_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 7 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_7_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI23_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI23_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 7 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI23_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI23_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI23_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI23_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 7 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_7_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI23_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI23_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI23_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI23_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 7 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI23_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI23_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI23_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI23_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 7 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_7_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 7 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 7 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_7_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 7 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 7 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> @@ -2295,109 +2299,109 @@ define <8 x i16> @ult_7_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_7_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 7 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI24_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI24_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI24_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI24_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 7 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_7_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 7 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI24_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI24_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI24_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI24_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 7 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_7_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI24_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI24_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI24_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI24_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 7 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI24_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI24_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI24_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI24_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 7 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_7_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 7 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 7 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_7_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 7 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 7 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> @@ -2408,106 +2412,106 @@ define <8 x i16> @ugt_7_v8i16(<8 x i16> %0) { define <8 x i16> @ult_8_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_8_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI25_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI25_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI25_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI25_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI25_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI25_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_8_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI25_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI25_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI25_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI25_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI25_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI25_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_8_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI25_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI25_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI25_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI25_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 6, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI25_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI25_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI25_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI25_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v6, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_8_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 8 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 8 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_8_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 8 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 8 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> @@ -2518,106 +2522,106 @@ define <8 x i16> @ult_8_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_8_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI26_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI26_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI26_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI26_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI26_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI26_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_8_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI26_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI26_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI26_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI26_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI26_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI26_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_8_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI26_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI26_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI26_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI26_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 6 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI26_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI26_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI26_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI26_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v6 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_8_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 8 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 8 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_8_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 8 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 8 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> @@ -2628,109 +2632,109 @@ define <8 x i16> @ugt_8_v8i16(<8 x i16> %0) { define <8 x i16> @ult_9_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_9_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI27_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI27_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 9 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI27_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI27_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI27_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI27_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 9 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_9_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI27_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI27_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 9 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI27_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI27_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI27_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI27_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 9 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_9_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI27_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI27_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI27_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI27_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 9 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI27_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI27_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI27_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI27_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 9 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_9_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 9 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 9 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_9_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 9 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 9 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9> @@ -2741,109 +2745,109 @@ define <8 x i16> @ult_9_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_9_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI28_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI28_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 9 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI28_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI28_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI28_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI28_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 9 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_9_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI28_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI28_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 9 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI28_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI28_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI28_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI28_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 9 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_9_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI28_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI28_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI28_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI28_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 9 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI28_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI28_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI28_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI28_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 9 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_9_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 9 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 9 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_9_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 9 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 9 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9> @@ -2854,109 +2858,109 @@ define <8 x i16> @ugt_9_v8i16(<8 x i16> %0) { define <8 x i16> @ult_10_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_10_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI29_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI29_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 10 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI29_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI29_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI29_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI29_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 10 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_10_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI29_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI29_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 10 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI29_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI29_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI29_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI29_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 10 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_10_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI29_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI29_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI29_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI29_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 10 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI29_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI29_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI29_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI29_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 10 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_10_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 10 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 10 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_10_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 10 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 10 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10> @@ -2967,109 +2971,109 @@ define <8 x i16> @ult_10_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_10_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI30_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI30_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 10 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI30_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI30_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI30_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI30_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 10 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_10_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI30_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI30_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 10 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI30_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI30_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI30_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI30_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 10 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_10_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI30_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI30_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI30_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI30_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 10 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI30_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI30_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI30_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI30_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 10 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_10_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 10 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 10 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_10_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 10 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 10 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10> @@ -3080,109 +3084,109 @@ define <8 x i16> @ugt_10_v8i16(<8 x i16> %0) { define <8 x i16> @ult_11_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_11_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI31_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI31_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 11 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI31_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI31_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI31_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI31_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 11 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_11_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI31_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI31_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 11 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI31_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI31_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI31_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI31_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 11 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_11_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI31_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI31_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI31_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI31_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 11 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI31_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI31_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI31_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI31_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 11 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_11_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 11 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 11 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_11_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 11 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 11 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11> @@ -3193,109 +3197,109 @@ define <8 x i16> @ult_11_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_11_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI32_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI32_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI32_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 11 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI32_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI32_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI32_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI32_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 11 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_11_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI32_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI32_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI32_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 11 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI32_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI32_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI32_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI32_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 11 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_11_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI32_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI32_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI32_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 11 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI32_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI32_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI32_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI32_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 11 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_11_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 11 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 11 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_11_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 11 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 11 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11> @@ -3306,109 +3310,109 @@ define <8 x i16> @ugt_11_v8i16(<8 x i16> %0) { define <8 x i16> @ult_12_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_12_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI33_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI33_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 12 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI33_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI33_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI33_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI33_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 12 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_12_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI33_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI33_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 12 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI33_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI33_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI33_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI33_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 12 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_12_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI33_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI33_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI33_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI33_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI33_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI33_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI33_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI33_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_12_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 12 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 12 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_12_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 12 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 12 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12> @@ -3419,109 +3423,109 @@ define <8 x i16> @ult_12_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_12_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI34_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI34_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI34_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 12 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI34_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI34_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI34_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI34_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 12 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_12_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI34_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI34_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI34_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 12 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI34_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI34_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI34_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI34_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 12 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_12_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI34_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI34_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI34_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI34_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI34_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI34_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI34_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI34_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_12_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 12 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 12 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_12_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 12 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 12 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12> @@ -3532,109 +3536,109 @@ define <8 x i16> @ugt_12_v8i16(<8 x i16> %0) { define <8 x i16> @ult_13_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_13_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI35_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI35_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 13 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI35_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI35_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI35_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI35_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 13 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_13_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI35_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI35_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 13 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI35_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI35_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI35_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI35_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 13 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_13_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI35_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI35_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI35_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI35_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 13 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI35_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI35_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI35_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI35_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 13 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_13_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 13 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 13 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_13_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 13 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 13 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13> @@ -3645,109 +3649,109 @@ define <8 x i16> @ult_13_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_13_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI36_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI36_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI36_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI36_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 13 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI36_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI36_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI36_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI36_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 13 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_13_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI36_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI36_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI36_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI36_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 13 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI36_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI36_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI36_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI36_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 13 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_13_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI36_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI36_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI36_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI36_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 13 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI36_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI36_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI36_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI36_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 13 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_13_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 13 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 13 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_13_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 13 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 13 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13, i16 13> @@ -3758,109 +3762,109 @@ define <8 x i16> @ugt_13_v8i16(<8 x i16> %0) { define <8 x i16> @ult_14_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_14_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI37_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI37_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI37_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 14 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI37_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI37_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI37_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI37_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 14 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_14_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI37_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI37_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI37_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 14 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI37_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI37_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI37_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI37_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 14 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_14_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI37_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI37_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI37_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 14 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI37_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI37_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI37_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI37_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 14 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_14_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 14 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 14 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_14_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 14 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 14 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14> @@ -3871,109 +3875,109 @@ define <8 x i16> @ult_14_v8i16(<8 x i16> %0) { define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ugt_14_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI38_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI38_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI38_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 14 -; PWR5-NEXT: vcmpgtuh 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI38_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI38_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI38_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI38_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 14 +; PWR5-NEXT: vcmpgtuh v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_14_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI38_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI38_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI38_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 14 -; PWR6-NEXT: vcmpgtuh 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI38_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI38_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI38_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI38_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 14 +; PWR6-NEXT: vcmpgtuh v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_14_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI38_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI38_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI38_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI38_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 14 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 2, 7 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI38_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI38_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI38_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI38_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 14 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_14_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 14 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 2, 3 +; PWR8-NEXT: vspltish v3, 14 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_14_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 14 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 2, 3 +; PWR9-NEXT: vspltish v3, 14 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ugt <8 x i16> %2, <i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14, i16 14> @@ -3984,109 +3988,109 @@ define <8 x i16> @ugt_14_v8i16(<8 x i16> %0) { define <8 x i16> @ult_15_v8i16(<8 x i16> %0) { ; PWR5-LABEL: ult_15_v8i16: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PWR5-NEXT: vspltish 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI39_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI39_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI39_1@toc@l -; PWR5-NEXT: vsrh 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 2 -; PWR5-NEXT: vsubuhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: vspltish 5, 4 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vsrh 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduhm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vmladduhm 2, 2, 4, 3 -; PWR5-NEXT: vspltish 3, 8 -; PWR5-NEXT: vsrh 2, 2, 3 -; PWR5-NEXT: vspltish 3, 15 -; PWR5-NEXT: vcmpgtuh 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI39_0@toc@ha +; PWR5-NEXT: vspltish v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI39_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI39_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI39_1@toc@l +; PWR5-NEXT: vsrh v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 2 +; PWR5-NEXT: vsubuhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: vspltish v5, 4 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vsrh v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduhm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vmladduhm v2, v2, v4, v3 +; PWR5-NEXT: vspltish v3, 8 +; PWR5-NEXT: vsrh v2, v2, v3 +; PWR5-NEXT: vspltish v3, 15 +; PWR5-NEXT: vcmpgtuh v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_15_v8i16: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PWR6-NEXT: vspltish 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI39_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI39_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI39_1@toc@l -; PWR6-NEXT: vsrh 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 2 -; PWR6-NEXT: vsubuhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: vspltish 5, 4 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vsrh 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduhm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vmladduhm 2, 2, 4, 3 -; PWR6-NEXT: vspltish 3, 8 -; PWR6-NEXT: vsrh 2, 2, 3 -; PWR6-NEXT: vspltish 3, 15 -; PWR6-NEXT: vcmpgtuh 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI39_0@toc@ha +; PWR6-NEXT: vspltish v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI39_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI39_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI39_1@toc@l +; PWR6-NEXT: vsrh v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 2 +; PWR6-NEXT: vsubuhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: vspltish v5, 4 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vsrh v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduhm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vmladduhm v2, v2, v4, v3 +; PWR6-NEXT: vspltish v3, 8 +; PWR6-NEXT: vsrh v2, v2, v3 +; PWR6-NEXT: vspltish v3, 15 +; PWR6-NEXT: vcmpgtuh v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_15_v8i16: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltish 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI39_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI39_0@toc@l -; PWR7-NEXT: vspltish 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI39_1@toc@ha -; PWR7-NEXT: vspltish 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI39_1@toc@l -; PWR7-NEXT: vsrh 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltish 6, 8 -; PWR7-NEXT: vspltish 7, 15 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vsrh 3, 2, 5 -; PWR7-NEXT: vadduhm 2, 2, 3 -; PWR7-NEXT: vxor 3, 3, 3 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmladduhm 2, 2, 1, 3 -; PWR7-NEXT: vsrh 2, 2, 6 -; PWR7-NEXT: vcmpgtuh 2, 7, 2 +; PWR7-NEXT: vspltish v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI39_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI39_0@toc@l +; PWR7-NEXT: vspltish v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI39_1@toc@ha +; PWR7-NEXT: vspltish v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI39_1@toc@l +; PWR7-NEXT: vsrh v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltish v6, 8 +; PWR7-NEXT: vspltish v7, 15 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vsrh v3, v2, v5 +; PWR7-NEXT: vadduhm v2, v2, v3 +; PWR7-NEXT: vxor v3, v3, v3 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmladduhm v2, v2, v1, v3 +; PWR7-NEXT: vsrh v2, v2, v6 +; PWR7-NEXT: vcmpgtuh v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_15_v8i16: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltish 3, 15 -; PWR8-NEXT: vpopcnth 2, 2 -; PWR8-NEXT: vcmpgtuh 2, 3, 2 +; PWR8-NEXT: vspltish v3, 15 +; PWR8-NEXT: vpopcnth v2, v2 +; PWR8-NEXT: vcmpgtuh v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_15_v8i16: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltish 3, 15 -; PWR9-NEXT: vpopcnth 2, 2 -; PWR9-NEXT: vcmpgtuh 2, 3, 2 +; PWR9-NEXT: vspltish v3, 15 +; PWR9-NEXT: vpopcnth v2, v2 +; PWR9-NEXT: vcmpgtuh v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0) %3 = icmp ult <8 x i16> %2, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> @@ -4097,46 +4101,46 @@ define <8 x i16> @ult_15_v8i16(<8 x i16> %0) { define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_1_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduwm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequw 2, 2, 3 -; PWR5-NEXT: vnot 2, 2 +; PWR5-NEXT: vspltisb v3, -1 +; PWR5-NEXT: vadduwm v3, v2, v3 +; PWR5-NEXT: vand v2, v2, v3 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: vcmpequw v2, v2, v3 +; PWR5-NEXT: vnot v2, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_1_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: vspltisb 3, -1 -; PWR6-NEXT: vadduwm 3, 2, 3 -; PWR6-NEXT: vand 2, 2, 3 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: vcmpequw 2, 2, 3 -; PWR6-NEXT: vnot 2, 2 +; PWR6-NEXT: vspltisb v3, -1 +; PWR6-NEXT: vadduwm v3, v2, v3 +; PWR6-NEXT: vand v2, v2, v3 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: vcmpequw v2, v2, v3 +; PWR6-NEXT: vnot v2, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_1_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, -1 -; PWR7-NEXT: vadduwm 3, 2, 3 -; PWR7-NEXT: xxland 34, 34, 35 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: vcmpequw 2, 2, 3 -; PWR7-NEXT: xxlnor 34, 34, 34 +; PWR7-NEXT: vspltisb v3, -1 +; PWR7-NEXT: vadduwm v3, v2, v3 +; PWR7-NEXT: xxland v2, v2, v3 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: vcmpequw v2, v2, v3 +; PWR7-NEXT: xxlnor v2, v2, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_1_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 1 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 1 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_1_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 1 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 1 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 1, i32 1, i32 1, i32 1> @@ -4147,43 +4151,43 @@ define <4 x i32> @ugt_1_v4i32(<4 x i32> %0) { define <4 x i32> @ult_2_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_2_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: vspltisb 3, -1 -; PWR5-NEXT: vadduwm 3, 2, 3 -; PWR5-NEXT: vand 2, 2, 3 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: vcmpequw 2, 2, 3 +; PWR5-NEXT: vspltisb v3, -1 +; PWR5-NEXT: vadduwm v3, v2, v3 +; PWR5-NEXT: vand v2, v2, v3 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: vcmpequw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_2_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: vspltisb 3, -1 -; PWR6-NEXT: vadduwm 3, 2, 3 -; PWR6-NEXT: vand 2, 2, 3 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: vcmpequw 2, 2, 3 +; PWR6-NEXT: vspltisb v3, -1 +; PWR6-NEXT: vadduwm v3, v2, v3 +; PWR6-NEXT: vand v2, v2, v3 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: vcmpequw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_2_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisb 3, -1 -; PWR7-NEXT: vadduwm 3, 2, 3 -; PWR7-NEXT: xxland 34, 34, 35 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: vcmpequw 2, 2, 3 +; PWR7-NEXT: vspltisb v3, -1 +; PWR7-NEXT: vadduwm v3, v2, v3 +; PWR7-NEXT: xxland v2, v2, v3 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: vcmpequw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_2_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 2 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 2 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_2_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 2 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 2 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2> @@ -4194,124 +4198,124 @@ define <4 x i32> @ult_2_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_2_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI42_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI42_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 1, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 0 +; PWR5-NEXT: addis r3, r2, .LCPI42_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI42_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI42_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI42_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v1, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v0 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_2_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI42_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI42_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 1, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 0 +; PWR6-NEXT: addis r3, r2, .LCPI42_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI42_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI42_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI42_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v1, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v0 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_2_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI42_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI42_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI42_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: xxland 35, 34, 0 -; PWR7-NEXT: vsrw 2, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: vadduwm 2, 3, 2 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI42_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI42_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI42_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI42_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: xxland v3, v2, vs0 +; PWR7-NEXT: vsrw v2, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: vadduwm v2, v3, v2 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_2_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 2 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 2 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_2_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 2 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 2 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2> @@ -4322,127 +4326,127 @@ define <4 x i32> @ugt_2_v4i32(<4 x i32> %0) { define <4 x i32> @ult_3_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_3_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI43_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI43_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI43_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI43_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI43_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI43_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI43_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_3_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI43_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI43_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI43_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI43_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI43_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI43_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI43_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_3_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI43_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI43_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI43_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI43_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 3 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI43_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI43_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI43_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI43_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 3 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_3_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 3 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 3 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_3_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3> @@ -4453,127 +4457,127 @@ define <4 x i32> @ult_3_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_3_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI44_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI44_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI44_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI44_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI44_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI44_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI44_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_3_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI44_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI44_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI44_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI44_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI44_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI44_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI44_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_3_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI44_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI44_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI44_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI44_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 3 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI44_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI44_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI44_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI44_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 3 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_3_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 3 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 3 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_3_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 3, i32 3, i32 3, i32 3> @@ -4584,124 +4588,124 @@ define <4 x i32> @ugt_3_v4i32(<4 x i32> %0) { define <4 x i32> @ult_4_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_4_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI45_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI45_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI45_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 4, 0 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 5, 2 +; PWR5-NEXT: addis r3, r2, .LCPI45_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI45_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI45_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI45_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vspltisb v0, 15 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v0 +; PWR5-NEXT: vspltisw v0, -16 +; PWR5-NEXT: vrlw v1, v4, v0 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v0 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vcmpgtuw v2, v5, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_4_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI45_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI45_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI45_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vspltisb 0, 15 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 0 -; PWR6-NEXT: vspltisw 0, -16 -; PWR6-NEXT: vrlw 1, 4, 0 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 0 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vcmpgtuw 2, 5, 2 +; PWR6-NEXT: addis r3, r2, .LCPI45_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI45_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI45_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI45_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vspltisb v0, 15 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v0 +; PWR6-NEXT: vspltisw v0, -16 +; PWR6-NEXT: vrlw v1, v4, v0 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v0 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vcmpgtuw v2, v5, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_4_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI45_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI45_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI45_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI45_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 5, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI45_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI45_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI45_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI45_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v5, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_4_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 4 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 4 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_4_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 4 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 4 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4> @@ -4712,124 +4716,124 @@ define <4 x i32> @ult_4_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_4_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI46_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI46_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI46_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 4, 0 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 5 +; PWR5-NEXT: addis r3, r2, .LCPI46_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI46_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI46_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI46_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vspltisb v0, 15 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v0 +; PWR5-NEXT: vspltisw v0, -16 +; PWR5-NEXT: vrlw v1, v4, v0 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v0 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_4_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI46_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI46_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI46_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vspltisb 0, 15 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 0 -; PWR6-NEXT: vspltisw 0, -16 -; PWR6-NEXT: vrlw 1, 4, 0 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 0 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 5 +; PWR6-NEXT: addis r3, r2, .LCPI46_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI46_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI46_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI46_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vspltisb v0, 15 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v0 +; PWR6-NEXT: vspltisw v0, -16 +; PWR6-NEXT: vrlw v1, v4, v0 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v0 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_4_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI46_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI46_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI46_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI46_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 5 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI46_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI46_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI46_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI46_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v5 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_4_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 4 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 4 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_4_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 4 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 4 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 4, i32 4, i32 4, i32 4> @@ -4840,127 +4844,127 @@ define <4 x i32> @ugt_4_v4i32(<4 x i32> %0) { define <4 x i32> @ult_5_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_5_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI47_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI47_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI47_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI47_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI47_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI47_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_5_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI47_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI47_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI47_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI47_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI47_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI47_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_5_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI47_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI47_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI47_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 5 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI47_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI47_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI47_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI47_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 5 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_5_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 5 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 5 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_5_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 5 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 5 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5> @@ -4971,127 +4975,127 @@ define <4 x i32> @ult_5_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_5_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI48_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI48_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI48_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI48_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI48_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI48_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI48_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_5_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI48_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI48_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI48_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI48_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI48_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI48_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI48_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_5_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI48_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI48_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI48_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI48_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 5 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI48_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI48_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI48_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI48_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 5 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_5_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 5 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 5 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_5_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 5 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 5 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 5, i32 5, i32 5, i32 5> @@ -5102,127 +5106,127 @@ define <4 x i32> @ugt_5_v4i32(<4 x i32> %0) { define <4 x i32> @ult_6_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_6_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI49_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI49_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI49_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 6 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI49_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI49_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI49_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI49_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 6 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_6_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI49_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI49_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI49_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 6 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI49_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI49_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI49_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI49_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 6 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_6_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI49_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI49_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI49_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI49_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 6 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI49_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI49_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI49_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI49_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 6 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_6_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 6 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 6 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_6_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 6 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 6 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6> @@ -5233,127 +5237,127 @@ define <4 x i32> @ult_6_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_6_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI50_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI50_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI50_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI50_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 6 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI50_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI50_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI50_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI50_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 6 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_6_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI50_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI50_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI50_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI50_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 6 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI50_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI50_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI50_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI50_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 6 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_6_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI50_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI50_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI50_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI50_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 6 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI50_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI50_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI50_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI50_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 6 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_6_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 6 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 6 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_6_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 6 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 6 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 6, i32 6, i32 6, i32 6> @@ -5364,127 +5368,127 @@ define <4 x i32> @ugt_6_v4i32(<4 x i32> %0) { define <4 x i32> @ult_7_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_7_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI51_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI51_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI51_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI51_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI51_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI51_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI51_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI51_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 7 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_7_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI51_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI51_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI51_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI51_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 7 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI51_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI51_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI51_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI51_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 7 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_7_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI51_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI51_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI51_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI51_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI51_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI51_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI51_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI51_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_7_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 7 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 7 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_7_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 7 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 7 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7> @@ -5495,127 +5499,127 @@ define <4 x i32> @ult_7_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_7_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI52_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI52_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI52_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI52_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI52_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI52_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI52_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 7 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_7_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI52_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI52_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI52_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 7 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI52_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI52_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI52_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI52_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 7 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_7_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI52_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI52_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI52_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI52_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI52_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI52_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI52_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_7_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 7 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 7 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_7_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 7 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 7 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 7, i32 7, i32 7, i32 7> @@ -5626,127 +5630,127 @@ define <4 x i32> @ugt_7_v4i32(<4 x i32> %0) { define <4 x i32> @ult_8_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_8_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI53_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI53_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI53_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI53_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI53_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI53_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI53_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI53_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 8 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_8_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI53_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI53_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI53_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI53_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 8 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI53_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI53_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI53_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI53_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 8 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_8_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI53_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI53_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI53_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI53_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 8 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI53_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI53_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI53_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI53_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 8 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_8_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 8 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 8 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_8_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 8 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 8 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8> @@ -5757,127 +5761,127 @@ define <4 x i32> @ult_8_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_8_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI54_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI54_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI54_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI54_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI54_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI54_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI54_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI54_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 8 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_8_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI54_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI54_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI54_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI54_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 8 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI54_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI54_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI54_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI54_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 8 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_8_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI54_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI54_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI54_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI54_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 8 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI54_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI54_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI54_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI54_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 8 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_8_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 8 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 8 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_8_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 8 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 8 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 8, i32 8, i32 8, i32 8> @@ -5888,127 +5892,127 @@ define <4 x i32> @ugt_8_v4i32(<4 x i32> %0) { define <4 x i32> @ult_9_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_9_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI55_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI55_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI55_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI55_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI55_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI55_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI55_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI55_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 9 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_9_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI55_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI55_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI55_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI55_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 9 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI55_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI55_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI55_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI55_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 9 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_9_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI55_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI55_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI55_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI55_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 9 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI55_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI55_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI55_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI55_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 9 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_9_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 9 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 9 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_9_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 9 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 9 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9> @@ -6019,127 +6023,127 @@ define <4 x i32> @ult_9_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_9_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI56_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI56_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI56_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI56_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI56_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI56_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI56_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 9 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_9_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI56_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI56_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI56_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 9 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI56_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI56_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI56_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI56_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 9 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_9_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI56_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI56_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI56_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI56_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 9 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI56_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI56_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI56_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI56_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 9 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_9_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 9 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 9 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_9_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 9 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 9 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 9, i32 9, i32 9, i32 9> @@ -6150,127 +6154,127 @@ define <4 x i32> @ugt_9_v4i32(<4 x i32> %0) { define <4 x i32> @ult_10_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_10_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI57_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI57_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI57_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI57_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI57_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI57_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI57_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 10 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_10_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI57_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI57_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI57_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 10 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI57_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI57_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI57_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI57_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 10 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_10_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI57_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI57_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI57_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 10 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI57_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI57_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI57_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI57_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 10 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_10_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 10 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 10 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_10_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 10 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 10 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10> @@ -6281,127 +6285,127 @@ define <4 x i32> @ult_10_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_10_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI58_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI58_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI58_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI58_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI58_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI58_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI58_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI58_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 10 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_10_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI58_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI58_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI58_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI58_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 10 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI58_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI58_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI58_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI58_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 10 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_10_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI58_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI58_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI58_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI58_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 10 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI58_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI58_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI58_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI58_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 10 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_10_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 10 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 10 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_10_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 10 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 10 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 10, i32 10, i32 10, i32 10> @@ -6412,127 +6416,127 @@ define <4 x i32> @ugt_10_v4i32(<4 x i32> %0) { define <4 x i32> @ult_11_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_11_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI59_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI59_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI59_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI59_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI59_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI59_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI59_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI59_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 11 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_11_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI59_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI59_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI59_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI59_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 11 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI59_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI59_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI59_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI59_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 11 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_11_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI59_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI59_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI59_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI59_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 11 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI59_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI59_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI59_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI59_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 11 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_11_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 11 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 11 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_11_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 11 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 11 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11> @@ -6543,127 +6547,127 @@ define <4 x i32> @ult_11_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_11_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI60_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI60_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI60_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI60_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI60_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI60_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI60_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 11 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_11_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI60_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI60_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI60_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 11 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI60_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI60_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI60_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI60_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 11 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_11_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI60_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI60_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI60_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI60_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 11 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI60_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI60_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI60_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI60_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 11 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_11_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 11 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 11 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_11_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 11 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 11 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 11, i32 11, i32 11, i32 11> @@ -6674,124 +6678,124 @@ define <4 x i32> @ugt_11_v4i32(<4 x i32> %0) { define <4 x i32> @ult_12_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_12_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI61_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI61_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI61_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 5, 3, 3 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI61_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI61_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI61_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI61_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v5, v3, v3 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_12_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI61_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI61_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI61_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 5, 3, 3 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI61_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI61_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI61_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI61_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v5, v3, v3 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_12_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI61_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI61_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI61_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI61_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 7, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI61_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI61_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI61_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI61_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v7, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_12_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 12 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 12 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_12_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 12 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 12 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12> @@ -6802,124 +6806,124 @@ define <4 x i32> @ult_12_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_12_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI62_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI62_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI62_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 5, 3, 3 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI62_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI62_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI62_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI62_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v5, v3, v3 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_12_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI62_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI62_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI62_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 5, 3, 3 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI62_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI62_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI62_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI62_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v5, v3, v3 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_12_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI62_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI62_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI62_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 7 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI62_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI62_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI62_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI62_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v7 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_12_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 12 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 12 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_12_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 12 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 12 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 12, i32 12, i32 12, i32 12> @@ -6930,127 +6934,127 @@ define <4 x i32> @ugt_12_v4i32(<4 x i32> %0) { define <4 x i32> @ult_13_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_13_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI63_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI63_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI63_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI63_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI63_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI63_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI63_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI63_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 13 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_13_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI63_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI63_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI63_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI63_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 13 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI63_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI63_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI63_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI63_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 13 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_13_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI63_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI63_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI63_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI63_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 13 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI63_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI63_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI63_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI63_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 13 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_13_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 13 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 13 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_13_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 13 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 13 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13> @@ -7061,127 +7065,127 @@ define <4 x i32> @ult_13_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_13_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI64_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI64_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI64_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI64_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI64_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI64_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI64_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI64_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 13 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_13_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI64_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI64_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI64_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI64_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 13 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI64_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI64_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI64_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI64_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 13 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_13_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI64_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI64_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI64_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI64_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 13 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI64_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI64_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI64_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI64_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 13 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_13_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 13 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 13 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_13_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 13 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 13 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 13, i32 13, i32 13, i32 13> @@ -7192,127 +7196,127 @@ define <4 x i32> @ugt_13_v4i32(<4 x i32> %0) { define <4 x i32> @ult_14_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_14_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI65_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI65_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI65_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI65_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI65_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI65_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI65_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 14 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_14_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI65_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI65_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI65_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 14 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI65_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI65_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI65_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI65_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 14 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_14_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI65_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI65_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI65_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI65_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 14 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI65_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI65_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI65_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI65_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 14 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_14_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 14 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 14 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_14_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 14 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 14 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14> @@ -7323,127 +7327,127 @@ define <4 x i32> @ult_14_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_14_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI66_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI66_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI66_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI66_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI66_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI66_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI66_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 14 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_14_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI66_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI66_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI66_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 14 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI66_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI66_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI66_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI66_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 14 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_14_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI66_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI66_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI66_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI66_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 14 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI66_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI66_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI66_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI66_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 14 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_14_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 14 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 14 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_14_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 14 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 14 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 14, i32 14, i32 14, i32 14> @@ -7454,127 +7458,127 @@ define <4 x i32> @ugt_14_v4i32(<4 x i32> %0) { define <4 x i32> @ult_15_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_15_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI67_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI67_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI67_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI67_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI67_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI67_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI67_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 15 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_15_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI67_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI67_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI67_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 15 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI67_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI67_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI67_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI67_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 15 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_15_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI67_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI67_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI67_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 15 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 4, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI67_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI67_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI67_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI67_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 15 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v4, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_15_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 15 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 15 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_15_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 15 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 15 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15> @@ -7585,127 +7589,127 @@ define <4 x i32> @ult_15_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_15_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI68_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI68_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI68_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI68_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI68_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI68_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI68_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI68_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 15 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_15_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI68_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI68_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI68_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI68_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 15 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI68_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI68_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI68_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI68_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 15 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_15_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI68_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI68_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI68_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI68_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vspltisw 4, 15 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 4 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI68_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI68_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI68_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI68_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vspltisw v4, 15 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v4 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_15_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 15 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 15 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_15_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vspltisw 3, 15 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vspltisw v3, 15 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 15, i32 15, i32 15, i32 15> @@ -7716,132 +7720,132 @@ define <4 x i32> @ugt_15_v4i32(<4 x i32> %0) { define <4 x i32> @ult_16_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_16_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI69_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI69_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI69_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI69_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI69_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI69_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI69_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI69_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 8 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_16_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI69_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI69_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI69_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI69_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 8 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI69_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI69_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI69_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI69_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 8 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_16_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI69_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI69_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI69_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI69_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 8 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI69_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI69_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI69_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI69_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 8 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_16_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 8 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 8 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_16_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 16 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 16 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16> @@ -7852,132 +7856,132 @@ define <4 x i32> @ult_16_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_16_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI70_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI70_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI70_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 8 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI70_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI70_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI70_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI70_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 8 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_16_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI70_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI70_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI70_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 8 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI70_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI70_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI70_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI70_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 8 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_16_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI70_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI70_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI70_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI70_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 8 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI70_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI70_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI70_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI70_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 8 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_16_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 8 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 8 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_16_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 16 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 16 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 16, i32 16, i32 16, i32 16> @@ -7988,130 +7992,130 @@ define <4 x i32> @ugt_16_v4i32(<4 x i32> %0) { define <4 x i32> @ult_17_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_17_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI71_0@toc@l -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI71_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI71_1@toc@l -; PWR5-NEXT: vspltisw 1, 2 -; PWR5-NEXT: vsrw 5, 2, 4 -; PWR5-NEXT: vand 5, 5, 0 -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 5 -; PWR5-NEXT: vand 5, 2, 0 -; PWR5-NEXT: vsrw 2, 2, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, 4 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 5, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vadduwm 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 5, 0 -; PWR5-NEXT: vmulouh 5, 2, 5 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vsubuwm 3, 4, 0 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI71_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI71_0@toc@l +; PWR5-NEXT: lvx v0, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI71_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI71_1@toc@l +; PWR5-NEXT: vspltisw v1, 2 +; PWR5-NEXT: vsrw v5, v2, v4 +; PWR5-NEXT: vand v5, v5, v0 +; PWR5-NEXT: lvx v0, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v5 +; PWR5-NEXT: vand v5, v2, v0 +; PWR5-NEXT: vsrw v2, v2, v1 +; PWR5-NEXT: vand v2, v2, v0 +; PWR5-NEXT: vspltisw v0, 4 +; PWR5-NEXT: vadduwm v2, v5, v2 +; PWR5-NEXT: vsrw v5, v2, v0 +; PWR5-NEXT: vspltisb v0, 15 +; PWR5-NEXT: vadduwm v2, v2, v5 +; PWR5-NEXT: vspltisb v5, 1 +; PWR5-NEXT: vand v2, v2, v0 +; PWR5-NEXT: vspltisw v0, -16 +; PWR5-NEXT: vrlw v1, v5, v0 +; PWR5-NEXT: vmulouh v5, v2, v5 +; PWR5-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v0 +; PWR5-NEXT: vadduwm v2, v5, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vsubuwm v3, v4, v0 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_17_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI71_0@toc@l -; PWR6-NEXT: lvx 0, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI71_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI71_1@toc@l -; PWR6-NEXT: vspltisw 1, 2 -; PWR6-NEXT: vsrw 5, 2, 4 -; PWR6-NEXT: vand 5, 5, 0 -; PWR6-NEXT: lvx 0, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 5 -; PWR6-NEXT: vand 5, 2, 0 -; PWR6-NEXT: vsrw 2, 2, 1 -; PWR6-NEXT: vand 2, 2, 0 -; PWR6-NEXT: vspltisw 0, 4 -; PWR6-NEXT: vadduwm 2, 5, 2 -; PWR6-NEXT: vsrw 5, 2, 0 -; PWR6-NEXT: vspltisb 0, 15 -; PWR6-NEXT: vadduwm 2, 2, 5 -; PWR6-NEXT: vspltisb 5, 1 -; PWR6-NEXT: vand 2, 2, 0 -; PWR6-NEXT: vspltisw 0, -16 -; PWR6-NEXT: vrlw 1, 5, 0 -; PWR6-NEXT: vmulouh 5, 2, 5 -; PWR6-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 0 -; PWR6-NEXT: vadduwm 2, 5, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vsubuwm 3, 4, 0 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI71_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI71_0@toc@l +; PWR6-NEXT: lvx v0, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI71_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI71_1@toc@l +; PWR6-NEXT: vspltisw v1, 2 +; PWR6-NEXT: vsrw v5, v2, v4 +; PWR6-NEXT: vand v5, v5, v0 +; PWR6-NEXT: lvx v0, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v5 +; PWR6-NEXT: vand v5, v2, v0 +; PWR6-NEXT: vsrw v2, v2, v1 +; PWR6-NEXT: vand v2, v2, v0 +; PWR6-NEXT: vspltisw v0, 4 +; PWR6-NEXT: vadduwm v2, v5, v2 +; PWR6-NEXT: vsrw v5, v2, v0 +; PWR6-NEXT: vspltisb v0, 15 +; PWR6-NEXT: vadduwm v2, v2, v5 +; PWR6-NEXT: vspltisb v5, 1 +; PWR6-NEXT: vand v2, v2, v0 +; PWR6-NEXT: vspltisw v0, -16 +; PWR6-NEXT: vrlw v1, v5, v0 +; PWR6-NEXT: vmulouh v5, v2, v5 +; PWR6-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v0 +; PWR6-NEXT: vadduwm v2, v5, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vsubuwm v3, v4, v0 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_17_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI71_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI71_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI71_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI71_1@toc@l -; PWR7-NEXT: vsrw 8, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vsubuwm 3, 3, 6 -; PWR7-NEXT: xxland 40, 40, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 8 -; PWR7-NEXT: vsrw 4, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 36, 36, 0 -; PWR7-NEXT: vadduwm 2, 2, 4 -; PWR7-NEXT: vsrw 4, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 4 -; PWR7-NEXT: vrlw 4, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 4, 2, 4, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 4, 4, 6 -; PWR7-NEXT: vadduwm 2, 2, 4 -; PWR7-NEXT: vadduwm 4, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 4 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI71_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI71_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI71_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI71_1@toc@l +; PWR7-NEXT: vsrw v8, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vsubuwm v3, v3, v6 +; PWR7-NEXT: xxland v8, v8, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v8 +; PWR7-NEXT: vsrw v4, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v4, v4, vs0 +; PWR7-NEXT: vadduwm v2, v2, v4 +; PWR7-NEXT: vsrw v4, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v4 +; PWR7-NEXT: vrlw v4, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v4, v2, v4, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v4, v4, v6 +; PWR7-NEXT: vadduwm v2, v2, v4 +; PWR7-NEXT: vadduwm v4, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v4 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_17_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 1 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 1 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_17_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 17 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 17 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17> @@ -8122,130 +8126,130 @@ define <4 x i32> @ult_17_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_17_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI72_0@toc@l -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI72_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI72_1@toc@l -; PWR5-NEXT: vspltisw 1, 2 -; PWR5-NEXT: vsrw 5, 2, 4 -; PWR5-NEXT: vand 5, 5, 0 -; PWR5-NEXT: lvx 0, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 5 -; PWR5-NEXT: vand 5, 2, 0 -; PWR5-NEXT: vsrw 2, 2, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, 4 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 5, 2, 0 -; PWR5-NEXT: vspltisb 0, 15 -; PWR5-NEXT: vadduwm 2, 2, 5 -; PWR5-NEXT: vspltisb 5, 1 -; PWR5-NEXT: vand 2, 2, 0 -; PWR5-NEXT: vspltisw 0, -16 -; PWR5-NEXT: vrlw 1, 5, 0 -; PWR5-NEXT: vmulouh 5, 2, 5 -; PWR5-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 0 -; PWR5-NEXT: vadduwm 2, 5, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vsubuwm 3, 4, 0 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI72_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI72_0@toc@l +; PWR5-NEXT: lvx v0, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI72_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI72_1@toc@l +; PWR5-NEXT: vspltisw v1, 2 +; PWR5-NEXT: vsrw v5, v2, v4 +; PWR5-NEXT: vand v5, v5, v0 +; PWR5-NEXT: lvx v0, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v5 +; PWR5-NEXT: vand v5, v2, v0 +; PWR5-NEXT: vsrw v2, v2, v1 +; PWR5-NEXT: vand v2, v2, v0 +; PWR5-NEXT: vspltisw v0, 4 +; PWR5-NEXT: vadduwm v2, v5, v2 +; PWR5-NEXT: vsrw v5, v2, v0 +; PWR5-NEXT: vspltisb v0, 15 +; PWR5-NEXT: vadduwm v2, v2, v5 +; PWR5-NEXT: vspltisb v5, 1 +; PWR5-NEXT: vand v2, v2, v0 +; PWR5-NEXT: vspltisw v0, -16 +; PWR5-NEXT: vrlw v1, v5, v0 +; PWR5-NEXT: vmulouh v5, v2, v5 +; PWR5-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v0 +; PWR5-NEXT: vadduwm v2, v5, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vsubuwm v3, v4, v0 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_17_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI72_0@toc@l -; PWR6-NEXT: lvx 0, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI72_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI72_1@toc@l -; PWR6-NEXT: vspltisw 1, 2 -; PWR6-NEXT: vsrw 5, 2, 4 -; PWR6-NEXT: vand 5, 5, 0 -; PWR6-NEXT: lvx 0, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 5 -; PWR6-NEXT: vand 5, 2, 0 -; PWR6-NEXT: vsrw 2, 2, 1 -; PWR6-NEXT: vand 2, 2, 0 -; PWR6-NEXT: vspltisw 0, 4 -; PWR6-NEXT: vadduwm 2, 5, 2 -; PWR6-NEXT: vsrw 5, 2, 0 -; PWR6-NEXT: vspltisb 0, 15 -; PWR6-NEXT: vadduwm 2, 2, 5 -; PWR6-NEXT: vspltisb 5, 1 -; PWR6-NEXT: vand 2, 2, 0 -; PWR6-NEXT: vspltisw 0, -16 -; PWR6-NEXT: vrlw 1, 5, 0 -; PWR6-NEXT: vmulouh 5, 2, 5 -; PWR6-NEXT: vmsumuhm 2, 2, 1, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 0 -; PWR6-NEXT: vadduwm 2, 5, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vsubuwm 3, 4, 0 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI72_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI72_0@toc@l +; PWR6-NEXT: lvx v0, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI72_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI72_1@toc@l +; PWR6-NEXT: vspltisw v1, 2 +; PWR6-NEXT: vsrw v5, v2, v4 +; PWR6-NEXT: vand v5, v5, v0 +; PWR6-NEXT: lvx v0, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v5 +; PWR6-NEXT: vand v5, v2, v0 +; PWR6-NEXT: vsrw v2, v2, v1 +; PWR6-NEXT: vand v2, v2, v0 +; PWR6-NEXT: vspltisw v0, 4 +; PWR6-NEXT: vadduwm v2, v5, v2 +; PWR6-NEXT: vsrw v5, v2, v0 +; PWR6-NEXT: vspltisb v0, 15 +; PWR6-NEXT: vadduwm v2, v2, v5 +; PWR6-NEXT: vspltisb v5, 1 +; PWR6-NEXT: vand v2, v2, v0 +; PWR6-NEXT: vspltisw v0, -16 +; PWR6-NEXT: vrlw v1, v5, v0 +; PWR6-NEXT: vmulouh v5, v2, v5 +; PWR6-NEXT: vmsumuhm v2, v2, v1, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v0 +; PWR6-NEXT: vadduwm v2, v5, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vsubuwm v3, v4, v0 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_17_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI72_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI72_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI72_1@toc@l -; PWR7-NEXT: vsrw 8, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vsubuwm 3, 3, 6 -; PWR7-NEXT: xxland 40, 40, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 8 -; PWR7-NEXT: vsrw 4, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxland 36, 36, 0 -; PWR7-NEXT: vadduwm 2, 2, 4 -; PWR7-NEXT: vsrw 4, 2, 5 -; PWR7-NEXT: xxlxor 37, 37, 37 -; PWR7-NEXT: vadduwm 2, 2, 4 -; PWR7-NEXT: vrlw 4, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 4, 2, 4, 5 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 4, 4, 6 -; PWR7-NEXT: vadduwm 2, 2, 4 -; PWR7-NEXT: vadduwm 4, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 4 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI72_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI72_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI72_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI72_1@toc@l +; PWR7-NEXT: vsrw v8, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vsubuwm v3, v3, v6 +; PWR7-NEXT: xxland v8, v8, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v8 +; PWR7-NEXT: vsrw v4, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxland v4, v4, vs0 +; PWR7-NEXT: vadduwm v2, v2, v4 +; PWR7-NEXT: vsrw v4, v2, v5 +; PWR7-NEXT: xxlxor v5, v5, v5 +; PWR7-NEXT: vadduwm v2, v2, v4 +; PWR7-NEXT: vrlw v4, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v4, v2, v4, v5 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v4, v4, v6 +; PWR7-NEXT: vadduwm v2, v2, v4 +; PWR7-NEXT: vadduwm v4, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v4 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_17_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 1 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 1 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_17_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 17 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 17 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 17, i32 17, i32 17, i32 17> @@ -8256,132 +8260,132 @@ define <4 x i32> @ugt_17_v4i32(<4 x i32> %0) { define <4 x i32> @ult_18_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_18_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI73_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI73_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI73_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI73_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI73_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI73_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI73_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI73_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 9 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_18_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI73_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI73_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI73_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI73_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 9 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI73_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI73_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI73_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI73_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 9 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_18_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI73_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI73_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI73_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI73_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 9 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI73_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI73_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI73_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI73_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 9 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_18_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 9 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 9 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_18_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 18 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 18 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18> @@ -8392,132 +8396,132 @@ define <4 x i32> @ult_18_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_18_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI74_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI74_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI74_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI74_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI74_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI74_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI74_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI74_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 9 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_18_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI74_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI74_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI74_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI74_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 9 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI74_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI74_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI74_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI74_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 9 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_18_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI74_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI74_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI74_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI74_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 9 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI74_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI74_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI74_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI74_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 9 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_18_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 9 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 9 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_18_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 18 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 18 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 18, i32 18, i32 18, i32 18> @@ -8528,133 +8532,133 @@ define <4 x i32> @ugt_18_v4i32(<4 x i32> %0) { define <4 x i32> @ult_19_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_19_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI75_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI75_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI75_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI75_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI75_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI75_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI75_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI75_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 3 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_19_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI75_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI75_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI75_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI75_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 3 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI75_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI75_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI75_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI75_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 3 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_19_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI75_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI75_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI75_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI75_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 3 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI75_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI75_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI75_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI75_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 3 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_19_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 3 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 3 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_19_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 19 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 19 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19> @@ -8665,133 +8669,133 @@ define <4 x i32> @ult_19_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_19_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI76_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI76_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI76_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 3 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI76_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI76_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI76_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI76_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 3 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_19_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI76_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI76_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI76_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 3 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI76_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI76_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI76_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI76_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 3 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_19_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI76_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI76_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI76_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI76_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 3 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI76_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI76_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI76_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI76_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 3 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_19_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 3 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 3 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_19_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 19 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 19 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 19, i32 19, i32 19, i32 19> @@ -8802,132 +8806,132 @@ define <4 x i32> @ugt_19_v4i32(<4 x i32> %0) { define <4 x i32> @ult_20_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_20_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI77_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI77_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI77_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI77_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI77_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI77_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI77_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI77_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 10 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_20_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI77_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI77_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI77_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI77_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 10 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI77_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI77_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI77_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI77_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 10 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_20_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI77_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI77_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI77_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI77_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 10 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI77_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI77_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI77_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI77_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 10 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_20_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 10 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 10 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_20_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 20 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 20 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20> @@ -8938,132 +8942,132 @@ define <4 x i32> @ult_20_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_20_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI78_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI78_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI78_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 10 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI78_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI78_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI78_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI78_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 10 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_20_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI78_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI78_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI78_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 10 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI78_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI78_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI78_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI78_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 10 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_20_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI78_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI78_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI78_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI78_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 10 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI78_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI78_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI78_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI78_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 10 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_20_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 10 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 10 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_20_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 20 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 20 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 20, i32 20, i32 20, i32 20> @@ -9074,133 +9078,133 @@ define <4 x i32> @ugt_20_v4i32(<4 x i32> %0) { define <4 x i32> @ult_21_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_21_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI79_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI79_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI79_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI79_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI79_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI79_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI79_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 5 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_21_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI79_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI79_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI79_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 5 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI79_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI79_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI79_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI79_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 5 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_21_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI79_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI79_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI79_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI79_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 5 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI79_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI79_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI79_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI79_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 5 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_21_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 5 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 5 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_21_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 21 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 21 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21> @@ -9211,133 +9215,133 @@ define <4 x i32> @ult_21_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_21_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI80_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI80_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI80_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI80_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 5 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI80_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI80_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI80_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI80_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 5 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_21_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI80_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI80_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI80_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI80_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 5 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI80_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI80_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI80_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI80_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 5 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_21_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI80_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI80_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI80_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI80_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 5 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI80_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI80_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI80_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI80_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 5 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_21_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 5 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 5 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_21_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 21 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 21 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 21, i32 21, i32 21, i32 21> @@ -9348,132 +9352,132 @@ define <4 x i32> @ugt_21_v4i32(<4 x i32> %0) { define <4 x i32> @ult_22_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_22_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI81_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI81_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI81_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI81_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI81_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI81_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI81_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI81_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 11 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_22_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI81_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI81_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI81_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI81_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 11 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI81_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI81_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI81_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI81_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 11 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_22_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI81_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI81_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI81_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI81_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 11 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI81_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI81_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI81_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI81_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 11 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_22_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 11 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 11 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_22_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 22 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 22 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22> @@ -9484,132 +9488,132 @@ define <4 x i32> @ult_22_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_22_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI82_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI82_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI82_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI82_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI82_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI82_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI82_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 11 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_22_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI82_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI82_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI82_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 11 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI82_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI82_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI82_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI82_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 11 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_22_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI82_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI82_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI82_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 11 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI82_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI82_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI82_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI82_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 11 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_22_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 11 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 11 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_22_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 22 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 22 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22> @@ -9620,133 +9624,133 @@ define <4 x i32> @ugt_22_v4i32(<4 x i32> %0) { define <4 x i32> @ult_23_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_23_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI83_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI83_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI83_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI83_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI83_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI83_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI83_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI83_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 7 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_23_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI83_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI83_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI83_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI83_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 7 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI83_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI83_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI83_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI83_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 7 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_23_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI83_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI83_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI83_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI83_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 7 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI83_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI83_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI83_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI83_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 7 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_23_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 7 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 7 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_23_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 23 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 23 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23> @@ -9757,133 +9761,133 @@ define <4 x i32> @ult_23_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_23_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI84_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI84_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI84_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI84_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 7 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI84_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI84_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI84_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI84_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 7 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_23_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI84_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI84_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI84_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI84_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 7 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI84_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI84_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI84_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI84_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 7 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_23_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI84_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI84_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI84_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI84_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 7 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI84_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI84_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI84_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI84_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 7 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_23_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 7 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 7 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_23_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 23 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 23 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 23, i32 23, i32 23, i32 23> @@ -9894,126 +9898,126 @@ define <4 x i32> @ugt_23_v4i32(<4 x i32> %0) { define <4 x i32> @ult_24_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_24_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI85_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI85_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI85_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI85_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI85_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI85_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI85_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI85_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_24_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI85_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI85_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI85_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI85_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI85_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI85_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI85_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI85_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_24_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI85_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI85_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI85_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI85_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI85_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI85_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI85_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI85_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_24_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 12 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 12 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_24_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 24 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 24 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24> @@ -10024,126 +10028,126 @@ define <4 x i32> @ult_24_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_24_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI86_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI86_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI86_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI86_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI86_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI86_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI86_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_24_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI86_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI86_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI86_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI86_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI86_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI86_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI86_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_24_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI86_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI86_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI86_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI86_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI86_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI86_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI86_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI86_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_24_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 12 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 12 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_24_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 24 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 24 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 24, i32 24, i32 24, i32 24> @@ -10154,133 +10158,133 @@ define <4 x i32> @ugt_24_v4i32(<4 x i32> %0) { define <4 x i32> @ult_25_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_25_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI87_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI87_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI87_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI87_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI87_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI87_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI87_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 9 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_25_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI87_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI87_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI87_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 9 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI87_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI87_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI87_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI87_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 9 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_25_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI87_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI87_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI87_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 9 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI87_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI87_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI87_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI87_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 9 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_25_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 9 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 9 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_25_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 25 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 25 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25> @@ -10291,133 +10295,133 @@ define <4 x i32> @ult_25_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_25_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI88_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI88_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI88_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI88_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 9 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI88_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI88_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI88_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI88_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 9 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_25_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI88_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI88_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI88_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI88_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 9 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI88_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI88_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI88_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI88_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 9 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_25_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI88_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI88_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI88_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI88_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 9 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI88_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI88_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI88_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI88_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 9 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_25_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 9 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 9 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_25_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 25 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 25 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 25, i32 25, i32 25, i32 25> @@ -10428,132 +10432,132 @@ define <4 x i32> @ugt_25_v4i32(<4 x i32> %0) { define <4 x i32> @ult_26_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_26_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI89_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI89_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI89_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI89_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI89_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI89_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI89_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 13 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_26_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI89_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI89_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI89_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 13 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI89_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI89_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI89_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI89_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 13 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_26_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI89_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI89_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI89_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI89_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 13 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI89_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI89_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI89_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI89_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 13 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_26_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 13 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 13 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_26_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 26 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 26 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26> @@ -10564,132 +10568,132 @@ define <4 x i32> @ult_26_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_26_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI90_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI90_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI90_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI90_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI90_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI90_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI90_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI90_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 13 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_26_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI90_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI90_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI90_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI90_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 13 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI90_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI90_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI90_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI90_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 13 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_26_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI90_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI90_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI90_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI90_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 13 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI90_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI90_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI90_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI90_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 13 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_26_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 13 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 13 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_26_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 26 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 26 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26> @@ -10700,133 +10704,133 @@ define <4 x i32> @ugt_26_v4i32(<4 x i32> %0) { define <4 x i32> @ult_27_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_27_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI91_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI91_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI91_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI91_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI91_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI91_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI91_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 11 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_27_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI91_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI91_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI91_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 11 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI91_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI91_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI91_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI91_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 11 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_27_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI91_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI91_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI91_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI91_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 11 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI91_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI91_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI91_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI91_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 11 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_27_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 11 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 11 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_27_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 27 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 27 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27> @@ -10837,133 +10841,133 @@ define <4 x i32> @ult_27_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_27_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI92_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI92_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI92_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 11 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI92_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI92_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI92_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI92_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 11 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_27_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI92_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI92_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI92_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 11 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI92_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI92_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI92_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI92_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 11 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_27_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI92_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI92_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI92_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 11 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI92_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI92_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI92_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI92_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 11 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_27_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 11 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 11 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_27_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 27 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 27 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 27, i32 27, i32 27, i32 27> @@ -10974,132 +10978,132 @@ define <4 x i32> @ugt_27_v4i32(<4 x i32> %0) { define <4 x i32> @ult_28_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_28_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI93_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI93_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI93_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI93_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI93_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI93_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI93_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI93_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 14 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_28_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI93_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI93_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI93_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI93_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 14 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI93_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI93_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI93_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI93_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 14 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_28_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI93_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI93_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI93_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI93_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 14 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI93_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI93_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI93_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI93_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 14 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_28_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 14 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 14 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_28_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 28 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 28 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28> @@ -11110,132 +11114,132 @@ define <4 x i32> @ult_28_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_28_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI94_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI94_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI94_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 14 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI94_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI94_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI94_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI94_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 14 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_28_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI94_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI94_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI94_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 14 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI94_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI94_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI94_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI94_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 14 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_28_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI94_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI94_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI94_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI94_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 14 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI94_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI94_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI94_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI94_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 14 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_28_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 14 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 14 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_28_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 28 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 28 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 28, i32 28, i32 28, i32 28> @@ -11246,133 +11250,133 @@ define <4 x i32> @ugt_28_v4i32(<4 x i32> %0) { define <4 x i32> @ult_29_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_29_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI95_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI95_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI95_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI95_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI95_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI95_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI95_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI95_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 13 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_29_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI95_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI95_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI95_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI95_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 13 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI95_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI95_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI95_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI95_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 13 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_29_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI95_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI95_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI95_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI95_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 13 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI95_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI95_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI95_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI95_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 13 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_29_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 13 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 13 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_29_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 29 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 29 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29> @@ -11383,133 +11387,133 @@ define <4 x i32> @ult_29_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_29_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI96_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI96_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI96_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI96_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 13 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI96_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI96_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI96_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI96_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 13 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_29_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI96_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI96_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI96_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI96_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 13 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI96_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI96_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI96_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI96_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 13 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_29_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI96_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI96_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI96_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI96_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 13 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI96_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI96_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI96_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI96_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 13 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_29_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 13 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 13 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_29_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 29 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 29 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 29, i32 29, i32 29, i32 29> @@ -11520,132 +11524,132 @@ define <4 x i32> @ugt_29_v4i32(<4 x i32> %0) { define <4 x i32> @ult_30_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_30_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI97_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI97_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI97_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI97_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI97_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI97_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 15 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_30_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI97_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI97_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 15 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI97_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI97_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI97_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI97_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 15 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_30_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI97_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI97_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 15 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI97_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI97_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI97_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI97_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 15 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_30_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 15 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 15 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_30_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 30 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 30 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30> @@ -11656,132 +11660,132 @@ define <4 x i32> @ult_30_v4i32(<4 x i32> %0) { define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ugt_30_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI98_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI98_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI98_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vcmpgtuw 2, 2, 3 +; PWR5-NEXT: addis r3, r2, .LCPI98_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI98_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI98_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI98_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 15 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vcmpgtuw v2, v2, v3 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_30_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI98_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI98_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI98_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 15 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vcmpgtuw 2, 2, 3 +; PWR6-NEXT: addis r3, r2, .LCPI98_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI98_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI98_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI98_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 15 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vcmpgtuw v2, v2, v3 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_30_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI98_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI98_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI98_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI98_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 15 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 8, 8 -; PWR7-NEXT: vcmpgtuw 2, 2, 3 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI98_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI98_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI98_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI98_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 15 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v8, v8 +; PWR7-NEXT: vcmpgtuw v2, v2, v3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_30_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 15 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vadduwm 3, 3, 3 -; PWR8-NEXT: vcmpgtuw 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 15 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vadduwm v3, v3, v3 +; PWR8-NEXT: vcmpgtuw v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_30_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 30 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 30 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ugt <4 x i32> %2, <i32 30, i32 30, i32 30, i32 30> @@ -11792,133 +11796,133 @@ define <4 x i32> @ugt_30_v4i32(<4 x i32> %0) { define <4 x i32> @ult_31_v4i32(<4 x i32> %0) { ; PWR5-LABEL: ult_31_v4i32: ; PWR5: # %bb.0: -; PWR5-NEXT: addis 3, 2, .LCPI99_0@toc@ha -; PWR5-NEXT: vspltisw 4, 1 -; PWR5-NEXT: vxor 3, 3, 3 -; PWR5-NEXT: addi 3, 3, .LCPI99_0@toc@l -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: addis 3, 2, .LCPI99_1@toc@ha -; PWR5-NEXT: addi 3, 3, .LCPI99_1@toc@l -; PWR5-NEXT: vspltisw 0, 2 -; PWR5-NEXT: vsrw 4, 2, 4 -; PWR5-NEXT: vand 4, 4, 5 -; PWR5-NEXT: lvx 5, 0, 3 -; PWR5-NEXT: vsubuwm 2, 2, 4 -; PWR5-NEXT: vand 4, 2, 5 -; PWR5-NEXT: vsrw 2, 2, 0 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, 4 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 4, 2, 5 -; PWR5-NEXT: vspltisb 5, 15 -; PWR5-NEXT: vadduwm 2, 2, 4 -; PWR5-NEXT: vspltisb 4, 1 -; PWR5-NEXT: vand 2, 2, 5 -; PWR5-NEXT: vspltisw 5, -16 -; PWR5-NEXT: vrlw 0, 4, 5 -; PWR5-NEXT: vmulouh 4, 2, 4 -; PWR5-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR5-NEXT: vspltisw 3, 12 -; PWR5-NEXT: vadduwm 3, 3, 3 -; PWR5-NEXT: vslw 2, 2, 5 -; PWR5-NEXT: vadduwm 2, 4, 2 -; PWR5-NEXT: vsrw 2, 2, 3 -; PWR5-NEXT: vspltisw 3, 15 -; PWR5-NEXT: vsubuwm 3, 3, 5 -; PWR5-NEXT: vcmpgtuw 2, 3, 2 +; PWR5-NEXT: addis r3, r2, .LCPI99_0@toc@ha +; PWR5-NEXT: vspltisw v4, 1 +; PWR5-NEXT: vxor v3, v3, v3 +; PWR5-NEXT: addi r3, r3, .LCPI99_0@toc@l +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: addis r3, r2, .LCPI99_1@toc@ha +; PWR5-NEXT: addi r3, r3, .LCPI99_1@toc@l +; PWR5-NEXT: vspltisw v0, 2 +; PWR5-NEXT: vsrw v4, v2, v4 +; PWR5-NEXT: vand v4, v4, v5 +; PWR5-NEXT: lvx v5, 0, r3 +; PWR5-NEXT: vsubuwm v2, v2, v4 +; PWR5-NEXT: vand v4, v2, v5 +; PWR5-NEXT: vsrw v2, v2, v0 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, 4 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v4, v2, v5 +; PWR5-NEXT: vspltisb v5, 15 +; PWR5-NEXT: vadduwm v2, v2, v4 +; PWR5-NEXT: vspltisb v4, 1 +; PWR5-NEXT: vand v2, v2, v5 +; PWR5-NEXT: vspltisw v5, -16 +; PWR5-NEXT: vrlw v0, v4, v5 +; PWR5-NEXT: vmulouh v4, v2, v4 +; PWR5-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR5-NEXT: vspltisw v3, 12 +; PWR5-NEXT: vadduwm v3, v3, v3 +; PWR5-NEXT: vslw v2, v2, v5 +; PWR5-NEXT: vadduwm v2, v4, v2 +; PWR5-NEXT: vsrw v2, v2, v3 +; PWR5-NEXT: vspltisw v3, 15 +; PWR5-NEXT: vsubuwm v3, v3, v5 +; PWR5-NEXT: vcmpgtuw v2, v3, v2 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_31_v4i32: ; PWR6: # %bb.0: -; PWR6-NEXT: addis 3, 2, .LCPI99_0@toc@ha -; PWR6-NEXT: vspltisw 4, 1 -; PWR6-NEXT: vxor 3, 3, 3 -; PWR6-NEXT: addi 3, 3, .LCPI99_0@toc@l -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: addis 3, 2, .LCPI99_1@toc@ha -; PWR6-NEXT: addi 3, 3, .LCPI99_1@toc@l -; PWR6-NEXT: vspltisw 0, 2 -; PWR6-NEXT: vsrw 4, 2, 4 -; PWR6-NEXT: vand 4, 4, 5 -; PWR6-NEXT: lvx 5, 0, 3 -; PWR6-NEXT: vsubuwm 2, 2, 4 -; PWR6-NEXT: vand 4, 2, 5 -; PWR6-NEXT: vsrw 2, 2, 0 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, 4 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 4, 2, 5 -; PWR6-NEXT: vspltisb 5, 15 -; PWR6-NEXT: vadduwm 2, 2, 4 -; PWR6-NEXT: vspltisb 4, 1 -; PWR6-NEXT: vand 2, 2, 5 -; PWR6-NEXT: vspltisw 5, -16 -; PWR6-NEXT: vrlw 0, 4, 5 -; PWR6-NEXT: vmulouh 4, 2, 4 -; PWR6-NEXT: vmsumuhm 2, 2, 0, 3 -; PWR6-NEXT: vspltisw 3, 12 -; PWR6-NEXT: vadduwm 3, 3, 3 -; PWR6-NEXT: vslw 2, 2, 5 -; PWR6-NEXT: vadduwm 2, 4, 2 -; PWR6-NEXT: vsrw 2, 2, 3 -; PWR6-NEXT: vspltisw 3, 15 -; PWR6-NEXT: vsubuwm 3, 3, 5 -; PWR6-NEXT: vcmpgtuw 2, 3, 2 +; PWR6-NEXT: addis r3, r2, .LCPI99_0@toc@ha +; PWR6-NEXT: vspltisw v4, 1 +; PWR6-NEXT: vxor v3, v3, v3 +; PWR6-NEXT: addi r3, r3, .LCPI99_0@toc@l +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: addis r3, r2, .LCPI99_1@toc@ha +; PWR6-NEXT: addi r3, r3, .LCPI99_1@toc@l +; PWR6-NEXT: vspltisw v0, 2 +; PWR6-NEXT: vsrw v4, v2, v4 +; PWR6-NEXT: vand v4, v4, v5 +; PWR6-NEXT: lvx v5, 0, r3 +; PWR6-NEXT: vsubuwm v2, v2, v4 +; PWR6-NEXT: vand v4, v2, v5 +; PWR6-NEXT: vsrw v2, v2, v0 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, 4 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v4, v2, v5 +; PWR6-NEXT: vspltisb v5, 15 +; PWR6-NEXT: vadduwm v2, v2, v4 +; PWR6-NEXT: vspltisb v4, 1 +; PWR6-NEXT: vand v2, v2, v5 +; PWR6-NEXT: vspltisw v5, -16 +; PWR6-NEXT: vrlw v0, v4, v5 +; PWR6-NEXT: vmulouh v4, v2, v4 +; PWR6-NEXT: vmsumuhm v2, v2, v0, v3 +; PWR6-NEXT: vspltisw v3, 12 +; PWR6-NEXT: vadduwm v3, v3, v3 +; PWR6-NEXT: vslw v2, v2, v5 +; PWR6-NEXT: vadduwm v2, v4, v2 +; PWR6-NEXT: vsrw v2, v2, v3 +; PWR6-NEXT: vspltisw v3, 15 +; PWR6-NEXT: vsubuwm v3, v3, v5 +; PWR6-NEXT: vcmpgtuw v2, v3, v2 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_31_v4i32: ; PWR7: # %bb.0: -; PWR7-NEXT: vspltisw 3, 1 -; PWR7-NEXT: addis 3, 2, .LCPI99_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI99_0@toc@l -; PWR7-NEXT: vspltisw 4, 2 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI99_1@toc@ha -; PWR7-NEXT: vspltisw 5, 4 -; PWR7-NEXT: addi 3, 3, .LCPI99_1@toc@l -; PWR7-NEXT: vsrw 3, 2, 3 -; PWR7-NEXT: vspltisb 0, 15 -; PWR7-NEXT: vspltisb 1, 1 -; PWR7-NEXT: vspltisw 6, -16 -; PWR7-NEXT: vspltisw 7, 12 -; PWR7-NEXT: vspltisw 8, 15 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: vsubuwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 4 -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: xxlxor 36, 36, 36 -; PWR7-NEXT: xxland 35, 35, 0 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vsrw 3, 2, 5 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vrlw 3, 1, 6 -; PWR7-NEXT: xxland 34, 34, 32 -; PWR7-NEXT: vmsumuhm 3, 2, 3, 4 -; PWR7-NEXT: vmulouh 2, 2, 1 -; PWR7-NEXT: vslw 3, 3, 6 -; PWR7-NEXT: vadduwm 2, 2, 3 -; PWR7-NEXT: vadduwm 3, 7, 7 -; PWR7-NEXT: vsrw 2, 2, 3 -; PWR7-NEXT: vsubuwm 3, 8, 6 -; PWR7-NEXT: vcmpgtuw 2, 3, 2 +; PWR7-NEXT: vspltisw v3, 1 +; PWR7-NEXT: addis r3, r2, .LCPI99_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI99_0@toc@l +; PWR7-NEXT: vspltisw v4, 2 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI99_1@toc@ha +; PWR7-NEXT: vspltisw v5, 4 +; PWR7-NEXT: addi r3, r3, .LCPI99_1@toc@l +; PWR7-NEXT: vsrw v3, v2, v3 +; PWR7-NEXT: vspltisb v0, 15 +; PWR7-NEXT: vspltisb v1, 1 +; PWR7-NEXT: vspltisw v6, -16 +; PWR7-NEXT: vspltisw v7, 12 +; PWR7-NEXT: vspltisw v8, 15 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: vsubuwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v4 +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: xxlxor v4, v4, v4 +; PWR7-NEXT: xxland v3, v3, vs0 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vsrw v3, v2, v5 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vrlw v3, v1, v6 +; PWR7-NEXT: xxland v2, v2, v0 +; PWR7-NEXT: vmsumuhm v3, v2, v3, v4 +; PWR7-NEXT: vmulouh v2, v2, v1 +; PWR7-NEXT: vslw v3, v3, v6 +; PWR7-NEXT: vadduwm v2, v2, v3 +; PWR7-NEXT: vadduwm v3, v7, v7 +; PWR7-NEXT: vsrw v2, v2, v3 +; PWR7-NEXT: vsubuwm v3, v8, v6 +; PWR7-NEXT: vcmpgtuw v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_31_v4i32: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, -16 -; PWR8-NEXT: vspltisw 4, 15 -; PWR8-NEXT: vpopcntw 2, 2 -; PWR8-NEXT: vsubuwm 3, 4, 3 -; PWR8-NEXT: vcmpgtuw 2, 3, 2 +; PWR8-NEXT: vspltisw v3, -16 +; PWR8-NEXT: vspltisw v4, 15 +; PWR8-NEXT: vpopcntw v2, v2 +; PWR8-NEXT: vsubuwm v3, v4, v3 +; PWR8-NEXT: vcmpgtuw v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_31_v4i32: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 31 -; PWR9-NEXT: vpopcntw 2, 2 -; PWR9-NEXT: vextsb2w 3, 3 -; PWR9-NEXT: vcmpgtuw 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 31 +; PWR9-NEXT: vpopcntw v2, v2 +; PWR9-NEXT: vextsb2w v3, v3 +; PWR9-NEXT: vcmpgtuw v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0) %3 = icmp ult <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31> @@ -11929,65 +11933,65 @@ define <4 x i32> @ult_31_v4i32(<4 x i32> %0) { define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_1_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: addi 5, 3, -1 -; PWR5-NEXT: addi 6, 4, -1 -; PWR5-NEXT: and 3, 3, 5 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: subfic 3, 3, 0 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subfic 4, 4, 0 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: addi r5, r3, -1 +; PWR5-NEXT: addi r6, r4, -1 +; PWR5-NEXT: and r3, r3, r5 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: subfic r3, r3, 0 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subfic r4, r4, 0 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_1_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: addi 5, 3, -1 -; PWR6-NEXT: addi 6, 4, -1 -; PWR6-NEXT: and 3, 3, 5 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: subfic 3, 3, 0 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subfic 4, 4, 0 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: addi r5, r3, -1 +; PWR6-NEXT: addi r6, r4, -1 +; PWR6-NEXT: and r3, r3, r5 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: subfic r3, r3, 0 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subfic r4, r4, 0 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_1_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 3, -24(1) -; PWR7-NEXT: addi 3, 3, -1 -; PWR7-NEXT: std 3, -8(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: addi 3, 3, -1 -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI100_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI100_0@toc@l -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: vcmpequw 2, 2, 3 -; PWR7-NEXT: lxvw4x 35, 0, 3 -; PWR7-NEXT: xxlnor 34, 34, 34 -; PWR7-NEXT: vperm 3, 2, 2, 3 -; PWR7-NEXT: xxlor 34, 35, 34 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r3, -24(r1) +; PWR7-NEXT: addi r3, r3, -1 +; PWR7-NEXT: std r3, -8(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: addi r3, r3, -1 +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI100_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI100_0@toc@l +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: vcmpequw v2, v2, v3 +; PWR7-NEXT: lxvw4x v3, 0, r3 +; PWR7-NEXT: xxlnor v2, v2, v2 +; PWR7-NEXT: vperm v3, v2, v2, v3 +; PWR7-NEXT: xxlor v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_1_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 1 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 1 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_1_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 1 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 1 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 1, i64 1> @@ -11998,64 +12002,64 @@ define <2 x i64> @ugt_1_v2i64(<2 x i64> %0) { define <2 x i64> @ult_2_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_2_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: addi 5, 3, -1 -; PWR5-NEXT: addi 6, 4, -1 -; PWR5-NEXT: and 3, 3, 5 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: addic 3, 3, -1 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: addic 4, 4, -1 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: addi r5, r3, -1 +; PWR5-NEXT: addi r6, r4, -1 +; PWR5-NEXT: and r3, r3, r5 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: addic r3, r3, -1 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: addic r4, r4, -1 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_2_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: addi 5, 3, -1 -; PWR6-NEXT: addi 6, 4, -1 -; PWR6-NEXT: and 3, 3, 5 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: addic 3, 3, -1 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: addic 4, 4, -1 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: addi r5, r3, -1 +; PWR6-NEXT: addi r6, r4, -1 +; PWR6-NEXT: and r3, r3, r5 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: addic r3, r3, -1 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: addic r4, r4, -1 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_2_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: xxlxor 35, 35, 35 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 3, -24(1) -; PWR7-NEXT: addi 3, 3, -1 -; PWR7-NEXT: std 3, -8(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: addi 3, 3, -1 -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvw4x 0, 0, 3 -; PWR7-NEXT: addis 3, 2, .LCPI101_0@toc@ha -; PWR7-NEXT: addi 3, 3, .LCPI101_0@toc@l -; PWR7-NEXT: xxland 34, 34, 0 -; PWR7-NEXT: vcmpequw 2, 2, 3 -; PWR7-NEXT: lxvw4x 35, 0, 3 -; PWR7-NEXT: vperm 3, 2, 2, 3 -; PWR7-NEXT: xxland 34, 35, 34 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: xxlxor v3, v3, v3 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r3, -24(r1) +; PWR7-NEXT: addi r3, r3, -1 +; PWR7-NEXT: std r3, -8(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: addi r3, r3, -1 +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvw4x vs0, 0, r3 +; PWR7-NEXT: addis r3, r2, .LCPI101_0@toc@ha +; PWR7-NEXT: addi r3, r3, .LCPI101_0@toc@l +; PWR7-NEXT: xxland v2, v2, vs0 +; PWR7-NEXT: vcmpequw v2, v2, v3 +; PWR7-NEXT: lxvw4x v3, 0, r3 +; PWR7-NEXT: vperm v3, v2, v2, v3 +; PWR7-NEXT: xxland v2, v3, v2 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_2_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 2 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 2 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_2_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 2 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 2 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 2, i64 2> @@ -12066,128 +12070,128 @@ define <2 x i64> @ult_2_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_2_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 2 -; PWR5-NEXT: subfic 3, 3, 2 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 2 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 2 +; PWR5-NEXT: subfic r3, r3, 2 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 2 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_2_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 2 -; PWR6-NEXT: subfic 3, 3, 2 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 2 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 2 +; PWR6-NEXT: subfic r3, r3, 2 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 2 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_2_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 2 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 2 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 2 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 2 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_2_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 2 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 2 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_2_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 2 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 2 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 2, i64 2> @@ -12198,128 +12202,128 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) { define <2 x i64> @ult_3_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_3_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 3 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 3 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_3_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 3 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 3 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_3_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 3 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 3 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 3 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 3 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_3_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 3 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 3 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_3_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 3 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 3 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 3, i64 3> @@ -12330,128 +12334,128 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_3_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 3 -; PWR5-NEXT: subfic 3, 3, 3 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 3 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 3 +; PWR5-NEXT: subfic r3, r3, 3 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 3 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_3_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 3 -; PWR6-NEXT: subfic 3, 3, 3 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 3 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 3 +; PWR6-NEXT: subfic r3, r3, 3 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 3 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_3_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 3 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 3 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 3 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 3 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_3_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 3 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 3 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_3_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 3 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 3 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 3, i64 3> @@ -12462,128 +12466,128 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) { define <2 x i64> @ult_4_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_4_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 4 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 4 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_4_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 4 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 4 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_4_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 4 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 4 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 4 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 4 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_4_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 4 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 4 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_4_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 4 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 4 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 4, i64 4> @@ -12594,128 +12598,128 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_4_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 4 -; PWR5-NEXT: subfic 3, 3, 4 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 4 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 4 +; PWR5-NEXT: subfic r3, r3, 4 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 4 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_4_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 4 -; PWR6-NEXT: subfic 3, 3, 4 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 4 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 4 +; PWR6-NEXT: subfic r3, r3, 4 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 4 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_4_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 4 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 4 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 4 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 4 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_4_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 4 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 4 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_4_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 4 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 4 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 4, i64 4> @@ -12726,128 +12730,128 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) { define <2 x i64> @ult_5_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_5_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 5 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 5 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_5_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 5 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 5 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_5_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 5 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 5 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 5 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 5 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_5_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 5 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 5 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_5_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 5 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 5 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 5, i64 5> @@ -12858,128 +12862,128 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_5_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 5 -; PWR5-NEXT: subfic 3, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 5 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 5 +; PWR5-NEXT: subfic r3, r3, 5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 5 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_5_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 5 -; PWR6-NEXT: subfic 3, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 5 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 5 +; PWR6-NEXT: subfic r3, r3, 5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 5 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_5_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 5 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 5 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 5 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 5 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_5_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 5 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 5 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_5_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 5 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 5 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 5, i64 5> @@ -12990,128 +12994,128 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) { define <2 x i64> @ult_6_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_6_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 6 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 6 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_6_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 6 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 6 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_6_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 6 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 6 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 6 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 6 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_6_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 6 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 6 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_6_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 6 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 6 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 6, i64 6> @@ -13122,128 +13126,128 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_6_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 6 -; PWR5-NEXT: subfic 3, 3, 6 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 6 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 6 +; PWR5-NEXT: subfic r3, r3, 6 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 6 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_6_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 6 -; PWR6-NEXT: subfic 3, 3, 6 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 6 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 6 +; PWR6-NEXT: subfic r3, r3, 6 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 6 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_6_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 6 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 6 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 6 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 6 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_6_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 6 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 6 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_6_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 6 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 6 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 6, i64 6> @@ -13254,128 +13258,128 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) { define <2 x i64> @ult_7_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_7_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 7 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 7 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_7_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 7 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 7 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_7_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 7 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 7 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 7 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 7 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_7_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 7 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 7 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_7_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 7 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 7 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 7, i64 7> @@ -13386,128 +13390,128 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_7_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 7 -; PWR5-NEXT: subfic 3, 3, 7 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 7 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 7 +; PWR5-NEXT: subfic r3, r3, 7 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 7 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_7_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 7 -; PWR6-NEXT: subfic 3, 3, 7 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 7 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 7 +; PWR6-NEXT: subfic r3, r3, 7 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 7 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_7_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 7 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 7 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 7 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 7 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_7_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 7 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 7 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_7_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 7 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 7 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 7, i64 7> @@ -13518,128 +13522,128 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) { define <2 x i64> @ult_8_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_8_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 8 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 8 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_8_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 8 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 8 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_8_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 8 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 8 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 8 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 8 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_8_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 8 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 8 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_8_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 8 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 8 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 8, i64 8> @@ -13650,128 +13654,128 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_8_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 8 -; PWR5-NEXT: subfic 3, 3, 8 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 8 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 8 +; PWR5-NEXT: subfic r3, r3, 8 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 8 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_8_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 8 -; PWR6-NEXT: subfic 3, 3, 8 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 8 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 8 +; PWR6-NEXT: subfic r3, r3, 8 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 8 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_8_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 8 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 8 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 8 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 8 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_8_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 8 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 8 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_8_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 8 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 8 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 8, i64 8> @@ -13782,128 +13786,128 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) { define <2 x i64> @ult_9_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_9_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 9 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 9 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_9_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 9 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 9 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_9_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 9 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 9 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 9 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 9 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_9_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 9 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 9 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_9_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 9 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 9 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 9, i64 9> @@ -13914,128 +13918,128 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_9_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 9 -; PWR5-NEXT: subfic 3, 3, 9 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 9 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 9 +; PWR5-NEXT: subfic r3, r3, 9 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 9 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_9_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 9 -; PWR6-NEXT: subfic 3, 3, 9 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 9 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 9 +; PWR6-NEXT: subfic r3, r3, 9 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 9 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_9_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 9 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 9 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 9 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 9 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_9_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 9 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 9 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_9_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 9 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 9 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 9, i64 9> @@ -14046,128 +14050,128 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) { define <2 x i64> @ult_10_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_10_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 10 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 10 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_10_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 10 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 10 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_10_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 10 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 10 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 10 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 10 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_10_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 10 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 10 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_10_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 10 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 10 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 10, i64 10> @@ -14178,128 +14182,128 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_10_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 10 -; PWR5-NEXT: subfic 3, 3, 10 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 10 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 10 +; PWR5-NEXT: subfic r3, r3, 10 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 10 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_10_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 10 -; PWR6-NEXT: subfic 3, 3, 10 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 10 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 10 +; PWR6-NEXT: subfic r3, r3, 10 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 10 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_10_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 10 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 10 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 10 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 10 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_10_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 10 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 10 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_10_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 10 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 10 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 10, i64 10> @@ -14310,128 +14314,128 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) { define <2 x i64> @ult_11_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_11_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 11 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 11 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_11_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 11 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 11 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_11_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 11 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 11 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 11 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 11 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_11_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 11 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 11 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_11_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 11 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 11 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 11, i64 11> @@ -14442,128 +14446,128 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_11_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 11 -; PWR5-NEXT: subfic 3, 3, 11 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 11 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 11 +; PWR5-NEXT: subfic r3, r3, 11 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 11 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_11_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 11 -; PWR6-NEXT: subfic 3, 3, 11 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 11 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 11 +; PWR6-NEXT: subfic r3, r3, 11 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 11 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_11_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 11 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 11 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 11 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 11 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_11_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 11 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 11 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_11_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 11 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 11 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 11, i64 11> @@ -14574,128 +14578,128 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) { define <2 x i64> @ult_12_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_12_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 12 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 12 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_12_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 12 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 12 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_12_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 12 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 12 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 12 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 12 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_12_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 12 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 12 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_12_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 12 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 12 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 12, i64 12> @@ -14706,128 +14710,128 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_12_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 12 -; PWR5-NEXT: subfic 3, 3, 12 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 12 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 12 +; PWR5-NEXT: subfic r3, r3, 12 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 12 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_12_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 12 -; PWR6-NEXT: subfic 3, 3, 12 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 12 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 12 +; PWR6-NEXT: subfic r3, r3, 12 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 12 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_12_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 12 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 12 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 12 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 12 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_12_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 12 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 12 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_12_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 12 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 12 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 12, i64 12> @@ -14838,128 +14842,128 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) { define <2 x i64> @ult_13_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_13_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 13 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 13 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_13_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 13 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 13 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_13_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 13 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 13 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 13 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 13 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_13_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 13 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 13 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_13_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 13 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 13 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 13, i64 13> @@ -14970,128 +14974,128 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_13_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 13 -; PWR5-NEXT: subfic 3, 3, 13 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 13 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 13 +; PWR5-NEXT: subfic r3, r3, 13 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 13 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_13_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 13 -; PWR6-NEXT: subfic 3, 3, 13 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 13 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 13 +; PWR6-NEXT: subfic r3, r3, 13 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 13 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_13_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 13 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 13 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 13 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 13 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_13_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 13 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 13 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_13_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 13 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 13 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 13, i64 13> @@ -15102,128 +15106,128 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) { define <2 x i64> @ult_14_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_14_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 14 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 14 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_14_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 14 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 14 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_14_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 14 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 14 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 14 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 14 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_14_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 14 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 14 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_14_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 14 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 14 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 14, i64 14> @@ -15234,128 +15238,128 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_14_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 14 -; PWR5-NEXT: subfic 3, 3, 14 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 14 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 14 +; PWR5-NEXT: subfic r3, r3, 14 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 14 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_14_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 14 -; PWR6-NEXT: subfic 3, 3, 14 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 14 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 14 +; PWR6-NEXT: subfic r3, r3, 14 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 14 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_14_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 14 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 14 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 14 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 14 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_14_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 14 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 14 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_14_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 14 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 14 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 14, i64 14> @@ -15366,128 +15370,128 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) { define <2 x i64> @ult_15_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_15_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 15 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 15 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_15_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 15 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 15 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_15_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 15 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 15 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 15 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 15 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_15_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 15 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: vspltisw v3, 15 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_15_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 15 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: vspltisw v3, 15 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 15, i64 15> @@ -15498,128 +15502,128 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_15_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 15 -; PWR5-NEXT: subfic 3, 3, 15 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 15 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 15 +; PWR5-NEXT: subfic r3, r3, 15 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 15 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_15_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 15 -; PWR6-NEXT: subfic 3, 3, 15 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 15 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 15 +; PWR6-NEXT: subfic r3, r3, 15 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 15 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_15_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 15 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 15 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 15 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 15 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_15_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: vspltisw 3, 15 -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: vupklsw 3, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: vspltisw v3, 15 +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: vupklsw v3, v3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_15_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: vspltisw 3, 15 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vupklsw 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: vspltisw v3, 15 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vupklsw v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 15, i64 15> @@ -15630,129 +15634,129 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) { define <2 x i64> @ult_16_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_16_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 16 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 16 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_16_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 16 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 16 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_16_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 16 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 16 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 16 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 16 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_16_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI129_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI129_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI129_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI129_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_16_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 16 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 16 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 16, i64 16> @@ -15763,129 +15767,129 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_16_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 16 -; PWR5-NEXT: subfic 3, 3, 16 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 16 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 16 +; PWR5-NEXT: subfic r3, r3, 16 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 16 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_16_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 16 -; PWR6-NEXT: subfic 3, 3, 16 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 16 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 16 +; PWR6-NEXT: subfic r3, r3, 16 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 16 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_16_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 16 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 16 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 16 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 16 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_16_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI130_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI130_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI130_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI130_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_16_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 16 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 16 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 16, i64 16> @@ -15896,129 +15900,129 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) { define <2 x i64> @ult_17_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_17_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 17 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 17 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_17_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 17 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 17 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_17_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 17 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 17 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 17 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 17 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_17_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI131_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI131_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI131_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI131_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_17_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 17 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 17 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 17, i64 17> @@ -16029,129 +16033,129 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_17_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 17 -; PWR5-NEXT: subfic 3, 3, 17 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 17 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 17 +; PWR5-NEXT: subfic r3, r3, 17 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 17 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_17_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 17 -; PWR6-NEXT: subfic 3, 3, 17 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 17 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 17 +; PWR6-NEXT: subfic r3, r3, 17 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 17 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_17_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 17 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 17 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 17 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 17 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_17_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI132_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI132_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI132_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI132_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_17_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 17 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 17 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 17, i64 17> @@ -16162,129 +16166,129 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) { define <2 x i64> @ult_18_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_18_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 18 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 18 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_18_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 18 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 18 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_18_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 18 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 18 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 18 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 18 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_18_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI133_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI133_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI133_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI133_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_18_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 18 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 18 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 18, i64 18> @@ -16295,129 +16299,129 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_18_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 18 -; PWR5-NEXT: subfic 3, 3, 18 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 18 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 18 +; PWR5-NEXT: subfic r3, r3, 18 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 18 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_18_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 18 -; PWR6-NEXT: subfic 3, 3, 18 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 18 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 18 +; PWR6-NEXT: subfic r3, r3, 18 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 18 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_18_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 18 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 18 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 18 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 18 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_18_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI134_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI134_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI134_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI134_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_18_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 18 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 18 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 18, i64 18> @@ -16428,129 +16432,129 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) { define <2 x i64> @ult_19_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_19_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 19 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 19 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_19_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 19 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 19 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_19_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 19 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 19 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 19 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 19 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_19_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI135_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI135_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI135_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI135_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_19_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 19 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 19 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 19, i64 19> @@ -16561,129 +16565,129 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_19_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 19 -; PWR5-NEXT: subfic 3, 3, 19 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 19 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 19 +; PWR5-NEXT: subfic r3, r3, 19 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 19 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_19_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 19 -; PWR6-NEXT: subfic 3, 3, 19 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 19 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 19 +; PWR6-NEXT: subfic r3, r3, 19 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 19 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_19_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 19 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 19 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 19 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 19 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_19_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI136_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI136_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI136_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI136_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_19_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 19 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 19 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 19, i64 19> @@ -16694,129 +16698,129 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) { define <2 x i64> @ult_20_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_20_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 20 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 20 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_20_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 20 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 20 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_20_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 20 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 20 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 20 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 20 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_20_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI137_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI137_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI137_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI137_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_20_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 20 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 20 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 20, i64 20> @@ -16827,129 +16831,129 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_20_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 20 -; PWR5-NEXT: subfic 3, 3, 20 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 20 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 20 +; PWR5-NEXT: subfic r3, r3, 20 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 20 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_20_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 20 -; PWR6-NEXT: subfic 3, 3, 20 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 20 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 20 +; PWR6-NEXT: subfic r3, r3, 20 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 20 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_20_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 20 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 20 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 20 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 20 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_20_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI138_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI138_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI138_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI138_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_20_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 20 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 20 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 20, i64 20> @@ -16960,129 +16964,129 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) { define <2 x i64> @ult_21_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_21_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 21 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 21 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_21_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 21 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 21 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_21_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 21 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 21 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 21 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 21 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_21_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI139_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI139_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI139_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI139_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_21_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 21 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 21 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 21, i64 21> @@ -17093,129 +17097,129 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_21_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 21 -; PWR5-NEXT: subfic 3, 3, 21 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 21 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 21 +; PWR5-NEXT: subfic r3, r3, 21 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 21 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_21_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 21 -; PWR6-NEXT: subfic 3, 3, 21 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 21 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 21 +; PWR6-NEXT: subfic r3, r3, 21 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 21 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_21_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 21 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 21 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 21 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 21 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_21_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI140_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI140_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI140_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI140_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_21_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 21 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 21 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 21, i64 21> @@ -17226,129 +17230,129 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) { define <2 x i64> @ult_22_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_22_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 22 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 22 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_22_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 22 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 22 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_22_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 22 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 22 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 22 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 22 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_22_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI141_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI141_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI141_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI141_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_22_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 22 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 22 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 22, i64 22> @@ -17359,129 +17363,129 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_22_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 22 -; PWR5-NEXT: subfic 3, 3, 22 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 22 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 22 +; PWR5-NEXT: subfic r3, r3, 22 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 22 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_22_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 22 -; PWR6-NEXT: subfic 3, 3, 22 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 22 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 22 +; PWR6-NEXT: subfic r3, r3, 22 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 22 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_22_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 22 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 22 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 22 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 22 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_22_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI142_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI142_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI142_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI142_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_22_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 22 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 22 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 22, i64 22> @@ -17492,129 +17496,129 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) { define <2 x i64> @ult_23_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_23_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 23 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 23 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_23_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 23 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 23 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_23_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 23 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 23 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 23 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 23 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_23_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI143_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI143_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI143_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI143_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_23_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 23 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 23 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 23, i64 23> @@ -17625,129 +17629,129 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_23_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 23 -; PWR5-NEXT: subfic 3, 3, 23 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 23 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 23 +; PWR5-NEXT: subfic r3, r3, 23 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 23 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_23_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 23 -; PWR6-NEXT: subfic 3, 3, 23 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 23 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 23 +; PWR6-NEXT: subfic r3, r3, 23 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 23 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_23_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 23 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 23 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 23 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 23 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_23_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI144_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI144_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI144_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI144_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_23_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 23 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 23 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 23, i64 23> @@ -17758,129 +17762,129 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) { define <2 x i64> @ult_24_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_24_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 24 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 24 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_24_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 24 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 24 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_24_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 24 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 24 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 24 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 24 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_24_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI145_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI145_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI145_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI145_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_24_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 24 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 24 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 24, i64 24> @@ -17891,129 +17895,129 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_24_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 24 -; PWR5-NEXT: subfic 3, 3, 24 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 24 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 24 +; PWR5-NEXT: subfic r3, r3, 24 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 24 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_24_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 24 -; PWR6-NEXT: subfic 3, 3, 24 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 24 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 24 +; PWR6-NEXT: subfic r3, r3, 24 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 24 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_24_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 24 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 24 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 24 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 24 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_24_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI146_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI146_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI146_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI146_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_24_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 24 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 24 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 24, i64 24> @@ -18024,129 +18028,129 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) { define <2 x i64> @ult_25_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_25_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 25 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 25 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_25_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 25 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 25 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_25_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 25 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 25 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 25 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 25 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_25_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI147_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI147_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI147_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI147_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_25_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 25 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 25 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 25, i64 25> @@ -18157,129 +18161,129 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_25_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 25 -; PWR5-NEXT: subfic 3, 3, 25 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 25 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 25 +; PWR5-NEXT: subfic r3, r3, 25 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 25 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_25_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 25 -; PWR6-NEXT: subfic 3, 3, 25 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 25 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 25 +; PWR6-NEXT: subfic r3, r3, 25 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 25 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_25_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 25 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 25 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 25 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 25 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_25_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI148_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI148_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI148_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI148_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_25_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 25 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 25 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 25, i64 25> @@ -18290,129 +18294,129 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) { define <2 x i64> @ult_26_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_26_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 26 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 26 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_26_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 26 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 26 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_26_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 26 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 26 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 26 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 26 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_26_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI149_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI149_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI149_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI149_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_26_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 26 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 26 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 26, i64 26> @@ -18423,129 +18427,129 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_26_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 26 -; PWR5-NEXT: subfic 3, 3, 26 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 26 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 26 +; PWR5-NEXT: subfic r3, r3, 26 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 26 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_26_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 26 -; PWR6-NEXT: subfic 3, 3, 26 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 26 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 26 +; PWR6-NEXT: subfic r3, r3, 26 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 26 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_26_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 26 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 26 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 26 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 26 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_26_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI150_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI150_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI150_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI150_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_26_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 26 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 26 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 26, i64 26> @@ -18556,129 +18560,129 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) { define <2 x i64> @ult_27_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_27_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 27 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 27 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_27_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 27 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 27 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_27_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 27 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 27 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 27 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 27 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_27_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI151_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI151_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI151_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI151_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_27_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 27 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 27 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 27, i64 27> @@ -18689,129 +18693,129 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_27_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 27 -; PWR5-NEXT: subfic 3, 3, 27 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 27 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 27 +; PWR5-NEXT: subfic r3, r3, 27 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 27 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_27_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 27 -; PWR6-NEXT: subfic 3, 3, 27 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 27 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 27 +; PWR6-NEXT: subfic r3, r3, 27 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 27 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_27_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 27 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 27 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 27 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 27 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_27_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI152_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI152_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI152_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI152_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_27_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 27 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 27 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 27, i64 27> @@ -18822,129 +18826,129 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) { define <2 x i64> @ult_28_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_28_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 28 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 28 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_28_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 28 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 28 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_28_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 28 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 28 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 28 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 28 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_28_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI153_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI153_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI153_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI153_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_28_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 28 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 28 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 28, i64 28> @@ -18955,129 +18959,129 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_28_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 28 -; PWR5-NEXT: subfic 3, 3, 28 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 28 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 28 +; PWR5-NEXT: subfic r3, r3, 28 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 28 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_28_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 28 -; PWR6-NEXT: subfic 3, 3, 28 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 28 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 28 +; PWR6-NEXT: subfic r3, r3, 28 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 28 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_28_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 28 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 28 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 28 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 28 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_28_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI154_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI154_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI154_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI154_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_28_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 28 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 28 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 28, i64 28> @@ -19088,129 +19092,129 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) { define <2 x i64> @ult_29_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_29_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 29 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 29 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_29_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 29 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 29 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_29_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 29 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 29 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 29 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 29 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_29_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI155_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI155_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI155_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI155_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_29_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 29 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 29 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 29, i64 29> @@ -19221,129 +19225,129 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_29_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 29 -; PWR5-NEXT: subfic 3, 3, 29 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 29 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 29 +; PWR5-NEXT: subfic r3, r3, 29 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 29 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_29_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 29 -; PWR6-NEXT: subfic 3, 3, 29 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 29 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 29 +; PWR6-NEXT: subfic r3, r3, 29 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 29 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_29_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 29 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 29 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 29 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 29 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_29_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI156_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI156_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI156_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI156_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_29_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 29 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 29 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 29, i64 29> @@ -19354,129 +19358,129 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) { define <2 x i64> @ult_30_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_30_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 30 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 30 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_30_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 30 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 30 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_30_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 30 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 30 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 30 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 30 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_30_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI157_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI157_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI157_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI157_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_30_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 30 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 30 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 30, i64 30> @@ -19487,129 +19491,129 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_30_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 30 -; PWR5-NEXT: subfic 3, 3, 30 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 30 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 30 +; PWR5-NEXT: subfic r3, r3, 30 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 30 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_30_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 30 -; PWR6-NEXT: subfic 3, 3, 30 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 30 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 30 +; PWR6-NEXT: subfic r3, r3, 30 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 30 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_30_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 30 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 30 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 30 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 30 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_30_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI158_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI158_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI158_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI158_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_30_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 30 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 30 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 30, i64 30> @@ -19620,129 +19624,129 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) { define <2 x i64> @ult_31_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_31_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 31 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 31 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_31_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 31 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 31 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_31_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 31 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 31 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 31 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 31 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_31_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI159_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI159_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI159_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI159_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_31_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 31 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 31 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 31, i64 31> @@ -19753,129 +19757,129 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_31_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 31 -; PWR5-NEXT: subfic 3, 3, 31 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 31 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 31 +; PWR5-NEXT: subfic r3, r3, 31 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 31 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_31_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 31 -; PWR6-NEXT: subfic 3, 3, 31 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 31 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 31 +; PWR6-NEXT: subfic r3, r3, 31 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 31 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_31_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 31 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 31 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 31 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 31 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_31_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI160_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI160_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI160_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI160_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_31_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 31 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 31 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 31, i64 31> @@ -19886,129 +19890,129 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) { define <2 x i64> @ult_32_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_32_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 32 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 32 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_32_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 32 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 32 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_32_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 32 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 32 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 32 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 32 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_32_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI161_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI161_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI161_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI161_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_32_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 32 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 32 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 32, i64 32> @@ -20019,129 +20023,129 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_32_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 32 -; PWR5-NEXT: subfic 3, 3, 32 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 32 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 32 +; PWR5-NEXT: subfic r3, r3, 32 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 32 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_32_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 32 -; PWR6-NEXT: subfic 3, 3, 32 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 32 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 32 +; PWR6-NEXT: subfic r3, r3, 32 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 32 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_32_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 32 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 32 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 32 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 32 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_32_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI162_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI162_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI162_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI162_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_32_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 32 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 32 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 32, i64 32> @@ -20152,129 +20156,129 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) { define <2 x i64> @ult_33_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_33_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 33 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 33 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_33_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 33 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 33 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_33_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 33 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 33 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 33 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 33 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_33_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI163_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI163_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI163_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI163_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_33_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 33 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 33 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 33, i64 33> @@ -20285,129 +20289,129 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_33_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 33 -; PWR5-NEXT: subfic 3, 3, 33 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 33 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 33 +; PWR5-NEXT: subfic r3, r3, 33 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 33 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_33_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 33 -; PWR6-NEXT: subfic 3, 3, 33 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 33 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 33 +; PWR6-NEXT: subfic r3, r3, 33 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 33 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_33_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 33 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 33 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 33 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 33 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_33_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI164_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI164_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI164_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI164_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_33_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 33 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 33 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 33, i64 33> @@ -20418,129 +20422,129 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) { define <2 x i64> @ult_34_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_34_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 34 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 34 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_34_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 34 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 34 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_34_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 34 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 34 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 34 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 34 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_34_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI165_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI165_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI165_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI165_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_34_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 34 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 34 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 34, i64 34> @@ -20551,129 +20555,129 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_34_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 34 -; PWR5-NEXT: subfic 3, 3, 34 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 34 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 34 +; PWR5-NEXT: subfic r3, r3, 34 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 34 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_34_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 34 -; PWR6-NEXT: subfic 3, 3, 34 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 34 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 34 +; PWR6-NEXT: subfic r3, r3, 34 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 34 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_34_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 34 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 34 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 34 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 34 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_34_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI166_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI166_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI166_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI166_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_34_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 34 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 34 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 34, i64 34> @@ -20684,129 +20688,129 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) { define <2 x i64> @ult_35_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_35_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 35 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 35 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_35_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 35 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 35 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_35_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 35 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 35 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 35 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 35 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_35_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI167_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI167_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI167_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI167_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_35_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 35 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 35 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 35, i64 35> @@ -20817,129 +20821,129 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_35_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 35 -; PWR5-NEXT: subfic 3, 3, 35 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 35 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 35 +; PWR5-NEXT: subfic r3, r3, 35 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 35 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_35_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 35 -; PWR6-NEXT: subfic 3, 3, 35 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 35 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 35 +; PWR6-NEXT: subfic r3, r3, 35 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 35 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_35_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 35 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 35 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 35 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 35 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_35_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI168_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI168_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI168_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI168_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_35_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 35 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 35 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 35, i64 35> @@ -20950,129 +20954,129 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) { define <2 x i64> @ult_36_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_36_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 36 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 36 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_36_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 36 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 36 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_36_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 36 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 36 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 36 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 36 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_36_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI169_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI169_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI169_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI169_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_36_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 36 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 36 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 36, i64 36> @@ -21083,129 +21087,129 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_36_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 36 -; PWR5-NEXT: subfic 3, 3, 36 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 36 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 36 +; PWR5-NEXT: subfic r3, r3, 36 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 36 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_36_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 36 -; PWR6-NEXT: subfic 3, 3, 36 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 36 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 36 +; PWR6-NEXT: subfic r3, r3, 36 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 36 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_36_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 36 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 36 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 36 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 36 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_36_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI170_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI170_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI170_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI170_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_36_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 36 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 36 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 36, i64 36> @@ -21216,129 +21220,129 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) { define <2 x i64> @ult_37_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_37_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 37 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 37 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_37_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 37 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 37 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_37_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 37 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 37 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 37 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 37 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_37_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI171_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI171_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI171_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI171_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_37_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 37 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 37 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 37, i64 37> @@ -21349,129 +21353,129 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_37_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 37 -; PWR5-NEXT: subfic 3, 3, 37 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 37 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 37 +; PWR5-NEXT: subfic r3, r3, 37 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 37 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_37_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 37 -; PWR6-NEXT: subfic 3, 3, 37 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 37 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 37 +; PWR6-NEXT: subfic r3, r3, 37 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 37 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_37_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 37 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 37 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 37 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 37 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_37_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI172_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI172_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI172_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI172_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_37_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 37 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 37 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 37, i64 37> @@ -21482,129 +21486,129 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) { define <2 x i64> @ult_38_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_38_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 38 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 38 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_38_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 38 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 38 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_38_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 38 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 38 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 38 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 38 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_38_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI173_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI173_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI173_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI173_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_38_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 38 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 38 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 38, i64 38> @@ -21615,129 +21619,129 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_38_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 38 -; PWR5-NEXT: subfic 3, 3, 38 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 38 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 38 +; PWR5-NEXT: subfic r3, r3, 38 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 38 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_38_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 38 -; PWR6-NEXT: subfic 3, 3, 38 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 38 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 38 +; PWR6-NEXT: subfic r3, r3, 38 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 38 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_38_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 38 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 38 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 38 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 38 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_38_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI174_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI174_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI174_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI174_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_38_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 38 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 38 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 38, i64 38> @@ -21748,129 +21752,129 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) { define <2 x i64> @ult_39_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_39_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 39 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 39 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_39_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 39 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 39 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_39_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 39 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 39 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 39 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 39 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_39_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI175_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI175_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI175_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI175_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_39_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 39 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 39 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 39, i64 39> @@ -21881,129 +21885,129 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_39_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 39 -; PWR5-NEXT: subfic 3, 3, 39 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 39 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 39 +; PWR5-NEXT: subfic r3, r3, 39 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 39 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_39_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 39 -; PWR6-NEXT: subfic 3, 3, 39 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 39 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 39 +; PWR6-NEXT: subfic r3, r3, 39 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 39 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_39_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 39 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 39 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 39 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 39 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_39_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI176_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI176_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI176_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI176_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_39_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 39 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 39 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 39, i64 39> @@ -22014,129 +22018,129 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) { define <2 x i64> @ult_40_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_40_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 40 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 40 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_40_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 40 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 40 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_40_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 40 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 40 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 40 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 40 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_40_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI177_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI177_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI177_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI177_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_40_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 40 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 40 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 40, i64 40> @@ -22147,129 +22151,129 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_40_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 40 -; PWR5-NEXT: subfic 3, 3, 40 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 40 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 40 +; PWR5-NEXT: subfic r3, r3, 40 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 40 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_40_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 40 -; PWR6-NEXT: subfic 3, 3, 40 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 40 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 40 +; PWR6-NEXT: subfic r3, r3, 40 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 40 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_40_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 40 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 40 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 40 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 40 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_40_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI178_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI178_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI178_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI178_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_40_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 40 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 40 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 40, i64 40> @@ -22280,129 +22284,129 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) { define <2 x i64> @ult_41_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_41_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 41 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 41 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_41_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 41 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 41 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_41_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 41 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 41 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 41 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 41 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_41_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI179_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI179_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI179_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI179_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_41_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 41 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 41 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 41, i64 41> @@ -22413,129 +22417,129 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_41_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 41 -; PWR5-NEXT: subfic 3, 3, 41 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 41 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 41 +; PWR5-NEXT: subfic r3, r3, 41 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 41 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_41_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 41 -; PWR6-NEXT: subfic 3, 3, 41 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 41 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 41 +; PWR6-NEXT: subfic r3, r3, 41 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 41 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_41_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 41 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 41 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 41 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 41 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_41_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI180_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI180_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI180_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI180_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_41_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 41 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 41 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 41, i64 41> @@ -22546,129 +22550,129 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) { define <2 x i64> @ult_42_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_42_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 42 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 42 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_42_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 42 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 42 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_42_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 42 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 42 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 42 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 42 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_42_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI181_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI181_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI181_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI181_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_42_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 42 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 42 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 42, i64 42> @@ -22679,129 +22683,129 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_42_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 42 -; PWR5-NEXT: subfic 3, 3, 42 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 42 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 42 +; PWR5-NEXT: subfic r3, r3, 42 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 42 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_42_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 42 -; PWR6-NEXT: subfic 3, 3, 42 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 42 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 42 +; PWR6-NEXT: subfic r3, r3, 42 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 42 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_42_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 42 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 42 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 42 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 42 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_42_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI182_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI182_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI182_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI182_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_42_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 42 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 42 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 42, i64 42> @@ -22812,129 +22816,129 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) { define <2 x i64> @ult_43_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_43_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 43 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 43 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_43_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 43 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 43 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_43_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 43 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 43 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 43 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 43 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_43_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI183_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI183_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI183_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI183_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_43_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 43 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 43 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 43, i64 43> @@ -22945,129 +22949,129 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_43_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 43 -; PWR5-NEXT: subfic 3, 3, 43 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 43 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 43 +; PWR5-NEXT: subfic r3, r3, 43 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 43 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_43_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 43 -; PWR6-NEXT: subfic 3, 3, 43 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 43 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 43 +; PWR6-NEXT: subfic r3, r3, 43 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 43 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_43_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 43 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 43 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 43 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 43 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_43_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI184_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI184_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI184_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI184_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_43_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 43 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 43 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 43, i64 43> @@ -23078,129 +23082,129 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) { define <2 x i64> @ult_44_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_44_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 44 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 44 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_44_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 44 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 44 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_44_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 44 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 44 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 44 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 44 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_44_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI185_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI185_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI185_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI185_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_44_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 44 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 44 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 44, i64 44> @@ -23211,129 +23215,129 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_44_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 44 -; PWR5-NEXT: subfic 3, 3, 44 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 44 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 44 +; PWR5-NEXT: subfic r3, r3, 44 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 44 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_44_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 44 -; PWR6-NEXT: subfic 3, 3, 44 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 44 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 44 +; PWR6-NEXT: subfic r3, r3, 44 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 44 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_44_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 44 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 44 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 44 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 44 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_44_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI186_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI186_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI186_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI186_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_44_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 44 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 44 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 44, i64 44> @@ -23344,129 +23348,129 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) { define <2 x i64> @ult_45_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_45_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 45 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 45 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_45_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 45 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 45 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_45_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 45 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 45 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 45 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 45 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_45_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI187_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI187_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI187_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI187_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_45_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 45 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 45 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 45, i64 45> @@ -23477,129 +23481,129 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_45_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 45 -; PWR5-NEXT: subfic 3, 3, 45 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 45 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 45 +; PWR5-NEXT: subfic r3, r3, 45 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 45 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_45_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 45 -; PWR6-NEXT: subfic 3, 3, 45 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 45 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 45 +; PWR6-NEXT: subfic r3, r3, 45 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 45 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_45_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 45 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 45 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 45 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 45 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_45_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI188_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI188_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI188_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI188_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_45_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 45 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 45 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 45, i64 45> @@ -23610,129 +23614,129 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) { define <2 x i64> @ult_46_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_46_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 46 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 46 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_46_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 46 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 46 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_46_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 46 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 46 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 46 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 46 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_46_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI189_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI189_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI189_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI189_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_46_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 46 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 46 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 46, i64 46> @@ -23743,129 +23747,129 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_46_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 46 -; PWR5-NEXT: subfic 3, 3, 46 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 46 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 46 +; PWR5-NEXT: subfic r3, r3, 46 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 46 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_46_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 46 -; PWR6-NEXT: subfic 3, 3, 46 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 46 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 46 +; PWR6-NEXT: subfic r3, r3, 46 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 46 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_46_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 46 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 46 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 46 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 46 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_46_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI190_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI190_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI190_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI190_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_46_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 46 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 46 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 46, i64 46> @@ -23876,129 +23880,129 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) { define <2 x i64> @ult_47_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_47_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 47 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 47 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_47_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 47 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 47 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_47_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 47 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 47 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 47 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 47 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_47_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI191_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI191_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI191_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI191_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_47_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 47 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 47 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 47, i64 47> @@ -24009,129 +24013,129 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_47_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 47 -; PWR5-NEXT: subfic 3, 3, 47 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 47 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 47 +; PWR5-NEXT: subfic r3, r3, 47 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 47 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_47_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 47 -; PWR6-NEXT: subfic 3, 3, 47 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 47 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 47 +; PWR6-NEXT: subfic r3, r3, 47 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 47 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_47_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 47 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 47 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 47 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 47 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_47_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI192_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI192_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI192_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI192_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_47_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 47 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 47 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 47, i64 47> @@ -24142,129 +24146,129 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) { define <2 x i64> @ult_48_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_48_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 48 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 48 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_48_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 48 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 48 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_48_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 48 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 48 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 48 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 48 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_48_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI193_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI193_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI193_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI193_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_48_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 48 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 48 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 48, i64 48> @@ -24275,129 +24279,129 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_48_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 48 -; PWR5-NEXT: subfic 3, 3, 48 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 48 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 48 +; PWR5-NEXT: subfic r3, r3, 48 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 48 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_48_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 48 -; PWR6-NEXT: subfic 3, 3, 48 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 48 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 48 +; PWR6-NEXT: subfic r3, r3, 48 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 48 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_48_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 48 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 48 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 48 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 48 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_48_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI194_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI194_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI194_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI194_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_48_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 48 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 48 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 48, i64 48> @@ -24408,129 +24412,129 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) { define <2 x i64> @ult_49_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_49_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 49 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 49 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_49_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 49 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 49 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_49_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 49 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 49 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 49 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 49 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_49_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI195_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI195_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI195_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI195_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_49_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 49 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 49 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 49, i64 49> @@ -24541,129 +24545,129 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_49_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 49 -; PWR5-NEXT: subfic 3, 3, 49 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 49 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 49 +; PWR5-NEXT: subfic r3, r3, 49 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 49 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_49_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 49 -; PWR6-NEXT: subfic 3, 3, 49 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 49 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 49 +; PWR6-NEXT: subfic r3, r3, 49 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 49 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_49_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 49 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 49 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 49 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 49 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_49_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI196_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI196_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI196_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI196_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_49_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 49 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 49 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 49, i64 49> @@ -24674,129 +24678,129 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) { define <2 x i64> @ult_50_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_50_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 50 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 50 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_50_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 50 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 50 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_50_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 50 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 50 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 50 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 50 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_50_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI197_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI197_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI197_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI197_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_50_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 50 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 50 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 50, i64 50> @@ -24807,129 +24811,129 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_50_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 50 -; PWR5-NEXT: subfic 3, 3, 50 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 50 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 50 +; PWR5-NEXT: subfic r3, r3, 50 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 50 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_50_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 50 -; PWR6-NEXT: subfic 3, 3, 50 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 50 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 50 +; PWR6-NEXT: subfic r3, r3, 50 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 50 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_50_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 50 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 50 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 50 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 50 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_50_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI198_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI198_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI198_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI198_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_50_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 50 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 50 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 50, i64 50> @@ -24940,129 +24944,129 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) { define <2 x i64> @ult_51_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_51_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 51 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 51 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_51_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 51 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 51 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_51_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 51 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 51 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 51 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 51 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_51_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI199_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI199_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI199_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI199_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_51_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 51 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 51 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 51, i64 51> @@ -25073,129 +25077,129 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_51_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 51 -; PWR5-NEXT: subfic 3, 3, 51 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 51 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 51 +; PWR5-NEXT: subfic r3, r3, 51 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 51 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_51_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 51 -; PWR6-NEXT: subfic 3, 3, 51 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 51 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 51 +; PWR6-NEXT: subfic r3, r3, 51 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 51 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_51_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 51 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 51 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 51 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 51 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_51_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI200_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI200_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI200_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI200_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_51_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 51 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 51 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 51, i64 51> @@ -25206,129 +25210,129 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) { define <2 x i64> @ult_52_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_52_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 52 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 52 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_52_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 52 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 52 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_52_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 52 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 52 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 52 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 52 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_52_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI201_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI201_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI201_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI201_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_52_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 52 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 52 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 52, i64 52> @@ -25339,129 +25343,129 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_52_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 52 -; PWR5-NEXT: subfic 3, 3, 52 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 52 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 52 +; PWR5-NEXT: subfic r3, r3, 52 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 52 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_52_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 52 -; PWR6-NEXT: subfic 3, 3, 52 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 52 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 52 +; PWR6-NEXT: subfic r3, r3, 52 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 52 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_52_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 52 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 52 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 52 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 52 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_52_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI202_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI202_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI202_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI202_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_52_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 52 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 52 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 52, i64 52> @@ -25472,129 +25476,129 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) { define <2 x i64> @ult_53_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_53_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 53 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 53 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_53_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 53 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 53 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_53_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 53 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 53 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 53 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 53 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_53_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI203_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI203_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI203_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI203_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_53_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 53 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 53 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 53, i64 53> @@ -25605,129 +25609,129 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_53_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 53 -; PWR5-NEXT: subfic 3, 3, 53 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 53 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 53 +; PWR5-NEXT: subfic r3, r3, 53 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 53 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_53_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 53 -; PWR6-NEXT: subfic 3, 3, 53 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 53 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 53 +; PWR6-NEXT: subfic r3, r3, 53 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 53 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_53_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 53 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 53 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 53 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 53 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_53_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI204_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI204_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI204_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI204_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_53_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 53 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 53 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 53, i64 53> @@ -25738,129 +25742,129 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) { define <2 x i64> @ult_54_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_54_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 54 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 54 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_54_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 54 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 54 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_54_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 54 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 54 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 54 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 54 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_54_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI205_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI205_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI205_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI205_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_54_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 54 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 54 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 54, i64 54> @@ -25871,129 +25875,129 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_54_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 54 -; PWR5-NEXT: subfic 3, 3, 54 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 54 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 54 +; PWR5-NEXT: subfic r3, r3, 54 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 54 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_54_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 54 -; PWR6-NEXT: subfic 3, 3, 54 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 54 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 54 +; PWR6-NEXT: subfic r3, r3, 54 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 54 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_54_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 54 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 54 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 54 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 54 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_54_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI206_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI206_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI206_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI206_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_54_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 54 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 54 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 54, i64 54> @@ -26004,129 +26008,129 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) { define <2 x i64> @ult_55_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_55_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 55 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 55 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_55_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 55 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 55 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_55_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 55 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 55 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 55 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 55 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_55_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI207_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI207_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI207_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI207_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_55_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 55 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 55 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 55, i64 55> @@ -26137,129 +26141,129 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_55_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 55 -; PWR5-NEXT: subfic 3, 3, 55 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 55 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 55 +; PWR5-NEXT: subfic r3, r3, 55 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 55 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_55_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 55 -; PWR6-NEXT: subfic 3, 3, 55 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 55 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 55 +; PWR6-NEXT: subfic r3, r3, 55 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 55 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_55_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 55 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 55 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 55 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 55 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_55_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI208_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI208_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI208_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI208_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_55_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 55 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 55 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 55, i64 55> @@ -26270,129 +26274,129 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) { define <2 x i64> @ult_56_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_56_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_56_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_56_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 56 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 56 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 56 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 56 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_56_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI209_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI209_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI209_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI209_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_56_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 56 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 56 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 56, i64 56> @@ -26403,129 +26407,129 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_56_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 56 -; PWR5-NEXT: subfic 3, 3, 56 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 56 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 56 +; PWR5-NEXT: subfic r3, r3, 56 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 56 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_56_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 56 -; PWR6-NEXT: subfic 3, 3, 56 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 56 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 56 +; PWR6-NEXT: subfic r3, r3, 56 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 56 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_56_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 56 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 56 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 56 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 56 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_56_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI210_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI210_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI210_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI210_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_56_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 56 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 56 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 56, i64 56> @@ -26536,129 +26540,129 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) { define <2 x i64> @ult_57_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_57_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 57 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 57 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_57_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 57 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 57 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_57_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 57 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 57 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 57 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 57 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_57_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI211_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI211_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI211_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI211_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_57_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 57 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 57 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 57, i64 57> @@ -26669,129 +26673,129 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_57_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 57 -; PWR5-NEXT: subfic 3, 3, 57 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 57 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 57 +; PWR5-NEXT: subfic r3, r3, 57 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 57 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_57_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 57 -; PWR6-NEXT: subfic 3, 3, 57 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 57 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 57 +; PWR6-NEXT: subfic r3, r3, 57 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 57 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_57_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 57 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 57 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 57 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 57 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_57_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI212_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI212_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI212_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI212_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_57_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 57 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 57 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 57, i64 57> @@ -26802,129 +26806,129 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) { define <2 x i64> @ult_58_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_58_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 58 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 58 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_58_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 58 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 58 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_58_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 58 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 58 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 58 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 58 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_58_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI213_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI213_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI213_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI213_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_58_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 58 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 58 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 58, i64 58> @@ -26935,129 +26939,129 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_58_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 58 -; PWR5-NEXT: subfic 3, 3, 58 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 58 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 58 +; PWR5-NEXT: subfic r3, r3, 58 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 58 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_58_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 58 -; PWR6-NEXT: subfic 3, 3, 58 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 58 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 58 +; PWR6-NEXT: subfic r3, r3, 58 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 58 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_58_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 58 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 58 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 58 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 58 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_58_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI214_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI214_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI214_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI214_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_58_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 58 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 58 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 58, i64 58> @@ -27068,129 +27072,129 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) { define <2 x i64> @ult_59_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_59_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 59 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 59 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_59_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 59 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 59 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_59_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 59 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 59 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 59 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 59 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_59_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI215_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI215_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI215_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI215_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_59_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 59 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 59 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 59, i64 59> @@ -27201,129 +27205,129 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_59_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 59 -; PWR5-NEXT: subfic 3, 3, 59 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 59 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 59 +; PWR5-NEXT: subfic r3, r3, 59 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 59 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_59_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 59 -; PWR6-NEXT: subfic 3, 3, 59 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 59 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 59 +; PWR6-NEXT: subfic r3, r3, 59 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 59 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_59_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 59 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 59 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 59 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 59 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_59_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI216_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI216_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI216_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI216_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_59_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 59 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 59 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 59, i64 59> @@ -27334,129 +27338,129 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) { define <2 x i64> @ult_60_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_60_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 60 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 60 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_60_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 60 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 60 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_60_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 60 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 60 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 60 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 60 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_60_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI217_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI217_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI217_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI217_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_60_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 60 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 60 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 60, i64 60> @@ -27467,129 +27471,129 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_60_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 60 -; PWR5-NEXT: subfic 3, 3, 60 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 60 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 60 +; PWR5-NEXT: subfic r3, r3, 60 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 60 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_60_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 60 -; PWR6-NEXT: subfic 3, 3, 60 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 60 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 60 +; PWR6-NEXT: subfic r3, r3, 60 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 60 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_60_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 60 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 60 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 60 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 60 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_60_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI218_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI218_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI218_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI218_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_60_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 60 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 60 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 60, i64 60> @@ -27600,129 +27604,129 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) { define <2 x i64> @ult_61_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_61_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 61 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 61 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_61_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 61 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 61 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_61_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 61 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 61 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 61 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 61 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_61_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI219_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI219_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI219_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI219_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_61_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 61 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 61 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 61, i64 61> @@ -27733,129 +27737,129 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_61_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 61 -; PWR5-NEXT: subfic 3, 3, 61 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 61 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 61 +; PWR5-NEXT: subfic r3, r3, 61 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 61 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_61_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 61 -; PWR6-NEXT: subfic 3, 3, 61 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 61 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 61 +; PWR6-NEXT: subfic r3, r3, 61 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 61 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_61_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 61 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 61 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 61 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 61 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_61_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI220_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI220_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI220_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI220_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_61_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 61 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 61 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 61, i64 61> @@ -27866,129 +27870,129 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) { define <2 x i64> @ult_62_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_62_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 62 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 62 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_62_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 62 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 62 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_62_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 62 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 62 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 62 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 62 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_62_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI221_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI221_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI221_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI221_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_62_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 62 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 62 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 62, i64 62> @@ -27999,129 +28003,129 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) { define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ugt_62_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: li 5, 62 -; PWR5-NEXT: subfic 3, 3, 62 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 5, 5 -; PWR5-NEXT: subfic 4, 4, 62 -; PWR5-NEXT: subfe 4, 5, 5 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: li r5, 62 +; PWR5-NEXT: subfic r3, r3, 62 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r5, r5 +; PWR5-NEXT: subfic r4, r4, 62 +; PWR5-NEXT: subfe r4, r5, r5 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ugt_62_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: li 5, 62 -; PWR6-NEXT: subfic 3, 3, 62 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 5, 5 -; PWR6-NEXT: subfic 4, 4, 62 -; PWR6-NEXT: subfe 4, 5, 5 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: li r5, 62 +; PWR6-NEXT: subfic r3, r3, 62 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r5, r5 +; PWR6-NEXT: subfic r4, r4, 62 +; PWR6-NEXT: subfe r4, r5, r5 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ugt_62_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 62 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: iselgt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 62 -; PWR7-NEXT: iselgt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 62 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: iselgt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 62 +; PWR7-NEXT: iselgt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ugt_62_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI222_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI222_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 2, 3 +; PWR8-NEXT: addis r3, r2, .LCPI222_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI222_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v2, v3 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ugt_62_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 62 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 2, 3 +; PWR9-NEXT: xxspltib v3, 62 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v2, v3 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ugt <2 x i64> %2, <i64 62, i64 62> @@ -28132,129 +28136,129 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) { define <2 x i64> @ult_63_v2i64(<2 x i64> %0) { ; PWR5-LABEL: ult_63_v2i64: ; PWR5: # %bb.0: -; PWR5-NEXT: lis 5, 21845 -; PWR5-NEXT: lis 6, 13107 -; PWR5-NEXT: ori 5, 5, 21845 -; PWR5-NEXT: rotldi 8, 4, 63 -; PWR5-NEXT: rotldi 9, 3, 63 -; PWR5-NEXT: rldimi 5, 5, 32, 0 -; PWR5-NEXT: and 8, 8, 5 -; PWR5-NEXT: and 5, 9, 5 -; PWR5-NEXT: ori 6, 6, 13107 -; PWR5-NEXT: sub 3, 3, 5 -; PWR5-NEXT: rldimi 6, 6, 32, 0 -; PWR5-NEXT: sub 4, 4, 8 -; PWR5-NEXT: and 8, 3, 6 -; PWR5-NEXT: rotldi 3, 3, 62 -; PWR5-NEXT: and 3, 3, 6 -; PWR5-NEXT: lis 7, 3855 -; PWR5-NEXT: and 5, 4, 6 -; PWR5-NEXT: rotldi 4, 4, 62 -; PWR5-NEXT: add 3, 8, 3 -; PWR5-NEXT: lis 9, 257 -; PWR5-NEXT: ori 7, 7, 3855 -; PWR5-NEXT: and 4, 4, 6 -; PWR5-NEXT: rldicl 6, 3, 60, 4 -; PWR5-NEXT: ori 9, 9, 257 -; PWR5-NEXT: rldimi 7, 7, 32, 0 -; PWR5-NEXT: add 4, 5, 4 -; PWR5-NEXT: add 3, 3, 6 -; PWR5-NEXT: rldimi 9, 9, 32, 0 -; PWR5-NEXT: rldicl 5, 4, 60, 4 -; PWR5-NEXT: and 3, 3, 7 -; PWR5-NEXT: add 4, 4, 5 -; PWR5-NEXT: mulld 3, 3, 9 -; PWR5-NEXT: and 4, 4, 7 -; PWR5-NEXT: rldicl 3, 3, 8, 56 -; PWR5-NEXT: li 5, 63 -; PWR5-NEXT: mulld 4, 4, 9 -; PWR5-NEXT: subc 6, 3, 5 -; PWR5-NEXT: rldicl 4, 4, 8, 56 -; PWR5-NEXT: subfe 3, 3, 3 -; PWR5-NEXT: subc 5, 4, 5 -; PWR5-NEXT: subfe 4, 4, 4 +; PWR5-NEXT: lis r5, 21845 +; PWR5-NEXT: lis r6, 13107 +; PWR5-NEXT: ori r5, r5, 21845 +; PWR5-NEXT: rotldi r8, r4, 63 +; PWR5-NEXT: rotldi r9, r3, 63 +; PWR5-NEXT: rldimi r5, r5, 32, 0 +; PWR5-NEXT: and r8, r8, r5 +; PWR5-NEXT: and r5, r9, r5 +; PWR5-NEXT: ori r6, r6, 13107 +; PWR5-NEXT: sub r3, r3, r5 +; PWR5-NEXT: rldimi r6, r6, 32, 0 +; PWR5-NEXT: sub r4, r4, r8 +; PWR5-NEXT: and r8, r3, r6 +; PWR5-NEXT: rotldi r3, r3, 62 +; PWR5-NEXT: and r3, r3, r6 +; PWR5-NEXT: lis r7, 3855 +; PWR5-NEXT: and r5, r4, r6 +; PWR5-NEXT: rotldi r4, r4, 62 +; PWR5-NEXT: add r3, r8, r3 +; PWR5-NEXT: lis r9, 257 +; PWR5-NEXT: ori r7, r7, 3855 +; PWR5-NEXT: and r4, r4, r6 +; PWR5-NEXT: rldicl r6, r3, 60, 4 +; PWR5-NEXT: ori r9, r9, 257 +; PWR5-NEXT: rldimi r7, r7, 32, 0 +; PWR5-NEXT: add r4, r5, r4 +; PWR5-NEXT: add r3, r3, r6 +; PWR5-NEXT: rldimi r9, r9, 32, 0 +; PWR5-NEXT: rldicl r5, r4, 60, 4 +; PWR5-NEXT: and r3, r3, r7 +; PWR5-NEXT: add r4, r4, r5 +; PWR5-NEXT: mulld r3, r3, r9 +; PWR5-NEXT: and r4, r4, r7 +; PWR5-NEXT: rldicl r3, r3, 8, 56 +; PWR5-NEXT: li r5, 63 +; PWR5-NEXT: mulld r4, r4, r9 +; PWR5-NEXT: subc r6, r3, r5 +; PWR5-NEXT: rldicl r4, r4, 8, 56 +; PWR5-NEXT: subfe r3, r3, r3 +; PWR5-NEXT: subc r5, r4, r5 +; PWR5-NEXT: subfe r4, r4, r4 ; PWR5-NEXT: blr ; ; PWR6-LABEL: ult_63_v2i64: ; PWR6: # %bb.0: -; PWR6-NEXT: lis 5, 21845 -; PWR6-NEXT: lis 6, 13107 -; PWR6-NEXT: ori 5, 5, 21845 -; PWR6-NEXT: rotldi 8, 4, 63 -; PWR6-NEXT: rotldi 9, 3, 63 -; PWR6-NEXT: rldimi 5, 5, 32, 0 -; PWR6-NEXT: and 8, 8, 5 -; PWR6-NEXT: and 5, 9, 5 -; PWR6-NEXT: ori 6, 6, 13107 -; PWR6-NEXT: sub 3, 3, 5 -; PWR6-NEXT: rldimi 6, 6, 32, 0 -; PWR6-NEXT: sub 4, 4, 8 -; PWR6-NEXT: and 8, 3, 6 -; PWR6-NEXT: rotldi 3, 3, 62 -; PWR6-NEXT: and 3, 3, 6 -; PWR6-NEXT: lis 7, 3855 -; PWR6-NEXT: and 5, 4, 6 -; PWR6-NEXT: rotldi 4, 4, 62 -; PWR6-NEXT: add 3, 8, 3 -; PWR6-NEXT: lis 9, 257 -; PWR6-NEXT: ori 7, 7, 3855 -; PWR6-NEXT: and 4, 4, 6 -; PWR6-NEXT: rldicl 6, 3, 60, 4 -; PWR6-NEXT: ori 9, 9, 257 -; PWR6-NEXT: rldimi 7, 7, 32, 0 -; PWR6-NEXT: add 4, 5, 4 -; PWR6-NEXT: add 3, 3, 6 -; PWR6-NEXT: rldimi 9, 9, 32, 0 -; PWR6-NEXT: rldicl 5, 4, 60, 4 -; PWR6-NEXT: and 3, 3, 7 -; PWR6-NEXT: add 4, 4, 5 -; PWR6-NEXT: mulld 3, 3, 9 -; PWR6-NEXT: and 4, 4, 7 -; PWR6-NEXT: rldicl 3, 3, 8, 56 -; PWR6-NEXT: li 5, 63 -; PWR6-NEXT: mulld 4, 4, 9 -; PWR6-NEXT: subc 6, 3, 5 -; PWR6-NEXT: rldicl 4, 4, 8, 56 -; PWR6-NEXT: subfe 3, 3, 3 -; PWR6-NEXT: subc 5, 4, 5 -; PWR6-NEXT: subfe 4, 4, 4 +; PWR6-NEXT: lis r5, 21845 +; PWR6-NEXT: lis r6, 13107 +; PWR6-NEXT: ori r5, r5, 21845 +; PWR6-NEXT: rotldi r8, r4, 63 +; PWR6-NEXT: rotldi r9, r3, 63 +; PWR6-NEXT: rldimi r5, r5, 32, 0 +; PWR6-NEXT: and r8, r8, r5 +; PWR6-NEXT: and r5, r9, r5 +; PWR6-NEXT: ori r6, r6, 13107 +; PWR6-NEXT: sub r3, r3, r5 +; PWR6-NEXT: rldimi r6, r6, 32, 0 +; PWR6-NEXT: sub r4, r4, r8 +; PWR6-NEXT: and r8, r3, r6 +; PWR6-NEXT: rotldi r3, r3, 62 +; PWR6-NEXT: and r3, r3, r6 +; PWR6-NEXT: lis r7, 3855 +; PWR6-NEXT: and r5, r4, r6 +; PWR6-NEXT: rotldi r4, r4, 62 +; PWR6-NEXT: add r3, r8, r3 +; PWR6-NEXT: lis r9, 257 +; PWR6-NEXT: ori r7, r7, 3855 +; PWR6-NEXT: and r4, r4, r6 +; PWR6-NEXT: rldicl r6, r3, 60, 4 +; PWR6-NEXT: ori r9, r9, 257 +; PWR6-NEXT: rldimi r7, r7, 32, 0 +; PWR6-NEXT: add r4, r5, r4 +; PWR6-NEXT: add r3, r3, r6 +; PWR6-NEXT: rldimi r9, r9, 32, 0 +; PWR6-NEXT: rldicl r5, r4, 60, 4 +; PWR6-NEXT: and r3, r3, r7 +; PWR6-NEXT: add r4, r4, r5 +; PWR6-NEXT: mulld r3, r3, r9 +; PWR6-NEXT: and r4, r4, r7 +; PWR6-NEXT: rldicl r3, r3, 8, 56 +; PWR6-NEXT: li r5, 63 +; PWR6-NEXT: mulld r4, r4, r9 +; PWR6-NEXT: subc r6, r3, r5 +; PWR6-NEXT: rldicl r4, r4, 8, 56 +; PWR6-NEXT: subfe r3, r3, r3 +; PWR6-NEXT: subc r5, r4, r5 +; PWR6-NEXT: subfe r4, r4, r4 ; PWR6-NEXT: blr ; ; PWR7-LABEL: ult_63_v2i64: ; PWR7: # %bb.0: -; PWR7-NEXT: addi 3, 1, -32 -; PWR7-NEXT: li 5, -1 -; PWR7-NEXT: stxvd2x 34, 0, 3 -; PWR7-NEXT: ld 4, -24(1) -; PWR7-NEXT: ld 3, -32(1) -; PWR7-NEXT: popcntd 4, 4 -; PWR7-NEXT: popcntd 3, 3 -; PWR7-NEXT: cmpldi 4, 63 -; PWR7-NEXT: li 4, 0 -; PWR7-NEXT: isellt 6, 5, 4 -; PWR7-NEXT: cmpldi 3, 63 -; PWR7-NEXT: isellt 3, 5, 4 -; PWR7-NEXT: std 6, -8(1) -; PWR7-NEXT: std 3, -16(1) -; PWR7-NEXT: addi 3, 1, -16 -; PWR7-NEXT: lxvd2x 34, 0, 3 +; PWR7-NEXT: addi r3, r1, -32 +; PWR7-NEXT: li r5, -1 +; PWR7-NEXT: stxvd2x v2, 0, r3 +; PWR7-NEXT: ld r4, -24(r1) +; PWR7-NEXT: ld r3, -32(r1) +; PWR7-NEXT: popcntd r4, r4 +; PWR7-NEXT: popcntd r3, r3 +; PWR7-NEXT: cmpldi r4, 63 +; PWR7-NEXT: li r4, 0 +; PWR7-NEXT: isellt r6, r5, r4 +; PWR7-NEXT: cmpldi r3, 63 +; PWR7-NEXT: isellt r3, r5, r4 +; PWR7-NEXT: std r6, -8(r1) +; PWR7-NEXT: std r3, -16(r1) +; PWR7-NEXT: addi r3, r1, -16 +; PWR7-NEXT: lxvd2x v2, 0, r3 ; PWR7-NEXT: blr ; ; PWR8-LABEL: ult_63_v2i64: ; PWR8: # %bb.0: -; PWR8-NEXT: addis 3, 2, .LCPI223_0@toc@ha -; PWR8-NEXT: vpopcntd 2, 2 -; PWR8-NEXT: addi 3, 3, .LCPI223_0@toc@l -; PWR8-NEXT: lxvd2x 35, 0, 3 -; PWR8-NEXT: vcmpgtud 2, 3, 2 +; PWR8-NEXT: addis r3, r2, .LCPI223_0@toc@ha +; PWR8-NEXT: vpopcntd v2, v2 +; PWR8-NEXT: addi r3, r3, .LCPI223_0@toc@l +; PWR8-NEXT: lxvd2x v3, 0, r3 +; PWR8-NEXT: vcmpgtud v2, v3, v2 ; PWR8-NEXT: blr ; ; PWR9-LABEL: ult_63_v2i64: ; PWR9: # %bb.0: -; PWR9-NEXT: xxspltib 35, 63 -; PWR9-NEXT: vpopcntd 2, 2 -; PWR9-NEXT: vextsb2d 3, 3 -; PWR9-NEXT: vcmpgtud 2, 3, 2 +; PWR9-NEXT: xxspltib v3, 63 +; PWR9-NEXT: vpopcntd v2, v2 +; PWR9-NEXT: vextsb2d v3, v3 +; PWR9-NEXT: vcmpgtud v2, v3, v2 ; PWR9-NEXT: blr %2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0) %3 = icmp ult <2 x i64> %2, <i64 63, i64 63> diff --git a/llvm/test/CodeGen/PowerPC/vsro-vsr-vsrq-dag-combine.ll b/llvm/test/CodeGen/PowerPC/vsro-vsr-vsrq-dag-combine.ll new file mode 100644 index 000000000000..afbdae6dfa09 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vsro-vsr-vsrq-dag-combine.ll @@ -0,0 +1,337 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 + +; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER10-LE + +; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64-ibm-aix-xcoff \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER10-BE + +; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc-ibm-aix-xcoff \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER3210-BE + +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER9-LE + +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \ +; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWER9-BE + +; Test VSRO + VSR peephole optimization to VSRQ on Power10+ +; This should combine consecutive VSRO (Vector Shift Right Octet) and VSR (Vector Shift Right) +; instructions using the same shift amount into a single VSRQ (Vector Shift Right Quadword) +; instruction when targeting Power10 or later processors. +declare <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32>, <4 x i32>) + +define <16 x i8> @shiftright128_v16i8(<16 x i8> %in, i8 zeroext %sh) { +; POWER10-LE-LABEL: shiftright128_v16i8: +; POWER10-LE: # %bb.0: # %entry +; POWER10-LE-NEXT: mtvsrd v3, r5 +; POWER10-LE-NEXT: vspltb v3, v3, 7 +; POWER10-LE-NEXT: vsrq v2, v2, v3 +; POWER10-LE-NEXT: blr +; +; POWER10-BE-LABEL: shiftright128_v16i8: +; POWER10-BE: # %bb.0: # %entry +; POWER10-BE-NEXT: mtvsrwz v3, r3 +; POWER10-BE-NEXT: vspltb v3, v3, 7 +; POWER10-BE-NEXT: vsrq v2, v2, v3 +; POWER10-BE-NEXT: blr +; +; POWER3210-BE-LABEL: shiftright128_v16i8: +; POWER3210-BE: # %bb.0: # %entry +; POWER3210-BE-NEXT: mtvsrwz v3, r3 +; POWER3210-BE-NEXT: vspltb v3, v3, 7 +; POWER3210-BE-NEXT: vsrq v2, v2, v3 +; POWER3210-BE-NEXT: blr +; +; POWER9-LE-LABEL: shiftright128_v16i8: +; POWER9-LE: # %bb.0: # %entry +; POWER9-LE-NEXT: mtvsrd v3, r5 +; POWER9-LE-NEXT: vspltb v3, v3, 7 +; POWER9-LE-NEXT: vsro v2, v2, v3 +; POWER9-LE-NEXT: vsr v2, v2, v3 +; POWER9-LE-NEXT: blr +; +; POWER9-BE-LABEL: shiftright128_v16i8: +; POWER9-BE: # %bb.0: # %entry +; POWER9-BE-NEXT: mtvsrwz v3, r3 +; POWER9-BE-NEXT: vspltb v3, v3, 7 +; POWER9-BE-NEXT: vsro v2, v2, v3 +; POWER9-BE-NEXT: vsr v2, v2, v3 +; POWER9-BE-NEXT: blr +entry: + %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0 + %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer + %0 = bitcast <16 x i8> %in to <4 x i32> + %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32> + %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1) + %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1) + %4 = bitcast <4 x i32> %3 to <16 x i8> + ret <16 x i8> %4 +} + +define <4 x i32> @shiftright128_v4i32(<4 x i32> %in, i8 zeroext %sh) { +; POWER10-LE-LABEL: shiftright128_v4i32: +; POWER10-LE: # %bb.0: # %entry +; POWER10-LE-NEXT: mtvsrd v3, r5 +; POWER10-LE-NEXT: vspltb v3, v3, 7 +; POWER10-LE-NEXT: vsrq v2, v2, v3 +; POWER10-LE-NEXT: blr +; +; POWER10-BE-LABEL: shiftright128_v4i32: +; POWER10-BE: # %bb.0: # %entry +; POWER10-BE-NEXT: mtvsrwz v3, r3 +; POWER10-BE-NEXT: vspltb v3, v3, 7 +; POWER10-BE-NEXT: vsrq v2, v2, v3 +; POWER10-BE-NEXT: blr +; +; POWER3210-BE-LABEL: shiftright128_v4i32: +; POWER3210-BE: # %bb.0: # %entry +; POWER3210-BE-NEXT: mtvsrwz v3, r3 +; POWER3210-BE-NEXT: vspltb v3, v3, 7 +; POWER3210-BE-NEXT: vsrq v2, v2, v3 +; POWER3210-BE-NEXT: blr +; +; POWER9-LE-LABEL: shiftright128_v4i32: +; POWER9-LE: # %bb.0: # %entry +; POWER9-LE-NEXT: mtvsrd v3, r5 +; POWER9-LE-NEXT: vspltb v3, v3, 7 +; POWER9-LE-NEXT: vsro v2, v2, v3 +; POWER9-LE-NEXT: vsr v2, v2, v3 +; POWER9-LE-NEXT: blr +; +; POWER9-BE-LABEL: shiftright128_v4i32: +; POWER9-BE: # %bb.0: # %entry +; POWER9-BE-NEXT: mtvsrwz v3, r3 +; POWER9-BE-NEXT: vspltb v3, v3, 7 +; POWER9-BE-NEXT: vsro v2, v2, v3 +; POWER9-BE-NEXT: vsr v2, v2, v3 +; POWER9-BE-NEXT: blr +entry: + %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0 + %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer + %0 = bitcast <16 x i8> %splat.splat.i to <4 x i32> + %1 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %in, <4 x i32> %0) + %2 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %1, <4 x i32> %0) + ret <4 x i32> %2 +} + +define <2 x i64> @shiftright128_v2i64(<2 x i64> %in, i8 zeroext %sh) { +; POWER10-LE-LABEL: shiftright128_v2i64: +; POWER10-LE: # %bb.0: # %entry +; POWER10-LE-NEXT: mtvsrd v3, r5 +; POWER10-LE-NEXT: vspltb v3, v3, 7 +; POWER10-LE-NEXT: vsrq v2, v2, v3 +; POWER10-LE-NEXT: blr +; +; POWER10-BE-LABEL: shiftright128_v2i64: +; POWER10-BE: # %bb.0: # %entry +; POWER10-BE-NEXT: mtvsrwz v3, r3 +; POWER10-BE-NEXT: vspltb v3, v3, 7 +; POWER10-BE-NEXT: vsrq v2, v2, v3 +; POWER10-BE-NEXT: blr +; +; POWER3210-BE-LABEL: shiftright128_v2i64: +; POWER3210-BE: # %bb.0: # %entry +; POWER3210-BE-NEXT: mtvsrwz v3, r3 +; POWER3210-BE-NEXT: vspltb v3, v3, 7 +; POWER3210-BE-NEXT: vsrq v2, v2, v3 +; POWER3210-BE-NEXT: blr +; +; POWER9-LE-LABEL: shiftright128_v2i64: +; POWER9-LE: # %bb.0: # %entry +; POWER9-LE-NEXT: mtvsrd v3, r5 +; POWER9-LE-NEXT: vspltb v3, v3, 7 +; POWER9-LE-NEXT: vsro v2, v2, v3 +; POWER9-LE-NEXT: vsr v2, v2, v3 +; POWER9-LE-NEXT: blr +; +; POWER9-BE-LABEL: shiftright128_v2i64: +; POWER9-BE: # %bb.0: # %entry +; POWER9-BE-NEXT: mtvsrwz v3, r3 +; POWER9-BE-NEXT: vspltb v3, v3, 7 +; POWER9-BE-NEXT: vsro v2, v2, v3 +; POWER9-BE-NEXT: vsr v2, v2, v3 +; POWER9-BE-NEXT: blr +entry: + %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0 + %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer + %0 = bitcast <2 x i64> %in to <4 x i32> + %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32> + %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1) + %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1) + %4 = bitcast <4 x i32> %3 to <2 x i64> + ret <2 x i64> %4 +} + +define <8 x i16> @shiftright128_v8i16(<8 x i16> %in, i8 zeroext %sh) { +; POWER10-LE-LABEL: shiftright128_v8i16: +; POWER10-LE: # %bb.0: # %entry +; POWER10-LE-NEXT: mtvsrd v3, r5 +; POWER10-LE-NEXT: vspltb v3, v3, 7 +; POWER10-LE-NEXT: vsrq v2, v2, v3 +; POWER10-LE-NEXT: blr +; +; POWER10-BE-LABEL: shiftright128_v8i16: +; POWER10-BE: # %bb.0: # %entry +; POWER10-BE-NEXT: mtvsrwz v3, r3 +; POWER10-BE-NEXT: vspltb v3, v3, 7 +; POWER10-BE-NEXT: vsrq v2, v2, v3 +; POWER10-BE-NEXT: blr +; +; POWER3210-BE-LABEL: shiftright128_v8i16: +; POWER3210-BE: # %bb.0: # %entry +; POWER3210-BE-NEXT: mtvsrwz v3, r3 +; POWER3210-BE-NEXT: vspltb v3, v3, 7 +; POWER3210-BE-NEXT: vsrq v2, v2, v3 +; POWER3210-BE-NEXT: blr +; +; POWER9-LE-LABEL: shiftright128_v8i16: +; POWER9-LE: # %bb.0: # %entry +; POWER9-LE-NEXT: mtvsrd v3, r5 +; POWER9-LE-NEXT: vspltb v3, v3, 7 +; POWER9-LE-NEXT: vsro v2, v2, v3 +; POWER9-LE-NEXT: vsr v2, v2, v3 +; POWER9-LE-NEXT: blr +; +; POWER9-BE-LABEL: shiftright128_v8i16: +; POWER9-BE: # %bb.0: # %entry +; POWER9-BE-NEXT: mtvsrwz v3, r3 +; POWER9-BE-NEXT: vspltb v3, v3, 7 +; POWER9-BE-NEXT: vsro v2, v2, v3 +; POWER9-BE-NEXT: vsr v2, v2, v3 +; POWER9-BE-NEXT: blr +entry: + %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0 + %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer + %0 = bitcast <8 x i16> %in to <4 x i32> + %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32> + %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1) + %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1) + %4 = bitcast <4 x i32> %3 to <8 x i16> + ret <8 x i16> %4 +} + +; Test case with different vectors (should not optimize - different shift amount registers) +define <16 x i8> @no_optimization_different_shifts(<16 x i8> %in, i8 zeroext %sh1, i8 zeroext %sh2) { +; POWER10-LE-LABEL: no_optimization_different_shifts: +; POWER10-LE: # %bb.0: # %entry +; POWER10-LE-NEXT: mtvsrd v3, r5 +; POWER10-LE-NEXT: mtvsrd v4, r6 +; POWER10-LE-NEXT: vspltb v3, v3, 7 +; POWER10-LE-NEXT: vspltb v4, v4, 7 +; POWER10-LE-NEXT: vsro v2, v2, v3 +; POWER10-LE-NEXT: vsr v2, v2, v4 +; POWER10-LE-NEXT: blr +; +; POWER10-BE-LABEL: no_optimization_different_shifts: +; POWER10-BE: # %bb.0: # %entry +; POWER10-BE-NEXT: mtvsrwz v3, r3 +; POWER10-BE-NEXT: mtvsrwz v4, r4 +; POWER10-BE-NEXT: vspltb v3, v3, 7 +; POWER10-BE-NEXT: vspltb v4, v4, 7 +; POWER10-BE-NEXT: vsro v2, v2, v3 +; POWER10-BE-NEXT: vsr v2, v2, v4 +; POWER10-BE-NEXT: blr +; +; POWER3210-BE-LABEL: no_optimization_different_shifts: +; POWER3210-BE: # %bb.0: # %entry +; POWER3210-BE-NEXT: mtvsrwz v3, r3 +; POWER3210-BE-NEXT: mtvsrwz v4, r4 +; POWER3210-BE-NEXT: vspltb v3, v3, 7 +; POWER3210-BE-NEXT: vspltb v4, v4, 7 +; POWER3210-BE-NEXT: vsro v2, v2, v3 +; POWER3210-BE-NEXT: vsr v2, v2, v4 +; POWER3210-BE-NEXT: blr +; +; POWER9-LE-LABEL: no_optimization_different_shifts: +; POWER9-LE: # %bb.0: # %entry +; POWER9-LE-NEXT: mtvsrd v3, r5 +; POWER9-LE-NEXT: mtvsrd v4, r6 +; POWER9-LE-NEXT: vspltb v3, v3, 7 +; POWER9-LE-NEXT: vspltb v4, v4, 7 +; POWER9-LE-NEXT: vsro v2, v2, v3 +; POWER9-LE-NEXT: vsr v2, v2, v4 +; POWER9-LE-NEXT: blr +; +; POWER9-BE-LABEL: no_optimization_different_shifts: +; POWER9-BE: # %bb.0: # %entry +; POWER9-BE-NEXT: mtvsrwz v3, r3 +; POWER9-BE-NEXT: mtvsrwz v4, r4 +; POWER9-BE-NEXT: vspltb v3, v3, 7 +; POWER9-BE-NEXT: vspltb v4, v4, 7 +; POWER9-BE-NEXT: vsro v2, v2, v3 +; POWER9-BE-NEXT: vsr v2, v2, v4 +; POWER9-BE-NEXT: blr +entry: + %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh1, i64 0 + %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer + %splat.splatinsert.i2 = insertelement <16 x i8> poison, i8 %sh2, i64 0 + %splat.splat.i2 = shufflevector <16 x i8> %splat.splatinsert.i2, <16 x i8> poison, <16 x i32> zeroinitializer + %0 = bitcast <16 x i8> %in to <4 x i32> + %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32> + %2 = bitcast <16 x i8> %splat.splat.i2 to <4 x i32> + %3 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1) + %4 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %3, <4 x i32> %2) + %5 = bitcast <4 x i32> %4 to <16 x i8> + ret <16 x i8> %5 +} + +; Test case with multiple uses of VSRO result (should not optimize) +define <16 x i8> @no_optimization_multiple_uses(<16 x i8> %in, i8 zeroext %sh) { +; POWER10-LE-LABEL: no_optimization_multiple_uses: +; POWER10-LE: # %bb.0: # %entry +; POWER10-LE-NEXT: mtvsrd v3, r5 +; POWER10-LE-NEXT: vspltb v3, v3, 7 +; POWER10-LE-NEXT: vsro v2, v2, v3 +; POWER10-LE-NEXT: vsr v3, v2, v3 +; POWER10-LE-NEXT: vaddubm v2, v2, v3 +; POWER10-LE-NEXT: blr +; +; POWER10-BE-LABEL: no_optimization_multiple_uses: +; POWER10-BE: # %bb.0: # %entry +; POWER10-BE-NEXT: mtvsrwz v3, r3 +; POWER10-BE-NEXT: vspltb v3, v3, 7 +; POWER10-BE-NEXT: vsro v2, v2, v3 +; POWER10-BE-NEXT: vsr v3, v2, v3 +; POWER10-BE-NEXT: vaddubm v2, v2, v3 +; POWER10-BE-NEXT: blr +; +; POWER3210-BE-LABEL: no_optimization_multiple_uses: +; POWER3210-BE: # %bb.0: # %entry +; POWER3210-BE-NEXT: mtvsrwz v3, r3 +; POWER3210-BE-NEXT: vspltb v3, v3, 7 +; POWER3210-BE-NEXT: vsro v2, v2, v3 +; POWER3210-BE-NEXT: vsr v3, v2, v3 +; POWER3210-BE-NEXT: vaddubm v2, v2, v3 +; POWER3210-BE-NEXT: blr +; +; POWER9-LE-LABEL: no_optimization_multiple_uses: +; POWER9-LE: # %bb.0: # %entry +; POWER9-LE-NEXT: mtvsrd v3, r5 +; POWER9-LE-NEXT: vspltb v3, v3, 7 +; POWER9-LE-NEXT: vsro v2, v2, v3 +; POWER9-LE-NEXT: vsr v3, v2, v3 +; POWER9-LE-NEXT: vaddubm v2, v2, v3 +; POWER9-LE-NEXT: blr +; +; POWER9-BE-LABEL: no_optimization_multiple_uses: +; POWER9-BE: # %bb.0: # %entry +; POWER9-BE-NEXT: mtvsrwz v3, r3 +; POWER9-BE-NEXT: vspltb v3, v3, 7 +; POWER9-BE-NEXT: vsro v2, v2, v3 +; POWER9-BE-NEXT: vsr v3, v2, v3 +; POWER9-BE-NEXT: vaddubm v2, v2, v3 +; POWER9-BE-NEXT: blr +entry: + %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %sh, i64 0 + %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer + %0 = bitcast <16 x i8> %in to <4 x i32> + %1 = bitcast <16 x i8> %splat.splat.i to <4 x i32> + %2 = tail call <4 x i32> @llvm.ppc.altivec.vsro(<4 x i32> %0, <4 x i32> %1) + %3 = tail call <4 x i32> @llvm.ppc.altivec.vsr(<4 x i32> %2, <4 x i32> %1) + %4 = bitcast <4 x i32> %3 to <16 x i8> + %5 = bitcast <4 x i32> %2 to <16 x i8> + %6 = add <16 x i8> %5, %4 + ret <16 x i8> %6 +} diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll index c366fd5f0a8c..a51e392279d5 100644 --- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll +++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-b.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; Test file to verify the emission of Vector Selection instructions when ternary operators are used. +; Test file to verify the emission of Vector Evaluation instructions when ternary operators are used. ; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s @@ -15,10 +15,9 @@ define <4 x i32> @ternary_A_and_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> % ; CHECK-LABEL: ternary_A_and_BC_B_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 49 ; CHECK-NEXT: blr entry: %and = and <4 x i32> %B, %C @@ -31,11 +30,10 @@ define <2 x i64> @ternary_A_and_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> % ; CHECK-LABEL: ternary_A_and_BC_B_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 49 ; CHECK-NEXT: blr entry: %and = and <2 x i64> %B, %C @@ -48,10 +46,9 @@ define <16 x i8> @ternary_A_and_BC_B_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_and_BC_B_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 49 ; CHECK-NEXT: blr entry: %and = and <16 x i8> %B, %C @@ -64,10 +61,9 @@ define <8 x i16> @ternary_A_and_BC_B_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> % ; CHECK-LABEL: ternary_A_and_BC_B_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 49 ; CHECK-NEXT: blr entry: %and = and <8 x i16> %B, %C @@ -80,10 +76,9 @@ define <4 x i32> @ternary_A_nor_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> % ; CHECK-LABEL: ternary_A_nor_BC_B_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 56 ; CHECK-NEXT: blr entry: %or = or <4 x i32> %B, %C @@ -97,11 +92,10 @@ define <2 x i64> @ternary_A_nor_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> % ; CHECK-LABEL: ternary_A_nor_BC_B_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 56 ; CHECK-NEXT: blr entry: %or = or <2 x i64> %B, %C @@ -115,10 +109,9 @@ define <16 x i8> @ternary_A_nor_BC_B_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_nor_BC_B_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 56 ; CHECK-NEXT: blr entry: %or = or <16 x i8> %B, %C @@ -132,10 +125,9 @@ define <8 x i16> @ternary_A_nor_BC_B_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> % ; CHECK-LABEL: ternary_A_nor_BC_B_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 56 ; CHECK-NEXT: blr entry: %or = or <8 x i16> %B, %C @@ -149,10 +141,9 @@ define <4 x i32> @ternary_A_eqv_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> % ; CHECK-LABEL: ternary_A_eqv_BC_B_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 57 ; CHECK-NEXT: blr entry: %xor = xor <4 x i32> %B, %C @@ -166,11 +157,10 @@ define <2 x i64> @ternary_A_eqv_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> % ; CHECK-LABEL: ternary_A_eqv_BC_B_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 57 ; CHECK-NEXT: blr entry: %xor = xor <2 x i64> %B, %C @@ -184,10 +174,9 @@ define <16 x i8> @ternary_A_eqv_BC_B_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_eqv_BC_B_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 57 ; CHECK-NEXT: blr entry: %xor = xor <16 x i8> %B, %C @@ -201,10 +190,9 @@ define <8 x i16> @ternary_A_eqv_BC_B_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> % ; CHECK-LABEL: ternary_A_eqv_BC_B_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 57 ; CHECK-NEXT: blr entry: %xor = xor <8 x i16> %B, %C @@ -218,10 +206,9 @@ define <4 x i32> @ternary_A_nand_BC_B_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> ; CHECK-LABEL: ternary_A_nand_BC_B_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 62 ; CHECK-NEXT: blr entry: %and = and <4 x i32> %B, %C @@ -235,11 +222,10 @@ define <2 x i64> @ternary_A_nand_BC_B_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> ; CHECK-LABEL: ternary_A_nand_BC_B_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 62 ; CHECK-NEXT: blr entry: %and = and <2 x i64> %B, %C @@ -253,10 +239,9 @@ define <16 x i8> @ternary_A_nand_BC_B_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_nand_BC_B_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 62 ; CHECK-NEXT: blr entry: %and = and <16 x i8> %B, %C @@ -270,10 +255,9 @@ define <8 x i16> @ternary_A_nand_BC_B_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> ; CHECK-LABEL: ternary_A_nand_BC_B_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v3, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 62 ; CHECK-NEXT: blr entry: %and = and <8 x i16> %B, %C diff --git a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll index f70f1d093f06..54bf6c03f8c1 100644 --- a/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll +++ b/llvm/test/CodeGen/PowerPC/xxeval-vselect-x-c.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; Test file to verify the emission of Vector Selection instructions when ternary operators are used. +; Test file to verify the emission of Vector Evaluation instructions when ternary operators are used. ; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s @@ -15,10 +15,9 @@ define <4 x i32> @ternary_A_and_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> % ; CHECK-LABEL: ternary_A_and_BC_C_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 81 ; CHECK-NEXT: blr entry: %and = and <4 x i32> %B, %C @@ -31,11 +30,10 @@ define <2 x i64> @ternary_A_and_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> % ; CHECK-LABEL: ternary_A_and_BC_C_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 81 ; CHECK-NEXT: blr entry: %and = and <2 x i64> %B, %C @@ -48,10 +46,9 @@ define <16 x i8> @ternary_A_and_BC_C_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_and_BC_C_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 81 ; CHECK-NEXT: blr entry: %and = and <16 x i8> %B, %C @@ -64,10 +61,9 @@ define <8 x i16> @ternary_A_and_BC_C_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> % ; CHECK-LABEL: ternary_A_and_BC_C_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxland vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 81 ; CHECK-NEXT: blr entry: %and = and <8 x i16> %B, %C @@ -80,10 +76,9 @@ define <4 x i32> @ternary_A_nor_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> % ; CHECK-LABEL: ternary_A_nor_BC_C_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 88 ; CHECK-NEXT: blr entry: %or = or <4 x i32> %B, %C @@ -97,11 +92,10 @@ define <2 x i64> @ternary_A_nor_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> % ; CHECK-LABEL: ternary_A_nor_BC_C_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 88 ; CHECK-NEXT: blr entry: %or = or <2 x i64> %B, %C @@ -115,10 +109,9 @@ define <16 x i8> @ternary_A_nor_BC_C_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_nor_BC_C_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 88 ; CHECK-NEXT: blr entry: %or = or <16 x i8> %B, %C @@ -132,10 +125,9 @@ define <8 x i16> @ternary_A_nor_BC_C_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> % ; CHECK-LABEL: ternary_A_nor_BC_C_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlnor vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 88 ; CHECK-NEXT: blr entry: %or = or <8 x i16> %B, %C @@ -149,10 +141,9 @@ define <4 x i32> @ternary_A_eqv_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> % ; CHECK-LABEL: ternary_A_eqv_BC_C_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 89 ; CHECK-NEXT: blr entry: %xor = xor <4 x i32> %B, %C @@ -166,11 +157,10 @@ define <2 x i64> @ternary_A_eqv_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> % ; CHECK-LABEL: ternary_A_eqv_BC_C_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 89 ; CHECK-NEXT: blr entry: %xor = xor <2 x i64> %B, %C @@ -184,10 +174,9 @@ define <16 x i8> @ternary_A_eqv_BC_C_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_eqv_BC_C_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 89 ; CHECK-NEXT: blr entry: %xor = xor <16 x i8> %B, %C @@ -201,10 +190,9 @@ define <8 x i16> @ternary_A_eqv_BC_C_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> % ; CHECK-LABEL: ternary_A_eqv_BC_C_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxleqv vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 89 ; CHECK-NEXT: blr entry: %xor = xor <8 x i16> %B, %C @@ -218,10 +206,9 @@ define <4 x i32> @ternary_A_nand_BC_C_4x32(<4 x i1> %A, <4 x i32> %B, <4 x i32> ; CHECK-LABEL: ternary_A_nand_BC_C_4x32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxleqv v5, v5, v5 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: vslw v2, v2, v5 ; CHECK-NEXT: vsraw v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 94 ; CHECK-NEXT: blr entry: %and = and <4 x i32> %B, %C @@ -235,11 +222,10 @@ define <2 x i64> @ternary_A_nand_BC_C_2x64(<2 x i1> %A, <2 x i64> %B, <2 x i64> ; CHECK-LABEL: ternary_A_nand_BC_C_2x64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxlxor v5, v5, v5 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: xxsplti32dx v5, 1, 63 ; CHECK-NEXT: vsld v2, v2, v5 ; CHECK-NEXT: vsrad v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 94 ; CHECK-NEXT: blr entry: %and = and <2 x i64> %B, %C @@ -253,10 +239,9 @@ define <16 x i8> @ternary_A_nand_BC_C_16x8(<16 x i1> %A, <16 x i8> %B, <16 x i8> ; CHECK-LABEL: ternary_A_nand_BC_C_16x8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltib v5, 7 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: vslb v2, v2, v5 ; CHECK-NEXT: vsrab v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 94 ; CHECK-NEXT: blr entry: %and = and <16 x i8> %B, %C @@ -270,10 +255,9 @@ define <8 x i16> @ternary_A_nand_BC_C_8x16(<8 x i1> %A, <8 x i16> %B, <8 x i16> ; CHECK-LABEL: ternary_A_nand_BC_C_8x16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: xxspltiw v5, 983055 -; CHECK-NEXT: xxlnand vs0, v3, v4 ; CHECK-NEXT: vslh v2, v2, v5 ; CHECK-NEXT: vsrah v2, v2, v5 -; CHECK-NEXT: xxsel v2, v4, vs0, v2 +; CHECK-NEXT: xxeval v2, v2, v3, v4, 94 ; CHECK-NEXT: blr entry: %and = and <8 x i16> %B, %C |