diff options
| author | Michael Kruse <llvm-project@meinersbur.de> | 2025-01-03 10:22:51 +0100 |
|---|---|---|
| committer | Michael Kruse <llvm-project@meinersbur.de> | 2025-01-03 10:22:51 +0100 |
| commit | 38500d63e14ce340236840f60d356cdefb56a52c (patch) | |
| tree | 17edbec446ce9b50d2f215a483b83afb293a635d /llvm/test/CodeGen/PowerPC | |
| parent | 1a3d5daaef7a6a63448a497da3eff7fc9e23df26 (diff) | |
| parent | 27f30029741ecf023baece7b3dde1ff9011ffefc (diff) | |
Merge branch 'main' into users/meinersbur/flang_runtime_split-headersusers/meinersbur/flang_runtime_split-headers
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
26 files changed, 320 insertions, 128 deletions
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll index 00d1c471c2fa..501227c9072c 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll @@ -1102,12 +1102,12 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6 ; 32BIT-NEXT: {{ $}} ; 32BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0) ; 32BIT-NEXT: renamable $r12 = LWZ 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4) - ; 32BIT-NEXT: renamable $r0 = LWZ 0, %fixed-stack.1 :: (load (s32) from %fixed-stack.1, align 8) + ; 32BIT-NEXT: renamable $r0 = LBZ 3, %fixed-stack.1 :: (load (s8) from %fixed-stack.1 + 3, basealign 4) ; 32BIT-NEXT: renamable $r31 = LWZ 4, %fixed-stack.3 :: (load (s32) from %fixed-stack.3 + 4, basealign 16) ; 32BIT-NEXT: renamable $r30 = LWZ 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3, align 16) ; 32BIT-NEXT: renamable $r29 = LWZ 0, %fixed-stack.5 :: (load (s32) from %fixed-stack.5, align 8) - ; 32BIT-NEXT: renamable $r28 = LWZ 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6) - ; 32BIT-NEXT: renamable $r27 = LWZ 0, %fixed-stack.7 :: (load (s32) from %fixed-stack.7, align 16) + ; 32BIT-NEXT: renamable $r28 = LBZ 3, %fixed-stack.6 :: (load (s8) from %fixed-stack.6 + 3, basealign 4) + ; 32BIT-NEXT: renamable $r27 = LHA 2, %fixed-stack.7 :: (load (s16) from %fixed-stack.7 + 2, basealign 4) ; 32BIT-NEXT: renamable $r26 = LWZ 4, %fixed-stack.9 :: (load (s32) from %fixed-stack.9 + 4, basealign 8) ; 32BIT-NEXT: renamable $r25 = LWZ 0, %fixed-stack.9 :: (load (s32) from %fixed-stack.9, align 8) ; 32BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, killed renamable $r4 @@ -1143,13 +1143,13 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6 ; 64BIT: bb.0.entry: ; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10 ; 64BIT-NEXT: {{ $}} - ; 64BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.1, implicit-def $x11 :: (load (s32) from %fixed-stack.1) + ; 64BIT-NEXT: renamable $r11 = LBZ 3, %fixed-stack.1, implicit-def $x11 :: (load (s8) from %fixed-stack.1 + 3, basealign 4) ; 64BIT-NEXT: renamable $x12 = LWZ8 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4) - ; 64BIT-NEXT: renamable $x0 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0) - ; 64BIT-NEXT: renamable $x2 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2) - ; 64BIT-NEXT: renamable $x31 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3) - ; 64BIT-NEXT: renamable $r30 = LWZ 0, %fixed-stack.5, implicit-def $x30 :: (load (s32) from %fixed-stack.5) - ; 64BIT-NEXT: renamable $x29 = LWA 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6) + ; 64BIT-NEXT: renamable $r0 = LBZ 3, %fixed-stack.5, implicit-def $x0 :: (load (s8) from %fixed-stack.5 + 3, basealign 4) + ; 64BIT-NEXT: renamable $x2 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0) + ; 64BIT-NEXT: renamable $x31 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2) + ; 64BIT-NEXT: renamable $x30 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3) + ; 64BIT-NEXT: renamable $x29 = LHA8 2, %fixed-stack.6 ; 64BIT-NEXT: renamable $x28 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16) ; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3 ; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5 @@ -1161,12 +1161,12 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6 ; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3 ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x28 ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x29 - ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x30 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x0 ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x12 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x30 ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x31 - ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x2 ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x11 - ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x0 + ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x2 ; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3 entry: %add = add nsw i32 %i1, %i2 @@ -1611,8 +1611,8 @@ define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroex ; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4 ; 32BIT-NEXT: {{ $}} ; 32BIT-NEXT: renamable $r3 = LWZ 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3) - ; 32BIT-NEXT: renamable $r4 = LWZ 0, %fixed-stack.5 :: (load (s32) from %fixed-stack.5) - ; 32BIT-NEXT: renamable $r5 = LWZ 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6, align 8) + ; 32BIT-NEXT: renamable $r4 = LHA 2, %fixed-stack.5 :: (load (s16) from %fixed-stack.5 + 2, basealign 4) + ; 32BIT-NEXT: renamable $r5 = LBZ 3, %fixed-stack.6 :: (load (s8) from %fixed-stack.6 + 3, basealign 4) ; 32BIT-NEXT: renamable $r6 = LWZ 0, %fixed-stack.2 :: (load (s32) from %fixed-stack.2, align 8) ; 32BIT-NEXT: renamable $r7 = LIS 17200 ; 32BIT-NEXT: STW killed renamable $r7, 0, %stack.1 :: (store (s32) into %stack.1, align 8) diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll index 433d42734446..79c59e925302 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll @@ -1181,78 +1181,95 @@ entry: declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...) -define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) { +define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16, i8 signext %si8, i1 zeroext %zi1) { ; ASM32PWR4-LABEL: test_ints_stack: ; ASM32PWR4: # %bb.0: # %entry ; ASM32PWR4-NEXT: add 3, 3, 4 -; ASM32PWR4-NEXT: lwz 11, 92(1) +; ASM32PWR4-NEXT: stw 31, -4(1) # 4-byte Folded Spill ; ASM32PWR4-NEXT: add 3, 3, 5 ; ASM32PWR4-NEXT: add 3, 3, 6 ; ASM32PWR4-NEXT: add 3, 3, 7 -; ASM32PWR4-NEXT: lwz 12, 76(1) +; ASM32PWR4-NEXT: lbz 12, 99(1) ; ASM32PWR4-NEXT: add 3, 3, 8 ; ASM32PWR4-NEXT: add 3, 3, 9 -; ASM32PWR4-NEXT: lwz 6, 60(1) +; ASM32PWR4-NEXT: lwz 0, 92(1) ; ASM32PWR4-NEXT: add 3, 3, 10 -; ASM32PWR4-NEXT: srawi 5, 11, 31 +; ASM32PWR4-NEXT: extsb 4, 12 ; ASM32PWR4-NEXT: srawi 8, 3, 31 -; ASM32PWR4-NEXT: lwz 4, 64(1) +; ASM32PWR4-NEXT: lwz 31, 76(1) +; ASM32PWR4-NEXT: srawi 12, 0, 31 +; ASM32PWR4-NEXT: lwz 6, 60(1) +; ASM32PWR4-NEXT: lha 11, 66(1) ; ASM32PWR4-NEXT: lwz 7, 56(1) -; ASM32PWR4-NEXT: stw 31, -4(1) # 4-byte Folded Spill -; ASM32PWR4-NEXT: srawi 31, 12, 31 +; ASM32PWR4-NEXT: stw 30, -8(1) # 4-byte Folded Spill +; ASM32PWR4-NEXT: srawi 30, 31, 31 ; ASM32PWR4-NEXT: addc 3, 3, 6 ; ASM32PWR4-NEXT: adde 7, 8, 7 -; ASM32PWR4-NEXT: lwz 6, 68(1) -; ASM32PWR4-NEXT: srawi 8, 4, 31 -; ASM32PWR4-NEXT: addc 3, 3, 4 +; ASM32PWR4-NEXT: lbz 6, 71(1) +; ASM32PWR4-NEXT: srawi 8, 11, 31 +; ASM32PWR4-NEXT: addc 3, 3, 11 ; ASM32PWR4-NEXT: adde 7, 7, 8 -; ASM32PWR4-NEXT: lwz 4, 72(1) +; ASM32PWR4-NEXT: lwz 9, 72(1) ; ASM32PWR4-NEXT: addc 3, 3, 6 ; ASM32PWR4-NEXT: addze 6, 7 -; ASM32PWR4-NEXT: addc 3, 3, 4 -; ASM32PWR4-NEXT: lwz 0, 84(1) -; ASM32PWR4-NEXT: addze 4, 6 -; ASM32PWR4-NEXT: addc 3, 3, 12 +; ASM32PWR4-NEXT: addc 3, 3, 9 +; ASM32PWR4-NEXT: lwz 5, 84(1) +; ASM32PWR4-NEXT: addze 6, 6 +; ASM32PWR4-NEXT: addc 3, 3, 31 ; ASM32PWR4-NEXT: lwz 7, 80(1) -; ASM32PWR4-NEXT: adde 4, 4, 31 +; ASM32PWR4-NEXT: adde 6, 6, 30 +; ASM32PWR4-NEXT: addc 3, 3, 5 +; ASM32PWR4-NEXT: lbz 8, 91(1) +; ASM32PWR4-NEXT: adde 5, 6, 7 +; ASM32PWR4-NEXT: addc 3, 3, 8 +; ASM32PWR4-NEXT: lbz 6, 103(1) +; ASM32PWR4-NEXT: addze 5, 5 ; ASM32PWR4-NEXT: addc 3, 3, 0 -; ASM32PWR4-NEXT: lwz 6, 88(1) -; ASM32PWR4-NEXT: adde 4, 4, 7 -; ASM32PWR4-NEXT: addc 3, 3, 6 +; ASM32PWR4-NEXT: adde 5, 5, 12 ; ASM32PWR4-NEXT: lwz 31, -4(1) # 4-byte Folded Reload -; ASM32PWR4-NEXT: addze 6, 4 -; ASM32PWR4-NEXT: addc 4, 3, 11 -; ASM32PWR4-NEXT: adde 3, 6, 5 +; ASM32PWR4-NEXT: srawi 7, 4, 31 +; ASM32PWR4-NEXT: addc 3, 3, 4 +; ASM32PWR4-NEXT: adde 5, 5, 7 +; ASM32PWR4-NEXT: lwz 30, -8(1) # 4-byte Folded Reload +; ASM32PWR4-NEXT: addc 4, 3, 6 +; ASM32PWR4-NEXT: addze 3, 5 ; ASM32PWR4-NEXT: blr ; ; ASM64PWR4-LABEL: test_ints_stack: ; ASM64PWR4: # %bb.0: # %entry ; ASM64PWR4-NEXT: add 3, 3, 4 -; ASM64PWR4-NEXT: ld 4, 112(1) +; ASM64PWR4-NEXT: std 31, -8(1) # 8-byte Folded Spill ; ASM64PWR4-NEXT: add 3, 3, 5 ; ASM64PWR4-NEXT: add 3, 3, 6 ; ASM64PWR4-NEXT: add 3, 3, 7 -; ASM64PWR4-NEXT: lwa 12, 124(1) +; ASM64PWR4-NEXT: std 2, -16(1) # 8-byte Folded Spill ; ASM64PWR4-NEXT: add 3, 3, 8 ; ASM64PWR4-NEXT: add 3, 3, 9 +; ASM64PWR4-NEXT: ld 6, 112(1) ; ASM64PWR4-NEXT: add 3, 3, 10 ; ASM64PWR4-NEXT: extsw 3, 3 -; ASM64PWR4-NEXT: lwz 5, 132(1) -; ASM64PWR4-NEXT: add 3, 3, 4 +; ASM64PWR4-NEXT: lha 0, 126(1) +; ASM64PWR4-NEXT: add 3, 3, 6 +; ASM64PWR4-NEXT: add 3, 3, 0 +; ASM64PWR4-NEXT: lbz 5, 135(1) +; ASM64PWR4-NEXT: lwz 7, 140(1) +; ASM64PWR4-NEXT: add 3, 3, 5 +; ASM64PWR4-NEXT: lwa 12, 148(1) +; ASM64PWR4-NEXT: add 3, 3, 7 ; ASM64PWR4-NEXT: add 3, 3, 12 -; ASM64PWR4-NEXT: std 2, -8(1) # 8-byte Folded Spill +; ASM64PWR4-NEXT: ld 31, 152(1) +; ASM64PWR4-NEXT: lbz 5, 167(1) +; ASM64PWR4-NEXT: add 3, 3, 31 +; ASM64PWR4-NEXT: lwa 11, 172(1) ; ASM64PWR4-NEXT: add 3, 3, 5 -; ASM64PWR4-NEXT: lwz 2, 140(1) -; ASM64PWR4-NEXT: lwa 11, 148(1) -; ASM64PWR4-NEXT: add 3, 3, 2 ; ASM64PWR4-NEXT: add 3, 3, 11 -; ASM64PWR4-NEXT: ld 4, 152(1) -; ASM64PWR4-NEXT: lwz 0, 164(1) +; ASM64PWR4-NEXT: lbz 2, 183(1) +; ASM64PWR4-NEXT: lbz 6, 191(1) +; ASM64PWR4-NEXT: extsb 4, 2 ; ASM64PWR4-NEXT: add 3, 3, 4 -; ASM64PWR4-NEXT: lwa 5, 172(1) -; ASM64PWR4-NEXT: add 3, 3, 0 -; ASM64PWR4-NEXT: add 3, 3, 5 -; ASM64PWR4-NEXT: ld 2, -8(1) # 8-byte Folded Reload +; ASM64PWR4-NEXT: add 3, 3, 6 +; ASM64PWR4-NEXT: ld 2, -16(1) # 8-byte Folded Reload +; ASM64PWR4-NEXT: ld 31, -8(1) # 8-byte Folded Reload ; ASM64PWR4-NEXT: blr entry: %add = add nsw i32 %i1, %i2 @@ -1277,7 +1294,11 @@ entry: %add18 = add nsw i64 %add16, %conv17 %conv19 = sext i32 %i16 to i64 %add20 = add nsw i64 %add18, %conv19 - ret i64 %add20 + %conv21 = sext i8 %si8 to i64 + %add22 = add nsw i64 %add20, %conv21 + %conv23 = zext i1 %zi1 to i64 + %add24 = add nsw i64 %add22, %conv23 + ret i64 %add24 } @ll1 = common global i64 0, align 8 @@ -1720,17 +1741,17 @@ entry: define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroext %c1, i16 signext %s1, i64 %ll1, i32 %i1, i32 %i2, i32 %i3) { ; ASM32PWR4-LABEL: mix_callee: ; ASM32PWR4: # %bb.0: # %entry -; ASM32PWR4-NEXT: lwz 4, 60(1) +; ASM32PWR4-NEXT: lha 3, 62(1) ; ASM32PWR4-NEXT: lis 8, 17200 ; ASM32PWR4-NEXT: fadd 1, 1, 2 ; ASM32PWR4-NEXT: fadd 1, 1, 3 -; ASM32PWR4-NEXT: lwz 5, 56(1) -; ASM32PWR4-NEXT: lwz 3, 68(1) -; ASM32PWR4-NEXT: add 4, 5, 4 -; ASM32PWR4-NEXT: lwz 5, L..C34(2) # %const.0 +; ASM32PWR4-NEXT: lbz 5, 59(1) ; ASM32PWR4-NEXT: fadd 1, 1, 4 +; ASM32PWR4-NEXT: lwz 4, 68(1) +; ASM32PWR4-NEXT: add 3, 5, 3 +; ASM32PWR4-NEXT: lwz 5, L..C34(2) # %const.0 ; ASM32PWR4-NEXT: lwz 6, 72(1) -; ASM32PWR4-NEXT: add 3, 4, 3 +; ASM32PWR4-NEXT: add 3, 3, 4 ; ASM32PWR4-NEXT: lwz 7, 76(1) ; ASM32PWR4-NEXT: add 3, 3, 6 ; ASM32PWR4-NEXT: stw 8, -16(1) diff --git a/llvm/test/CodeGen/PowerPC/aix-cpu-version-multifunction.ll b/llvm/test/CodeGen/PowerPC/aix-cpu-version-multifunction.ll new file mode 100644 index 000000000000..2cdb864f450b --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-cpu-version-multifunction.ll @@ -0,0 +1,30 @@ +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s + +; For the .machine directive emitted on AIX, the "target-cpu" attribute that is +; the newest will be used as the CPU for the module (in this case, PWR10). + +; CHECK: .file "file.c" +; CHECK-NEXT: .csect ..text..[PR],5 +; CHECK-NEXT: .rename ..text..[PR],"" +; CHECK-NEXT: .machine "PWR10" +; CHECK-NOT: .machine "PWR8" + +source_filename = "file.c" + +define dso_local signext i32 @testFunc1() #0 { +entry: + %retval = alloca i32, align 4 + store i32 0, ptr %retval, align 4 + ret i32 0 +} + +define dso_local signext i32 @testFunc2() #1 { +entry: + %retval = alloca i32, align 4 + store i32 0, ptr %retval, align 4 + ret i32 0 +} + +attributes #0 = { "target-cpu" = "pwr8" } +attributes #1 = { "target-cpu" = "pwr10" } + diff --git a/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll new file mode 100644 index 000000000000..630a09cc58dc --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll @@ -0,0 +1,17 @@ +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s + +; CHECK: .file "1.c" +; CHECK-NEXT: .csect ..text..[PR],5 +; CHECK-NEXT: .rename ..text..[PR],"" +; CHECK-NEXT: .machine "PWR8" + +source_filename = "1.c" + +define dso_local signext i32 @main() #0 { +entry: + %retval = alloca i32, align 4 + store i32 0, ptr %retval, align 4 + ret i32 0 +} + +attributes #0 = {"target-cpu"="pwr8"} diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll index 173c58567e40..0cca7eab9104 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll @@ -68,8 +68,7 @@ declare extern_weak void @foo_ext_weak(ptr) ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) -; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) +; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) ; CHECKSYM-NEXT: NumberOfAuxEntries: 2 ; CHECKSYM: Symbol { diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll index ff2a80360880..71b17ad35c70 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll @@ -91,8 +91,7 @@ declare i32 @bar_extern(ptr) ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) -; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) +; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) ; CHECKSYM-NEXT: NumberOfAuxEntries: 2 ; CHECKSYM: Symbol { diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll index c4202a0c58ce..1fec0665c4ca 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll @@ -1,12 +1,57 @@ -; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s -; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s -; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr9 < %s | FileCheck --check-prefixes=ASM %s + +; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr9 -filetype=obj -o %t.o < %s +; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ32 %s +; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr9 -filetype=obj -o %t64.o < %s +; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ64 %s source_filename = "1.c" -; OBJ: Name: .file -; OBJ: Source Language ID: TB_C (0x0) -; OBJ32: CPU Version ID: TCPU_COM (0x3) -; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) -; OBJ: Name: 1.c +; ASM: .file "1.c",,"LLVM{{.*}}" +; ASM-NEXT: .csect ..text..[PR],5 +; ASM-NEXT: .rename ..text..[PR],"" +; ASM-NEXT: .machine "PWR9" + +; OBJ32: Symbol { +; OBJ32-NEXT: Index: 0 +; OBJ32-NEXT: Name: .file +; OBJ32-NEXT: Value (SymbolTableIndex): 0x0 +; OBJ32-NEXT: Section: N_DEBUG +; OBJ32-NEXT: Source Language ID: TB_C (0x0) +; OBJ32-NEXT: CPU Version ID: TCPU_PWR9 (0x1A) +; OBJ32-NEXT: StorageClass: C_FILE (0x67) +; OBJ32-NEXT: NumberOfAuxEntries: 2 +; OBJ32-NEXT: File Auxiliary Entry { +; OBJ32-NEXT: Index: 1 +; OBJ32-NEXT: Name: 1.c +; OBJ32-NEXT: Type: XFT_FN (0x0) +; OBJ32-NEXT: } +; OBJ32-NEXT: File Auxiliary Entry { +; OBJ32-NEXT: Index: 2 +; OBJ32-NEXT: Name: LLVM +; OBJ32-NEXT: Type: XFT_CV (0x2) +; OBJ32-NEXT: } +; OBJ32-NEXT: } + +; OBJ64: Symbol { +; OBJ64-NEXT: Index: 0 +; OBJ64-NEXT: Name: .file +; OBJ64-NEXT: Value (SymbolTableIndex): 0x0 +; OBJ64-NEXT: Section: N_DEBUG +; OBJ64-NEXT: Source Language ID: TB_C (0x0) +; OBJ64-NEXT: CPU Version ID: TCPU_PWR9 (0x1A) +; OBJ64-NEXT: StorageClass: C_FILE (0x67) +; OBJ64-NEXT: NumberOfAuxEntries: 2 +; OBJ64-NEXT: File Auxiliary Entry { +; OBJ64-NEXT: Index: 1 +; OBJ64-NEXT: Name: 1.c +; OBJ64-NEXT: Type: XFT_FN (0x0) +; OBJ64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; OBJ64-NEXT: } +; OBJ64-NEXT: File Auxiliary Entry { +; OBJ64-NEXT: Index: 2 +; OBJ64-NEXT: Name: LLVM +; OBJ64-NEXT: Type: XFT_CV (0x2) +; OBJ64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; OBJ64-NEXT: } +; OBJ64-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll index 802281b6c1ea..873619d20cd2 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll @@ -1,12 +1,11 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s +; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s -; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s +; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ %s source_filename = "1.cpp" ; OBJ: Name: .file ; OBJ: Source Language ID: TB_CPLUSPLUS (0x9) -; OBJ32: CPU Version ID: TCPU_COM (0x3) -; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: CPU Version ID: TCPU_PWR7 (0x18) ; OBJ: Name: 1.cpp diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll index 99036bde702d..1167148d21a7 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll @@ -1,12 +1,11 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s +; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s -; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s +; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ %s source_filename = "1.f95" ; OBJ: Name: .file ; OBJ: Source Language ID: TB_Fortran (0x1) -; OBJ32: CPU Version ID: TCPU_COM (0x3) -; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: CPU Version ID: TCPU_PWR7 (0x18) ; OBJ: Name: 1.f95 diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll index 4cca1b4d6f7b..50221acc2b3a 100644 --- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll @@ -17,7 +17,7 @@ entry: ; CHECK-NEXT: Value (SymbolTableIndex): 0x0 ; CHECK-NEXT: Section: N_DEBUG ; CHECK-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; CHECK-NEXT: CPU Version ID: TCPU_COM (0x3) +; CHECK-NEXT: CPU Version ID: TCPU_PWR7 (0x18) ; CHECK-NEXT: StorageClass: C_FILE (0x67) ; CHECK-NEXT: NumberOfAuxEntries: 2 ; CHECK-NEXT: File Auxiliary Entry { diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll index 50677f36e3f7..e2a3febd6c97 100644 --- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll +++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll @@ -44,8 +44,7 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) -; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) +; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) ; CHECKSYM-NEXT: NumberOfAuxEntries: 2 ; CHECKSYM: } diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll index f9a1a6161776..3c84aa1225d2 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll @@ -70,7 +70,7 @@ ; SYMS-NEXT: Value (SymbolTableIndex): 0x0 ; SYMS-NEXT: Section: N_DEBUG ; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; SYMS-NEXT: CPU Version ID: TCPU_COM (0x3) +; SYMS-NEXT: CPU Version ID: TCPU_PWR7 (0x18) ; SYMS-NEXT: StorageClass: C_FILE (0x67) ; SYMS-NEXT: NumberOfAuxEntries: 2 ; SYMS: Symbol { diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll index 7bf80ad19e9e..3b2917ec9728 100644 --- a/llvm/test/CodeGen/PowerPC/aix-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll @@ -104,8 +104,7 @@ entry: ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) -; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) +; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) ; CHECKSYM-NEXT: NumberOfAuxEntries: 2 ; CHECKSYM: Symbol { diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll index de937386b8b7..10b04b570fa3 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -45,8 +45,10 @@ ; CHECK-NOT: .toc -; CHECK: .file -; CHECK-NEXT: .csect ..text..[PR],5 +; CHECK: .file +; CHECK-NEXT: .csect ..text..[PR],5 +; CHECK-NEXT: .rename ..text..[PR],"" +; CHECK-NEXT: .machine "PWR7" ; CHECK: .csect .data[RW],5 ; CHECK-NEXT: .globl ivar @@ -212,8 +214,7 @@ ; SYMS-NEXT: Value (SymbolTableIndex): 0x0 ; SYMS-NEXT: Section: N_DEBUG ; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; SYMS32-NEXT: CPU Version ID: TCPU_COM (0x3) -; SYMS64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) +; SYMS-NEXT: CPU Version ID: TCPU_PWR7 (0x18) ; SYMS-NEXT: StorageClass: C_FILE (0x67) ; SYMS-NEXT: NumberOfAuxEntries: 2 ; SYMS-NEXT: File Auxiliary Entry { diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll index 950d65b7e291..77dd56f80311 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll @@ -163,8 +163,7 @@ declare i32 @bar(i32) ; SYM-NEXT: Value (SymbolTableIndex): 0x0 ; SYM-NEXT: Section: N_DEBUG ; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) -; SYM32-NEXT: CPU Version ID: TCPU_COM (0x3) -; SYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) +; SYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM-NEXT: StorageClass: C_FILE (0x67) ; SYM-NEXT: NumberOfAuxEntries: 2 ; SYM-NEXT: File Auxiliary Entry { diff --git a/llvm/test/CodeGen/PowerPC/check-cpu.ll b/llvm/test/CodeGen/PowerPC/check-cpu.ll index 1dc532cb428f..5eba85a3acf3 100644 --- a/llvm/test/CodeGen/PowerPC/check-cpu.ll +++ b/llvm/test/CodeGen/PowerPC/check-cpu.ll @@ -20,5 +20,3 @@ ; Test -mcpu=[pwr9|pwr10|pwr11|future] is recognized on PowerPC. ; CHECK-NOT: is not a recognized processor for this target -; CHECK: .text - diff --git a/llvm/test/CodeGen/PowerPC/data-align.ll b/llvm/test/CodeGen/PowerPC/data-align.ll new file mode 100644 index 000000000000..bfedec139369 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/data-align.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=powerpc-unknown-linux | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux | FileCheck %s + +; CHECK: .set .Li8, +; CHECK-NEXT: .size .Li8, 1 +@i8 = private constant i8 42 + +; CHECK: .set .Li16, +; CHECK-NEXT: .size .Li16, 2 +@i16 = private constant i16 42 + +; CHECK: .set .Li32, +; CHECK-NEXT: .size .Li32, 4 +@i32 = private constant i32 42 + +; CHECK: .set .Li64, +; CHECK-NEXT: .size .Li64, 8 +@i64 = private constant i64 42 + +; CHECK: .set .Li128, +; CHECK-NEXT: .size .Li128, 16 +@i128 = private constant i128 42 + diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll index 35e5d61947ea..decc4a38f7cc 100644 --- a/llvm/test/CodeGen/PowerPC/f128-arith.ll +++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll @@ -1365,45 +1365,33 @@ define dso_local fp128 @qpFREXP(ptr %a, ptr %b) { ; CHECK-LABEL: qpFREXP: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: mflr r0 -; CHECK-NEXT: .cfi_def_cfa_offset 64 +; CHECK-NEXT: stdu r1, -32(r1) +; CHECK-NEXT: std r0, 48(r1) +; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_offset lr, 16 -; CHECK-NEXT: .cfi_offset r30, -16 -; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-NEXT: stdu r1, -64(r1) -; CHECK-NEXT: std r0, 80(r1) -; CHECK-NEXT: addi r5, r1, 44 -; CHECK-NEXT: mr r30, r4 ; CHECK-NEXT: lxv v2, 0(r3) +; CHECK-NEXT: mr r5, r4 ; CHECK-NEXT: bl frexpf128 ; CHECK-NEXT: nop -; CHECK-NEXT: lwz r3, 44(r1) -; CHECK-NEXT: stw r3, 0(r30) -; CHECK-NEXT: addi r1, r1, 64 +; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr ; ; CHECK-P8-LABEL: qpFREXP: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: mflr r0 -; CHECK-P8-NEXT: .cfi_def_cfa_offset 64 +; CHECK-P8-NEXT: stdu r1, -32(r1) +; CHECK-P8-NEXT: std r0, 48(r1) +; CHECK-P8-NEXT: .cfi_def_cfa_offset 32 ; CHECK-P8-NEXT: .cfi_offset lr, 16 -; CHECK-P8-NEXT: .cfi_offset r30, -16 -; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill -; CHECK-P8-NEXT: stdu r1, -64(r1) -; CHECK-P8-NEXT: std r0, 80(r1) -; CHECK-P8-NEXT: addi r5, r1, 44 -; CHECK-P8-NEXT: mr r30, r4 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 +; CHECK-P8-NEXT: mr r5, r4 ; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: bl frexpf128 ; CHECK-P8-NEXT: nop -; CHECK-P8-NEXT: lwz r3, 44(r1) -; CHECK-P8-NEXT: stw r3, 0(r30) -; CHECK-P8-NEXT: addi r1, r1, 64 +; CHECK-P8-NEXT: addi r1, r1, 32 ; CHECK-P8-NEXT: ld r0, 16(r1) -; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P8-NEXT: mtlr r0 ; CHECK-P8-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll b/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll index 83763f5ef76a..2c5ad949dcc5 100644 --- a/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll +++ b/llvm/test/CodeGen/PowerPC/lsr-postinc-pos.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -print-lsr-output 2>&1 | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -stop-after=loop-reduce | FileCheck %s ; The icmp is a post-inc use, and the increment is in %bb11, but the ; scevgep needs to be inserted in %bb so that it is dominated by %t. diff --git a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll index a7d372c5e61a..e4d96678b287 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll @@ -2,7 +2,7 @@ ; ; Check that misuse of anyregcc results in a compile time error. -; CHECK: error: ran out of registers during register allocation +; CHECK: error: <unknown>:0:0: ran out of registers during register allocation define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16, i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24, diff --git a/llvm/test/CodeGen/PowerPC/ppc64-stackmap-args.ll b/llvm/test/CodeGen/PowerPC/ppc64-stackmap-args.ll new file mode 100644 index 000000000000..4e83db71793d --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/ppc64-stackmap-args.ll @@ -0,0 +1,22 @@ +; RUN: not llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-gnu-linux < %s 2>&1 | FileCheck %s +; Tests error when we pass non-immediate parameters to @llvm.experiment.stackmap + +define void @first_arg() { +; CHECK: immarg operand has non-immediate parameter +entry: + ; First operand should be immediate + %id = add i64 0, 0 + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 %id, i32 0) + ret void +} + +define void @second_arg() { +; CHECK: immarg operand has non-immediate parameter +entry: + ; Second operand should be immediate + %numShadowByte = add i32 0, 0 + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 1, i32 %numShadowByte) + ret void +} + +declare void @llvm.experimental.stackmap(i64, i32, ...) diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll index eba481e3345d..1fb2cbe5fb50 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -8,7 +8,7 @@ ; Currently VSX support is disabled for this test because we generate lxsdx ; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we ; have reg+imm addressing, and is on the list of things to be fixed. -; The second run step is to ensure that -march=ppc64le is adequate to select +; The second run step is to ensure that is adequate to select ; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le. target datalayout = "e-m:e-i64:64-n32:64" diff --git a/llvm/test/CodeGen/PowerPC/pr116071.ll b/llvm/test/CodeGen/PowerPC/pr116071.ll new file mode 100644 index 000000000000..29f11fc1d3a6 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr116071.ll @@ -0,0 +1,26 @@ +; RUN: llc -disable-ppc-vsx-fma-mutation=false -mcpu=pwr10 -verify-machineinstrs \ +; RUN: -ppc-asm-full-reg-names -mtriple powerpc64-ibm-aix7.2.0.0 < %s | FileCheck %s + +target datalayout = "E-m:a-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512" + +define void @initial(<2 x double> %0){ +entry: + %1 = fmul <2 x double> %0, zeroinitializer + br label %for.cond251.preheader.lr.ph + +for.cond251.preheader.lr.ph: ; preds = %for.cond251.preheader.lr.ph, %entry + %2 = phi double [ %3, %for.cond251.preheader.lr.ph ], [ 0.000000e+00, %entry ] + %3 = phi double [ %7, %for.cond251.preheader.lr.ph ], [ 0.000000e+00, %entry ] + %add737 = fadd double %3, %2 + %4 = insertelement <2 x double> zeroinitializer, double %add737, i64 0 + %5 = fmul contract <2 x double> %4, zeroinitializer + %6 = fadd contract <2 x double> %1, %5 + %7 = extractelement <2 x double> %6, i64 0 + br label %for.cond251.preheader.lr.ph +} + +; CHECK: xsadddp f4, f3, f4 +; CHECK-NEXT: xxmrghd vs5, vs4, vs2 +; CHECK-NEXT: fmr f4, f3 +; CHECK-NEXT: xvmaddmdp vs5, vs0, vs1 +; CHECK-NEXT: fmr f3, f5 diff --git a/llvm/test/CodeGen/PowerPC/pr118695.ll b/llvm/test/CodeGen/PowerPC/pr118695.ll new file mode 100644 index 000000000000..719a5d38b02c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr118695.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc-aix- -mcpu=pwr10 | FileCheck %s + +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: lwz 3, L..C0(2) # @dvar +; CHECK-NEXT: plxv 0, -152758(3), 0 +; CHECK-NEXT: stxv 0, 0(3) +; CHECK-NEXT: blr + +%0 = type <{ double }> +@dvar = external global [2352637 x %0] + +define void @Test() { +bb: + %i9 = load <2 x double>, ptr getelementptr inbounds (i8, ptr @dvar, i64 -152758), align 8 + store <2 x double> %i9, ptr @dvar, align 8 + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll index 4c11f7f919a3..c0f3b6012252 100644 --- a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll +++ b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll @@ -144,12 +144,11 @@ entry: define i1 @test_ssubo_i64(i64 %a, i64 %b) nounwind { ; CHECK-LABEL: test_ssubo_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: sub 5, 3, 4 -; CHECK-NEXT: cmpdi 1, 4, 0 -; CHECK-NEXT: cmpd 5, 3 -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: creqv 20, 5, 0 -; CHECK-NEXT: isel 3, 0, 3, 20 +; CHECK-NEXT: xor 5, 4, 3 +; CHECK-NEXT: sub 4, 3, 4 +; CHECK-NEXT: xor 3, 4, 3 +; CHECK-NEXT: and 3, 5, 3 +; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: blr entry: %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) nounwind diff --git a/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll b/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll index b6799c8a88e0..f62f70ca7ac1 100644 --- a/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll +++ b/llvm/test/CodeGen/PowerPC/scalar_vector_test_5.ll @@ -11,24 +11,35 @@ define i8 @scalar_to_vector_half(ptr nocapture readonly %ad) { ; P9LE-LABEL: scalar_to_vector_half: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: lhz r3, 0(r3) +; P9LE-NEXT: lxsihzx v2, 0, r3 +; P9LE-NEXT: li r3, 0 +; P9LE-NEXT: vsplth v2, v2, 3 +; P9LE-NEXT: vextubrx r3, r3, v2 ; P9LE-NEXT: blr ; ; P9BE-LABEL: scalar_to_vector_half: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: lhz r3, 0(r3) -; P9BE-NEXT: srwi r3, r3, 24 +; P9BE-NEXT: lxsihzx v2, 0, r3 +; P9BE-NEXT: li r3, 0 +; P9BE-NEXT: vsplth v2, v2, 3 +; P9BE-NEXT: vextublx r3, r3, v2 ; P9BE-NEXT: blr ; ; P8LE-LABEL: scalar_to_vector_half: ; P8LE: # %bb.0: # %entry ; P8LE-NEXT: lhz r3, 0(r3) +; P8LE-NEXT: mtfprd f0, r3 +; P8LE-NEXT: mffprd r3, f0 +; P8LE-NEXT: clrldi r3, r3, 56 ; P8LE-NEXT: blr ; ; P8BE-LABEL: scalar_to_vector_half: ; P8BE: # %bb.0: # %entry ; P8BE-NEXT: lhz r3, 0(r3) -; P8BE-NEXT: srwi r3, r3, 24 +; P8BE-NEXT: sldi r3, r3, 48 +; P8BE-NEXT: mtfprd f0, r3 +; P8BE-NEXT: mffprd r3, f0 +; P8BE-NEXT: rldicl r3, r3, 8, 56 ; P8BE-NEXT: blr entry: %0 = load <2 x i8>, ptr %ad, align 1 |