diff options
| author | Michael Kruse <llvm-project@meinersbur.de> | 2025-01-03 10:22:51 +0100 |
|---|---|---|
| committer | Michael Kruse <llvm-project@meinersbur.de> | 2025-01-03 10:22:51 +0100 |
| commit | 38500d63e14ce340236840f60d356cdefb56a52c (patch) | |
| tree | 17edbec446ce9b50d2f215a483b83afb293a635d /llvm/test/CodeGen/MIR | |
| parent | 1a3d5daaef7a6a63448a497da3eff7fc9e23df26 (diff) | |
| parent | 27f30029741ecf023baece7b3dde1ff9011ffefc (diff) | |
Merge branch 'main' into users/meinersbur/flang_runtime_split-headersusers/meinersbur/flang_runtime_split-headers
Diffstat (limited to 'llvm/test/CodeGen/MIR')
166 files changed, 188 insertions, 163 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll index 0f7a5f8e0941..eb4ee118ec2e 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll @@ -29,6 +29,7 @@ ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true @@ -295,6 +296,7 @@ ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll index 7759501ea422..6f5467b00ebc 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll @@ -29,6 +29,7 @@ ; AFTER-PEI-NEXT: workItemIDX: { reg: '$vgpr0' } ; AFTER-PEI-NEXT: psInputAddr: 0 ; AFTER-PEI-NEXT: psInputEnable: 0 +; AFTER-PEI-NEXT: maxMemoryClusterDWords: 8 ; AFTER-PEI-NEXT: mode: ; AFTER-PEI-NEXT: ieee: true ; AFTER-PEI-NEXT: dx10-clamp: true diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll index 4545c8bbeb3e..d1d8240a1007 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll @@ -30,6 +30,7 @@ ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll index 8215ba834170..ad6e92a25b86 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll @@ -30,6 +30,7 @@ ; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir index 51795a4fea51..3eff89239d54 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -39,6 +39,7 @@ # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } # FULL-NEXT: psInputAddr: 0 # FULL-NEXT: psInputEnable: 0 +# FULL-NEXT: maxMemoryClusterDWords: 8 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true @@ -143,6 +144,7 @@ body: | # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } # FULL-NEXT: psInputAddr: 0 # FULL-NEXT: psInputEnable: 0 +# FULL-NEXT: maxMemoryClusterDWords: 8 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true @@ -218,6 +220,7 @@ body: | # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } # FULL-NEXT: psInputAddr: 0 # FULL-NEXT: psInputEnable: 0 +# FULL-NEXT: maxMemoryClusterDWords: 8 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true @@ -294,6 +297,7 @@ body: | # FULL-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } # FULL-NEXT: psInputAddr: 0 # FULL-NEXT: psInputEnable: 0 +# FULL-NEXT: maxMemoryClusterDWords: 8 # FULL-NEXT: mode: # FULL-NEXT: ieee: true # FULL-NEXT: dx10-clamp: true @@ -593,3 +597,15 @@ body: | %2:sgpr_64 = COPY %1 %1:sgpr_64 = COPY %0 ... + +--- +# ALL-LABEL: name: max_memory_cluster_dwords +# ALL: maxMemoryClusterDWords: 16 +name: max_memory_cluster_dwords +machineFunctionInfo: + maxMemoryClusterDWords: 16 +body: | + bb.0: + SI_RETURN + +... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index 077d22fc895a..eca3f99b6495 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -40,6 +40,7 @@ ; CHECK-NEXT: workItemIDZ: { reg: '$vgpr2' } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true @@ -86,6 +87,7 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { ; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' } ; CHECK-NEXT: psInputAddr: 1 ; CHECK-NEXT: psInputEnable: 1 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: false ; CHECK-NEXT: dx10-clamp: true @@ -156,6 +158,7 @@ define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 { ; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true @@ -208,6 +211,7 @@ define void @function() { ; CHECK-NEXT: workItemIDZ: { reg: '$vgpr31', mask: 1072693248 } ; CHECK-NEXT: psInputAddr: 0 ; CHECK-NEXT: psInputEnable: 0 +; CHECK-NEXT: maxMemoryClusterDWords: 8 ; CHECK-NEXT: mode: ; CHECK-NEXT: ieee: true ; CHECK-NEXT: dx10-clamp: true diff --git a/llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir b/llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir index f6296d8ddf37..6115c144c31f 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/addrmode-opt-nonreaching.mir @@ -1,7 +1,7 @@ # It is not safe to make the transformation if the definition is killed by a call. # Use debug output for simplicity and test resilience. # -# RUN: llc -march=hexagon -run-pass amode-opt %s -print-after-all -o %t_1.mir 2>&1 | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass amode-opt %s -print-after-all -o %t_1.mir 2>&1 | FileCheck %s # CHECK: bb.4.if.else # CHECK-NOT: liveins: $r2 --- | diff --git a/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir b/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir index 915c354b5a0f..8eb2e82eadc4 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass none -o - %s | FileCheck %s # Check that the MIR parser can parse lane masks in block liveins. # CHECK-LABEL: name: foo diff --git a/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir b/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir index a4ea8821eb65..9c4a30ea83cd 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/target-flags.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=hexagon -run-pass none -o - %s | FileCheck %s --- name: fred diff --git a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir index 4874410c6a6e..da0af94b9826 100644 --- a/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir +++ b/llvm/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { entry: diff --git a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir index c64b9dacd9a6..f7da11372fa6 100644 --- a/llvm/test/CodeGen/MIR/Mips/memory-operands.mir +++ b/llvm/test/CodeGen/MIR/Mips/memory-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the call entry pseudo source # values in memory operands correctly. diff --git a/llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir b/llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir index a75765ffe40e..d6f792b354e0 100644 --- a/llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir +++ b/llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=nvptx -mcpu=sm_20 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=nvptx -mcpu=sm_20 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir index a40b4d85773b..9122ef7e6013 100644 --- a/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir +++ b/llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=nvptx -mcpu=sm_20 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=nvptx -mcpu=sm_20 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses floating point constant operands # correctly. diff --git a/llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir b/llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir index e5d8f9ba6a9d..6280d4e90ebf 100644 --- a/llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir +++ b/llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=nvptx -mcpu=sm_20 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=nvptx -mcpu=sm_20 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir index 40bd1a86990b..971e895322ad 100644 --- a/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir +++ b/llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses basic block liveins correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir b/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir index 9358c7c19c41..bfce65331497 100644 --- a/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir +++ b/llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir index 6108bef31a5a..64d4d00fc0e9 100644 --- a/llvm/test/CodeGen/MIR/X86/block-address-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/block-address-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the block address operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir index 8337117e3718..f0a19d895771 100644 --- a/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir +++ b/llvm/test/CodeGen/MIR/X86/callee-saved-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses callee saved information in the # stack objects correctly. diff --git a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir index 2ef5eb3ecc37..527407f4c015 100644 --- a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir +++ b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the cfi offset operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir index 55b3fa474e2c..ffdd45215e96 100644 --- a/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir +++ b/llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the cfi def_cfa_register # operands correctly. diff --git a/llvm/test/CodeGen/MIR/X86/cfi-offset.mir b/llvm/test/CodeGen/MIR/X86/cfi-offset.mir index 1e1a8ad2011b..94a7c5464163 100644 --- a/llvm/test/CodeGen/MIR/X86/cfi-offset.mir +++ b/llvm/test/CodeGen/MIR/X86/cfi-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the cfi offset operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir index acae12b07de3..848592402822 100644 --- a/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/constant-pool.mir b/llvm/test/CodeGen/MIR/X86/constant-pool.mir index e367c2658cba..6e78f44c9e79 100644 --- a/llvm/test/CodeGen/MIR/X86/constant-pool.mir +++ b/llvm/test/CodeGen/MIR/X86/constant-pool.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses constant pool constants and # constant pool operands correctly. diff --git a/llvm/test/CodeGen/MIR/X86/constant-value-error.mir b/llvm/test/CodeGen/MIR/X86/constant-value-error.mir index ca5b78984c81..15d71e345125 100644 --- a/llvm/test/CodeGen/MIR/X86/constant-value-error.mir +++ b/llvm/test/CodeGen/MIR/X86/constant-value-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when parsing an invalid # constant value. diff --git a/llvm/test/CodeGen/MIR/X86/copyIRflags.mir b/llvm/test/CodeGen/MIR/X86/copyIRflags.mir index 27eb9feb92ba..05f412919ed1 100644 --- a/llvm/test/CodeGen/MIR/X86/copyIRflags.mir +++ b/llvm/test/CodeGen/MIR/X86/copyIRflags.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the fast math instruction flags. ... diff --git a/llvm/test/CodeGen/MIR/X86/dbg-value-list.mir b/llvm/test/CodeGen/MIR/X86/dbg-value-list.mir index e9d6156a0eae..c384a815e5f9 100644 --- a/llvm/test/CodeGen/MIR/X86/dbg-value-list.mir +++ b/llvm/test/CodeGen/MIR/X86/dbg-value-list.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=x86-64 -run-pass machineverifier -o - %s | FileCheck %s -# RUN: llc -march=x86-64 --passes='machine-function(verify)' -o - %s | FileCheck %s +# RUN: llc -run-pass machineverifier -o - %s | FileCheck %s +# RUN: llc --passes='machine-function(verify)' -o - %s | FileCheck %s # Simple round-trip test for DBG_VALUE_LIST. # CHECK: [[VAR_C:![0-9]+]] = !DILocalVariable(name: "c" # CHECK: DBG_VALUE_LIST [[VAR_C]], !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_stack_value), $edi, $esi, debug-location diff --git a/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir b/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir index e01fd8d2b082..3fd179caf28b 100644 --- a/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/dead-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'dead' register flags # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir index 765d2e09ba82..aea49eef1dda 100644 --- a/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir +++ b/llvm/test/CodeGen/MIR/X86/def-register-already-tied-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir b/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir index 6b6adf3d08dc..08ae87084e10 100644 --- a/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir b/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir index b7d7221fb790..9140971d2d9a 100644 --- a/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir +++ b/llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir index aff96f49c9aa..5df0d65c6df1 100644 --- a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'early-clobber' register # flags correctly. diff --git a/llvm/test/CodeGen/MIR/X86/exception-function-state.mir b/llvm/test/CodeGen/MIR/X86/exception-function-state.mir index f401da1dde16..af974ad0e79e 100644 --- a/llvm/test/CodeGen/MIR/X86/exception-function-state.mir +++ b/llvm/test/CodeGen/MIR/X86/exception-function-state.mir @@ -1,5 +1,5 @@ -# RUN: llc -simplify-mir=0 -march=x86-64 -run-pass=none -o - %s | FileCheck -check-prefixes=FULL,ALL %s -# RUN: llc -simplify-mir=1 -march=x86-64 -run-pass=none -o - %s | FileCheck -check-prefixes=SIMPLE,ALL %s +# RUN: llc -simplify-mir=0 -mtriple=x86_64 -run-pass=none -o - %s | FileCheck -check-prefixes=FULL,ALL %s +# RUN: llc -simplify-mir=1 -mtriple=x86_64 -run-pass=none -o - %s | FileCheck -check-prefixes=SIMPLE,ALL %s # This test ensures that the MIR parser parses callee saved information in the # stack objects correctly. diff --git a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir index b1d374501512..397df6d7d2ab 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir index 1b31b5ee4411..7b3145389d4f 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir b/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir index a4e19a4ec96b..fec30ba3d231 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir index 2a47393f8d64..a8ab62904c28 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir b/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir index a0d9dcd84ee5..164f1bf9a44a 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir index a21ed0e6188c..b9b520e86de0 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir index 5e81481eda9a..577a7fa8411d 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir index ae36a3e54ae3..57c5bc7e5436 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir index 27f44fdd3cda..d91a92869763 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir index cb75cdd3cfbc..c4c4bcb150a6 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir index 9f1a15b500b6..c5f3a7b86f46 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir index f8b6baddd41d..7160a3e3c3d8 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir b/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir index 4a9c425fbfda..aed994e8cb1b 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir index cb7fb2586e41..0d1aac89a59c 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir index db927be80bc0..0ad92ad0f76a 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir index f79b93c67774..8cea9dde563a 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir index 4befc5394760..8350344e2700 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir index 4ef479d13b0a..e50ced1132ce 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %x) { entry: diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir index 03f2ec4d6cd3..45d4c3cd15ce 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir index 30f80f9ed719..fc1915e47303 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir index b0c5b979277e..b49a5fd04a4f 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir index 9257807d2879..b3b2e0dbb187 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir b/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir index dd0f4d39b09a..e3b7b79ea6e3 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir index b0df32477833..39566aa1081d 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir index 44ebcbc8a446..06ac6d8d5cb9 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir index 21970038dd04..9fd6a266ad6a 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir b/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir index d2beda69696e..f79b84197019 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir b/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir index 1cf57719fa87..d80dbee5af1c 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-power-of-2-after-align.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- name: align_0 diff --git a/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir index 65f2c0b63879..426426a04238 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir b/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir index d507de953118..6af814bbbe45 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when a register operand doesn't # follow register flags. diff --git a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir index 98073d91843f..499fcd7115f2 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir index 8b56239dc0fb..fb931c8c5fc6 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir b/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir index 59d77b32f7fb..bc7667d9a9a9 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-stack-object-function-context.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s --- name: test diff --git a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir index e819e3fa772d..c6adb28913c7 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir index 25a352a06d20..c81524e667c4 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir b/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir index 3f08e46f8971..164d3a034f3c 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir index f15db555f33f..a2c65dd3f019 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir index 87995babe09c..601e1a3f077c 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir index 6b56f39c7e2d..d03797c69a53 100644 --- a/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir +++ b/llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir b/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir index 785662e59a49..2bbe1ebcde57 100644 --- a/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the external symbol machine # operands correctly. diff --git a/llvm/test/CodeGen/MIR/X86/fastmath.mir b/llvm/test/CodeGen/MIR/X86/fastmath.mir index 5697d8bb2592..0e8d382b6a9a 100644 --- a/llvm/test/CodeGen/MIR/X86/fastmath.mir +++ b/llvm/test/CodeGen/MIR/X86/fastmath.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the fast math instruction flags. ... diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir index d59085128c0a..5715af5bef1f 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=i686 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack memory operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir index 2ce41fdada60..575f99dacdc4 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=i686 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir index 7cba6e3d03c2..9cbd891d5ab5 100644 --- a/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=i686 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack objects correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir b/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir index 0c68a3a3ed1a..e26233f94660 100644 --- a/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir +++ b/llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the save and restore points in # the machine frame info correctly. diff --git a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir index 2aa469287291..7766c8e2e2dd 100644 --- a/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir +++ b/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the stack protector stack # object reference in the machine frame info correctly. diff --git a/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir b/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir index 01341b3a6da6..410d3e230c27 100644 --- a/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the frame setup instruction flag. --- | diff --git a/llvm/test/CodeGen/MIR/X86/function-liveins.mir b/llvm/test/CodeGen/MIR/X86/function-liveins.mir index 7e71d2e05f16..87df43524969 100644 --- a/llvm/test/CodeGen/MIR/X86/function-liveins.mir +++ b/llvm/test/CodeGen/MIR/X86/function-liveins.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine function's liveins # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir index 7514cdab0ab1..c2e508868da4 100644 --- a/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir +++ b/llvm/test/CodeGen/MIR/X86/generic-instr-type.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # Test that the MIR parser parses types on generic instructions correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir index d981abf8ba5b..08e51870ba47 100644 --- a/llvm/test/CodeGen/MIR/X86/global-value-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/global-value-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses global value operands correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/immediate-operands.mir b/llvm/test/CodeGen/MIR/X86/immediate-operands.mir index 2fef51ca2305..043cf9bf47fb 100644 --- a/llvm/test/CodeGen/MIR/X86/immediate-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/immediate-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses immediate machine operands. --- | diff --git a/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir b/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir index 61c4b6c98a73..8cece8451871 100644 --- a/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'implicit' and 'implicit-def' # register flags correctly. diff --git a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir index 2ac4d7cccac0..54145a422489 100644 --- a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s --- | define i64 @test(i64 %x, i64 %y) #0 { diff --git a/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir b/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir index 136e491a2e3b..30873a27790b 100644 --- a/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir +++ b/llvm/test/CodeGen/MIR/X86/instr-cfi-type.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses cfi-type correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir b/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir index e1edb19c9a74..f776e38b448b 100644 --- a/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses heap alloc markers correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir b/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir index ad1b8efe7f86..947d93ef3593 100644 --- a/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir +++ b/llvm/test/CodeGen/MIR/X86/instr-pcsections.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses pcsections metadata correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir b/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir index aade83275544..761f4fe43bd9 100644 --- a/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/instr-symbols-and-mcsymbol-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses pre- and post-instruction symbols # and MCSymbol operands correctly. diff --git a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir index 78403629c7b0..11fed8ae64fd 100644 --- a/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir +++ b/llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the machine instruction's # debug location metadata correctly. diff --git a/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir b/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir index bcfdc6a316fa..e3009e3237a1 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when parsing an invalid # constant pool item operand. diff --git a/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir b/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir index 63f394356f20..1a83f891d1fa 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 diff --git a/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir b/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir index c30d58a642c0..7f31318c813b 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir index 65aab15442a5..091cbb0c40c9 100644 --- a/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir +++ b/llvm/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/llvm/test/CodeGen/MIR/X86/jump-table-info.mir b/llvm/test/CodeGen/MIR/X86/jump-table-info.mir index 8bbfb96a8190..aad6caa47774 100644 --- a/llvm/test/CodeGen/MIR/X86/jump-table-info.mir +++ b/llvm/test/CodeGen/MIR/X86/jump-table-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the jump table info and jump # table operands correctly. diff --git a/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir index a965f9938b2c..a1041f04fe52 100644 --- a/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir b/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir index 6641848c75be..39e88fe3180d 100644 --- a/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/killed-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'killed' register flags # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir index 1d53de61d435..c895d845708a 100644 --- a/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir b/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir index 84e1c4fa8c12..ddbd876c97e1 100644 --- a/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir index 4fdb17f8a171..785066111ecc 100644 --- a/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-index-number-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir b/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir index a14cf3388980..1b0ebbc1d19f 100644 --- a/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir b/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir index 51438ac53f08..9bcbd341b6a7 100644 --- a/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir +++ b/llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir b/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir index 69a5fd437085..6058912c61be 100644 --- a/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir +++ b/llvm/test/CodeGen/MIR/X86/liveout-register-mask.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the liveout register mask # machine operands correctly. diff --git a/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir b/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir index fc6a81fcef02..c6fe89d62350 100644 --- a/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir +++ b/llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass=none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass=none -o - %s | FileCheck %s # CHECK: name: truly_aligned_load # CHECK: MOV32rm {{.*}} :: (load (s32), align 4294967296) diff --git a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir index 72e36f5e5716..5429d25a8e7d 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine basic block operands. --- | diff --git a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir index 38d80ebf304a..07aafd088f7f 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-instructions.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-instructions.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses X86 machine instructions # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir b/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir index 64c07ae16f03..6479bdd400a4 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the address is checked in machine verifier. --- diff --git a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir index 6966b3e6778e..329117464b10 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the VerifyInstrumentation works for machine function. --- | diff --git a/llvm/test/CodeGen/MIR/X86/memory-operands.mir b/llvm/test/CodeGen/MIR/X86/memory-operands.mir index 3beddf024531..70353cfb0197 100644 --- a/llvm/test/CodeGen/MIR/X86/memory-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/memory-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the machine memory operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir index e6f8e05dcb1f..c80af7dd6501 100644 --- a/llvm/test/CodeGen/MIR/X86/metadata-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/metadata-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the metadata machine operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir b/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir index 6b7b577f8ca5..44f8c3ca3dc9 100644 --- a/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir +++ b/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir @@ -1,5 +1,5 @@ -# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s -# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass mir-canonicalizer -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %s | FileCheck %s # The purpose of this test is to ensure that differing flags do in-fact cause # naming collisions with the new vreg renamers naming scheme. --- | diff --git a/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir b/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir index dc4c3638f48b..51ef95877068 100644 --- a/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir +++ b/llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/missing-comma.mir b/llvm/test/CodeGen/MIR/X86/missing-comma.mir index 3500f05966fc..82ea21de39fe 100644 --- a/llvm/test/CodeGen/MIR/X86/missing-comma.mir +++ b/llvm/test/CodeGen/MIR/X86/missing-comma.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir index dcb39e86d680..8cd13895923b 100644 --- a/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when an instruction # is missing one of its implicit register operands. diff --git a/llvm/test/CodeGen/MIR/X86/named-registers.mir b/llvm/test/CodeGen/MIR/X86/named-registers.mir index 9d4dd8b8427a..23e1762f3558 100644 --- a/llvm/test/CodeGen/MIR/X86/named-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/named-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses X86 registers correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/newline-handling.mir b/llvm/test/CodeGen/MIR/X86/newline-handling.mir index 8b425a2f98cc..6a248bb90fbe 100644 --- a/llvm/test/CodeGen/MIR/X86/newline-handling.mir +++ b/llvm/test/CodeGen/MIR/X86/newline-handling.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/null-register-operands.mir b/llvm/test/CodeGen/MIR/X86/null-register-operands.mir index 5d22399cd72d..7f99af02e7b0 100644 --- a/llvm/test/CodeGen/MIR/X86/null-register-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/null-register-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses null register operands correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir index 761d44d84ffb..c74e22586fa2 100644 --- a/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/register-mask-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses register mask operands correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir index c0eaddc64909..35e3f4dd9a91 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid0.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s +# RUN: not llc -o /dev/null %s -mtriple=x86_64 -run-pass none 2>&1 | FileCheck %s # This test ensures that an error is reported for specifying the register class # of a physical register. --- | diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir index 5d6777c63cc8..559fa3189880 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class-invalid1.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o /dev/null %s -march=x86-64 -run-pass none 2>&1 | FileCheck %s +# RUN: not llc -o /dev/null %s -mtriple=x86_64 -run-pass none 2>&1 | FileCheck %s # This test ensures that an error is reported for specifying the register class # of a physical register. --- | diff --git a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir index 521722d9f24c..a6bdde82ff06 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operand-class.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operand-class.mir @@ -1,4 +1,4 @@ -# RUN: llc -o - %s -march=x86-64 -run-pass none | FileCheck %s +# RUN: llc -o - %s -mtriple=x86_64 -run-pass none | FileCheck %s # Test various aspects of register class specification on machine operands. --- | define void @func() { ret void } diff --git a/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir b/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir index dff926e1ebc0..e103385cddc0 100644 --- a/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir +++ b/llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir b/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir index 3a773b132086..06f7b22814f5 100644 --- a/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/renamable-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'renamable' register flags # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir index aacf66c98cf5..44b4c346cdd2 100644 --- a/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir +++ b/llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses simple register allocation hints # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir index f3a60a91f6d0..5f440f6ea551 100644 --- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir +++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir index a705beaca1e8..f8f6edd5ca6f 100644 --- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir +++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir index fd634b02c208..69c3deccd675 100644 --- a/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack objects correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir index 9c5f549a9ea9..9cc25d8882bf 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the stack object's debug info # correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir b/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir index 78281839866a..4721a02eef27 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when it encounters a # stack object with a name that can't be associated with an alloca instruction. diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir index 15b33e181838..2ff08e739bf9 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an stack object reference # uses a different name then the stack object definition. diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir b/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir index 672f8297160a..2977b38e8acf 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-operands.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=i686 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses stack object machine operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir index 20b93077609c..6217ad35c13b 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/stack-objects.mir b/llvm/test/CodeGen/MIR/X86/stack-objects.mir index 4a97455e2038..0eaf6b9fb597 100644 --- a/llvm/test/CodeGen/MIR/X86/stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses stack objects correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir index 30df44da56c6..2afdda47c852 100644 --- a/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir +++ b/llvm/test/CodeGen/MIR/X86/standalone-register-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { body: diff --git a/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir b/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir index 832576fbb688..4adae94978b1 100644 --- a/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir +++ b/llvm/test/CodeGen/MIR/X86/subreg-on-physreg.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported for subreg index on a physreg. --- | define void @t() { ret void } diff --git a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir index f34816bf9a1b..db53873faffc 100644 --- a/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses and prints subregisters index # operands correctly. diff --git a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir index a7d854fde1ed..039122a030ed 100644 --- a/llvm/test/CodeGen/MIR/X86/subregister-operands.mir +++ b/llvm/test/CodeGen/MIR/X86/subregister-operands.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses subregisters in register operands # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir index 54fbd01eae7a..6770f03e2504 100644 --- a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir +++ b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses basic block successors and # probabilities correctly. diff --git a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir index d08919692a49..2c01ab187df6 100644 --- a/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir +++ b/llvm/test/CodeGen/MIR/X86/successor-basic-blocks.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses basic block successors correctly. --- | diff --git a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir index 7509b31964e5..3ad5d2e8c935 100644 --- a/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir +++ b/llvm/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir index 1e4104e8ebda..ff67990b22d4 100644 --- a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir +++ b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the Machine Verifier detects tied physical registers # that doesn't match. diff --git a/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir index e0220cfdb706..7e84591d92b5 100644 --- a/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir +++ b/llvm/test/CodeGen/MIR/X86/undef-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'undef' register flags # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir index f319108e5628..5434ea0b0153 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { diff --git a/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir b/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir index 650695c0a9cb..1f568eb81055 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-global-value.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an invalid global value index # is used. diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir index 185897987046..a88a9308d0d5 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir index 309da51ca830..ed860d23ede5 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir b/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir index 246b0c996461..46bfaa301aab 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-jump-table-id.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir b/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir index 48f17ef3b006..57bcf9585694 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an undefined global value is # used. diff --git a/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir b/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir index 8fb9dbc2c568..a677bbf68441 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-register-class.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when it encounters an # unknown register class. diff --git a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir index ea77d137eb82..03585f8704b4 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { diff --git a/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir b/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir index 7bfb6ad197d9..6954ffbf9abc 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir index c31735a52eb6..820291c26989 100644 --- a/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir +++ b/llvm/test/CodeGen/MIR/X86/undefined-virtual-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when parsing a # reference to an undefined virtual register. diff --git a/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir b/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir index 953b9f666bfe..4c12c768a3f3 100644 --- a/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir +++ b/llvm/test/CodeGen/MIR/X86/unexpected-type-phys.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when a register operand is sized # but isn't generic, like a physical register. diff --git a/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir b/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir index 4377347f0a9f..143e542fa6f5 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-instruction.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown instruction is # encountered. diff --git a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir index 6e6796c06464..bc11ee3e6ea7 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an invalid machine basic # block index is used. diff --git a/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir b/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir index e08ad4c93b01..022ea0390445 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @inc(ptr %x) { diff --git a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir index 95fc53b441fb..295e356c2be3 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir index 10819bfafd9a..fc5deb4d6dd5 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown named machine # basic block is encountered. diff --git a/llvm/test/CodeGen/MIR/X86/unknown-register.mir b/llvm/test/CodeGen/MIR/X86/unknown-register.mir index cdd85f0b1b36..c8f007874c35 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-register.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown register is # encountered. diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir index 30ec530fad3d..bc95dd3a295f 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown subregister index # is encountered. diff --git a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir index 6db338dc9fca..69ff69623c31 100644 --- a/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir +++ b/llvm/test/CodeGen/MIR/X86/unknown-subregister-index.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown subregister index # is encountered. diff --git a/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir b/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir index 15817d06a28a..0849b7155249 100644 --- a/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir +++ b/llvm/test/CodeGen/MIR/X86/unrecognized-character.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir index ebf0b41c09e4..3c8594abd97a 100644 --- a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir +++ b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { diff --git a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir index a34754c8ed48..6e27bc064234 100644 --- a/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir +++ b/llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses variable sized stack objects # correctly. diff --git a/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir index 423e892da4a4..03e0653b1d6e 100644 --- a/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir +++ b/llvm/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir index 819f65638b67..f85dd15f3302 100644 --- a/llvm/test/CodeGen/MIR/X86/virtual-registers.mir +++ b/llvm/test/CodeGen/MIR/X86/virtual-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses virtual register definitions and # references correctly. |