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| author | Matthias Braun <matze@braunis.de> | 2016-08-24 01:32:41 +0000 |
|---|---|---|
| committer | Matthias Braun <matze@braunis.de> | 2016-08-24 01:32:41 +0000 |
| commit | 79f85b3b8ff8e54e9c94870477f2868929e481b7 (patch) | |
| tree | 67b36c04f6c3f2f4f73e0361a42cf993bb619d41 /llvm/test/CodeGen/MIR/PowerPC | |
| parent | b31163136ca249127b95a457308c7de3cb7a9841 (diff) | |
MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.
Specifying isSSA is an extra line at best and results in invalid MI at
worst. Compute the value instead.
Differential Revision: http://reviews.llvm.org/D22722
llvm-svn: 279600
Diffstat (limited to 'llvm/test/CodeGen/MIR/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir b/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir index 3caab2c7a578..d1c38acd5d33 100644 --- a/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir +++ b/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir @@ -20,7 +20,6 @@ ... --- name: main -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: g8rc_and_g8rc_nox0 } |