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| author | Mingming Liu <mingmingl@google.com> | 2025-09-10 15:25:31 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-10 15:25:31 -0700 |
| commit | 1417dafa1db9cb1b2b09438aa9f53ea5ab6e36e2 (patch) | |
| tree | 57f4b1f313c8cf74eed8819870f39c36ea263c68 /llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll | |
| parent | 898b813bc8a6d0276bf0f4769f5f2f64b34e632d (diff) | |
| parent | b8cefcb601ddaa18482555c4ff363c01a270c2fe (diff) | |
Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format
Diffstat (limited to 'llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll')
| -rw-r--r-- | llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll index e9a0c8a11045..65aff8071897 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s +; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32 +; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64 define <16 x i8> @insert_extract_v16i8(<16 x i8> %a) nounwind { ; CHECK-LABEL: insert_extract_v16i8: @@ -46,10 +47,18 @@ entry: } define <2 x i64> @insert_extract_v2i64(<2 x i64> %a) nounwind { -; CHECK-LABEL: insert_extract_v2i64: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vextrins.d $vr0, $vr0, 1 -; CHECK-NEXT: ret +; LA32-LABEL: insert_extract_v2i64: +; LA32: # %bb.0: # %entry +; LA32-NEXT: vori.b $vr1, $vr0, 0 +; LA32-NEXT: vextrins.w $vr1, $vr0, 2 +; LA32-NEXT: vextrins.w $vr1, $vr0, 19 +; LA32-NEXT: vori.b $vr0, $vr1, 0 +; LA32-NEXT: ret +; +; LA64-LABEL: insert_extract_v2i64: +; LA64: # %bb.0: # %entry +; LA64-NEXT: vextrins.d $vr0, $vr0, 1 +; LA64-NEXT: ret entry: %b = extractelement <2 x i64> %a, i32 1 %c = insertelement <2 x i64> %a, i64 %b, i32 0 |
