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| author | Peter Collingbourne <peter@pcc.me.uk> | 2025-07-18 13:26:00 -0700 |
|---|---|---|
| committer | Peter Collingbourne <peter@pcc.me.uk> | 2025-07-18 13:26:00 -0700 |
| commit | 9bf3524731070cadc6175707314f3b6ca37190d5 (patch) | |
| tree | 86dcab7604336b01ae938fe81062c29ff69efba8 /llvm/test/CodeGen/AMDGPU/select-undef.ll | |
| parent | 3a84c15cc13b6daf8e812592898ab6c7f19091a9 (diff) | |
| parent | 4f43f0606c3d7e1ce6d069583b5e59f036e112ce (diff) | |
Created using spr 1.3.6-beta.1
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/select-undef.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/select-undef.ll | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/select-undef.ll b/llvm/test/CodeGen/AMDGPU/select-undef.ll index ec3781fbf0fc..f49775299485 100644 --- a/llvm/test/CodeGen/AMDGPU/select-undef.ll +++ b/llvm/test/CodeGen/AMDGPU/select-undef.ll @@ -841,3 +841,23 @@ ret: ret void } +define i64 @poison_should_freeze(i1 %cond1, i32 %val, i16 %val2, i64 %a, i64 %b) { +; GCN-LABEL: poison_should_freeze: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_and_b32_e32 v0, 1, v0 +; GCN-NEXT: v_mov_b32_e32 v7, 0x5040100 +; GCN-NEXT: v_perm_b32 v2, v2, s4, v7 +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc +; GCN-NEXT: s_setpc_b64 s[30:31] + %poisonv = insertelement <2 x i16> poison, i16 %val2, i32 1 + %poison = bitcast <2 x i16> %poisonv to i32 + %cond2 = select i1 %cond1, i32 %poison, i32 %val + %cmp = icmp eq i32 %cond2, 0 + %select = select i1 %cmp, i64 %a, i64 %b + ret i64 %select +} |