Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format

1 files changed, 15096 insertions, 3115 deletions

diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 35913b9a21d3..c4a38dcd7b5f 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -14,6 +14,1250 @@
 define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,
 ; SI-LABEL: frem_f16:
 ; SI:       ; %bb.0:
+; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s6, -1
+; SI-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-NEXT:    s_mov_b32 s4, s10
+; SI-NEXT:    s_mov_b32 s5, s11
+; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    s_mov_b32 s3, s7
+; SI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
+; SI-NEXT:    s_waitcnt vmcnt(0)
+; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
+; SI-NEXT:    s_waitcnt vmcnt(0)
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_and_b32_e32 v3, 0x7fffffff, v0
+; SI-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v1
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    v_cvt_f16_f32_e32 v4, v0
+; SI-NEXT:    s_cbranch_vccz .LBB0_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    v_bfi_b32 v5, s0, 0, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v3, v2
+; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v5, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB0_3
+; SI-NEXT:    s_branch .LBB0_8
+; SI-NEXT:  .LBB0_2:
+; SI-NEXT:    ; implicit-def: $vgpr4
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB0_3: ; %frem.compute
+; SI-NEXT:    s_mov_b32 s3, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v3|, s3
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v3
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v4
+; SI-NEXT:    s_cselect_b32 s2, s0, 0
+; SI-NEXT:    v_frexp_mant_f32_e32 v4, v3
+; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 11
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v2|, s3
+; SI-NEXT:    v_frexp_mant_f32_e32 v4, v2
+; SI-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v2
+; SI-NEXT:    s_cselect_b32 s3, s0, 0
+; SI-NEXT:    s_add_i32 s0, s3, -1
+; SI-NEXT:    v_ldexp_f32_e64 v2, v4, 1
+; SI-NEXT:    s_not_b32 s1, s0
+; SI-NEXT:    s_add_i32 s1, s1, s2
+; SI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
+; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v2, v2, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v6, v5
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
+; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
+; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
+; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
+; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
+; SI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s1, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB0_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s1, s2, s3
+; SI-NEXT:    s_add_i32 s1, s1, 11
+; SI-NEXT:  .LBB0_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v5, v3
+; SI-NEXT:    v_mul_f32_e32 v3, v5, v4
+; SI-NEXT:    v_rndne_f32_e32 v3, v3
+; SI-NEXT:    v_fma_f32 v3, -v3, v2, v5
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT:    v_add_f32_e32 v6, v3, v2
+; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 11
+; SI-NEXT:    s_add_i32 s1, s1, -11
+; SI-NEXT:    s_cmp_gt_i32 s1, 11
+; SI-NEXT:    s_cbranch_scc1 .LBB0_5
+; SI-NEXT:  ; %bb.6: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v3, v5
+; SI-NEXT:  .LBB0_7: ; %frem.loop_exit
+; SI-NEXT:    s_add_i32 s1, s1, -10
+; SI-NEXT:    v_ldexp_f32_e64 v3, v3, s1
+; SI-NEXT:    v_mul_f32_e32 v4, v3, v4
+; SI-NEXT:    v_rndne_f32_e32 v4, v4
+; SI-NEXT:    v_fma_f32 v3, -v4, v2, v3
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT:    v_add_f32_e32 v2, v3, v2
+; SI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v2, v2, s0
+; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v4, s0, v2, v0
+; SI-NEXT:  .LBB0_8: ; %Flow19
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v4
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; SI-NEXT:    s_movk_i32 s0, 0x7c00
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s0, v0
+; SI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    buffer_store_short v0, off, s[8:11], 0
+; SI-NEXT:    s_endpgm
+;
+; CI-LABEL: frem_f16:
+; CI:       ; %bb.0:
+; CI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
+; CI-NEXT:    s_mov_b32 s7, 0xf000
+; CI-NEXT:    s_mov_b32 s6, -1
+; CI-NEXT:    s_mov_b32 s2, s6
+; CI-NEXT:    s_waitcnt lgkmcnt(0)
+; CI-NEXT:    s_mov_b32 s4, s10
+; CI-NEXT:    s_mov_b32 s5, s11
+; CI-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
+; CI-NEXT:    s_mov_b32 s3, s7
+; CI-NEXT:    buffer_load_ushort v1, off, s[0:3], 0 offset:8
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    s_waitcnt vmcnt(1)
+; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT:    s_waitcnt vmcnt(0)
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_cvt_f16_f32_e32 v3, v0
+; CI-NEXT:    v_and_b32_e32 v4, 0x7fffffff, v0
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; CI-NEXT:    v_and_b32_e32 v2, 0x7fffffff, v1
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB0_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; CI-NEXT:    v_bfi_b32 v5, s0, 0, v0
+; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v2
+; CI-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
+; CI-NEXT:    s_cbranch_execz .LBB0_3
+; CI-NEXT:    s_branch .LBB0_8
+; CI-NEXT:  .LBB0_2:
+; CI-NEXT:    ; implicit-def: $vgpr3
+; CI-NEXT:  .LBB0_3: ; %frem.compute
+; CI-NEXT:    v_frexp_mant_f32_e32 v3, v4
+; CI-NEXT:    v_ldexp_f32_e64 v5, v3, 11
+; CI-NEXT:    v_frexp_mant_f32_e32 v3, v2
+; CI-NEXT:    v_ldexp_f32_e64 v3, v3, 1
+; CI-NEXT:    v_div_scale_f32 v9, s[0:1], v3, v3, 1.0
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v2
+; CI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
+; CI-NEXT:    v_not_b32_e32 v4, v2
+; CI-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v10, v9
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
+; CI-NEXT:    v_mul_f32_e32 v11, v6, v10
+; CI-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
+; CI-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
+; CI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB0_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v4, vcc, v7, v8
+; CI-NEXT:    v_add_i32_e32 v4, vcc, 11, v4
+; CI-NEXT:  .LBB0_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v7, v5
+; CI-NEXT:    v_mul_f32_e32 v5, v7, v6
+; CI-NEXT:    v_rndne_f32_e32 v5, v5
+; CI-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; CI-NEXT:    v_add_f32_e32 v8, v5, v3
+; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; CI-NEXT:    v_add_i32_e32 v4, vcc, -11, v4
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
+; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 11
+; CI-NEXT:    s_cbranch_vccnz .LBB0_5
+; CI-NEXT:  ; %bb.6: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v5, v7
+; CI-NEXT:  .LBB0_7: ; %frem.loop_exit
+; CI-NEXT:    v_add_i32_e32 v4, vcc, -10, v4
+; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT:    v_mul_f32_e32 v5, v4, v6
+; CI-NEXT:    v_rndne_f32_e32 v5, v5
+; CI-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
+; CI-NEXT:    v_add_f32_e32 v3, v4, v3
+; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
+; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT:    v_bfi_b32 v3, s0, v2, v0
+; CI-NEXT:  .LBB0_8: ; %Flow19
+; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT:    s_movk_i32 s0, 0x7c00
+; CI-NEXT:    s_mov_b32 s11, 0xf000
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; CI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s0, v0
+; CI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; CI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v1
+; CI-NEXT:    v_cvt_f16_f32_e32 v1, v3
+; CI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; CI-NEXT:    s_mov_b32 s10, -1
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
+; CI-NEXT:    s_endpgm
+;
+; VI-LABEL: frem_f16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    s_add_u32 s2, s4, 8
+; VI-NEXT:    s_addc_u32 s3, s5, 0
+; VI-NEXT:    flat_load_ushort v0, v[0:1]
+; VI-NEXT:    v_mov_b32_e32 v1, s2
+; VI-NEXT:    v_mov_b32_e32 v2, s3
+; VI-NEXT:    flat_load_ushort v1, v[1:2]
+; VI-NEXT:    s_waitcnt vmcnt(1)
+; VI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
+; VI-NEXT:    s_waitcnt vmcnt(0)
+; VI-NEXT:    v_cvt_f32_f16_e64 v2, |v1|
+; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v2
+; VI-NEXT:    s_cbranch_vccz .LBB0_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v3, s2, 0, v0
+; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v2
+; VI-NEXT:    v_cndmask_b32_e32 v3, v0, v3, vcc
+; VI-NEXT:    s_cbranch_execz .LBB0_3
+; VI-NEXT:    s_branch .LBB0_8
+; VI-NEXT:  .LBB0_2:
+; VI-NEXT:    ; implicit-def: $vgpr3
+; VI-NEXT:  .LBB0_3: ; %frem.compute
+; VI-NEXT:    v_frexp_mant_f32_e32 v3, v4
+; VI-NEXT:    v_ldexp_f32 v5, v3, 11
+; VI-NEXT:    v_frexp_mant_f32_e32 v3, v2
+; VI-NEXT:    v_ldexp_f32 v3, v3, 1
+; VI-NEXT:    v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v2
+; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
+; VI-NEXT:    v_not_b32_e32 v4, v2
+; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
+; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v10, v9
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
+; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
+; VI-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
+; VI-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
+; VI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB0_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
+; VI-NEXT:    v_add_u32_e32 v4, vcc, 11, v4
+; VI-NEXT:  .LBB0_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v7, v5
+; VI-NEXT:    v_mul_f32_e32 v5, v7, v6
+; VI-NEXT:    v_rndne_f32_e32 v5, v5
+; VI-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; VI-NEXT:    v_add_f32_e32 v8, v5, v3
+; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
+; VI-NEXT:    v_ldexp_f32 v5, v5, 11
+; VI-NEXT:    s_cbranch_vccnz .LBB0_5
+; VI-NEXT:  ; %bb.6: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v5, v7
+; VI-NEXT:  .LBB0_7: ; %frem.loop_exit
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -10, v4
+; VI-NEXT:    v_ldexp_f32 v4, v5, v4
+; VI-NEXT:    v_mul_f32_e32 v5, v4, v6
+; VI-NEXT:    v_rndne_f32_e32 v5, v5
+; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
+; VI-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-NEXT:    v_ldexp_f32 v2, v3, v2
+; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v3, s2, v2, v0
+; VI-NEXT:  .LBB0_8: ; %Flow19
+; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    s_movk_i32 s0, 0x7c00
+; VI-NEXT:    v_mov_b32_e32 v5, s1
+; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
+; VI-NEXT:    v_cmp_nge_f16_e64 s[0:1], |v0|, s0
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_mov_b32_e32 v0, 0x7e00
+; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-NEXT:    flat_store_short v[4:5], v0
+; VI-NEXT:    s_endpgm
+;
+; GFX9-LABEL: frem_f16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    global_load_ushort v0, v2, s[2:3]
+; GFX9-NEXT:    global_load_ushort v1, v2, s[6:7] offset:8
+; GFX9-NEXT:    s_waitcnt vmcnt(1)
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v2, |v1|
+; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v2
+; GFX9-NEXT:    s_cbranch_vccz .LBB0_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v3, s2, 0, v0
+; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v2
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v0, v3, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB0_3
+; GFX9-NEXT:    s_branch .LBB0_8
+; GFX9-NEXT:  .LBB0_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr3
+; GFX9-NEXT:  .LBB0_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v3, v4
+; GFX9-NEXT:    v_ldexp_f32 v5, v3, 11
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v3, v2
+; GFX9-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX9-NEXT:    v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
+; GFX9-NEXT:    v_not_b32_e32 v4, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
+; GFX9-NEXT:    v_mul_f32_e32 v11, v6, v10
+; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
+; GFX9-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
+; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
+; GFX9-NEXT:    v_add_u32_e32 v4, 11, v4
+; GFX9-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v7, v5
+; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v6
+; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX9-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; GFX9-NEXT:    v_add_f32_e32 v8, v5, v3
+; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
+; GFX9-NEXT:    v_ldexp_f32 v5, v5, 11
+; GFX9-NEXT:    s_cbranch_vccnz .LBB0_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v5, v7
+; GFX9-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_add_u32_e32 v4, -10, v4
+; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v6
+; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
+; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v3, s2, v2, v0
+; GFX9-NEXT:  .LBB0_8: ; %Flow19
+; GFX9-NEXT:    s_movk_i32 s2, 0x7c00
+; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
+; GFX9-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v0|, s2
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7e00
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT:    global_store_short v2, v0, s[0:1]
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: frem_f16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_clause 0x1
+; GFX10-NEXT:    global_load_ushort v0, v2, s[2:3]
+; GFX10-NEXT:    global_load_ushort v1, v2, s[6:7] offset:8
+; GFX10-NEXT:    s_waitcnt vmcnt(1)
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v3, |v0|
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v2, |v1|
+; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v3, v2
+; GFX10-NEXT:    s_cbranch_vccz .LBB0_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, 0, v0
+; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX10-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB0_3
+; GFX10-NEXT:    s_branch .LBB0_8
+; GFX10-NEXT:  .LBB0_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr4
+; GFX10-NEXT:  .LBB0_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v3, v3
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX10-NEXT:    v_ldexp_f32 v4, v3, 11
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v3, v2
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
+; GFX10-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX10-NEXT:    v_div_scale_f32 v7, s4, v3, v3, 1.0
+; GFX10-NEXT:    v_not_b32_e32 v6, v2
+; GFX10-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX10-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX10-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX10-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 11
+; GFX10-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v7, v4
+; GFX10-NEXT:    s_add_i32 s2, s2, -11
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX10-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX10-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX10-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX10-NEXT:    s_cbranch_scc1 .LBB0_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v6, s2
+; GFX10-NEXT:    v_mov_b32_e32 v4, v7
+; GFX10-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX10-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, v2, v0
+; GFX10-NEXT:  .LBB0_8: ; %Flow19
+; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
+; GFX10-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
+; GFX10-NEXT:    global_store_short v2, v0, s[0:1]
+; GFX10-NEXT:    s_endpgm
+;
+; GFX11-TRUE16-LABEL: frem_f16:
+; GFX11-TRUE16:       ; %bb.0:
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-TRUE16-NEXT:    s_clause 0x1
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v0, s[4:5] offset:8
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1.l|
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v2, |v0.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB0_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v5, v4
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v1.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB0_3
+; GFX11-TRUE16-NEXT:    s_branch .LBB0_8
+; GFX11-TRUE16-NEXT:  .LBB0_2:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT:  .LBB0_3: ; %frem.compute
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v3, 11
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, v2
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-TRUE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT:    s_denorm_mode 15
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX11-TRUE16-NEXT:    s_denorm_mode 12
+; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB0_5
+; GFX11-TRUE16-NEXT:  ; %bb.6: ; %Flow
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, s2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX11-TRUE16-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v2, v3
+; GFX11-TRUE16-NEXT:  .LBB0_8: ; %Flow19
+; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT:    s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v4.l, s2
+; GFX11-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-FAKE16-LABEL: frem_f16:
+; GFX11-FAKE16:       ; %bb.0:
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-FAKE16-NEXT:    s_clause 0x1
+; GFX11-FAKE16-NEXT:    global_load_u16 v0, v1, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_u16 v1, v1, s[4:5] offset:8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v0|
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v2, |v1|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB0_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, 0, v0
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB0_3
+; GFX11-FAKE16-NEXT:    s_branch .LBB0_8
+; GFX11-FAKE16-NEXT:  .LBB0_2:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:  .LBB0_3: ; %frem.compute
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v3, 11
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, v2
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-FAKE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-FAKE16-NEXT:    s_denorm_mode 15
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX11-FAKE16-NEXT:    s_denorm_mode 12
+; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX11-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-FAKE16-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB0_5
+; GFX11-FAKE16-NEXT:  ; %bb.6: ; %Flow
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, s2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX11-FAKE16-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, v2, v0
+; GFX11-FAKE16-NEXT:  .LBB0_8: ; %Flow19
+; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    global_store_b16 v2, v0, s[0:1]
+; GFX11-FAKE16-NEXT:    s_endpgm
+;
+; GFX1150-TRUE16-LABEL: frem_f16:
+; GFX1150-TRUE16:       ; %bb.0:
+; GFX1150-TRUE16-NEXT:    s_clause 0x1
+; GFX1150-TRUE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1150-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1150-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1150-TRUE16-NEXT:    s_clause 0x1
+; GFX1150-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[10:11]
+; GFX1150-TRUE16-NEXT:    global_load_d16_b16 v1, v1, s[0:1] offset:8
+; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s1, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s1, s0
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s0, s2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT:    s_cmp_ngt_f32 s1, s0
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB0_2
+; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s1, s0
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v3, v2
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, v2.l, s2
+; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB0_3
+; GFX1150-TRUE16-NEXT:    s_branch .LBB0_8
+; GFX1150-TRUE16-NEXT:  .LBB0_2:
+; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT:  .LBB0_3: ; %frem.compute
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s0
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s1
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s1, v5
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX1150-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT:    s_sub_i32 s0, s1, s0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_add_i32 s0, s0, 11
+; GFX1150-TRUE16-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1150-TRUE16-NEXT:    s_add_i32 s0, s0, -11
+; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s0, 11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB0_5
+; GFX1150-TRUE16-NEXT:  ; %bb.6: ; %Flow
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, s0
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1150-TRUE16-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1150-TRUE16-NEXT:  .LBB0_8: ; %Flow19
+; GFX1150-TRUE16-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
+; GFX1150-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_nle_f16_e64 s0, 0x7c00, v0.l
+; GFX1150-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
+; GFX1150-TRUE16-NEXT:    global_store_b16 v3, v0, s[8:9]
+; GFX1150-TRUE16-NEXT:    s_endpgm
+;
+; GFX1150-FAKE16-LABEL: frem_f16:
+; GFX1150-FAKE16:       ; %bb.0:
+; GFX1150-FAKE16-NEXT:    s_clause 0x1
+; GFX1150-FAKE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1150-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1150-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1150-FAKE16-NEXT:    s_clause 0x1
+; GFX1150-FAKE16-NEXT:    global_load_u16 v0, v1, s[10:11]
+; GFX1150-FAKE16-NEXT:    global_load_u16 v1, v1, s[0:1] offset:8
+; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX1150-FAKE16-NEXT:    s_and_b32 s0, s0, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_and_b32 s2, s1, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s1, s0
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s0, s2
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-FAKE16-NEXT:    s_cmp_ngt_f32 s1, s0
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB0_2
+; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s1, s0
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, 0, v0
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB0_3
+; GFX1150-FAKE16-NEXT:    s_branch .LBB0_8
+; GFX1150-FAKE16-NEXT:  .LBB0_2:
+; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1150-FAKE16-NEXT:  .LBB0_3: ; %frem.compute
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s0
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s1
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s1, v5
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX1150-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT:    s_sub_i32 s0, s1, s0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_add_i32 s0, s0, 11
+; GFX1150-FAKE16-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1150-FAKE16-NEXT:    s_add_i32 s0, s0, -11
+; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s0, 11
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB0_5
+; GFX1150-FAKE16-NEXT:  ; %bb.6: ; %Flow
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, s0
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1150-FAKE16-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
+; GFX1150-FAKE16-NEXT:  .LBB0_8: ; %Flow19
+; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
+; GFX1150-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_cmp_nle_f16_e64 s0, 0x7c00, v0
+; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX1150-FAKE16-NEXT:    global_store_b16 v3, v0, s[8:9]
+; GFX1150-FAKE16-NEXT:    s_endpgm
+;
+; GFX1200-TRUE16-LABEL: frem_f16:
+; GFX1200-TRUE16:       ; %bb.0:
+; GFX1200-TRUE16-NEXT:    s_clause 0x1
+; GFX1200-TRUE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1200-TRUE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1200-TRUE16-NEXT:    s_clause 0x1
+; GFX1200-TRUE16-NEXT:    global_load_d16_b16 v0, v1, s[10:11]
+; GFX1200-TRUE16-NEXT:    global_load_d16_b16 v1, v1, s[0:1] offset:8
+; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s1, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s1, s0
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s0, s2
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1200-TRUE16-NEXT:    s_cmp_ngt_f32 s1, s0
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB0_2
+; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s1, s0
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v3, v2
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, v2.l, s2
+; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB0_3
+; GFX1200-TRUE16-NEXT:    s_branch .LBB0_8
+; GFX1200-TRUE16-NEXT:  .LBB0_2:
+; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT:  .LBB0_3: ; %frem.compute
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s0
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s1
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s1, v5
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX1200-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s0, s1, s0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s0, s0, 11
+; GFX1200-TRUE16-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s0, s0, -11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s0, 11
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB0_5
+; GFX1200-TRUE16-NEXT:  ; %bb.6: ; %Flow
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, s0
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1200-TRUE16-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1200-TRUE16-NEXT:  .LBB0_8: ; %Flow19
+; GFX1200-TRUE16-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
+; GFX1200-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_cmp_nle_f16_e64 s0, 0x7c00, v0.l
+; GFX1200-TRUE16-NEXT:    s_and_b32 s0, s0, vcc_lo
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
+; GFX1200-TRUE16-NEXT:    global_store_b16 v3, v0, s[8:9]
+; GFX1200-TRUE16-NEXT:    s_endpgm
+;
+; GFX1200-FAKE16-LABEL: frem_f16:
+; GFX1200-FAKE16:       ; %bb.0:
+; GFX1200-FAKE16-NEXT:    s_clause 0x1
+; GFX1200-FAKE16-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1200-FAKE16-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1200-FAKE16-NEXT:    s_clause 0x1
+; GFX1200-FAKE16-NEXT:    global_load_u16 v0, v1, s[10:11]
+; GFX1200-FAKE16-NEXT:    global_load_u16 v1, v1, s[0:1] offset:8
+; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX1200-FAKE16-NEXT:    s_and_b32 s0, s0, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_and_b32 s2, s1, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s1, s0
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s0, s2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1200-FAKE16-NEXT:    s_cmp_ngt_f32 s1, s0
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB0_2
+; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s1, s0
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, 0, v0
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB0_3
+; GFX1200-FAKE16-NEXT:    s_branch .LBB0_8
+; GFX1200-FAKE16-NEXT:  .LBB0_2:
+; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1200-FAKE16-NEXT:  .LBB0_3: ; %frem.compute
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s0
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s1
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s1, v5
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB0_7
+; GFX1200-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s0, s1, s0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s0, s0, 11
+; GFX1200-FAKE16-NEXT:  .LBB0_5: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s0, s0, -11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s0, 11
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB0_5
+; GFX1200-FAKE16-NEXT:  ; %bb.6: ; %Flow
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, s0
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1200-FAKE16-NEXT:  .LBB0_7: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
+; GFX1200-FAKE16-NEXT:  .LBB0_8: ; %Flow19
+; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
+; GFX1200-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_cmp_nle_f16_e64 s0, 0x7c00, v0
+; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX1200-FAKE16-NEXT:    global_store_b16 v3, v0, s[8:9]
+; GFX1200-FAKE16-NEXT:    s_endpgm
+                      ptr addrspace(1) %in2) #0 {
+   %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4
+   %r0 = load half, ptr addrspace(1) %in1, align 4
+   %r1 = load half, ptr addrspace(1) %gep2, align 4
+   %r2 = frem half %r0, %r1
+   store half %r2, ptr addrspace(1) %out, align 4
+   ret void
+}
+
+define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,
+; SI-LABEL: fast_frem_f16:
+; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
 ; SI-NEXT:    s_mov_b32 s11, 0xf000
@@ -53,7 +1297,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; SI-NEXT:    buffer_store_short v0, off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
-; CI-LABEL: frem_f16:
+; CI-LABEL: fast_frem_f16:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -94,7 +1338,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
 ; CI-NEXT:    s_endpgm
 ;
-; VI-LABEL: frem_f16:
+; VI-LABEL: fast_frem_f16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -128,7 +1372,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: frem_f16:
+; GFX9-LABEL: fast_frem_f16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -155,7 +1399,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX10-LABEL: frem_f16:
+; GFX10-LABEL: fast_frem_f16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
@@ -184,7 +1428,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-TRUE16-LABEL: frem_f16:
+; GFX11-TRUE16-LABEL: fast_frem_f16:
 ; GFX11-TRUE16:       ; %bb.0:
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
 ; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -222,7 +1466,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX11-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
 ; GFX11-TRUE16-NEXT:    s_endpgm
 ;
-; GFX11-FAKE16-LABEL: frem_f16:
+; GFX11-FAKE16-LABEL: fast_frem_f16:
 ; GFX11-FAKE16:       ; %bb.0:
 ; GFX11-FAKE16-NEXT:    s_clause 0x1
 ; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -258,7 +1502,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX1150-TRUE16-LABEL: frem_f16:
+; GFX1150-TRUE16-LABEL: fast_frem_f16:
 ; GFX1150-TRUE16:       ; %bb.0:
 ; GFX1150-TRUE16-NEXT:    s_clause 0x1
 ; GFX1150-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -297,7 +1541,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX1150-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
 ; GFX1150-TRUE16-NEXT:    s_endpgm
 ;
-; GFX1150-FAKE16-LABEL: frem_f16:
+; GFX1150-FAKE16-LABEL: fast_frem_f16:
 ; GFX1150-FAKE16:       ; %bb.0:
 ; GFX1150-FAKE16-NEXT:    s_clause 0x1
 ; GFX1150-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -334,7 +1578,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX1150-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
 ; GFX1150-FAKE16-NEXT:    s_endpgm
 ;
-; GFX1200-TRUE16-LABEL: frem_f16:
+; GFX1200-TRUE16-LABEL: fast_frem_f16:
 ; GFX1200-TRUE16:       ; %bb.0:
 ; GFX1200-TRUE16-NEXT:    s_clause 0x1
 ; GFX1200-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -373,7 +1617,7 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX1200-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
 ; GFX1200-TRUE16-NEXT:    s_endpgm
 ;
-; GFX1200-FAKE16-LABEL: frem_f16:
+; GFX1200-FAKE16-LABEL: fast_frem_f16:
 ; GFX1200-FAKE16:       ; %bb.0:
 ; GFX1200-FAKE16-NEXT:    s_clause 0x1
 ; GFX1200-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -413,13 +1657,13 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
    %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4
    %r0 = load half, ptr addrspace(1) %in1, align 4
    %r1 = load half, ptr addrspace(1) %gep2, align 4
-   %r2 = frem half %r0, %r1
+   %r2 = frem fast half %r0, %r1
    store half %r2, ptr addrspace(1) %out, align 4
    ret void
 }
 
-define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,
-; SI-LABEL: fast_frem_f16:
+define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,
+; SI-LABEL: unsafe_frem_f16:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -440,44 +1684,68 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; SI-NEXT:    buffer_load_ushort v1, off, s[4:7], 0 offset:8
 ; SI-NEXT:    s_waitcnt vmcnt(0)
 ; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT:    v_rcp_f32_e32 v2, v1
-; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
+; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
+; SI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
+; SI-NEXT:    v_rcp_f32_e32 v4, v3
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
+; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
+; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
+; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
+; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
+; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
 ; SI-NEXT:    v_trunc_f32_e32 v2, v2
 ; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; SI-NEXT:    buffer_store_short v0, off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
-; CI-LABEL: fast_frem_f16:
+; CI-LABEL: unsafe_frem_f16:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
 ; CI-NEXT:    s_mov_b32 s11, 0xf000
 ; CI-NEXT:    s_mov_b32 s10, -1
 ; CI-NEXT:    s_mov_b32 s6, s10
-; CI-NEXT:    s_mov_b32 s7, s11
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    buffer_load_ushort v1, off, s[4:7], 0 offset:8
 ; CI-NEXT:    s_mov_b32 s8, s0
 ; CI-NEXT:    s_mov_b32 s9, s1
 ; CI-NEXT:    s_mov_b32 s0, s2
 ; CI-NEXT:    s_mov_b32 s1, s3
 ; CI-NEXT:    s_mov_b32 s2, s10
 ; CI-NEXT:    s_mov_b32 s3, s11
+; CI-NEXT:    s_mov_b32 s7, s11
 ; CI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
+; CI-NEXT:    buffer_load_ushort v1, off, s[4:7], 0 offset:8
 ; CI-NEXT:    s_waitcnt vmcnt(1)
-; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT:    v_rcp_f32_e32 v2, v1
-; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
+; CI-NEXT:    s_waitcnt vmcnt(0)
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
+; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
+; CI-NEXT:    v_rcp_f32_e32 v4, v3
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
+; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
+; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
+; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
+; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
+; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
 ; CI-NEXT:    v_trunc_f32_e32 v2, v2
 ; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
 ; CI-NEXT:    s_endpgm
 ;
-; VI-LABEL: fast_frem_f16:
+; VI-LABEL: unsafe_frem_f16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -492,15 +1760,26 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_load_ushort v2, v[2:3]
+; VI-NEXT:    s_waitcnt vmcnt(1)
+; VI-NEXT:    v_cvt_f32_f16_e32 v3, v4
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_rcp_f16_e32 v3, v2
-; VI-NEXT:    v_mul_f16_e32 v3, v4, v3
+; VI-NEXT:    v_cvt_f32_f16_e32 v5, v2
+; VI-NEXT:    v_rcp_f32_e32 v6, v5
+; VI-NEXT:    v_mul_f32_e32 v7, v3, v6
+; VI-NEXT:    v_mad_f32 v8, -v5, v7, v3
+; VI-NEXT:    v_mac_f32_e32 v7, v8, v6
+; VI-NEXT:    v_mad_f32 v3, -v5, v7, v3
+; VI-NEXT:    v_mul_f32_e32 v3, v3, v6
+; VI-NEXT:    v_and_b32_e32 v3, 0xff800000, v3
+; VI-NEXT:    v_add_f32_e32 v3, v3, v7
+; VI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; VI-NEXT:    v_div_fixup_f16 v3, v3, v2, v4
 ; VI-NEXT:    v_trunc_f16_e32 v3, v3
 ; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
 ; VI-NEXT:    flat_store_short v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: fast_frem_f16:
+; GFX9-LABEL: unsafe_frem_f16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -508,15 +1787,26 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3]
 ; GFX9-NEXT:    global_load_ushort v2, v0, s[6:7] offset:8
+; GFX9-NEXT:    s_waitcnt vmcnt(1)
+; GFX9-NEXT:    v_cvt_f32_f16_e32 v3, v1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX9-NEXT:    v_mul_f16_e32 v3, v1, v3
+; GFX9-NEXT:    v_cvt_f32_f16_e32 v4, v2
+; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX9-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX9-NEXT:    v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX9-NEXT:    v_mac_f32_e32 v3, v5, v4
+; GFX9-NEXT:    v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX9-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX9-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
 ; GFX9-NEXT:    v_trunc_f16_e32 v3, v3
 ; GFX9-NEXT:    v_fma_f16 v1, -v3, v2, v1
 ; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX10-LABEL: fast_frem_f16:
+; GFX10-LABEL: unsafe_frem_f16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
@@ -526,15 +1816,26 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3]
 ; GFX10-NEXT:    global_load_ushort v2, v0, s[6:7] offset:8
+; GFX10-NEXT:    s_waitcnt vmcnt(1)
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX10-NEXT:    v_mul_f16_e32 v3, v1, v3
+; GFX10-NEXT:    v_cvt_f32_f16_e32 v4, v2
+; GFX10-NEXT:    v_rcp_f32_e32 v5, v4
+; GFX10-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX10-NEXT:    v_mad_f32 v7, -v4, v6, v3
+; GFX10-NEXT:    v_mac_f32_e32 v6, v7, v5
+; GFX10-NEXT:    v_mad_f32 v3, -v4, v6, v3
+; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v5
+; GFX10-NEXT:    v_and_b32_e32 v3, 0xff800000, v3
+; GFX10-NEXT:    v_add_f32_e32 v3, v3, v6
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
 ; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
 ; GFX10-NEXT:    v_fma_f16 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-TRUE16-LABEL: fast_frem_f16:
+; GFX11-TRUE16-LABEL: unsafe_frem_f16:
 ; GFX11-TRUE16:       ; %bb.0:
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
 ; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -543,18 +1844,36 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
 ; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
-; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
+; GFX11-TRUE16-NEXT:    global_load_d16_b16 v1, v2, s[4:5] offset:8
+; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v0.l
 ; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
 ; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v3, v7, v4
+; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v1.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v1.l, v0.l
+; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.h, v1.l, v0.l
 ; GFX11-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
 ; GFX11-TRUE16-NEXT:    s_endpgm
 ;
-; GFX11-FAKE16-LABEL: fast_frem_f16:
+; GFX11-FAKE16-LABEL: unsafe_frem_f16:
 ; GFX11-FAKE16:       ; %bb.0:
 ; GFX11-FAKE16-NEXT:    s_clause 0x1
 ; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -564,17 +1883,33 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX11-FAKE16-NEXT:    s_clause 0x1
 ; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
 ; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
+; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v4, v4
 ; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v5, v4
+; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
 ; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v3, v2, v1
 ; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
-; GFX1150-TRUE16-LABEL: fast_frem_f16:
+; GFX1150-TRUE16-LABEL: unsafe_frem_f16:
 ; GFX1150-TRUE16:       ; %bb.0:
 ; GFX1150-TRUE16-NEXT:    s_clause 0x1
 ; GFX1150-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -583,19 +1918,37 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX1150-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1150-TRUE16-NEXT:    s_clause 0x1
 ; GFX1150-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
-; GFX1150-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
+; GFX1150-TRUE16-NEXT:    global_load_d16_b16 v1, v2, s[4:5] offset:8
+; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v0.l
 ; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
+; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v1.l
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.l
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v3, v4
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x8000, v1
-; GFX1150-TRUE16-NEXT:    v_fmac_f16_e32 v0.l, v1.l, v0.h
+; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v3, v7, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v5, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v3
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v1.l, v0.l
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v3.l, v0.h
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x8000, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fmac_f16_e32 v0.l, v3.l, v1.l
 ; GFX1150-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
 ; GFX1150-TRUE16-NEXT:    s_endpgm
 ;
-; GFX1150-FAKE16-LABEL: fast_frem_f16:
+; GFX1150-FAKE16-LABEL: unsafe_frem_f16:
 ; GFX1150-FAKE16:       ; %bb.0:
 ; GFX1150-FAKE16-NEXT:    s_clause 0x1
 ; GFX1150-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -605,18 +1958,34 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX1150-FAKE16-NEXT:    s_clause 0x1
 ; GFX1150-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
 ; GFX1150-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
+; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(1)
+; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
 ; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v2
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v3, v5, v4
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
 ; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x8000, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX1150-FAKE16-NEXT:    v_fmac_f16_e32 v1, v3, v2
 ; GFX1150-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
 ; GFX1150-FAKE16-NEXT:    s_endpgm
 ;
-; GFX1200-TRUE16-LABEL: fast_frem_f16:
+; GFX1200-TRUE16-LABEL: unsafe_frem_f16:
 ; GFX1200-TRUE16:       ; %bb.0:
 ; GFX1200-TRUE16-NEXT:    s_clause 0x1
 ; GFX1200-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -625,19 +1994,37 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
 ; GFX1200-TRUE16-NEXT:    s_clause 0x1
 ; GFX1200-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
-; GFX1200-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
+; GFX1200-TRUE16-NEXT:    global_load_d16_b16 v1, v2, s[4:5] offset:8
+; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x1
+; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v3, v0.l
 ; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
+; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v1.l
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v1.l
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v0.l
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v3, v7, v4
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x8000, v1
-; GFX1200-TRUE16-NEXT:    v_fmac_f16_e32 v0.l, v1.l, v0.h
+; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v5, -v5, v3, v6 op_sel_hi:[1,0,1]
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v3
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v1.l, v0.l
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v3.l, v0.h
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x8000, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f16_e32 v0.l, v3.l, v1.l
 ; GFX1200-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
 ; GFX1200-TRUE16-NEXT:    s_endpgm
 ;
-; GFX1200-FAKE16-LABEL: fast_frem_f16:
+; GFX1200-FAKE16-LABEL: unsafe_frem_f16:
 ; GFX1200-FAKE16:       ; %bb.0:
 ; GFX1200-FAKE16-NEXT:    s_clause 0x1
 ; GFX1200-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -647,275 +2034,856 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX1200-FAKE16-NEXT:    s_clause 0x1
 ; GFX1200-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
 ; GFX1200-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
+; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x1
+; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
 ; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
+; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v3, v5, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v5, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
 ; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x8000, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX1200-FAKE16-NEXT:    v_fmac_f16_e32 v1, v3, v2
 ; GFX1200-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
 ; GFX1200-FAKE16-NEXT:    s_endpgm
-                      ptr addrspace(1) %in2) #0 {
+                             ptr addrspace(1) %in2) #1 {
    %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4
    %r0 = load half, ptr addrspace(1) %in1, align 4
    %r1 = load half, ptr addrspace(1) %gep2, align 4
-   %r2 = frem fast half %r0, %r1
+   %r2 = frem afn half %r0, %r1
    store half %r2, ptr addrspace(1) %out, align 4
    ret void
 }
 
-define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1,
-; SI-LABEL: unsafe_frem_f16:
+define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
+; SI-LABEL: frem_f32:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
 ; SI-NEXT:    s_mov_b32 s11, 0xf000
 ; SI-NEXT:    s_mov_b32 s10, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s8, s0
-; SI-NEXT:    s_mov_b32 s9, s1
-; SI-NEXT:    s_mov_b32 s0, s2
-; SI-NEXT:    s_mov_b32 s1, s3
-; SI-NEXT:    s_mov_b32 s2, s10
-; SI-NEXT:    s_mov_b32 s3, s11
+; SI-NEXT:    s_mov_b32 s8, s2
+; SI-NEXT:    s_mov_b32 s9, s3
 ; SI-NEXT:    s_mov_b32 s6, s10
 ; SI-NEXT:    s_mov_b32 s7, s11
-; SI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
-; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT:    buffer_load_ushort v1, off, s[4:7], 0 offset:8
+; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
+; SI-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:16
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT:    v_rcp_f32_e32 v2, v1
-; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
-; SI-NEXT:    v_trunc_f32_e32 v2, v2
-; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
-; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT:    buffer_store_short v0, off, s[8:11], 0
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    s_cbranch_vccz .LBB3_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v2, s2, 0, v0
+; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; SI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB3_3
+; SI-NEXT:    s_branch .LBB3_8
+; SI-NEXT:  .LBB3_2:
+; SI-NEXT:    ; implicit-def: $vgpr2
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB3_3: ; %frem.compute
+; SI-NEXT:    s_mov_b32 s6, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v0|, s6
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v2, v0
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s4, v2
+; SI-NEXT:    s_cselect_b32 s4, s4, 0
+; SI-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
+; SI-NEXT:    v_cndmask_b32_e64 v2, |v0|, v2, s[2:3]
+; SI-NEXT:    v_ldexp_f32_e64 v3, v2, 12
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v1|, s6
+; SI-NEXT:    v_frexp_mant_f32_e64 v2, |v1|
+; SI-NEXT:    v_cndmask_b32_e64 v2, |v1|, v2, s[2:3]
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v1
+; SI-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v4
+; SI-NEXT:    s_cselect_b32 s5, s2, 0
+; SI-NEXT:    s_add_i32 s2, s5, -1
+; SI-NEXT:    v_ldexp_f32_e64 v2, v2, 1
+; SI-NEXT:    s_not_b32 s3, s2
+; SI-NEXT:    s_add_i32 s3, s3, s4
+; SI-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v2, 1.0
+; SI-NEXT:    v_div_scale_f32 v5, s[6:7], v2, v2, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v6, v5
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
+; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
+; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
+; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
+; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
+; SI-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s3, 13
+; SI-NEXT:    s_cbranch_scc1 .LBB3_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s3, s4, s5
+; SI-NEXT:    s_add_i32 s3, s3, 12
+; SI-NEXT:  .LBB3_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v5, v3
+; SI-NEXT:    v_mul_f32_e32 v3, v5, v4
+; SI-NEXT:    v_rndne_f32_e32 v3, v3
+; SI-NEXT:    v_fma_f32 v3, -v3, v2, v5
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT:    v_add_f32_e32 v6, v3, v2
+; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v3, v3, 12
+; SI-NEXT:    s_add_i32 s3, s3, -12
+; SI-NEXT:    s_cmp_gt_i32 s3, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB3_5
+; SI-NEXT:  ; %bb.6: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v3, v5
+; SI-NEXT:  .LBB3_7: ; %frem.loop_exit
+; SI-NEXT:    s_add_i32 s3, s3, -11
+; SI-NEXT:    v_ldexp_f32_e64 v3, v3, s3
+; SI-NEXT:    v_mul_f32_e32 v4, v3, v4
+; SI-NEXT:    v_rndne_f32_e32 v4, v4
+; SI-NEXT:    v_fma_f32 v3, -v4, v2, v3
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v3
+; SI-NEXT:    v_add_f32_e32 v2, v3, v2
+; SI-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v2, v2, s2
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v2, s2, v2, v0
+; SI-NEXT:  .LBB3_8: ; %Flow17
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
+; SI-NEXT:    s_mov_b32 s4, 0x7f800000
+; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s4
+; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; SI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; SI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
-; CI-LABEL: unsafe_frem_f16:
+; CI-LABEL: frem_f32:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
 ; CI-NEXT:    s_mov_b32 s11, 0xf000
 ; CI-NEXT:    s_mov_b32 s10, -1
 ; CI-NEXT:    s_mov_b32 s6, s10
-; CI-NEXT:    s_mov_b32 s7, s11
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    buffer_load_ushort v1, off, s[4:7], 0 offset:8
-; CI-NEXT:    s_mov_b32 s8, s0
-; CI-NEXT:    s_mov_b32 s9, s1
-; CI-NEXT:    s_mov_b32 s0, s2
-; CI-NEXT:    s_mov_b32 s1, s3
-; CI-NEXT:    s_mov_b32 s2, s10
-; CI-NEXT:    s_mov_b32 s3, s11
-; CI-NEXT:    buffer_load_ushort v0, off, s[0:3], 0
-; CI-NEXT:    s_waitcnt vmcnt(1)
-; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT:    v_rcp_f32_e32 v2, v1
+; CI-NEXT:    s_mov_b32 s8, s2
+; CI-NEXT:    s_mov_b32 s9, s3
+; CI-NEXT:    s_mov_b32 s7, s11
+; CI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
+; CI-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:16
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
-; CI-NEXT:    v_trunc_f32_e32 v2, v2
-; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
-; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT:    buffer_store_short v0, off, s[8:11], 0
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB3_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v2, s2, 0, v0
+; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; CI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
+; CI-NEXT:    s_cbranch_execz .LBB3_3
+; CI-NEXT:    s_branch .LBB3_8
+; CI-NEXT:  .LBB3_2:
+; CI-NEXT:    ; implicit-def: $vgpr2
+; CI-NEXT:  .LBB3_3: ; %frem.compute
+; CI-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
+; CI-NEXT:    v_ldexp_f32_e64 v3, v3, 1
+; CI-NEXT:    v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
+; CI-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
+; CI-NEXT:    v_ldexp_f32_e64 v5, v2, 12
+; CI-NEXT:    v_add_i32_e32 v2, vcc, -1, v8
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
+; CI-NEXT:    v_not_b32_e32 v4, v2
+; CI-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v10, v9
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
+; CI-NEXT:    v_mul_f32_e32 v11, v6, v10
+; CI-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
+; CI-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
+; CI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB3_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v4, vcc, v7, v8
+; CI-NEXT:    v_add_i32_e32 v4, vcc, 12, v4
+; CI-NEXT:  .LBB3_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v7, v5
+; CI-NEXT:    v_mul_f32_e32 v5, v7, v6
+; CI-NEXT:    v_rndne_f32_e32 v5, v5
+; CI-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; CI-NEXT:    v_add_f32_e32 v8, v5, v3
+; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; CI-NEXT:    v_add_i32_e32 v4, vcc, -12, v4
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
+; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 12
+; CI-NEXT:    s_cbranch_vccnz .LBB3_5
+; CI-NEXT:  ; %bb.6: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v5, v7
+; CI-NEXT:  .LBB3_7: ; %frem.loop_exit
+; CI-NEXT:    v_add_i32_e32 v4, vcc, -11, v4
+; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT:    v_mul_f32_e32 v5, v4, v6
+; CI-NEXT:    v_rndne_f32_e32 v5, v5
+; CI-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
+; CI-NEXT:    v_add_f32_e32 v3, v4, v3
+; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v2, v3, v2
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v2, s2, v2, v0
+; CI-NEXT:  .LBB3_8: ; %Flow17
+; CI-NEXT:    s_mov_b32 s4, 0x7f800000
+; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
+; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v0|, s4
+; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; CI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; CI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; CI-NEXT:    s_endpgm
 ;
-; VI-LABEL: unsafe_frem_f16:
+; VI-LABEL: frem_f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_add_u32 s0, s4, 8
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    s_addc_u32 s1, s5, 0
-; VI-NEXT:    flat_load_ushort v4, v[2:3]
-; VI-NEXT:    v_mov_b32_e32 v3, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s0
-; VI-NEXT:    flat_load_ushort v2, v[2:3]
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    s_add_u32 s2, s4, 16
+; VI-NEXT:    s_addc_u32 s3, s5, 0
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    v_mov_b32_e32 v1, s2
+; VI-NEXT:    v_mov_b32_e32 v2, s3
+; VI-NEXT:    flat_load_dword v1, v[1:2]
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_rcp_f16_e32 v3, v2
-; VI-NEXT:    v_mul_f16_e32 v3, v4, v3
-; VI-NEXT:    v_trunc_f16_e32 v3, v3
-; VI-NEXT:    v_fma_f16 v2, -v3, v2, v4
-; VI-NEXT:    flat_store_short v[0:1], v2
+; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB3_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v2, s2, 0, v0
+; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-NEXT:    s_cbranch_execz .LBB3_3
+; VI-NEXT:    s_branch .LBB3_8
+; VI-NEXT:  .LBB3_2:
+; VI-NEXT:    ; implicit-def: $vgpr2
+; VI-NEXT:  .LBB3_3: ; %frem.compute
+; VI-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
+; VI-NEXT:    v_ldexp_f32 v3, v3, 1
+; VI-NEXT:    v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
+; VI-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
+; VI-NEXT:    v_ldexp_f32 v5, v2, 12
+; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
+; VI-NEXT:    v_not_b32_e32 v4, v2
+; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
+; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v10, v9
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
+; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
+; VI-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
+; VI-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
+; VI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB3_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
+; VI-NEXT:    v_add_u32_e32 v4, vcc, 12, v4
+; VI-NEXT:  .LBB3_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v7, v5
+; VI-NEXT:    v_mul_f32_e32 v5, v7, v6
+; VI-NEXT:    v_rndne_f32_e32 v5, v5
+; VI-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; VI-NEXT:    v_add_f32_e32 v8, v5, v3
+; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -12, v4
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
+; VI-NEXT:    v_ldexp_f32 v5, v5, 12
+; VI-NEXT:    s_cbranch_vccnz .LBB3_5
+; VI-NEXT:  ; %bb.6: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v5, v7
+; VI-NEXT:  .LBB3_7: ; %frem.loop_exit
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
+; VI-NEXT:    v_ldexp_f32 v4, v5, v4
+; VI-NEXT:    v_mul_f32_e32 v5, v4, v6
+; VI-NEXT:    v_rndne_f32_e32 v5, v5
+; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
+; VI-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-NEXT:    v_ldexp_f32 v2, v3, v2
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v2, s2, v2, v0
+; VI-NEXT:  .LBB3_8: ; %Flow17
+; VI-NEXT:    v_mov_b32_e32 v3, s0
+; VI-NEXT:    s_mov_b32 s0, 0x7f800000
+; VI-NEXT:    v_mov_b32_e32 v4, s1
+; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
+; VI-NEXT:    v_cmp_nge_f32_e64 s[0:1], |v0|, s0
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; VI-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; VI-NEXT:    flat_store_dword v[3:4], v0
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: unsafe_frem_f16:
+; GFX9-LABEL: frem_f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_ushort v1, v0, s[2:3]
-; GFX9-NEXT:    global_load_ushort v2, v0, s[6:7] offset:8
+; GFX9-NEXT:    global_load_dword v0, v2, s[2:3]
+; GFX9-NEXT:    global_load_dword v1, v2, s[6:7] offset:16
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX9-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX9-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX9-NEXT:    v_fma_f16 v1, -v3, v2, v1
-; GFX9-NEXT:    global_store_short v0, v1, s[0:1]
+; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v1|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB3_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v2, s2, 0, v0
+; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v1|
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB3_3
+; GFX9-NEXT:    s_branch .LBB3_8
+; GFX9-NEXT:  .LBB3_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr2
+; GFX9-NEXT:  .LBB3_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
+; GFX9-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX9-NEXT:    v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
+; GFX9-NEXT:    v_ldexp_f32 v5, v2, 12
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
+; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
+; GFX9-NEXT:    v_not_b32_e32 v4, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
+; GFX9-NEXT:    v_mul_f32_e32 v11, v6, v10
+; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
+; GFX9-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v4
+; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB3_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
+; GFX9-NEXT:    v_add_u32_e32 v4, 12, v4
+; GFX9-NEXT:  .LBB3_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v7, v5
+; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v6
+; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX9-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; GFX9-NEXT:    v_add_f32_e32 v8, v5, v3
+; GFX9-NEXT:    v_add_u32_e32 v4, -12, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v4
+; GFX9-NEXT:    v_ldexp_f32 v5, v5, 12
+; GFX9-NEXT:    s_cbranch_vccnz .LBB3_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v5, v7
+; GFX9-NEXT:  .LBB3_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
+; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v6
+; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
+; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v2, s2, v2, v0
+; GFX9-NEXT:  .LBB3_8: ; %Flow17
+; GFX9-NEXT:    s_mov_b32 s2, 0x7f800000
+; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v1
+; GFX9-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s2
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-NEXT:    global_store_dword v3, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX10-LABEL: unsafe_frem_f16:
+; GFX10-LABEL: frem_f32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3]
-; GFX10-NEXT:    global_load_ushort v2, v0, s[6:7] offset:8
+; GFX10-NEXT:    global_load_dword v0, v2, s[2:3]
+; GFX10-NEXT:    global_load_dword v1, v2, s[6:7] offset:16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX10-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fma_f16 v1, -v3, v2, v1
-; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
+; GFX10-NEXT:    v_cmp_ngt_f32_e64 s2, |v0|, |v1|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB3_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_bfi_b32 v2, 0x7fffffff, 0, v0
+; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB3_3
+; GFX10-NEXT:    s_branch .LBB3_8
+; GFX10-NEXT:  .LBB3_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr2
+; GFX10-NEXT:  .LBB3_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v5, v0
+; GFX10-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX10-NEXT:    v_ldexp_f32 v4, v2, 12
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v2, v1
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX10-NEXT:    v_div_scale_f32 v7, s4, v3, v3, 1.0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX10-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX10-NEXT:    v_not_b32_e32 v6, v2
+; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX10-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX10-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX10-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
+; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB3_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 12
+; GFX10-NEXT:  .LBB3_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v7, v4
+; GFX10-NEXT:    s_add_i32 s2, s2, -12
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX10-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX10-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX10-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v4, v4, 12
+; GFX10-NEXT:    s_cbranch_scc1 .LBB3_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v6, s2
+; GFX10-NEXT:    v_mov_b32_e32 v4, v7
+; GFX10-NEXT:  .LBB3_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_add_nc_u32_e32 v6, -11, v6
+; GFX10-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX10-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, v0
+; GFX10-NEXT:  .LBB3_8: ; %Flow17
+; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v1
+; GFX10-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
+; GFX10-NEXT:    v_mov_b32_e32 v3, 0
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
+; GFX10-NEXT:    global_store_dword v3, v0, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-TRUE16-LABEL: unsafe_frem_f16:
-; GFX11-TRUE16:       ; %bb.0:
-; GFX11-TRUE16-NEXT:    s_clause 0x1
-; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT:    s_clause 0x1
-; GFX11-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
-; GFX11-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
-; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
-; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v1.l, v0.h, v0.l
-; GFX11-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
-; GFX11-TRUE16-NEXT:    s_endpgm
-;
-; GFX11-FAKE16-LABEL: unsafe_frem_f16:
-; GFX11-FAKE16:       ; %bb.0:
-; GFX11-FAKE16-NEXT:    s_clause 0x1
-; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
-; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT:    s_clause 0x1
-; GFX11-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX11-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
-; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v3, v2, v1
-; GFX11-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT:    s_endpgm
-;
-; GFX1150-TRUE16-LABEL: unsafe_frem_f16:
-; GFX1150-TRUE16:       ; %bb.0:
-; GFX1150-TRUE16-NEXT:    s_clause 0x1
-; GFX1150-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX1150-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1150-TRUE16-NEXT:    s_clause 0x1
-; GFX1150-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
-; GFX1150-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
-; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x8000, v1
-; GFX1150-TRUE16-NEXT:    v_fmac_f16_e32 v0.l, v1.l, v0.h
-; GFX1150-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
-; GFX1150-TRUE16-NEXT:    s_endpgm
-;
-; GFX1150-FAKE16-LABEL: unsafe_frem_f16:
-; GFX1150-FAKE16:       ; %bb.0:
-; GFX1150-FAKE16-NEXT:    s_clause 0x1
-; GFX1150-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
-; GFX1150-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1150-FAKE16-NEXT:    s_clause 0x1
-; GFX1150-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX1150-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
-; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x8000, v3
-; GFX1150-FAKE16-NEXT:    v_fmac_f16_e32 v1, v3, v2
-; GFX1150-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX1150-FAKE16-NEXT:    s_endpgm
+; GFX11-LABEL: frem_f32:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX11-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    global_load_b32 v0, v1, s[2:3]
+; GFX11-NEXT:    global_load_b32 v1, v1, s[4:5] offset:16
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s2, |v0|, |v1|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB3_2
+; GFX11-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-NEXT:    v_bfi_b32 v2, 0x7fffffff, 0, v0
+; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v1|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB3_3
+; GFX11-NEXT:    s_branch .LBB3_8
+; GFX11-NEXT:  .LBB3_2:
+; GFX11-NEXT:    ; implicit-def: $vgpr2
+; GFX11-NEXT:  .LBB3_3: ; %frem.compute
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v3, |v1|
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v2, |v0|
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v5, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX11-NEXT:    v_ldexp_f32 v4, v2, 12
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v2, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX11-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX11-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX11-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v6, v2
+; GFX11-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX11-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-NEXT:    s_denorm_mode 15
+; GFX11-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX11-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX11-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB3_7
+; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 12
+; GFX11-NEXT:  .LBB3_5: ; %frem.loop_body
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_mov_b32_e32 v7, v4
+; GFX11-NEXT:    s_add_i32 s2, s2, -12
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX11-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v4, v4, 12
+; GFX11-NEXT:    s_cbranch_scc1 .LBB3_5
+; GFX11-NEXT:  ; %bb.6: ; %Flow
+; GFX11-NEXT:    v_mov_b32_e32 v6, s2
+; GFX11-NEXT:    v_mov_b32_e32 v4, v7
+; GFX11-NEXT:  .LBB3_7: ; %frem.loop_exit
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_add_nc_u32_e32 v6, -11, v6
+; GFX11-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX11-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, v0
+; GFX11-NEXT:  .LBB3_8: ; %Flow17
+; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v1
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v0, 0x7fc00000, v2
+; GFX11-NEXT:    global_store_b32 v3, v0, s[0:1]
+; GFX11-NEXT:    s_endpgm
 ;
-; GFX1200-TRUE16-LABEL: unsafe_frem_f16:
-; GFX1200-TRUE16:       ; %bb.0:
-; GFX1200-TRUE16-NEXT:    s_clause 0x1
-; GFX1200-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1200-TRUE16-NEXT:    s_clause 0x1
-; GFX1200-TRUE16-NEXT:    global_load_d16_b16 v0, v2, s[2:3]
-; GFX1200-TRUE16-NEXT:    global_load_d16_hi_b16 v0, v2, s[4:5] offset:8
-; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT:    v_rcp_f16_e32 v1.l, v0.h
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_mul_f16_e32 v1.l, v0.l, v1.l
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v1.l, v1.l
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v1, 0x8000, v1
-; GFX1200-TRUE16-NEXT:    v_fmac_f16_e32 v0.l, v1.l, v0.h
-; GFX1200-TRUE16-NEXT:    global_store_b16 v2, v0, s[0:1]
-; GFX1200-TRUE16-NEXT:    s_endpgm
+; GFX1150-LABEL: frem_f32:
+; GFX1150:       ; %bb.0:
+; GFX1150-NEXT:    s_clause 0x1
+; GFX1150-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1150-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1150-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1150-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX1150-NEXT:    s_clause 0x1
+; GFX1150-NEXT:    global_load_b32 v2, v0, s[10:11]
+; GFX1150-NEXT:    global_load_b32 v0, v0, s[0:1] offset:16
+; GFX1150-NEXT:    s_waitcnt vmcnt(1)
+; GFX1150-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX1150-NEXT:    s_waitcnt vmcnt(0)
+; GFX1150-NEXT:    v_and_b32_e32 v3, 0x7fffffff, v0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v1, v3
+; GFX1150-NEXT:    s_cbranch_vccz .LBB3_2
+; GFX1150-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-NEXT:    v_bfi_b32 v4, 0x7fffffff, 0, v2
+; GFX1150-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v3
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v2, v4, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB3_3
+; GFX1150-NEXT:    s_branch .LBB3_8
+; GFX1150-NEXT:  .LBB3_2:
+; GFX1150-NEXT:    ; implicit-def: $vgpr3
+; GFX1150-NEXT:  .LBB3_3: ; %frem.compute
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v3, |v2|
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1150-NEXT:    v_ldexp_f32 v5, v3, 12
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, v0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_readfirstlane_b32 s0, v6
+; GFX1150-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_readfirstlane_b32 s1, v3
+; GFX1150-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-NEXT:    v_rcp_f32_e32 v9, v8
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v7, v3
+; GFX1150-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1150-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1150-NEXT:    s_denorm_mode 15
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; GFX1150-NEXT:    v_fmac_f32_e32 v9, v10, v9
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1150-NEXT:    v_fma_f32 v11, -v8, v10, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fmac_f32_e32 v10, v11, v9
+; GFX1150-NEXT:    v_fma_f32 v6, -v8, v10, v6
+; GFX1150-NEXT:    s_denorm_mode 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
+; GFX1150-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB3_7
+; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-NEXT:    s_sub_i32 s0, s0, s1
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s0, s0, 12
+; GFX1150-NEXT:  .LBB3_5: ; %frem.loop_body
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1150-NEXT:    s_add_i32 s0, s0, -12
+; GFX1150-NEXT:    s_cmp_gt_i32 s0, 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v5, v8, v6
+; GFX1150-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-NEXT:    v_fma_f32 v5, v5, v4, v8
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v5, v5, 12
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB3_5
+; GFX1150-NEXT:  ; %bb.6: ; %Flow
+; GFX1150-NEXT:    v_mov_b32_e32 v7, s0
+; GFX1150-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1150-NEXT:  .LBB3_7: ; %frem.loop_exit
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_add_nc_u32_e32 v7, -11, v7
+; GFX1150-NEXT:    v_ldexp_f32 v5, v5, v7
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1150-NEXT:    v_rndne_f32_e32 v6, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1150-NEXT:    v_fmac_f32_e32 v5, v6, v4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-NEXT:    v_add_f32_e32 v4, v5, v4
+; GFX1150-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1150-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, v2
+; GFX1150-NEXT:  .LBB3_8: ; %Flow17
+; GFX1150-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v0
+; GFX1150-NEXT:    v_cmp_nle_f32_e64 s0, 0x7f800000, v1
+; GFX1150-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
+; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
+; GFX1150-NEXT:    global_store_b32 v2, v0, s[8:9]
+; GFX1150-NEXT:    s_endpgm
 ;
-; GFX1200-FAKE16-LABEL: unsafe_frem_f16:
-; GFX1200-FAKE16:       ; %bb.0:
-; GFX1200-FAKE16-NEXT:    s_clause 0x1
-; GFX1200-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
-; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1200-FAKE16-NEXT:    s_clause 0x1
-; GFX1200-FAKE16-NEXT:    global_load_u16 v1, v0, s[2:3]
-; GFX1200-FAKE16-NEXT:    global_load_u16 v2, v0, s[4:5] offset:8
-; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-FAKE16-NEXT:    v_rcp_f16_e32 v3, v2
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f16_e32 v3, v1, v3
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x8000, v3
-; GFX1200-FAKE16-NEXT:    v_fmac_f16_e32 v1, v3, v2
-; GFX1200-FAKE16-NEXT:    global_store_b16 v0, v1, s[0:1]
-; GFX1200-FAKE16-NEXT:    s_endpgm
-                             ptr addrspace(1) %in2) #1 {
-   %gep2 = getelementptr half, ptr addrspace(1) %in2, i32 4
-   %r0 = load half, ptr addrspace(1) %in1, align 4
-   %r1 = load half, ptr addrspace(1) %gep2, align 4
-   %r2 = frem afn half %r0, %r1
-   store half %r2, ptr addrspace(1) %out, align 4
+; GFX1200-LABEL: frem_f32:
+; GFX1200:       ; %bb.0:
+; GFX1200-NEXT:    s_clause 0x1
+; GFX1200-NEXT:    s_load_b128 s[8:11], s[4:5], 0x24
+; GFX1200-NEXT:    s_load_b64 s[0:1], s[4:5], 0x34
+; GFX1200-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1200-NEXT:    s_wait_kmcnt 0x0
+; GFX1200-NEXT:    s_clause 0x1
+; GFX1200-NEXT:    global_load_b32 v2, v0, s[10:11]
+; GFX1200-NEXT:    global_load_b32 v0, v0, s[0:1] offset:16
+; GFX1200-NEXT:    s_wait_loadcnt 0x1
+; GFX1200-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v2
+; GFX1200-NEXT:    s_wait_loadcnt 0x0
+; GFX1200-NEXT:    v_and_b32_e32 v3, 0x7fffffff, v0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v1, v3
+; GFX1200-NEXT:    s_cbranch_vccz .LBB3_2
+; GFX1200-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-NEXT:    v_bfi_b32 v4, 0x7fffffff, 0, v2
+; GFX1200-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v1, v3
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v2, v4, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB3_3
+; GFX1200-NEXT:    s_branch .LBB3_8
+; GFX1200-NEXT:  .LBB3_2:
+; GFX1200-NEXT:    ; implicit-def: $vgpr3
+; GFX1200-NEXT:  .LBB3_3: ; %frem.compute
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v3, |v2|
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1200-NEXT:    v_ldexp_f32 v5, v3, 12
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, v0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_readfirstlane_b32 s0, v6
+; GFX1200-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_readfirstlane_b32 s1, v3
+; GFX1200-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-NEXT:    v_rcp_f32_e32 v9, v8
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v7, v3
+; GFX1200-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1200-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1200-NEXT:    s_denorm_mode 15
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; GFX1200-NEXT:    v_fmac_f32_e32 v9, v10, v9
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1200-NEXT:    v_fma_f32 v11, -v8, v10, v6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fmac_f32_e32 v10, v11, v9
+; GFX1200-NEXT:    v_fma_f32 v6, -v8, v10, v6
+; GFX1200-NEXT:    s_denorm_mode 12
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
+; GFX1200-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB3_7
+; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s0, s0, s1
+; GFX1200-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT:    s_add_co_i32 s0, s0, 12
+; GFX1200-NEXT:  .LBB3_5: ; %frem.loop_body
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1200-NEXT:    s_add_co_i32 s0, s0, -12
+; GFX1200-NEXT:    s_cmp_gt_i32 s0, 12
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v5, v8, v6
+; GFX1200-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-NEXT:    v_fma_f32 v5, v5, v4, v8
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v5, v5, 12
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB3_5
+; GFX1200-NEXT:  ; %bb.6: ; %Flow
+; GFX1200-NEXT:    v_mov_b32_e32 v7, s0
+; GFX1200-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1200-NEXT:  .LBB3_7: ; %frem.loop_exit
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_add_nc_u32_e32 v7, -11, v7
+; GFX1200-NEXT:    v_ldexp_f32 v5, v5, v7
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1200-NEXT:    v_rndne_f32_e32 v6, v6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1200-NEXT:    v_fmac_f32_e32 v5, v6, v4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-NEXT:    v_add_f32_e32 v4, v5, v4
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1200-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, v2
+; GFX1200-NEXT:  .LBB3_8: ; %Flow17
+; GFX1200-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v0
+; GFX1200-NEXT:    v_cmp_nle_f32_e64 s0, 0x7f800000, v1
+; GFX1200-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s0, vcc_lo
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v3, vcc_lo
+; GFX1200-NEXT:    global_store_b32 v2, v0, s[8:9]
+; GFX1200-NEXT:    s_endpgm
+                      ptr addrspace(1) %in2) #0 {
+   %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4
+   %r0 = load float, ptr addrspace(1) %in1, align 4
+   %r1 = load float, ptr addrspace(1) %gep2, align 4
+   %r2 = frem float %r0, %r1
+   store float %r2, ptr addrspace(1) %out, align 4
    ret void
 }
 
-define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
-; SI-LABEL: frem_f32:
+define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
+; SI-LABEL: fast_frem_f32:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -951,7 +2919,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; SI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
-; CI-LABEL: frem_f32:
+; CI-LABEL: fast_frem_f32:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -987,7 +2955,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
 ; CI-NEXT:    s_endpgm
 ;
-; VI-LABEL: frem_f32:
+; VI-LABEL: fast_frem_f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1021,7 +2989,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: frem_f32:
+; GFX9-LABEL: fast_frem_f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -1048,7 +3016,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX10-LABEL: frem_f32:
+; GFX10-LABEL: fast_frem_f32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
@@ -1077,7 +3045,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: frem_f32:
+; GFX11-LABEL: fast_frem_f32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1112,7 +3080,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
-; GFX1150-LABEL: frem_f32:
+; GFX1150-LABEL: fast_frem_f32:
 ; GFX1150:       ; %bb.0:
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1148,7 +3116,7 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX1150-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
-; GFX1200-LABEL: frem_f32:
+; GFX1200-LABEL: fast_frem_f32:
 ; GFX1200:       ; %bb.0:
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1187,13 +3155,13 @@ define amdgpu_kernel void @frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1
    %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4
    %r0 = load float, ptr addrspace(1) %in1, align 4
    %r1 = load float, ptr addrspace(1) %gep2, align 4
-   %r2 = frem float %r0, %r1
+   %r2 = frem fast float %r0, %r1
    store float %r2, ptr addrspace(1) %out, align 4
    ret void
 }
 
-define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
-; SI-LABEL: fast_frem_f32:
+define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
+; SI-LABEL: unsafe_frem_f32:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1211,14 +3179,25 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; SI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
 ; SI-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:16
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_rcp_f32_e32 v2, v1
-; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
+; SI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
+; SI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
+; SI-NEXT:    v_rcp_f32_e32 v4, v3
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; SI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
+; SI-NEXT:    v_fma_f32 v4, v5, v4, v4
+; SI-NEXT:    v_mul_f32_e32 v5, v2, v4
+; SI-NEXT:    v_fma_f32 v6, -v3, v5, v2
+; SI-NEXT:    v_fma_f32 v5, v6, v4, v5
+; SI-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; SI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; SI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
 ; SI-NEXT:    v_trunc_f32_e32 v2, v2
 ; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
 ; SI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
-; CI-LABEL: fast_frem_f32:
+; CI-LABEL: unsafe_frem_f32:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1236,14 +3215,25 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; CI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
 ; CI-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:16
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_rcp_f32_e32 v2, v1
-; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
+; CI-NEXT:    v_div_scale_f32 v3, s[0:1], v1, v1, v0
+; CI-NEXT:    v_div_scale_f32 v2, vcc, v0, v1, v0
+; CI-NEXT:    v_rcp_f32_e32 v4, v3
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; CI-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
+; CI-NEXT:    v_fma_f32 v4, v5, v4, v4
+; CI-NEXT:    v_mul_f32_e32 v5, v2, v4
+; CI-NEXT:    v_fma_f32 v6, -v3, v5, v2
+; CI-NEXT:    v_fma_f32 v5, v6, v4, v5
+; CI-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; CI-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; CI-NEXT:    v_div_fixup_f32 v2, v2, v1, v0
 ; CI-NEXT:    v_trunc_f32_e32 v2, v2
 ; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
 ; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
 ; CI-NEXT:    s_endpgm
 ;
-; VI-LABEL: fast_frem_f32:
+; VI-LABEL: unsafe_frem_f32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1259,14 +3249,25 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; VI-NEXT:    v_mov_b32_e32 v2, s0
 ; VI-NEXT:    flat_load_dword v2, v[2:3]
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_rcp_f32_e32 v3, v2
-; VI-NEXT:    v_mul_f32_e32 v3, v4, v3
+; VI-NEXT:    v_div_scale_f32 v5, s[0:1], v2, v2, v4
+; VI-NEXT:    v_div_scale_f32 v3, vcc, v4, v2, v4
+; VI-NEXT:    v_rcp_f32_e32 v6, v5
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; VI-NEXT:    v_fma_f32 v6, v7, v6, v6
+; VI-NEXT:    v_mul_f32_e32 v7, v3, v6
+; VI-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; VI-NEXT:    v_fma_f32 v7, v8, v6, v7
+; VI-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; VI-NEXT:    v_div_fixup_f32 v3, v3, v2, v4
 ; VI-NEXT:    v_trunc_f32_e32 v3, v3
 ; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: fast_frem_f32:
+; GFX9-LABEL: unsafe_frem_f32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -1275,14 +3276,25 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
 ; GFX9-NEXT:    global_load_dword v2, v0, s[6:7] offset:16
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
+; GFX9-NEXT:    v_div_scale_f32 v4, s[2:3], v2, v2, v1
+; GFX9-NEXT:    v_div_scale_f32 v3, vcc, v1, v2, v1
+; GFX9-NEXT:    v_rcp_f32_e32 v5, v4
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX9-NEXT:    v_fma_f32 v5, v6, v5, v5
+; GFX9-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX9-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX9-NEXT:    v_fma_f32 v6, v7, v5, v6
+; GFX9-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
+; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX9-NEXT:    v_fma_f32 v1, -v3, v2, v1
 ; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX10-LABEL: fast_frem_f32:
+; GFX10-LABEL: unsafe_frem_f32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
@@ -1293,14 +3305,25 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX10-NEXT:    global_load_dword v1, v0, s[2:3]
 ; GFX10-NEXT:    global_load_dword v2, v0, s[6:7] offset:16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX10-NEXT:    v_mul_f32_e32 v3, v1, v3
+; GFX10-NEXT:    v_div_scale_f32 v4, s2, v2, v2, v1
+; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, v1, v2, v1
+; GFX10-NEXT:    v_rcp_f32_e32 v5, v4
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v5, v6, v5
+; GFX10-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX10-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v5
+; GFX10-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
+; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
 ; GFX10-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX10-NEXT:    v_fma_f32 v1, -v3, v2, v1
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: fast_frem_f32:
+; GFX11-LABEL: unsafe_frem_f32:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1311,16 +3334,31 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3]
 ; GFX11-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_rcp_f32_e32 v3, v2
+; GFX11-NEXT:    v_div_scale_f32 v4, null, v2, v2, v1
+; GFX11-NEXT:    v_div_scale_f32 v3, vcc_lo, v1, v2, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_rcp_f32_e32 v5, v4
+; GFX11-NEXT:    s_denorm_mode 15
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f32_e32 v3, v1, v3
+; GFX11-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX11-NEXT:    v_fmac_f32_e32 v5, v6, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX11-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fmac_f32_e32 v6, v7, v5
+; GFX11-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
+; GFX11-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX11-NEXT:    v_fma_f32 v1, -v3, v2, v1
 ; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
-; GFX1150-LABEL: fast_frem_f32:
+; GFX1150-LABEL: unsafe_frem_f32:
 ; GFX1150:       ; %bb.0:
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1331,9 +3369,24 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX1150-NEXT:    global_load_b32 v1, v0, s[2:3]
 ; GFX1150-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
 ; GFX1150-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_mul_f32_e32 v3, v1, v3
+; GFX1150-NEXT:    v_div_scale_f32 v4, null, v2, v2, v1
+; GFX1150-NEXT:    v_div_scale_f32 v3, vcc_lo, v1, v2, v1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1150-NEXT:    v_rcp_f32_e32 v5, v4
+; GFX1150-NEXT:    s_denorm_mode 15
+; GFX1150-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fmac_f32_e32 v5, v6, v5
+; GFX1150-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX1150-NEXT:    v_fmac_f32_e32 v6, v7, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX1150-NEXT:    s_denorm_mode 12
+; GFX1150-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
 ; GFX1150-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
@@ -1341,7 +3394,7 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX1150-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
-; GFX1200-LABEL: fast_frem_f32:
+; GFX1200-LABEL: unsafe_frem_f32:
 ; GFX1200:       ; %bb.0:
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1352,51 +3405,180 @@ define amdgpu_kernel void @fast_frem_f32(ptr addrspace(1) %out, ptr addrspace(1)
 ; GFX1200-NEXT:    global_load_b32 v1, v0, s[2:3]
 ; GFX1200-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
 ; GFX1200-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_mul_f32_e32 v3, v1, v3
+; GFX1200-NEXT:    v_div_scale_f32 v4, null, v2, v2, v1
+; GFX1200-NEXT:    v_div_scale_f32 v3, vcc_lo, v1, v2, v1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1200-NEXT:    v_rcp_f32_e32 v5, v4
+; GFX1200-NEXT:    s_denorm_mode 15
+; GFX1200-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fmac_f32_e32 v5, v6, v5
+; GFX1200-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX1200-NEXT:    v_fmac_f32_e32 v6, v7, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX1200-NEXT:    s_denorm_mode 12
+; GFX1200-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_div_fixup_f32 v3, v3, v2, v1
 ; GFX1200-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
 ; GFX1200-NEXT:    v_fmac_f32_e32 v1, v3, v2
 ; GFX1200-NEXT:    global_store_b32 v0, v1, s[0:1]
 ; GFX1200-NEXT:    s_endpgm
-                      ptr addrspace(1) %in2) #0 {
+                             ptr addrspace(1) %in2) #1 {
    %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4
    %r0 = load float, ptr addrspace(1) %in1, align 4
    %r1 = load float, ptr addrspace(1) %gep2, align 4
-   %r2 = frem fast float %r0, %r1
+   %r2 = frem afn float %r0, %r1
    store float %r2, ptr addrspace(1) %out, align 4
    ret void
 }
 
-define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
-; SI-LABEL: unsafe_frem_f32:
+define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
+; SI-LABEL: frem_f64:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT:    s_mov_b32 s11, 0xf000
-; SI-NEXT:    s_mov_b32 s10, -1
+; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s8, s0
-; SI-NEXT:    s_mov_b32 s9, s1
-; SI-NEXT:    s_mov_b32 s0, s2
-; SI-NEXT:    s_mov_b32 s1, s3
-; SI-NEXT:    s_mov_b32 s2, s10
-; SI-NEXT:    s_mov_b32 s3, s11
-; SI-NEXT:    s_mov_b32 s6, s10
-; SI-NEXT:    s_mov_b32 s7, s11
-; SI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
-; SI-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:16
+; SI-NEXT:    s_mov_b32 s4, s10
+; SI-NEXT:    s_mov_b32 s5, s11
+; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    s_mov_b32 s3, s7
+; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[0:3], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_rcp_f32_e32 v2, v1
-; SI-NEXT:    v_mul_f32_e32 v2, v0, v2
-; SI-NEXT:    v_trunc_f32_e32 v2, v2
-; SI-NEXT:    v_fma_f32 v0, -v2, v1, v0
-; SI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
+; SI-NEXT:    v_cmp_ngt_f64_e64 s[0:1], |v[0:1]|, |v[2:3]|
+; SI-NEXT:    s_and_b64 vcc, exec, s[0:1]
+; SI-NEXT:    s_cbranch_vccz .LBB6_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; SI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
+; SI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB6_3
+; SI-NEXT:    s_branch .LBB6_8
+; SI-NEXT:  .LBB6_2:
+; SI-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB6_3: ; %frem.compute
+; SI-NEXT:    s_brev_b32 s5, -2
+; SI-NEXT:    v_and_b32_e32 v6, 0x7fffffff, v1
+; SI-NEXT:    s_mov_b32 s0, 0
+; SI-NEXT:    s_mov_b32 s1, 0x7ff00000
+; SI-NEXT:    v_cmp_lt_f64_e64 vcc, |v[0:1]|, s[0:1]
+; SI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
+; SI-NEXT:    v_frexp_exp_i32_f64_e32 v6, v[0:1]
+; SI-NEXT:    s_and_b64 s[2:3], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v6
+; SI-NEXT:    s_cselect_b32 s3, s2, 0
+; SI-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; SI-NEXT:    v_and_b32_e32 v8, 0x7fffffff, v3
+; SI-NEXT:    v_cmp_lt_f64_e64 vcc, |v[2:3]|, s[0:1]
+; SI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; SI-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc
+; SI-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[2:3]
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v8
+; SI-NEXT:    s_cselect_b32 s7, s0, 0
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_add_i32 s4, s7, -1
+; SI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; SI-NEXT:    s_not_b32 s0, s4
+; SI-NEXT:    s_add_i32 s6, s0, s3
+; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[4:5], v[4:5], 1.0
+; SI-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
+; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
+; SI-NEXT:    v_div_scale_f64 v[12:13], s[0:1], 1.0, v[4:5], 1.0
+; SI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
+; SI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], v[12:13]
+; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v9
+; SI-NEXT:    s_mov_b32 s0, 0x3ff00000
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s0, v13
+; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
+; SI-NEXT:    s_nop 0
+; SI-NEXT:    v_div_fmas_f64 v[8:9], v[16:17], v[10:11], v[14:15]
+; SI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; SI-NEXT:    s_cmp_lt_i32 s6, 27
+; SI-NEXT:    s_cbranch_scc1 .LBB6_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s0, s3, s7
+; SI-NEXT:    s_add_i32 s6, s0, 26
+; SI-NEXT:    s_mov_b32 s3, 0x432fffff
+; SI-NEXT:    v_mov_b32_e32 v14, 0x43300000
+; SI-NEXT:    v_mov_b32_e32 v10, 0
+; SI-NEXT:  .LBB6_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v13, v7
+; SI-NEXT:    v_mov_b32_e32 v12, v6
+; SI-NEXT:    v_mul_f64 v[6:7], v[12:13], v[8:9]
+; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[6:7]|, s[2:3]
+; SI-NEXT:    v_bfi_b32 v11, s5, v14, v7
+; SI-NEXT:    v_add_f64 v[15:16], v[6:7], v[10:11]
+; SI-NEXT:    v_add_f64 v[15:16], v[15:16], -v[10:11]
+; SI-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v6, v15, v6, vcc
+; SI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[12:13]
+; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; SI-NEXT:    v_add_f64 v[15:16], v[6:7], v[4:5]
+; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v16, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v15, vcc
+; SI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; SI-NEXT:    s_sub_i32 s6, s6, 26
+; SI-NEXT:    s_cmp_gt_i32 s6, 26
+; SI-NEXT:    s_cbranch_scc1 .LBB6_5
+; SI-NEXT:  ; %bb.6: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v6, v12
+; SI-NEXT:    v_mov_b32_e32 v7, v13
+; SI-NEXT:  .LBB6_7: ; %frem.loop_exit
+; SI-NEXT:    s_sub_i32 s0, s6, 25
+; SI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], s0
+; SI-NEXT:    v_mul_f64 v[8:9], v[6:7], v[8:9]
+; SI-NEXT:    s_mov_b32 s0, -1
+; SI-NEXT:    s_mov_b32 s1, 0x432fffff
+; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[8:9]|, s[0:1]
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_mov_b32_e32 v10, 0x43300000
+; SI-NEXT:    v_bfi_b32 v11, s0, v10, v9
+; SI-NEXT:    v_mov_b32_e32 v10, 0
+; SI-NEXT:    v_add_f64 v[12:13], v[8:9], v[10:11]
+; SI-NEXT:    v_add_f64 v[10:11], v[12:13], -v[10:11]
+; SI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; SI-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; SI-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
+; SI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; SI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], s4
+; SI-NEXT:    v_bfi_b32 v5, s0, v5, v1
+; SI-NEXT:  .LBB6_8: ; %Flow17
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
+; SI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
+; SI-NEXT:    s_mov_b32 s0, 0
+; SI-NEXT:    s_mov_b32 s1, 0x7ff00000
+; SI-NEXT:    v_cmp_nge_f64_e64 s[0:1], |v[0:1]|, s[0:1]
+; SI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
+; SI-NEXT:    v_cndmask_b32_e32 v1, v0, v5, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
-; CI-LABEL: unsafe_frem_f32:
+; CI-LABEL: frem_f64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1404,152 +3586,707 @@ define amdgpu_kernel void @unsafe_frem_f32(ptr addrspace(1) %out, ptr addrspace(
 ; CI-NEXT:    s_mov_b32 s10, -1
 ; CI-NEXT:    s_mov_b32 s6, s10
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_mov_b32 s8, s0
-; CI-NEXT:    s_mov_b32 s9, s1
-; CI-NEXT:    s_mov_b32 s0, s2
-; CI-NEXT:    s_mov_b32 s1, s3
-; CI-NEXT:    s_mov_b32 s2, s10
-; CI-NEXT:    s_mov_b32 s3, s11
+; CI-NEXT:    s_mov_b32 s8, s2
+; CI-NEXT:    s_mov_b32 s9, s3
 ; CI-NEXT:    s_mov_b32 s7, s11
-; CI-NEXT:    buffer_load_dword v0, off, s[0:3], 0
-; CI-NEXT:    buffer_load_dword v1, off, s[4:7], 0 offset:16
+; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[4:7], 0
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_rcp_f32_e32 v2, v1
-; CI-NEXT:    v_mul_f32_e32 v2, v0, v2
-; CI-NEXT:    v_trunc_f32_e32 v2, v2
-; CI-NEXT:    v_fma_f32 v0, -v2, v1, v0
-; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
+; CI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB6_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; CI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; CI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
+; CI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
+; CI-NEXT:    s_cbranch_execz .LBB6_3
+; CI-NEXT:    s_branch .LBB6_8
+; CI-NEXT:  .LBB6_2:
+; CI-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; CI-NEXT:  .LBB6_3: ; %frem.compute
+; CI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; CI-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
+; CI-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; CI-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; CI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; CI-NEXT:    v_add_i32_e32 v12, vcc, -1, v11
+; CI-NEXT:    v_not_b32_e32 v8, v12
+; CI-NEXT:    v_add_i32_e32 v13, vcc, v8, v10
+; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; CI-NEXT:    v_div_scale_f64 v[8:9], s[2:3], v[4:5], v[4:5], 1.0
+; CI-NEXT:    v_rcp_f64_e32 v[14:15], v[8:9]
+; CI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], 1.0
+; CI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; CI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], 1.0
+; CI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; CI-NEXT:    v_div_scale_f64 v[16:17], vcc, 1.0, v[4:5], 1.0
+; CI-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
+; CI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; CI-NEXT:    s_nop 1
+; CI-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[18:19]
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v13
+; CI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB6_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v10, vcc, v10, v11
+; CI-NEXT:    v_add_i32_e32 v13, vcc, 26, v10
+; CI-NEXT:  .LBB6_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v11, v7
+; CI-NEXT:    v_mov_b32_e32 v10, v6
+; CI-NEXT:    v_mul_f64 v[6:7], v[10:11], v[8:9]
+; CI-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
+; CI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; CI-NEXT:    v_add_f64 v[14:15], v[6:7], v[4:5]
+; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc
+; CI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; CI-NEXT:    v_subrev_i32_e32 v13, vcc, 26, v13
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v13
+; CI-NEXT:    s_cbranch_vccnz .LBB6_5
+; CI-NEXT:  ; %bb.6: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v6, v10
+; CI-NEXT:    v_mov_b32_e32 v7, v11
+; CI-NEXT:  .LBB6_7: ; %frem.loop_exit
+; CI-NEXT:    v_subrev_i32_e32 v10, vcc, 25, v13
+; CI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v10
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_mul_f64 v[8:9], v[6:7], v[8:9]
+; CI-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
+; CI-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; CI-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
+; CI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; CI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
+; CI-NEXT:    v_bfi_b32 v5, s2, v5, v1
+; CI-NEXT:  .LBB6_8: ; %Flow17
+; CI-NEXT:    s_mov_b32 s4, 0
+; CI-NEXT:    s_mov_b32 s5, 0x7ff00000
+; CI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
+; CI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[0:1]|, s[4:5]
+; CI-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; CI-NEXT:    v_cndmask_b32_e32 v1, v0, v5, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; CI-NEXT:    s_endpgm
 ;
-; VI-LABEL: unsafe_frem_f32:
+; VI-LABEL: frem_f64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_add_u32 s0, s4, 16
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    s_addc_u32 s1, s5, 0
-; VI-NEXT:    flat_load_dword v4, v[2:3]
-; VI-NEXT:    v_mov_b32_e32 v3, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s0
-; VI-NEXT:    flat_load_dword v2, v[2:3]
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    v_mov_b32_e32 v2, s4
+; VI-NEXT:    v_mov_b32_e32 v3, s5
+; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
+; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_rcp_f32_e32 v3, v2
-; VI-NEXT:    v_mul_f32_e32 v3, v4, v3
-; VI-NEXT:    v_trunc_f32_e32 v3, v3
-; VI-NEXT:    v_fma_f32 v2, -v3, v2, v4
-; VI-NEXT:    flat_store_dword v[0:1], v2
+; VI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB6_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; VI-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; VI-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
+; VI-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
+; VI-NEXT:    s_cbranch_execz .LBB6_3
+; VI-NEXT:    s_branch .LBB6_8
+; VI-NEXT:  .LBB6_2:
+; VI-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; VI-NEXT:  .LBB6_3: ; %frem.compute
+; VI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; VI-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
+; VI-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; VI-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; VI-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; VI-NEXT:    v_add_u32_e32 v12, vcc, -1, v11
+; VI-NEXT:    v_not_b32_e32 v8, v12
+; VI-NEXT:    v_add_u32_e32 v13, vcc, v8, v10
+; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; VI-NEXT:    v_div_scale_f64 v[8:9], s[2:3], v[4:5], v[4:5], 1.0
+; VI-NEXT:    v_rcp_f64_e32 v[14:15], v[8:9]
+; VI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], 1.0
+; VI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; VI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], 1.0
+; VI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; VI-NEXT:    v_div_scale_f64 v[16:17], vcc, 1.0, v[4:5], 1.0
+; VI-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
+; VI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; VI-NEXT:    s_nop 1
+; VI-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[18:19]
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v13
+; VI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB6_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v10, vcc, v10, v11
+; VI-NEXT:    v_add_u32_e32 v13, vcc, 26, v10
+; VI-NEXT:  .LBB6_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v11, v7
+; VI-NEXT:    v_mov_b32_e32 v10, v6
+; VI-NEXT:    v_mul_f64 v[6:7], v[10:11], v[8:9]
+; VI-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
+; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; VI-NEXT:    v_add_f64 v[14:15], v[6:7], v[4:5]
+; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc
+; VI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; VI-NEXT:    v_subrev_u32_e32 v13, vcc, 26, v13
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v13
+; VI-NEXT:    s_cbranch_vccnz .LBB6_5
+; VI-NEXT:  ; %bb.6: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v6, v10
+; VI-NEXT:    v_mov_b32_e32 v7, v11
+; VI-NEXT:  .LBB6_7: ; %frem.loop_exit
+; VI-NEXT:    v_subrev_u32_e32 v10, vcc, 25, v13
+; VI-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v10
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_mul_f64 v[8:9], v[6:7], v[8:9]
+; VI-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
+; VI-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; VI-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
+; VI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; VI-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
+; VI-NEXT:    v_bfi_b32 v5, s2, v5, v1
+; VI-NEXT:  .LBB6_8: ; %Flow17
+; VI-NEXT:    v_mov_b32_e32 v6, s0
+; VI-NEXT:    v_mov_b32_e32 v7, s1
+; VI-NEXT:    s_mov_b32 s0, 0
+; VI-NEXT:    s_mov_b32 s1, 0x7ff00000
+; VI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
+; VI-NEXT:    v_cmp_nge_f64_e64 s[0:1], |v[0:1]|, s[0:1]
+; VI-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v1, v0, v5, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; VI-NEXT:    flat_store_dwordx2 v[6:7], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: unsafe_frem_f32:
+; GFX9-LABEL: frem_f64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
-; GFX9-NEXT:    global_load_dword v2, v0, s[6:7] offset:16
+; GFX9-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
+; GFX9-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
-; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX9-NEXT:    v_fma_f32 v1, -v3, v2, v1
-; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[2:3]|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB6_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[2:3]|
+; GFX9-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB6_3
+; GFX9-NEXT:    s_branch .LBB6_8
+; GFX9-NEXT:  .LBB6_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; GFX9-NEXT:  .LBB6_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v11, v[2:3]
+; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX9-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX9-NEXT:    v_add_u32_e32 v12, -1, v11
+; GFX9-NEXT:    v_not_b32_e32 v8, v12
+; GFX9-NEXT:    v_add_u32_e32 v13, v8, v10
+; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; GFX9-NEXT:    v_div_scale_f64 v[8:9], s[2:3], v[4:5], v[4:5], 1.0
+; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[8:9]
+; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, 1.0, v[4:5], 1.0
+; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX9-NEXT:    s_nop 1
+; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[18:19]
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v13
+; GFX9-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB6_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v10, v10, v11
+; GFX9-NEXT:    v_add_u32_e32 v13, 26, v10
+; GFX9-NEXT:  .LBB6_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v11, v7
+; GFX9-NEXT:    v_mov_b32_e32 v10, v6
+; GFX9-NEXT:    v_mul_f64 v[6:7], v[10:11], v[8:9]
+; GFX9-NEXT:    v_subrev_u32_e32 v13, 26, v13
+; GFX9-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX9-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; GFX9-NEXT:    v_add_f64 v[14:15], v[6:7], v[4:5]
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc
+; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v13
+; GFX9-NEXT:    s_cbranch_vccnz .LBB6_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v6, v10
+; GFX9-NEXT:    v_mov_b32_e32 v7, v11
+; GFX9-NEXT:  .LBB6_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_subrev_u32_e32 v10, 25, v13
+; GFX9-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v10
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_mul_f64 v[8:9], v[6:7], v[8:9]
+; GFX9-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX9-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[6:7]
+; GFX9-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX9-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
+; GFX9-NEXT:    v_bfi_b32 v5, s2, v5, v1
+; GFX9-NEXT:  .LBB6_8: ; %Flow17
+; GFX9-NEXT:    s_mov_b32 s2, 0
+; GFX9-NEXT:    s_mov_b32 s3, 0x7ff00000
+; GFX9-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[2:3]
+; GFX9-NEXT:    v_cmp_nge_f64_e64 s[2:3], |v[0:1]|, s[2:3]
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0x7ff80000
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v0, v5, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
+; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX10-LABEL: unsafe_frem_f32:
+; GFX10-LABEL: frem_f64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    global_load_dword v1, v0, s[2:3]
-; GFX10-NEXT:    global_load_dword v2, v0, s[6:7] offset:16
+; GFX10-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
+; GFX10-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX10-NEXT:    v_mul_f32_e32 v3, v1, v3
-; GFX10-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX10-NEXT:    v_fma_f32 v1, -v3, v2, v1
-; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB6_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX10-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; GFX10-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB6_3
+; GFX10-NEXT:    s_branch .LBB6_8
+; GFX10-NEXT:  .LBB6_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; GFX10-NEXT:  .LBB6_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX10-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX10-NEXT:    v_add_nc_u32_e32 v12, -1, v9
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v9
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX10-NEXT:    v_not_b32_e32 v9, v12
+; GFX10-NEXT:    v_add_nc_u32_e32 v13, v9, v8
+; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; GFX10-NEXT:    v_div_scale_f64 v[8:9], s4, v[4:5], v[4:5], 1.0
+; GFX10-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX10-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX10-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX10-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX10-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX10-NEXT:    v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
+; GFX10-NEXT:    v_mul_f64 v[16:17], v[14:15], v[10:11]
+; GFX10-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX10-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
+; GFX10-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB6_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 26
+; GFX10-NEXT:  .LBB6_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v11, v7
+; GFX10-NEXT:    v_mov_b32_e32 v10, v6
+; GFX10-NEXT:    s_sub_i32 s2, s2, 26
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX10-NEXT:    v_mul_f64 v[6:7], v[10:11], v[8:9]
+; GFX10-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX10-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX10-NEXT:    v_add_f64 v[13:14], v[6:7], v[4:5]
+; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v14, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v13, vcc_lo
+; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX10-NEXT:    s_cbranch_scc1 .LBB6_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v6, v10
+; GFX10-NEXT:    v_mov_b32_e32 v13, s2
+; GFX10-NEXT:    v_mov_b32_e32 v7, v11
+; GFX10-NEXT:  .LBB6_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
+; GFX10-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v10
+; GFX10-NEXT:    v_mul_f64 v[8:9], v[6:7], v[8:9]
+; GFX10-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX10-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX10-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
+; GFX10-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc_lo
+; GFX10-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
+; GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX10-NEXT:  .LBB6_8: ; %Flow17
+; GFX10-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
+; GFX10-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX10-NEXT:    v_mov_b32_e32 v6, 0
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v5, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX10-NEXT:    global_store_dwordx2 v6, v[0:1], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: unsafe_frem_f32:
+; GFX11-LABEL: frem_f64:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX11-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
+; GFX11-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX11-NEXT:    global_load_b64 v[2:3], v2, s[4:5]
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_rcp_f32_e32 v3, v2
+; GFX11-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB6_2
+; GFX11-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX11-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB6_3
+; GFX11-NEXT:    s_branch .LBB6_8
+; GFX11-NEXT:  .LBB6_2:
+; GFX11-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; GFX11-NEXT:  .LBB6_3: ; %frem.compute
+; GFX11-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX11-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX11-NEXT:    v_add_nc_u32_e32 v12, -1, v9
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v9
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v9, v12
+; GFX11-NEXT:    v_add_nc_u32_e32 v13, v9, v8
+; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
+; GFX11-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_mul_f32_e32 v3, v1, v3
+; GFX11-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX11-NEXT:    v_fma_f32 v1, -v3, v2, v1
-; GFX11-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX11-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX11-NEXT:    v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
+; GFX11-NEXT:    v_mul_f64 v[16:17], v[14:15], v[10:11]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX11-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB6_7
+; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 26
+; GFX11-NEXT:    .p2align 6
+; GFX11-NEXT:  .LBB6_5: ; %frem.loop_body
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
+; GFX11-NEXT:    s_sub_i32 s2, s2, 26
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f64 v[6:7], v[10:11], v[8:9]
+; GFX11-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX11-NEXT:    v_add_f64 v[13:14], v[6:7], v[4:5]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
+; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX11-NEXT:    s_cbranch_scc1 .LBB6_5
+; GFX11-NEXT:  ; %bb.6: ; %Flow
+; GFX11-NEXT:    v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
+; GFX11-NEXT:    v_mov_b32_e32 v7, v11
+; GFX11-NEXT:  .LBB6_7: ; %frem.loop_exit
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
+; GFX11-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v10
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f64 v[8:9], v[6:7], v[8:9]
+; GFX11-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX11-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
+; GFX11-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX11-NEXT:  .LBB6_8: ; %Flow17
+; GFX11-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
+; GFX11-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX11-NEXT:    global_store_b64 v6, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
-; GFX1150-LABEL: unsafe_frem_f32:
+; GFX1150-LABEL: frem_f64:
 ; GFX1150:       ; %bb.0:
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1150-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1150-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1150-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1150-NEXT:    s_clause 0x1
-; GFX1150-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX1150-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
+; GFX1150-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX1150-NEXT:    global_load_b64 v[2:3], v2, s[4:5]
 ; GFX1150-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-NEXT:    v_rcp_f32_e32 v3, v2
+; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX1150-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT:    s_cbranch_vccz .LBB6_2
+; GFX1150-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1150-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1150-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB6_3
+; GFX1150-NEXT:    s_branch .LBB6_8
+; GFX1150-NEXT:  .LBB6_2:
+; GFX1150-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; GFX1150-NEXT:  .LBB6_3: ; %frem.compute
+; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX1150-NEXT:    v_add_nc_u32_e32 v12, -1, v9
+; GFX1150-NEXT:    v_readfirstlane_b32 s3, v9
+; GFX1150-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v9, v12
+; GFX1150-NEXT:    v_add_nc_u32_e32 v13, v9, v8
+; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
+; GFX1150-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
 ; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_mul_f32_e32 v3, v1, v3
-; GFX1150-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX1150-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1150-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1150-NEXT:    v_fmac_f32_e32 v1, v3, v2
-; GFX1150-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1150-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1150-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX1150-NEXT:    v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f64 v[16:17], v[14:15], v[10:11]
+; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
+; GFX1150-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB6_7
+; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-NEXT:    s_sub_i32 s2, s2, s3
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s2, s2, 26
+; GFX1150-NEXT:    .p2align 6
+; GFX1150-NEXT:  .LBB6_5: ; %frem.loop_body
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
+; GFX1150-NEXT:    s_sub_i32 s2, s2, 26
+; GFX1150-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f64 v[6:7], v[10:11], v[8:9]
+; GFX1150-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1150-NEXT:    v_add_f64 v[13:14], v[6:7], v[4:5]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
+; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB6_5
+; GFX1150-NEXT:  ; %bb.6: ; %Flow
+; GFX1150-NEXT:    v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
+; GFX1150-NEXT:    v_mov_b32_e32 v7, v11
+; GFX1150-NEXT:  .LBB6_7: ; %frem.loop_exit
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
+; GFX1150-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v10
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f64 v[8:9], v[6:7], v[8:9]
+; GFX1150-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1150-NEXT:    v_add_f64 v[4:5], v[6:7], v[4:5]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
+; GFX1150-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX1150-NEXT:  .LBB6_8: ; %Flow17
+; GFX1150-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
+; GFX1150-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX1150-NEXT:    v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
+; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX1150-NEXT:    global_store_b64 v6, v[0:1], s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
-; GFX1200-LABEL: unsafe_frem_f32:
+; GFX1200-LABEL: frem_f64:
 ; GFX1200:       ; %bb.0:
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1200-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-NEXT:    v_mov_b32_e32 v0, 0
+; GFX1200-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1200-NEXT:    s_wait_kmcnt 0x0
 ; GFX1200-NEXT:    s_clause 0x1
-; GFX1200-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX1200-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
+; GFX1200-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX1200-NEXT:    global_load_b64 v[2:3], v2, s[4:5]
 ; GFX1200-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-NEXT:    v_rcp_f32_e32 v3, v2
+; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[2:3]|
+; GFX1200-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT:    s_cbranch_vccz .LBB6_2
+; GFX1200-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[2:3]|
+; GFX1200-NEXT:    v_and_b32_e32 v4, 0x80000000, v1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v1, v4, vcc_lo
+; GFX1200-NEXT:    v_cndmask_b32_e64 v4, v0, 0, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB6_3
+; GFX1200-NEXT:    s_branch .LBB6_8
+; GFX1200-NEXT:  .LBB6_2:
+; GFX1200-NEXT:    ; implicit-def: $vgpr4_vgpr5
+; GFX1200-NEXT:  .LBB6_3: ; %frem.compute
+; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
+; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v9, v[2:3]
+; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v8, v[0:1]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[4:5], 26
+; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
+; GFX1200-NEXT:    v_add_nc_u32_e32 v12, -1, v9
+; GFX1200-NEXT:    v_readfirstlane_b32 s3, v9
+; GFX1200-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v9, v12
+; GFX1200-NEXT:    v_add_nc_u32_e32 v13, v9, v8
+; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], 1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], 1.0
+; GFX1200-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
 ; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_mul_f32_e32 v3, v1, v3
-; GFX1200-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX1200-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1200-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-NEXT:    v_fmac_f32_e32 v1, v3, v2
-; GFX1200-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1200-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX1200-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX1200-NEXT:    v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[4:5], 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f64_e32 v[16:17], v[14:15], v[10:11]
+; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[14:15]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[16:17]
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v13
+; GFX1200-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[4:5], 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB6_7
+; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s2, s2, s3
+; GFX1200-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT:    s_add_co_i32 s2, s2, 26
+; GFX1200-NEXT:  .LBB6_5: ; %frem.loop_body
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT:    v_dual_mov_b32 v11, v7 :: v_dual_mov_b32 v10, v6
+; GFX1200-NEXT:    s_sub_co_i32 s2, s2, 26
+; GFX1200-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f64_e32 v[6:7], v[10:11], v[8:9]
+; GFX1200-NEXT:    v_rndne_f64_e32 v[6:7], v[6:7]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[4:5], v[10:11]
+; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT:    v_add_f64_e32 v[13:14], v[6:7], v[4:5]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_dual_cndmask_b32 v7, v7, v14 :: v_dual_cndmask_b32 v6, v6, v13
+; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[6:7], 26
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB6_5
+; GFX1200-NEXT:  ; %bb.6: ; %Flow
+; GFX1200-NEXT:    v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v6, v10
+; GFX1200-NEXT:    v_mov_b32_e32 v7, v11
+; GFX1200-NEXT:  .LBB6_7: ; %frem.loop_exit
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_subrev_nc_u32_e32 v10, 25, v13
+; GFX1200-NEXT:    v_ldexp_f64 v[6:7], v[6:7], v10
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f64_e32 v[8:9], v[6:7], v[8:9]
+; GFX1200-NEXT:    v_rndne_f64_e32 v[8:9], v[8:9]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[8:9], v[4:5], v[6:7]
+; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT:    v_add_f64_e32 v[4:5], v[6:7], v[4:5]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_dual_cndmask_b32 v5, v7, v5 :: v_dual_cndmask_b32 v4, v6, v4
+; GFX1200-NEXT:    v_ldexp_f64 v[4:5], v[4:5], v12
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX1200-NEXT:  .LBB6_8: ; %Flow17
+; GFX1200-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[2:3]
+; GFX1200-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_dual_mov_b32 v6, 0 :: v_dual_cndmask_b32 v1, 0x7ff80000, v5
+; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc_lo
+; GFX1200-NEXT:    global_store_b64 v6, v[0:1], s[0:1]
 ; GFX1200-NEXT:    s_endpgm
-                             ptr addrspace(1) %in2) #1 {
-   %gep2 = getelementptr float, ptr addrspace(1) %in2, i32 4
-   %r0 = load float, ptr addrspace(1) %in1, align 4
-   %r1 = load float, ptr addrspace(1) %gep2, align 4
-   %r2 = frem afn float %r0, %r1
-   store float %r2, ptr addrspace(1) %out, align 4
+                      ptr addrspace(1) %in2) #0 {
+   %r0 = load double, ptr addrspace(1) %in1, align 8
+   %r1 = load double, ptr addrspace(1) %in2, align 8
+   %r2 = frem double %r0, %r1
+   store double %r2, ptr addrspace(1) %out, align 8
    ret void
 }
 
-define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
-; SI-LABEL: frem_f64:
+define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
+; SI-LABEL: fast_frem_f64:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd
@@ -1601,7 +4338,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
-; CI-LABEL: frem_f64:
+; CI-LABEL: fast_frem_f64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
@@ -1636,7 +4373,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; CI-NEXT:    s_endpgm
 ;
-; VI-LABEL: frem_f64:
+; VI-LABEL: fast_frem_f64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
@@ -1667,7 +4404,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; VI-NEXT:    s_endpgm
 ;
-; GFX9-LABEL: frem_f64:
+; GFX9-LABEL: fast_frem_f64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
@@ -1693,7 +4430,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX9-NEXT:    global_store_dwordx2 v12, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
-; GFX10-LABEL: frem_f64:
+; GFX10-LABEL: fast_frem_f64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
@@ -1720,7 +4457,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX10-NEXT:    global_store_dwordx2 v12, v[0:1], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-LABEL: frem_f64:
+; GFX11-LABEL: fast_frem_f64:
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1753,7 +4490,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX11-NEXT:    global_store_b64 v12, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
-; GFX1150-LABEL: frem_f64:
+; GFX1150-LABEL: fast_frem_f64:
 ; GFX1150:       ; %bb.0:
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1786,7 +4523,7 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
 ; GFX1150-NEXT:    global_store_b64 v12, v[0:1], s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
-; GFX1200-LABEL: frem_f64:
+; GFX1200-LABEL: fast_frem_f64:
 ; GFX1200:       ; %bb.0:
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
@@ -1821,250 +4558,6 @@ define amdgpu_kernel void @frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1
                       ptr addrspace(1) %in2) #0 {
    %r0 = load double, ptr addrspace(1) %in1, align 8
    %r1 = load double, ptr addrspace(1) %in2, align 8
-   %r2 = frem double %r0, %r1
-   store double %r2, ptr addrspace(1) %out, align 8
-   ret void
-}
-
-define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
-; SI-LABEL: fast_frem_f64:
-; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
-; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
-; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s0, s8
-; SI-NEXT:    s_mov_b32 s1, s9
-; SI-NEXT:    s_mov_b32 s8, s10
-; SI-NEXT:    s_mov_b32 s9, s11
-; SI-NEXT:    s_mov_b32 s10, s2
-; SI-NEXT:    s_mov_b32 s11, s3
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_mov_b32 s7, s3
-; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[4:7], 0
-; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; SI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; SI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; SI-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; SI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; SI-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; SI-NEXT:    v_readfirstlane_b32 s4, v4
-; SI-NEXT:    v_readfirstlane_b32 s5, v5
-; SI-NEXT:    s_bfe_u32 s6, s5, 0xb0014
-; SI-NEXT:    s_add_i32 s8, s6, 0xfffffc01
-; SI-NEXT:    s_mov_b32 s7, 0xfffff
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s8
-; SI-NEXT:    s_andn2_b64 s[6:7], s[4:5], s[6:7]
-; SI-NEXT:    s_and_b32 s9, s5, 0x80000000
-; SI-NEXT:    s_cmp_lt_i32 s8, 0
-; SI-NEXT:    s_cselect_b32 s6, 0, s6
-; SI-NEXT:    s_cselect_b32 s7, s9, s7
-; SI-NEXT:    s_cmp_gt_i32 s8, 51
-; SI-NEXT:    s_cselect_b32 s5, s5, s7
-; SI-NEXT:    s_cselect_b32 s4, s4, s6
-; SI-NEXT:    v_fma_f64 v[0:1], -s[4:5], v[2:3], v[0:1]
-; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-NEXT:    s_endpgm
-;
-; CI-LABEL: fast_frem_f64:
-; CI:       ; %bb.0:
-; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
-; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT:    s_mov_b32 s11, 0xf000
-; CI-NEXT:    s_mov_b32 s10, -1
-; CI-NEXT:    s_mov_b32 s6, s10
-; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_mov_b32 s8, s0
-; CI-NEXT:    s_mov_b32 s9, s1
-; CI-NEXT:    s_mov_b32 s0, s2
-; CI-NEXT:    s_mov_b32 s1, s3
-; CI-NEXT:    s_mov_b32 s2, s10
-; CI-NEXT:    s_mov_b32 s3, s11
-; CI-NEXT:    s_mov_b32 s7, s11
-; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
-; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[4:7], 0
-; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; CI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; CI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; CI-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; CI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; CI-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
-; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
-; CI-NEXT:    s_endpgm
-;
-; VI-LABEL: fast_frem_f64:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    v_mov_b32_e32 v4, s4
-; VI-NEXT:    v_mov_b32_e32 v5, s5
-; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
-; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; VI-NEXT:    v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
-; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; VI-NEXT:    v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
-; VI-NEXT:    v_mul_f64 v[8:9], v[2:3], v[6:7]
-; VI-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[8:9], v[2:3]
-; VI-NEXT:    v_fma_f64 v[6:7], v[10:11], v[6:7], v[8:9]
-; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
-;
-; GFX9-LABEL: fast_frem_f64:
-; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT:    v_mov_b32_e32 v10, 0
-; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_dwordx2 v[0:1], v10, s[2:3]
-; GFX9-NEXT:    global_load_dwordx2 v[2:3], v10, s[6:7]
-; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX9-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX9-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX9-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; GFX9-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
-; GFX9-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX9-NEXT:    global_store_dwordx2 v10, v[0:1], s[0:1]
-; GFX9-NEXT:    s_endpgm
-;
-; GFX10-LABEL: fast_frem_f64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v10, 0
-; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    global_load_dwordx2 v[0:1], v10, s[2:3]
-; GFX10-NEXT:    global_load_dwordx2 v[2:3], v10, s[6:7]
-; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX10-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX10-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX10-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX10-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX10-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; GFX10-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX10-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; GFX10-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
-; GFX10-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX10-NEXT:    global_store_dwordx2 v10, v[0:1], s[0:1]
-; GFX10-NEXT:    s_endpgm
-;
-; GFX11-LABEL: fast_frem_f64:
-; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v10, 0
-; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b64 v[0:1], v10, s[2:3]
-; GFX11-NEXT:    global_load_b64 v[2:3], v10, s[4:5]
-; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX11-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX11-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX11-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
-; GFX11-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX11-NEXT:    global_store_b64 v10, v[0:1], s[0:1]
-; GFX11-NEXT:    s_endpgm
-;
-; GFX1150-LABEL: fast_frem_f64:
-; GFX1150:       ; %bb.0:
-; GFX1150-NEXT:    s_clause 0x1
-; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-NEXT:    v_mov_b32_e32 v10, 0
-; GFX1150-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1150-NEXT:    s_clause 0x1
-; GFX1150-NEXT:    global_load_b64 v[0:1], v10, s[2:3]
-; GFX1150-NEXT:    global_load_b64 v[2:3], v10, s[4:5]
-; GFX1150-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1150-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1150-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; GFX1150-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX1150-NEXT:    global_store_b64 v10, v[0:1], s[0:1]
-; GFX1150-NEXT:    s_endpgm
-;
-; GFX1200-LABEL: fast_frem_f64:
-; GFX1200:       ; %bb.0:
-; GFX1200-NEXT:    s_clause 0x1
-; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-NEXT:    v_mov_b32_e32 v10, 0
-; GFX1200-NEXT:    s_wait_kmcnt 0x0
-; GFX1200-NEXT:    s_clause 0x1
-; GFX1200-NEXT:    global_load_b64 v[0:1], v10, s[2:3]
-; GFX1200-NEXT:    global_load_b64 v[2:3], v10, s[4:5]
-; GFX1200-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1200-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1200-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_mul_f64_e32 v[6:7], v[0:1], v[4:5]
-; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; GFX1200-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX1200-NEXT:    global_store_b64 v10, v[0:1], s[0:1]
-; GFX1200-NEXT:    s_endpgm
-                      ptr addrspace(1) %in2) #0 {
-   %r0 = load double, ptr addrspace(1) %in1, align 8
-   %r1 = load double, ptr addrspace(1) %in2, align 8
    %r2 = frem fast double %r0, %r1
    store double %r2, ptr addrspace(1) %out, align 8
    ret void
@@ -2073,47 +4566,54 @@ define amdgpu_kernel void @fast_frem_f64(ptr addrspace(1) %out, ptr addrspace(1)
 define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
 ; SI-LABEL: unsafe_frem_f64:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
-; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s0, s8
-; SI-NEXT:    s_mov_b32 s1, s9
-; SI-NEXT:    s_mov_b32 s8, s10
-; SI-NEXT:    s_mov_b32 s9, s11
-; SI-NEXT:    s_mov_b32 s10, s2
-; SI-NEXT:    s_mov_b32 s11, s3
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_mov_b32 s7, s3
-; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[4:7], 0
+; SI-NEXT:    s_mov_b32 s4, s0
+; SI-NEXT:    s_mov_b32 s5, s1
+; SI-NEXT:    s_mov_b32 s0, s2
+; SI-NEXT:    s_mov_b32 s1, s3
+; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    s_mov_b32 s3, s7
+; SI-NEXT:    s_mov_b32 s10, s6
+; SI-NEXT:    s_mov_b32 s11, s7
+; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[8:11], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; SI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; SI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; SI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; SI-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; SI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; SI-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
-; SI-NEXT:    v_readfirstlane_b32 s4, v4
-; SI-NEXT:    v_readfirstlane_b32 s5, v5
-; SI-NEXT:    s_bfe_u32 s6, s5, 0xb0014
-; SI-NEXT:    s_add_i32 s8, s6, 0xfffffc01
-; SI-NEXT:    s_mov_b32 s7, 0xfffff
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_lshr_b64 s[6:7], s[6:7], s8
-; SI-NEXT:    s_andn2_b64 s[6:7], s[4:5], s[6:7]
-; SI-NEXT:    s_and_b32 s9, s5, 0x80000000
+; SI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
+; SI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
+; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
+; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
+; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
+; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v9
+; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
+; SI-NEXT:    s_nop 1
+; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
+; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
+; SI-NEXT:    v_readfirstlane_b32 s0, v4
+; SI-NEXT:    v_readfirstlane_b32 s1, v5
+; SI-NEXT:    s_bfe_u32 s2, s1, 0xb0014
+; SI-NEXT:    s_add_i32 s8, s2, 0xfffffc01
+; SI-NEXT:    s_mov_b32 s3, 0xfffff
+; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    s_lshr_b64 s[2:3], s[2:3], s8
+; SI-NEXT:    s_andn2_b64 s[2:3], s[0:1], s[2:3]
+; SI-NEXT:    s_and_b32 s9, s1, 0x80000000
 ; SI-NEXT:    s_cmp_lt_i32 s8, 0
-; SI-NEXT:    s_cselect_b32 s6, 0, s6
-; SI-NEXT:    s_cselect_b32 s7, s9, s7
+; SI-NEXT:    s_cselect_b32 s2, 0, s2
+; SI-NEXT:    s_cselect_b32 s3, s9, s3
 ; SI-NEXT:    s_cmp_gt_i32 s8, 51
-; SI-NEXT:    s_cselect_b32 s5, s5, s7
-; SI-NEXT:    s_cselect_b32 s4, s4, s6
-; SI-NEXT:    v_fma_f64 v[0:1], -s[4:5], v[2:3], v[0:1]
-; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT:    s_cselect_b32 s1, s1, s3
+; SI-NEXT:    s_cselect_b32 s0, s0, s2
+; SI-NEXT:    v_fma_f64 v[0:1], -s[0:1], v[2:3], v[0:1]
+; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: unsafe_frem_f64:
@@ -2134,14 +4634,18 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
 ; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[0:3], 0
 ; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[4:7], 0
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; CI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; CI-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; CI-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; CI-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; CI-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; CI-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
+; CI-NEXT:    v_div_scale_f64 v[4:5], s[0:1], v[2:3], v[2:3], v[0:1]
+; CI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
+; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; CI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; CI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; CI-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
+; CI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
+; CI-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
+; CI-NEXT:    s_nop 1
+; CI-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
+; CI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; CI-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
 ; CI-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
 ; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
@@ -2161,14 +4665,18 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
 ; VI-NEXT:    v_mov_b32_e32 v0, s0
 ; VI-NEXT:    v_mov_b32_e32 v1, s1
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; VI-NEXT:    v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
-; VI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; VI-NEXT:    v_fma_f64 v[6:7], v[8:9], v[6:7], v[6:7]
-; VI-NEXT:    v_mul_f64 v[8:9], v[2:3], v[6:7]
-; VI-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[8:9], v[2:3]
-; VI-NEXT:    v_fma_f64 v[6:7], v[10:11], v[6:7], v[8:9]
+; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[2:3]
+; VI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
+; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
+; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
+; VI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
+; VI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
+; VI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[2:3], v[4:5], v[2:3]
+; VI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
+; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
+; VI-NEXT:    s_nop 1
+; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
+; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[2:3]
 ; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
 ; VI-NEXT:    v_fma_f64 v[2:3], -v[6:7], v[4:5], v[2:3]
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
@@ -2178,22 +4686,26 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT:    v_mov_b32_e32 v10, 0
+; GFX9-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_dwordx2 v[0:1], v10, s[2:3]
-; GFX9-NEXT:    global_load_dwordx2 v[2:3], v10, s[6:7]
+; GFX9-NEXT:    global_load_dwordx2 v[0:1], v12, s[2:3]
+; GFX9-NEXT:    global_load_dwordx2 v[2:3], v12, s[6:7]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX9-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX9-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX9-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX9-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
+; GFX9-NEXT:    v_div_scale_f64 v[4:5], s[2:3], v[2:3], v[2:3], v[0:1]
+; GFX9-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX9-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX9-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX9-NEXT:    v_div_scale_f64 v[8:9], vcc, v[0:1], v[2:3], v[0:1]
+; GFX9-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
+; GFX9-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
+; GFX9-NEXT:    s_nop 1
+; GFX9-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
+; GFX9-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; GFX9-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
 ; GFX9-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX9-NEXT:    global_store_dwordx2 v10, v[0:1], s[0:1]
+; GFX9-NEXT:    global_store_dwordx2 v12, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: unsafe_frem_f64:
@@ -2201,23 +4713,26 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v10, 0
+; GFX10-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    global_load_dwordx2 v[0:1], v10, s[2:3]
-; GFX10-NEXT:    global_load_dwordx2 v[2:3], v10, s[6:7]
+; GFX10-NEXT:    global_load_dwordx2 v[0:1], v12, s[2:3]
+; GFX10-NEXT:    global_load_dwordx2 v[2:3], v12, s[6:7]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX10-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX10-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX10-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX10-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX10-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; GFX10-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX10-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
+; GFX10-NEXT:    v_div_scale_f64 v[4:5], s2, v[2:3], v[2:3], v[0:1]
+; GFX10-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
+; GFX10-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX10-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX10-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX10-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
+; GFX10-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
+; GFX10-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
+; GFX10-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
+; GFX10-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; GFX10-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
 ; GFX10-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX10-NEXT:    global_store_dwordx2 v10, v[0:1], s[0:1]
+; GFX10-NEXT:    global_store_dwordx2 v12, v[0:1], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: unsafe_frem_f64:
@@ -2225,28 +4740,32 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v10, 0
+; GFX11-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b64 v[0:1], v10, s[2:3]
-; GFX11-NEXT:    global_load_b64 v[2:3], v10, s[4:5]
+; GFX11-NEXT:    global_load_b64 v[0:1], v12, s[2:3]
+; GFX11-NEXT:    global_load_b64 v[2:3], v12, s[4:5]
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
+; GFX11-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; GFX11-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX11-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
+; GFX11-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX11-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX11-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
-; GFX11-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
+; GFX11-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
+; GFX11-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
-; GFX11-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
+; GFX11-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
+; GFX11-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX11-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
 ; GFX11-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX11-NEXT:    global_store_b64 v10, v[0:1], s[0:1]
+; GFX11-NEXT:    global_store_b64 v12, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: unsafe_frem_f64:
@@ -2254,28 +4773,32 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1150-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-NEXT:    v_mov_b32_e32 v10, 0
+; GFX1150-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX1150-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1150-NEXT:    s_clause 0x1
-; GFX1150-NEXT:    global_load_b64 v[0:1], v10, s[2:3]
-; GFX1150-NEXT:    global_load_b64 v[2:3], v10, s[4:5]
+; GFX1150-NEXT:    global_load_b64 v[0:1], v12, s[2:3]
+; GFX1150-NEXT:    global_load_b64 v[2:3], v12, s[4:5]
 ; GFX1150-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1150-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
+; GFX1150-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1150-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
+; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1150-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
+; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX1150-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
+; GFX1150-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_mul_f64 v[6:7], v[0:1], v[4:5]
-; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
+; GFX1150-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
+; GFX1150-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
+; GFX1150-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; GFX1150-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX1150-NEXT:    global_store_b64 v10, v[0:1], s[0:1]
+; GFX1150-NEXT:    global_store_b64 v12, v[0:1], s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
 ; GFX1200-LABEL: unsafe_frem_f64:
@@ -2283,28 +4806,32 @@ define amdgpu_kernel void @unsafe_frem_f64(ptr addrspace(1) %out, ptr addrspace(
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1200-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-NEXT:    v_mov_b32_e32 v10, 0
+; GFX1200-NEXT:    v_mov_b32_e32 v12, 0
 ; GFX1200-NEXT:    s_wait_kmcnt 0x0
 ; GFX1200-NEXT:    s_clause 0x1
-; GFX1200-NEXT:    global_load_b64 v[0:1], v10, s[2:3]
-; GFX1200-NEXT:    global_load_b64 v[2:3], v10, s[4:5]
+; GFX1200-NEXT:    global_load_b64 v[0:1], v12, s[2:3]
+; GFX1200-NEXT:    global_load_b64 v[2:3], v12, s[4:5]
 ; GFX1200-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-NEXT:    v_rcp_f64_e32 v[4:5], v[2:3]
-; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1200-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
+; GFX1200-NEXT:    v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], v[0:1]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX1200-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
+; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
-; GFX1200-NEXT:    v_fma_f64 v[4:5], v[6:7], v[4:5], v[4:5]
+; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
+; GFX1200-NEXT:    v_div_scale_f64 v[8:9], vcc_lo, v[0:1], v[2:3], v[0:1]
+; GFX1200-NEXT:    v_mul_f64_e32 v[10:11], v[8:9], v[6:7]
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_mul_f64_e32 v[6:7], v[0:1], v[4:5]
-; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[2:3], v[6:7], v[0:1]
+; GFX1200-NEXT:    v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
+; GFX1200-NEXT:    v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[4:5], v[8:9], v[4:5], v[6:7]
+; GFX1200-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; GFX1200-NEXT:    v_trunc_f64_e32 v[4:5], v[4:5]
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[4:5], v[2:3], v[0:1]
-; GFX1200-NEXT:    global_store_b64 v10, v[0:1], s[0:1]
+; GFX1200-NEXT:    global_store_b64 v12, v[0:1], s[0:1]
 ; GFX1200-NEXT:    s_endpgm
                              ptr addrspace(1) %in2) #1 {
    %r0 = load double, ptr addrspace(1) %in1, align 8
@@ -2318,127 +4845,427 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; SI-LABEL: frem_v2f16:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
-; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s0, s8
-; SI-NEXT:    s_mov_b32 s1, s9
-; SI-NEXT:    s_mov_b32 s8, s10
-; SI-NEXT:    s_mov_b32 s9, s11
-; SI-NEXT:    s_mov_b32 s10, s2
-; SI-NEXT:    s_mov_b32 s11, s3
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_mov_b32 s7, s3
-; SI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
+; SI-NEXT:    s_mov_b32 s4, s10
+; SI-NEXT:    s_mov_b32 s5, s11
+; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    s_mov_b32 s3, s7
+; SI-NEXT:    buffer_load_dword v1, off, s[4:7], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_cvt_f32_f16_e32 v1, v0
-; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
 ; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT:    buffer_load_dword v2, off, s[4:7], 0 offset:16
+; SI-NEXT:    v_cvt_f32_f16_e32 v2, v1
+; SI-NEXT:    buffer_load_dword v3, off, s[0:3], 0 offset:16
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_cvt_f32_f16_e32 v3, v2
-; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT:    v_div_scale_f32 v4, vcc, v0, v2, v0
-; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v2, v2, v0
-; SI-NEXT:    v_rcp_f32_e32 v6, v5
+; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_and_b32_e32 v5, 0x7fffffff, v2
+; SI-NEXT:    v_and_b32_e32 v6, 0x7fffffff, v3
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v2|, |v3|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    v_cvt_f16_f32_e32 v4, v2
+; SI-NEXT:    s_cbranch_vccz .LBB9_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    v_bfi_b32 v7, s0, 0, v2
+; SI-NEXT:    v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v5, v6
+; SI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB9_3
+; SI-NEXT:    s_branch .LBB9_8
+; SI-NEXT:  .LBB9_2:
+; SI-NEXT:    ; implicit-def: $vgpr4
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB9_3: ; %frem.compute
+; SI-NEXT:    s_mov_b32 s3, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v5|, s3
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v5
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v4
+; SI-NEXT:    s_cselect_b32 s2, s0, 0
+; SI-NEXT:    v_frexp_mant_f32_e32 v4, v5
+; SI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v5, v4, 11
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v6|, s3
+; SI-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; SI-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v6
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v6
+; SI-NEXT:    s_cselect_b32 s3, s0, 0
+; SI-NEXT:    s_add_i32 s0, s3, -1
+; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 1
+; SI-NEXT:    s_not_b32 s1, s0
+; SI-NEXT:    s_add_i32 s1, s1, s2
+; SI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
+; SI-NEXT:    v_div_scale_f32 v7, s[4:5], v4, v4, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v8, v7
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
-; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
-; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
-; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
-; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; SI-NEXT:    v_fma_f32 v8, v9, v8, v8
+; SI-NEXT:    v_mul_f32_e32 v9, v6, v8
+; SI-NEXT:    v_fma_f32 v10, -v7, v9, v6
+; SI-NEXT:    v_fma_f32 v9, v10, v8, v9
+; SI-NEXT:    v_fma_f32 v6, -v7, v9, v6
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
-; SI-NEXT:    v_div_fixup_f32 v4, v4, v2, v0
-; SI-NEXT:    v_trunc_f32_e32 v4, v4
-; SI-NEXT:    v_fma_f32 v0, -v4, v2, v0
-; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
-; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v1
-; SI-NEXT:    v_rcp_f32_e32 v5, v4
+; SI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
+; SI-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s1, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB9_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s1, s2, s3
+; SI-NEXT:    s_add_i32 s1, s1, 11
+; SI-NEXT:  .LBB9_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v7, v5
+; SI-NEXT:    v_mul_f32_e32 v5, v7, v6
+; SI-NEXT:    v_rndne_f32_e32 v5, v5
+; SI-NEXT:    v_fma_f32 v5, -v5, v4, v7
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT:    v_add_f32_e32 v8, v5, v4
+; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, 11
+; SI-NEXT:    s_add_i32 s1, s1, -11
+; SI-NEXT:    s_cmp_gt_i32 s1, 11
+; SI-NEXT:    s_cbranch_scc1 .LBB9_5
+; SI-NEXT:  ; %bb.6: ; %Flow55
+; SI-NEXT:    v_mov_b32_e32 v5, v7
+; SI-NEXT:  .LBB9_7: ; %frem.loop_exit
+; SI-NEXT:    s_add_i32 s1, s1, -10
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, s1
+; SI-NEXT:    v_mul_f32_e32 v6, v5, v6
+; SI-NEXT:    v_rndne_f32_e32 v6, v6
+; SI-NEXT:    v_fma_f32 v5, -v6, v4, v5
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT:    v_add_f32_e32 v4, v5, v4
+; SI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v4, v4, s0
+; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT:    v_cvt_f32_f16_e32 v4, v4
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v4, s0, v4, v2
+; SI-NEXT:  .LBB9_8:
+; SI-NEXT:    v_cvt_f16_f32_e32 v5, v0
+; SI-NEXT:    v_cvt_f16_f32_e32 v7, v1
+; SI-NEXT:    v_cvt_f32_f16_e64 v6, |v5|
+; SI-NEXT:    v_cvt_f32_f16_e64 v7, |v7|
+; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v7
+; SI-NEXT:    s_cbranch_vccz .LBB9_10
+; SI-NEXT:  ; %bb.9: ; %frem.else20
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v8, s0, 0, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v7
+; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB9_11
+; SI-NEXT:    s_branch .LBB9_16
+; SI-NEXT:  .LBB9_10:
+; SI-NEXT:    ; implicit-def: $vgpr5
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB9_11: ; %frem.compute19
+; SI-NEXT:    s_mov_b32 s3, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v6|, s3
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v6
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v5
+; SI-NEXT:    s_cselect_b32 s2, s0, 0
+; SI-NEXT:    v_frexp_mant_f32_e32 v5, v6
+; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v6, v5, 11
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v7|, s3
+; SI-NEXT:    v_frexp_mant_f32_e32 v5, v7
+; SI-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v7
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v7
+; SI-NEXT:    s_cselect_b32 s3, s0, 0
+; SI-NEXT:    s_add_i32 s0, s3, -1
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, 1
+; SI-NEXT:    s_not_b32 s1, s0
+; SI-NEXT:    s_add_i32 s1, s1, s2
+; SI-NEXT:    v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; SI-NEXT:    v_div_scale_f32 v8, s[4:5], v5, v5, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v9, v8
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
-; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
-; SI-NEXT:    v_mul_f32_e32 v6, v2, v5
-; SI-NEXT:    v_fma_f32 v7, -v4, v6, v2
-; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
-; SI-NEXT:    v_fma_f32 v2, -v4, v6, v2
+; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
+; SI-NEXT:    v_mul_f32_e32 v10, v7, v9
+; SI-NEXT:    v_fma_f32 v11, -v8, v10, v7
+; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
+; SI-NEXT:    v_fma_f32 v7, -v8, v10, v7
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v2, v2, v5, v6
-; SI-NEXT:    v_div_fixup_f32 v2, v2, v3, v1
-; SI-NEXT:    v_trunc_f32_e32 v2, v2
-; SI-NEXT:    v_fma_f32 v1, -v2, v3, v1
+; SI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
+; SI-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s1, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB9_15
+; SI-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; SI-NEXT:    s_sub_i32 s1, s2, s3
+; SI-NEXT:    s_add_i32 s1, s1, 11
+; SI-NEXT:  .LBB9_13: ; %frem.loop_body27
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v8, v6
+; SI-NEXT:    v_mul_f32_e32 v6, v8, v7
+; SI-NEXT:    v_rndne_f32_e32 v6, v6
+; SI-NEXT:    v_fma_f32 v6, -v6, v5, v8
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; SI-NEXT:    v_add_f32_e32 v9, v6, v5
+; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v6, v6, 11
+; SI-NEXT:    s_add_i32 s1, s1, -11
+; SI-NEXT:    s_cmp_gt_i32 s1, 11
+; SI-NEXT:    s_cbranch_scc1 .LBB9_13
+; SI-NEXT:  ; %bb.14: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v6, v8
+; SI-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; SI-NEXT:    s_add_i32 s1, s1, -10
+; SI-NEXT:    v_ldexp_f32_e64 v6, v6, s1
+; SI-NEXT:    v_mul_f32_e32 v7, v6, v7
+; SI-NEXT:    v_rndne_f32_e32 v7, v7
+; SI-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; SI-NEXT:    v_add_f32_e32 v5, v6, v5
+; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, s0
+; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v5, s0, v5, v0
+; SI-NEXT:  .LBB9_16: ; %Flow54
+; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v3
+; SI-NEXT:    v_cvt_f16_f32_e32 v3, v4
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
+; SI-NEXT:    s_movk_i32 s2, 0x7c00
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v2
+; SI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
+; SI-NEXT:    v_cndmask_b32_e32 v3, v3, v2, vcc
+; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
 ; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT:    v_or_b32_e32 v0, v1, v0
-; SI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v5
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v0
+; SI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT:    v_or_b32_e32 v0, v3, v0
+; SI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: frem_v2f16:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
-; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    s_mov_b32 s6, s2
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
+; CI-NEXT:    s_mov_b32 s7, 0xf000
+; CI-NEXT:    s_mov_b32 s6, -1
+; CI-NEXT:    s_mov_b32 s2, s6
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_mov_b32 s0, s8
-; CI-NEXT:    s_mov_b32 s1, s9
-; CI-NEXT:    s_mov_b32 s8, s10
-; CI-NEXT:    s_mov_b32 s9, s11
-; CI-NEXT:    s_mov_b32 s10, s2
-; CI-NEXT:    s_mov_b32 s11, s3
-; CI-NEXT:    s_mov_b32 s7, s3
-; CI-NEXT:    buffer_load_dword v0, off, s[8:11], 0
-; CI-NEXT:    buffer_load_dword v2, off, s[4:7], 0 offset:16
+; CI-NEXT:    s_mov_b32 s4, s10
+; CI-NEXT:    s_mov_b32 s5, s11
+; CI-NEXT:    buffer_load_dword v1, off, s[4:7], 0
+; CI-NEXT:    s_mov_b32 s3, s7
+; CI-NEXT:    buffer_load_dword v3, off, s[0:3], 0 offset:16
+; CI-NEXT:    s_brev_b32 s0, -2
 ; CI-NEXT:    s_waitcnt vmcnt(1)
-; CI-NEXT:    v_cvt_f32_f16_e32 v1, v0
-; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; CI-NEXT:    v_cvt_f32_f16_e32 v2, v1
+; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_cvt_f32_f16_e32 v3, v2
-; CI-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
+; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
+; CI-NEXT:    v_cvt_f32_f16_e32 v3, v3
 ; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT:    v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v2, v2, v0
-; CI-NEXT:    v_div_scale_f32 v4, vcc, v0, v2, v0
-; CI-NEXT:    v_rcp_f32_e32 v6, v5
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_cvt_f16_f32_e32 v4, v2
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v2|, |v3|
+; CI-NEXT:    v_and_b32_e32 v6, 0x7fffffff, v2
+; CI-NEXT:    v_and_b32_e32 v5, 0x7fffffff, v3
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB9_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    v_cvt_f32_f16_e32 v4, v4
+; CI-NEXT:    v_bfi_b32 v7, s0, 0, v2
+; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
+; CI-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
+; CI-NEXT:    s_cbranch_execz .LBB9_3
+; CI-NEXT:    s_branch .LBB9_8
+; CI-NEXT:  .LBB9_2:
+; CI-NEXT:    ; implicit-def: $vgpr4
+; CI-NEXT:  .LBB9_3: ; %frem.compute
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
+; CI-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; CI-NEXT:    v_frexp_mant_f32_e32 v6, v5
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
+; CI-NEXT:    v_ldexp_f32_e64 v5, v6, 1
+; CI-NEXT:    v_div_scale_f32 v11, s[0:1], v5, v5, 1.0
+; CI-NEXT:    v_ldexp_f32_e64 v7, v4, 11
+; CI-NEXT:    v_add_i32_e32 v4, vcc, -1, v10
+; CI-NEXT:    v_not_b32_e32 v6, v4
+; CI-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v12, v11
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
-; CI-NEXT:    v_mul_f32_e32 v7, v4, v6
-; CI-NEXT:    v_fma_f32 v8, -v5, v7, v4
-; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
-; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
+; CI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; CI-NEXT:    v_fma_f32 v12, v13, v12, v12
+; CI-NEXT:    v_mul_f32_e32 v13, v8, v12
+; CI-NEXT:    v_fma_f32 v14, -v11, v13, v8
+; CI-NEXT:    v_fma_f32 v13, v14, v12, v13
+; CI-NEXT:    v_fma_f32 v8, -v11, v13, v8
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
-; CI-NEXT:    v_div_fixup_f32 v4, v4, v2, v0
-; CI-NEXT:    v_trunc_f32_e32 v4, v4
-; CI-NEXT:    v_fma_f32 v0, -v4, v2, v0
-; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v3, v3, v1
-; CI-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
-; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; CI-NEXT:    v_rcp_f32_e32 v5, v4
+; CI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
+; CI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB9_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v6, vcc, v9, v10
+; CI-NEXT:    v_add_i32_e32 v6, vcc, 11, v6
+; CI-NEXT:  .LBB9_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v9, v7
+; CI-NEXT:    v_mul_f32_e32 v7, v9, v8
+; CI-NEXT:    v_rndne_f32_e32 v7, v7
+; CI-NEXT:    v_fma_f32 v7, -v7, v5, v9
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; CI-NEXT:    v_add_f32_e32 v10, v7, v5
+; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
+; CI-NEXT:    v_add_i32_e32 v6, vcc, -11, v6
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
+; CI-NEXT:    v_ldexp_f32_e64 v7, v7, 11
+; CI-NEXT:    s_cbranch_vccnz .LBB9_5
+; CI-NEXT:  ; %bb.6: ; %Flow55
+; CI-NEXT:    v_mov_b32_e32 v7, v9
+; CI-NEXT:  .LBB9_7: ; %frem.loop_exit
+; CI-NEXT:    v_add_i32_e32 v6, vcc, -10, v6
+; CI-NEXT:    v_ldexp_f32_e32 v6, v7, v6
+; CI-NEXT:    v_mul_f32_e32 v7, v6, v8
+; CI-NEXT:    v_rndne_f32_e32 v7, v7
+; CI-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; CI-NEXT:    v_add_f32_e32 v5, v6, v5
+; CI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_cvt_f32_f16_e32 v4, v4
+; CI-NEXT:    v_bfi_b32 v4, s0, v4, v2
+; CI-NEXT:  .LBB9_8:
+; CI-NEXT:    v_cvt_f16_f32_e32 v5, v0
+; CI-NEXT:    v_cvt_f16_f32_e32 v6, v1
+; CI-NEXT:    v_cvt_f32_f16_e64 v7, |v5|
+; CI-NEXT:    v_cvt_f32_f16_e64 v6, |v6|
+; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v7, v6
+; CI-NEXT:    s_cbranch_vccz .LBB9_10
+; CI-NEXT:  ; %bb.9: ; %frem.else20
+; CI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_bfi_b32 v8, s0, 0, v0
+; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v7, v6
+; CI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; CI-NEXT:    s_cbranch_execz .LBB9_11
+; CI-NEXT:    s_branch .LBB9_16
+; CI-NEXT:  .LBB9_10:
+; CI-NEXT:    ; implicit-def: $vgpr5
+; CI-NEXT:  .LBB9_11: ; %frem.compute19
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
+; CI-NEXT:    v_frexp_mant_f32_e32 v5, v7
+; CI-NEXT:    v_frexp_mant_f32_e32 v7, v6
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
+; CI-NEXT:    v_ldexp_f32_e64 v6, v7, 1
+; CI-NEXT:    v_div_scale_f32 v12, s[0:1], v6, v6, 1.0
+; CI-NEXT:    v_ldexp_f32_e64 v8, v5, 11
+; CI-NEXT:    v_add_i32_e32 v5, vcc, -1, v11
+; CI-NEXT:    v_not_b32_e32 v7, v5
+; CI-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v13, v12
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
-; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
-; CI-NEXT:    v_mul_f32_e32 v6, v2, v5
-; CI-NEXT:    v_fma_f32 v7, -v4, v6, v2
-; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
-; CI-NEXT:    v_fma_f32 v2, -v4, v6, v2
+; CI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; CI-NEXT:    v_fma_f32 v13, v14, v13, v13
+; CI-NEXT:    v_mul_f32_e32 v14, v9, v13
+; CI-NEXT:    v_fma_f32 v15, -v12, v14, v9
+; CI-NEXT:    v_fma_f32 v14, v15, v13, v14
+; CI-NEXT:    v_fma_f32 v9, -v12, v14, v9
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v2, v2, v5, v6
-; CI-NEXT:    v_div_fixup_f32 v2, v2, v3, v1
-; CI-NEXT:    v_trunc_f32_e32 v2, v2
-; CI-NEXT:    v_fma_f32 v1, -v2, v3, v1
+; CI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v7
+; CI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB9_15
+; CI-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; CI-NEXT:    v_sub_i32_e32 v7, vcc, v10, v11
+; CI-NEXT:    v_add_i32_e32 v7, vcc, 11, v7
+; CI-NEXT:  .LBB9_13: ; %frem.loop_body27
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v10, v8
+; CI-NEXT:    v_mul_f32_e32 v8, v10, v9
+; CI-NEXT:    v_rndne_f32_e32 v8, v8
+; CI-NEXT:    v_fma_f32 v8, -v8, v6, v10
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
+; CI-NEXT:    v_add_f32_e32 v11, v8, v6
+; CI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
+; CI-NEXT:    v_add_i32_e32 v7, vcc, -11, v7
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v7
+; CI-NEXT:    v_ldexp_f32_e64 v8, v8, 11
+; CI-NEXT:    s_cbranch_vccnz .LBB9_13
+; CI-NEXT:  ; %bb.14: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v8, v10
+; CI-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; CI-NEXT:    v_add_i32_e32 v7, vcc, -10, v7
+; CI-NEXT:    v_ldexp_f32_e32 v7, v8, v7
+; CI-NEXT:    v_mul_f32_e32 v8, v7, v9
+; CI-NEXT:    v_rndne_f32_e32 v8, v8
+; CI-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; CI-NEXT:    v_add_f32_e32 v6, v7, v6
+; CI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v5, v6, v5
+; CI-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; CI-NEXT:    v_bfi_b32 v5, s0, v5, v0
+; CI-NEXT:  .LBB9_16: ; %Flow54
+; CI-NEXT:    v_cvt_f16_f32_e32 v3, v3
 ; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT:    v_or_b32_e32 v0, v1, v0
-; CI-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT:    s_movk_i32 s2, 0x7c00
+; CI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
+; CI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v2
+; CI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v3
+; CI-NEXT:    v_cvt_f16_f32_e32 v3, v4
+; CI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; CI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
+; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; CI-NEXT:    s_mov_b32 s11, 0xf000
+; CI-NEXT:    s_mov_b32 s10, -1
+; CI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; CI-NEXT:    v_cndmask_b32_e32 v3, v3, v2, vcc
+; CI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v1
+; CI-NEXT:    v_cvt_f16_f32_e32 v1, v5
+; CI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v0
+; CI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; CI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc
+; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; CI-NEXT:    v_or_b32_e32 v0, v3, v0
+; CI-NEXT:    buffer_store_dword v0, off, s[8:11], 0
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: frem_v2f16:
@@ -2446,50 +5273,171 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_add_u32 s0, s4, 16
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    s_addc_u32 s1, s5, 0
-; VI-NEXT:    flat_load_dword v4, v[2:3]
-; VI-NEXT:    v_mov_b32_e32 v3, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s0
-; VI-NEXT:    flat_load_dword v2, v[2:3]
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    s_add_u32 s2, s4, 16
+; VI-NEXT:    s_addc_u32 s3, s5, 0
+; VI-NEXT:    flat_load_dword v0, v[0:1]
+; VI-NEXT:    v_mov_b32_e32 v1, s2
+; VI-NEXT:    v_mov_b32_e32 v2, s3
+; VI-NEXT:    flat_load_dword v1, v[1:2]
 ; VI-NEXT:    s_waitcnt vmcnt(1)
-; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v4
-; VI-NEXT:    v_cvt_f32_f16_e32 v5, v3
+; VI-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; VI-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; VI-NEXT:    v_rcp_f32_e32 v8, v7
-; VI-NEXT:    v_mul_f32_e32 v9, v5, v8
-; VI-NEXT:    v_mad_f32 v10, -v7, v9, v5
-; VI-NEXT:    v_mac_f32_e32 v9, v10, v8
-; VI-NEXT:    v_mad_f32 v5, -v7, v9, v5
-; VI-NEXT:    v_mul_f32_e32 v5, v5, v8
-; VI-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
-; VI-NEXT:    v_add_f32_e32 v5, v5, v9
-; VI-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; VI-NEXT:    v_div_fixup_f16 v5, v5, v6, v3
-; VI-NEXT:    v_trunc_f16_e32 v5, v5
-; VI-NEXT:    v_fma_f16 v3, -v5, v6, v3
-; VI-NEXT:    v_cvt_f32_f16_e32 v6, v2
-; VI-NEXT:    v_cvt_f32_f16_e32 v5, v4
-; VI-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT:    v_rcp_f32_e32 v7, v6
-; VI-NEXT:    v_mul_f32_e32 v8, v5, v7
-; VI-NEXT:    v_mad_f32 v9, -v6, v8, v5
-; VI-NEXT:    v_mac_f32_e32 v8, v9, v7
-; VI-NEXT:    v_mad_f32 v5, -v6, v8, v5
-; VI-NEXT:    v_mul_f32_e32 v5, v5, v7
-; VI-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
-; VI-NEXT:    v_add_f32_e32 v5, v5, v8
+; VI-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
+; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
+; VI-NEXT:    s_cbranch_vccz .LBB9_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v2, s2, 0, v0
+; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
+; VI-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc
+; VI-NEXT:    s_cbranch_execz .LBB9_3
+; VI-NEXT:    s_branch .LBB9_8
+; VI-NEXT:  .LBB9_2:
+; VI-NEXT:    ; implicit-def: $vgpr2
+; VI-NEXT:  .LBB9_3: ; %frem.compute
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
+; VI-NEXT:    v_frexp_mant_f32_e32 v2, v4
+; VI-NEXT:    v_frexp_mant_f32_e32 v4, v3
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
+; VI-NEXT:    v_ldexp_f32 v3, v4, 1
+; VI-NEXT:    v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
+; VI-NEXT:    v_ldexp_f32 v5, v2, 11
+; VI-NEXT:    v_add_u32_e32 v2, vcc, -1, v8
+; VI-NEXT:    v_not_b32_e32 v4, v2
+; VI-NEXT:    v_add_u32_e32 v4, vcc, v4, v7
+; VI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v10, v9
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
+; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
+; VI-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
+; VI-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
+; VI-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB9_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v4, vcc, v7, v8
+; VI-NEXT:    v_add_u32_e32 v4, vcc, 11, v4
+; VI-NEXT:  .LBB9_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v7, v5
+; VI-NEXT:    v_mul_f32_e32 v5, v7, v6
+; VI-NEXT:    v_rndne_f32_e32 v5, v5
+; VI-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; VI-NEXT:    v_add_f32_e32 v8, v5, v3
+; VI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -11, v4
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
+; VI-NEXT:    v_ldexp_f32 v5, v5, 11
+; VI-NEXT:    s_cbranch_vccnz .LBB9_5
+; VI-NEXT:  ; %bb.6: ; %Flow55
+; VI-NEXT:    v_mov_b32_e32 v5, v7
+; VI-NEXT:  .LBB9_7: ; %frem.loop_exit
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -10, v4
+; VI-NEXT:    v_ldexp_f32 v4, v5, v4
+; VI-NEXT:    v_mul_f32_e32 v5, v4, v6
+; VI-NEXT:    v_rndne_f32_e32 v5, v5
+; VI-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
+; VI-NEXT:    v_add_f32_e32 v3, v4, v3
+; VI-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-NEXT:    v_ldexp_f32 v2, v3, v2
+; VI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v2, s2, v2, v0
+; VI-NEXT:  .LBB9_8:
+; VI-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; VI-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
+; VI-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
+; VI-NEXT:    v_cvt_f32_f16_e64 v6, |v4|
+; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v7, v6
+; VI-NEXT:    s_cbranch_vccz .LBB9_10
+; VI-NEXT:  ; %bb.9: ; %frem.else20
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v5, s2, 0, v3
+; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v7, v6
+; VI-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc
+; VI-NEXT:    s_cbranch_execz .LBB9_11
+; VI-NEXT:    s_branch .LBB9_16
+; VI-NEXT:  .LBB9_10:
+; VI-NEXT:    ; implicit-def: $vgpr5
+; VI-NEXT:  .LBB9_11: ; %frem.compute19
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v7
+; VI-NEXT:    v_frexp_mant_f32_e32 v5, v7
+; VI-NEXT:    v_frexp_mant_f32_e32 v7, v6
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v6
+; VI-NEXT:    v_ldexp_f32 v6, v7, 1
+; VI-NEXT:    v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
+; VI-NEXT:    v_ldexp_f32 v8, v5, 11
+; VI-NEXT:    v_add_u32_e32 v5, vcc, -1, v11
+; VI-NEXT:    v_not_b32_e32 v7, v5
+; VI-NEXT:    v_add_u32_e32 v7, vcc, v7, v10
+; VI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v13, v12
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; VI-NEXT:    v_fma_f32 v13, v14, v13, v13
+; VI-NEXT:    v_mul_f32_e32 v14, v9, v13
+; VI-NEXT:    v_fma_f32 v15, -v12, v14, v9
+; VI-NEXT:    v_fma_f32 v14, v15, v13, v14
+; VI-NEXT:    v_fma_f32 v9, -v12, v14, v9
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v7
+; VI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB9_15
+; VI-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; VI-NEXT:    v_sub_u32_e32 v7, vcc, v10, v11
+; VI-NEXT:    v_add_u32_e32 v7, vcc, 11, v7
+; VI-NEXT:  .LBB9_13: ; %frem.loop_body27
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v10, v8
+; VI-NEXT:    v_mul_f32_e32 v8, v10, v9
+; VI-NEXT:    v_rndne_f32_e32 v8, v8
+; VI-NEXT:    v_fma_f32 v8, -v8, v6, v10
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
+; VI-NEXT:    v_add_f32_e32 v11, v8, v6
+; VI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
+; VI-NEXT:    v_add_u32_e32 v7, vcc, -11, v7
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v7
+; VI-NEXT:    v_ldexp_f32 v8, v8, 11
+; VI-NEXT:    s_cbranch_vccnz .LBB9_13
+; VI-NEXT:  ; %bb.14: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v8, v10
+; VI-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; VI-NEXT:    v_add_u32_e32 v7, vcc, -10, v7
+; VI-NEXT:    v_ldexp_f32 v7, v8, v7
+; VI-NEXT:    v_mul_f32_e32 v8, v7, v9
+; VI-NEXT:    v_rndne_f32_e32 v8, v8
+; VI-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; VI-NEXT:    v_add_f32_e32 v6, v7, v6
+; VI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; VI-NEXT:    v_ldexp_f32 v5, v6, v5
 ; VI-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; VI-NEXT:    v_div_fixup_f16 v5, v5, v2, v4
-; VI-NEXT:    v_trunc_f16_e32 v5, v5
-; VI-NEXT:    v_fma_f16 v2, -v5, v2, v4
-; VI-NEXT:    v_or_b32_e32 v2, v2, v3
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v5, s2, v5, v3
+; VI-NEXT:  .LBB9_16: ; %Flow54
+; VI-NEXT:    s_movk_i32 s4, 0x7c00
+; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
+; VI-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v0|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_mov_b32_e32 v6, 0x7e00
+; VI-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v4
+; VI-NEXT:    v_cmp_nge_f16_e64 s[0:1], |v3|, s4
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_cndmask_b32_sdwa v3, v6, v5, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
@@ -2497,44 +5445,167 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT:    v_mov_b32_e32 v0, 0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_dword v1, v0, s[2:3]
-; GFX9-NEXT:    global_load_dword v2, v0, s[6:7] offset:16
+; GFX9-NEXT:    global_load_dword v1, v2, s[2:3]
+; GFX9-NEXT:    global_load_dword v0, v2, s[6:7] offset:16
 ; GFX9-NEXT:    s_waitcnt vmcnt(1)
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v4, |v1|
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v4, v2
-; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_rcp_f32_e32 v7, v7
-; GFX9-NEXT:    v_mul_f32_e32 v3, v3, v4
-; GFX9-NEXT:    v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mac_f32_e32 v3, v5, v4
-; GFX9-NEXT:    v_mad_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mul_f32_e32 v4, v5, v4
-; GFX9-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v3, |v0|
+; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v4, v3
+; GFX9-NEXT:    s_cbranch_vccz .LBB9_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v2, s2, 0, v1
+; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v4, v3
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v1, v2, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB9_3
+; GFX9-NEXT:    s_branch .LBB9_8
+; GFX9-NEXT:  .LBB9_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr2
+; GFX9-NEXT:  .LBB9_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v7, v4
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v2, v4
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v3
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v8, v3
+; GFX9-NEXT:    v_ldexp_f32 v3, v4, 1
+; GFX9-NEXT:    v_div_scale_f32 v9, s[2:3], v3, v3, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v3, 1.0
+; GFX9-NEXT:    v_ldexp_f32 v5, v2, 11
+; GFX9-NEXT:    v_add_u32_e32 v2, -1, v8
+; GFX9-NEXT:    v_not_b32_e32 v4, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
+; GFX9-NEXT:    v_mul_f32_e32 v11, v6, v10
+; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v6
+; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
+; GFX9-NEXT:    v_fma_f32 v6, -v9, v11, v6
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v4
+; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v3, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v4, v7, v8
+; GFX9-NEXT:    v_add_u32_e32 v4, 11, v4
+; GFX9-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v7, v5
+; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v6
+; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX9-NEXT:    v_fma_f32 v5, -v5, v3, v7
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; GFX9-NEXT:    v_add_f32_e32 v8, v5, v3
+; GFX9-NEXT:    v_add_u32_e32 v4, -11, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v4
+; GFX9-NEXT:    v_ldexp_f32 v5, v5, 11
+; GFX9-NEXT:    s_cbranch_vccnz .LBB9_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow55
+; GFX9-NEXT:    v_mov_b32_e32 v5, v7
+; GFX9-NEXT:  .LBB9_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_add_u32_e32 v4, -10, v4
+; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v6
+; GFX9-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX9-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v4
 ; GFX9-NEXT:    v_add_f32_e32 v3, v4, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v5, v4
-; GFX9-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX9-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX9-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
-; GFX9-NEXT:    v_mad_mix_f32 v8, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX9-NEXT:    v_mac_f32_e32 v5, v8, v7
-; GFX9-NEXT:    v_fma_f16 v3, -v3, v2, v1
-; GFX9-NEXT:    v_mad_mix_f32 v1, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mul_f32_e32 v1, v1, v7
-; GFX9-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX9-NEXT:    v_add_f32_e32 v1, v1, v5
-; GFX9-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX9-NEXT:    v_div_fixup_f16 v1, v1, v6, v4
-; GFX9-NEXT:    v_trunc_f16_e32 v1, v1
-; GFX9-NEXT:    v_fma_f16 v1, -v1, v6, v4
-; GFX9-NEXT:    v_pack_b32_f16 v1, v3, v1
-; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX9-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v2, s2, v2, v1
+; GFX9-NEXT:  .LBB9_8:
+; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v6, |v3|
+; GFX9-NEXT:    v_cvt_f32_f16_sdwa v5, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
+; GFX9-NEXT:    s_cbranch_vccz .LBB9_10
+; GFX9-NEXT:  ; %bb.9: ; %frem.else20
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v4, s2, 0, v3
+; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v3, v4, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB9_11
+; GFX9-NEXT:    s_branch .LBB9_16
+; GFX9-NEXT:  .LBB9_10:
+; GFX9-NEXT:    ; implicit-def: $vgpr4
+; GFX9-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v6, v5
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
+; GFX9-NEXT:    v_ldexp_f32 v5, v6, 1
+; GFX9-NEXT:    v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; GFX9-NEXT:    v_ldexp_f32 v7, v4, 11
+; GFX9-NEXT:    v_add_u32_e32 v4, -1, v10
+; GFX9-NEXT:    v_not_b32_e32 v6, v4
+; GFX9-NEXT:    v_add_u32_e32 v6, v6, v9
+; GFX9-NEXT:    v_rcp_f32_e32 v12, v11
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; GFX9-NEXT:    v_fma_f32 v12, v13, v12, v12
+; GFX9-NEXT:    v_mul_f32_e32 v13, v8, v12
+; GFX9-NEXT:    v_fma_f32 v14, -v11, v13, v8
+; GFX9-NEXT:    v_fma_f32 v13, v14, v12, v13
+; GFX9-NEXT:    v_fma_f32 v8, -v11, v13, v8
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
+; GFX9-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v6, v9, v10
+; GFX9-NEXT:    v_add_u32_e32 v6, 11, v6
+; GFX9-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v9, v7
+; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v8
+; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX9-NEXT:    v_fma_f32 v7, -v7, v5, v9
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; GFX9-NEXT:    v_add_f32_e32 v10, v7, v5
+; GFX9-NEXT:    v_add_u32_e32 v6, -11, v6
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
+; GFX9-NEXT:    v_ldexp_f32 v7, v7, 11
+; GFX9-NEXT:    s_cbranch_vccnz .LBB9_13
+; GFX9-NEXT:  ; %bb.14: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v7, v9
+; GFX9-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; GFX9-NEXT:    v_add_u32_e32 v6, -10, v6
+; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
+; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v8
+; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX9-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; GFX9-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v4, s2, v4, v3
+; GFX9-NEXT:  .LBB9_16: ; %Flow54
+; GFX9-NEXT:    s_movk_i32 s4, 0x7c00
+; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v0
+; GFX9-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v1|, s4
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0x7e00
+; GFX9-NEXT:    v_cmp_lg_f16_sdwa s[2:3], v0, v5 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v3|, s4
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v1, v2, vcc
+; GFX9-NEXT:    s_and_b64 vcc, s[4:5], s[2:3]
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v4, vcc
+; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v2
+; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-NEXT:    global_store_dword v5, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: frem_v2f16:
@@ -2542,45 +5613,168 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v0, 0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    global_load_dword v1, v0, s[2:3]
-; GFX10-NEXT:    global_load_dword v2, v0, s[6:7] offset:16
+; GFX10-NEXT:    global_load_dword v1, v2, s[2:3]
+; GFX10-NEXT:    global_load_dword v0, v2, s[6:7] offset:16
 ; GFX10-NEXT:    s_waitcnt vmcnt(1)
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v4, |v1|
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v4, v2
-; GFX10-NEXT:    v_rcp_f32_e32 v5, v4
-; GFX10-NEXT:    v_mul_f32_e32 v6, v3, v5
-; GFX10-NEXT:    v_mad_f32 v7, -v4, v6, v3
-; GFX10-NEXT:    v_mac_f32_e32 v6, v7, v5
-; GFX10-NEXT:    v_mad_f32 v3, -v4, v6, v3
-; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v5
-; GFX10-NEXT:    v_and_b32_e32 v3, 0xff800000, v3
-; GFX10-NEXT:    v_add_f32_e32 v3, v3, v6
-; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
-; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fma_f16 v3, -v3, v2, v1
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v4, v1
-; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
-; GFX10-NEXT:    v_mul_f32_e32 v7, v4, v6
-; GFX10-NEXT:    v_mad_f32 v8, -v5, v7, v4
-; GFX10-NEXT:    v_mac_f32_e32 v7, v8, v6
-; GFX10-NEXT:    v_mad_f32 v4, -v5, v7, v4
-; GFX10-NEXT:    v_mul_f32_e32 v4, v4, v6
-; GFX10-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
-; GFX10-NEXT:    v_add_f32_e32 v4, v4, v7
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v3, |v0|
+; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v4, v3
+; GFX10-NEXT:    s_cbranch_vccz .LBB9_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff, 0, v1
+; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v1, v2, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB9_3
+; GFX10-NEXT:    s_branch .LBB9_8
+; GFX10-NEXT:  .LBB9_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr2
+; GFX10-NEXT:  .LBB9_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v2, v4
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v6, v3
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v5, v4
+; GFX10-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v2, v3
+; GFX10-NEXT:    v_ldexp_f32 v3, v6, 1
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX10-NEXT:    v_div_scale_f32 v7, s4, v3, v3, 1.0
+; GFX10-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX10-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX10-NEXT:    v_not_b32_e32 v6, v2
+; GFX10-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX10-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX10-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX10-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 11
+; GFX10-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v7, v4
+; GFX10-NEXT:    s_add_i32 s2, s2, -11
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX10-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX10-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX10-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX10-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX10-NEXT:    s_cbranch_scc1 .LBB9_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow55
+; GFX10-NEXT:    v_mov_b32_e32 v6, s2
+; GFX10-NEXT:    v_mov_b32_e32 v4, v7
+; GFX10-NEXT:  .LBB9_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX10-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX10-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX10-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX10-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX10-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v1
+; GFX10-NEXT:  .LBB9_8:
+; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX10-NEXT:    v_cvt_f32_f16_sdwa v4, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v6, |v3|
+; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v6, v4
+; GFX10-NEXT:    s_cbranch_vccz .LBB9_10
+; GFX10-NEXT:  ; %bb.9: ; %frem.else20
+; GFX10-NEXT:    v_bfi_b32 v5, 0x7fff, 0, v3
+; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v4
+; GFX10-NEXT:    v_cndmask_b32_e32 v5, v3, v5, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB9_11
+; GFX10-NEXT:    s_branch .LBB9_16
+; GFX10-NEXT:  .LBB9_10:
+; GFX10-NEXT:    ; implicit-def: $vgpr5
+; GFX10-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v5, v6
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v7, v6
+; GFX10-NEXT:    v_ldexp_f32 v6, v5, 11
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v5, v4
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v4, v4
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v7
+; GFX10-NEXT:    v_ldexp_f32 v5, v5, 1
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX10-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX10-NEXT:    v_div_scale_f32 v9, s4, v5, v5, 1.0
+; GFX10-NEXT:    v_not_b32_e32 v8, v4
+; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX10-NEXT:    v_add_nc_u32_e32 v8, v8, v7
+; GFX10-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v10
+; GFX10-NEXT:    v_mul_f32_e32 v11, v7, v10
+; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v7
+; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v10
+; GFX10-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
+; GFX10-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 11
+; GFX10-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v9, v6
+; GFX10-NEXT:    s_add_i32 s2, s2, -11
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX10-NEXT:    v_mul_f32_e32 v6, v9, v7
+; GFX10-NEXT:    v_rndne_f32_e32 v6, v6
+; GFX10-NEXT:    v_fma_f32 v6, -v6, v5, v9
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX10-NEXT:    v_add_f32_e32 v8, v6, v5
+; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v6, v6, 11
+; GFX10-NEXT:    s_cbranch_scc1 .LBB9_13
+; GFX10-NEXT:  ; %bb.14: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v8, s2
+; GFX10-NEXT:    v_mov_b32_e32 v6, v9
+; GFX10-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; GFX10-NEXT:    v_add_nc_u32_e32 v8, -10, v8
+; GFX10-NEXT:    v_ldexp_f32 v6, v6, v8
+; GFX10-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX10-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX10-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX10-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
 ; GFX10-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; GFX10-NEXT:    v_div_fixup_f16 v4, v4, v2, v1
-; GFX10-NEXT:    v_trunc_f16_e32 v4, v4
-; GFX10-NEXT:    v_fma_f16 v1, -v4, v2, v1
-; GFX10-NEXT:    v_pack_b32_f16 v1, v3, v1
-; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT:    v_bfi_b32 v5, 0x7fff, v4, v3
+; GFX10-NEXT:  .LBB9_16: ; %Flow54
+; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v1|
+; GFX10-NEXT:    v_cmp_nle_f16_e64 s3, 0x7c00, |v3|
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v2, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX10-NEXT:    v_cmp_lg_f16_sdwa s2, v0, v2 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v5, vcc_lo
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 16, v1
+; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-TRUE16-LABEL: frem_v2f16:
@@ -2591,55 +5785,215 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
-; GFX11-TRUE16-NEXT:    global_load_b32 v2, v1, s[2:3]
-; GFX11-TRUE16-NEXT:    global_load_b32 v3, v1, s[4:5] offset:16
+; GFX11-TRUE16-NEXT:    global_load_b32 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_b32 v1, v1, s[4:5] offset:16
 ; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0.l|
 ; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v3.l
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v4, v3
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB9_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, 0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v7, v6.l
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v5, v2
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, v0.l, v2.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB9_3
+; GFX11-TRUE16-NEXT:    s_branch .LBB9_8
+; GFX11-TRUE16-NEXT:  .LBB9_2:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-TRUE16-NEXT:  .LBB9_3: ; %frem.compute
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v3, v6, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT:    s_denorm_mode 15
 ; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v4
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v5, v4
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v5, -v3, v0, v2 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v5, v4
-; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v4, v0
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX11-TRUE16-NEXT:    s_denorm_mode 12
+; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB9_5
+; GFX11-TRUE16-NEXT:  ; %bb.6: ; %Flow55
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, s2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX11-TRUE16-NEXT:  .LBB9_7: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX11-TRUE16-NEXT:  .LBB9_8:
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v5, v4.l
-; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v3.l|
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v4.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB9_10
+; GFX11-TRUE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, 0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v8, v7
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v3.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB9_11
+; GFX11-TRUE16-NEXT:    s_branch .LBB9_16
+; GFX11-TRUE16-NEXT:  .LBB9_10:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v6
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v6
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v6, 11
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v5
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v8, -v3, v5, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v3.l, v2.l
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v6, 1
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v5
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -1, v5
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v10, null, v6, v6, 1.0
+; GFX11-TRUE16-NEXT:    v_not_b32_e32 v9, v5
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v5, v8, v7
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -v3, v5, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, v9, v8
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
+; GFX11-TRUE16-NEXT:    s_denorm_mode 15
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v7
-; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v11
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v12, v8, v11
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
+; GFX11-TRUE16-NEXT:    v_fma_f32 v13, -v10, v12, v8
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v12, v13, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v8, -v10, v12, v8
+; GFX11-TRUE16-NEXT:    s_denorm_mode 12
+; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v8, v8, v11, v12
+; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX11-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v6.l, v4.l
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v10, v8
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v7, v6, v10
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v9, v7, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v7, 11
+; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB9_13
+; GFX11-TRUE16-NEXT:  ; %bb.14: ; %Flow
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, s2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v7, v10
+; GFX11-TRUE16-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v7, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v8, v7, v8
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v8, v8
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.h, -v0.h, v6.l, v4.l
-; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v0, v0.l, v0.h
+; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v6, v7, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v6, v5
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.l, v3.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v5.l, v5
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v5, v6
+; GFX11-TRUE16-NEXT:  .LBB9_16: ; %Flow54
+; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
+; GFX11-TRUE16-NEXT:    s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v2.l, s2
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v3.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, 0x7e00, v7.l, s2
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
 ; GFX11-TRUE16-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX11-TRUE16-NEXT:    s_endpgm
 ;
@@ -2648,123 +6002,451 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX11-FAKE16-NEXT:    s_clause 0x1
 ; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-FAKE16-NEXT:    s_clause 0x1
-; GFX11-FAKE16-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX11-FAKE16-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
+; GFX11-FAKE16-NEXT:    global_load_b32 v0, v1, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_b32 v1, v1, s[4:5] offset:16
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v4, |v0|
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v2
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v3, |v1|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v4, v3
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB9_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, 0, v0
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v4, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v0, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB9_3
+; GFX11-FAKE16-NEXT:    s_branch .LBB9_8
+; GFX11-FAKE16-NEXT:  .LBB9_2:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX11-FAKE16-NEXT:  .LBB9_3: ; %frem.compute
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, v4
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v6, v3
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, v3
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v3, v6, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v5
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v4
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v5, -v2, v3, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v5, v4
-; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX11-FAKE16-NEXT:    s_denorm_mode 12
+; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX11-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-FAKE16-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v4, v3, v7
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB9_5
+; GFX11-FAKE16-NEXT:  ; %bb.6: ; %Flow55
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, s2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX11-FAKE16-NEXT:  .LBB9_7: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v4, -v5, v3, v4
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
 ; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v0
+; GFX11-FAKE16-NEXT:  .LBB9_8:
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v4
-; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v1
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v8, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-FAKE16-NEXT:    v_fma_f16 v3, -v3, v2, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v7, |v3|
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v5, |v4|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v7, v5
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB9_10
+; GFX11-FAKE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v6, 0x7fff, 0, v3
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v7, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v3, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB9_11
+; GFX11-FAKE16-NEXT:    s_branch .LBB9_16
+; GFX11-FAKE16-NEXT:  .LBB9_10:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr6
+; GFX11-FAKE16-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v6, v7
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v6, 11
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v6, v5
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v6, v6, 1
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v5
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -1, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v10, null, v6, v6, 1.0
+; GFX11-FAKE16-NEXT:    v_not_b32_e32 v9, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, v9, v8
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
+; GFX11-FAKE16-NEXT:    s_denorm_mode 15
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v11
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v12, v8, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v13, -v10, v12, v8
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v12, v13, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v8, -v10, v12, v8
+; GFX11-FAKE16-NEXT:    s_denorm_mode 12
+; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v8, v8, v11, v12
+; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX11-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-FAKE16-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v7
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v10, v8
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v7, v6, v10
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, v7, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v7, 11
+; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB9_13
+; GFX11-FAKE16-NEXT:  ; %bb.14: ; %Flow
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, s2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v7, v10
+; GFX11-FAKE16-NEXT:  .LBB9_15: ; %frem.loop_exit28
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v5, v8, v7
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v1, -v2, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v9, -10, v9
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v7, v9
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v1, v1, v7
-; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v8, v7, v8
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v8, v8
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v5
-; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v6, v7, v6
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v1, v1, v6, v4
-; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v6, v5
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v1, v6, v4
-; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v3, v1
-; GFX11-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v6, 0x7fff, v5, v3
+; GFX11-FAKE16-NEXT:  .LBB9_16: ; %Flow54
+; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v1, 0
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v3|
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v6, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT:    global_store_b32 v1, v0, s[0:1]
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1150-TRUE16-LABEL: frem_v2f16:
 ; GFX1150-TRUE16:       ; %bb.0:
 ; GFX1150-TRUE16-NEXT:    s_clause 0x1
 ; GFX1150-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1150-TRUE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x34
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX1150-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1150-TRUE16-NEXT:    s_clause 0x1
-; GFX1150-TRUE16-NEXT:    global_load_b32 v3, v2, s[2:3]
-; GFX1150-TRUE16-NEXT:    global_load_b32 v4, v2, s[4:5] offset:16
+; GFX1150-TRUE16-NEXT:    global_load_b32 v1, v0, s[2:3]
+; GFX1150-TRUE16-NEXT:    global_load_b32 v0, v0, s[6:7] offset:16
 ; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.h
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s4, v1
 ; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.h
-; GFX1150-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s4, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_and_b32 s5, s3, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s6, s2
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s5, s5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT:    s_cmp_ngt_f32 s6, s5
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB9_2
+; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s4
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s6, s5
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s7, -1, 0
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v5, -v4, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v0, v5, v1
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, s4, v0.l, s7
+; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB9_3
+; GFX1150-TRUE16-NEXT:    s_branch .LBB9_8
+; GFX1150-TRUE16-NEXT:  .LBB9_2:
+; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1150-TRUE16-NEXT:  .LBB9_3: ; %frem.compute
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s6
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s6, v3
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v5, -v4, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v1, v5, v1
-; GFX1150-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v6.l, v1.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.l
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX1150-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT:    s_sub_i32 s5, s6, s5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_add_i32 s5, s5, 11
+; GFX1150-TRUE16-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1150-TRUE16-NEXT:    s_add_i32 s5, s5, -11
+; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s5, 11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB9_5
+; GFX1150-TRUE16-NEXT:  ; %bb.6: ; %Flow55
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v4, s5
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1150-TRUE16-NEXT:  .LBB9_7: ; %frem.loop_exit
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s4
+; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fmac_f16_e32 v5.l, v0.l, v6.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.l
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1150-TRUE16-NEXT:  .LBB9_8:
+; GFX1150-TRUE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1150-TRUE16-NEXT:    s_lshr_b32 s5, s3, 16
+; GFX1150-TRUE16-NEXT:    s_and_b32 s4, s6, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_and_b32 s7, s5, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s8, s4
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s7, s7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT:    s_cmp_ngt_f32 s8, s7
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB9_10
+; GFX1150-TRUE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s6
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s8, s7
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s9, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v2, v1
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, s6, v1.l, s9
+; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB9_11
+; GFX1150-TRUE16-NEXT:    s_branch .LBB9_16
+; GFX1150-TRUE16-NEXT:  .LBB9_10:
+; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1150-TRUE16-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s8
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s8, v4
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v6, -v4, v0, v3 op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v0, v6, v1
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX1150-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT:    s_sub_i32 s7, s8, s7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_add_i32 s7, s7, 11
+; GFX1150-TRUE16-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1150-TRUE16-NEXT:    s_add_i32 s7, s7, -11
+; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s7, 11
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v6, -v4, v0, v3 op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v1, v6, v1
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB9_13
+; GFX1150-TRUE16-NEXT:  ; %bb.14: ; %Flow
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, s7
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1150-TRUE16-NEXT:  .LBB9_15: ; %frem.loop_exit28
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v4.l, v1.l
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, v5
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fmac_f16_e32 v3.l, v0.l, v4.l
-; GFX1150-TRUE16-NEXT:    v_pack_b32_f16 v0, v3.l, v5.l
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s6
+; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1150-TRUE16-NEXT:  .LBB9_16: ; %Flow54
+; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s3, 0
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s2, s3
+; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s5, 0
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
+; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s3, s2
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v1.l, s2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX1150-TRUE16-NEXT:    global_store_b32 v2, v0, s[0:1]
 ; GFX1150-TRUE16-NEXT:    s_endpgm
 ;
@@ -2772,127 +6454,480 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX1150-FAKE16:       ; %bb.0:
 ; GFX1150-FAKE16-NEXT:    s_clause 0x1
 ; GFX1150-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX1150-FAKE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x34
 ; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX1150-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1150-FAKE16-NEXT:    s_clause 0x1
 ; GFX1150-FAKE16-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX1150-FAKE16-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
+; GFX1150-FAKE16-NEXT:    global_load_b32 v0, v0, s[6:7] offset:16
 ; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s4, v1
 ; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v3
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v4, v6
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX1150-FAKE16-NEXT:    s_and_b32 s2, s4, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_and_b32 s5, s3, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s6, s2
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s5, s5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-FAKE16-NEXT:    s_cmp_ngt_f32 s6, s5
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB9_2
+; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s6, s5
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, 0, s4
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB9_3
+; GFX1150-FAKE16-NEXT:    s_branch .LBB9_8
+; GFX1150-FAKE16-NEXT:  .LBB9_2:
+; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1150-FAKE16-NEXT:  .LBB9_3: ; %frem.compute
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s6
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s6, v3
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v7, -v2, v4, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v4, v7, v6
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX1150-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT:    s_sub_i32 s5, s6, s5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_add_i32 s5, s5, 11
+; GFX1150-FAKE16-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1150-FAKE16-NEXT:    s_add_i32 s5, s5, -11
+; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s5, 11
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v7, -v2, v4, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v6, v7, v6
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v6, v4
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB9_5
+; GFX1150-FAKE16-NEXT:  ; %bb.6: ; %Flow55
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, s5
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1150-FAKE16-NEXT:  .LBB9_7: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, v4
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v4, v4, v5, v3
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s4
+; GFX1150-FAKE16-NEXT:  .LBB9_8:
+; GFX1150-FAKE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1150-FAKE16-NEXT:    s_lshr_b32 s5, s3, 16
+; GFX1150-FAKE16-NEXT:    s_and_b32 s4, s6, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_and_b32 s7, s5, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s8, s4
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s7, s7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-FAKE16-NEXT:    s_cmp_ngt_f32 s8, s7
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB9_10
+; GFX1150-FAKE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s8, s7
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, 0, s6
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s6, v1, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB9_11
+; GFX1150-FAKE16-NEXT:    s_branch .LBB9_16
+; GFX1150-FAKE16-NEXT:  .LBB9_10:
+; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1150-FAKE16-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s8
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s8, v4
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v4, v4
-; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x8000, v4
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1150-FAKE16-NEXT:    v_fmac_f16_e32 v3, v4, v5
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v1
-; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v5, v5
+; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v4, v5
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v4, v1 op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v4, v6, v5
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v4, v1 op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v6, v5
-; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX1150-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT:    s_sub_i32 s7, s8, s7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_add_i32 s7, s7, 11
+; GFX1150-FAKE16-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1150-FAKE16-NEXT:    s_add_i32 s7, s7, -11
+; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s7, 11
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v5, v4
-; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB9_13
+; GFX1150-FAKE16-NEXT:  ; %bb.14: ; %Flow
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, s7
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1150-FAKE16-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, v5
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v4, v4, v2, v1
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v4, v4
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x8000, v4
-; GFX1150-FAKE16-NEXT:    v_fmac_f16_e32 v1, v4, v2
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1150-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s6
+; GFX1150-FAKE16-NEXT:  .LBB9_16: ; %Flow54
+; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s3, 0
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, s3
+; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s5, 0
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
+; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1150-FAKE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x7e00, v1
+; GFX1150-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX1150-FAKE16-NEXT:    global_store_b32 v2, v0, s[0:1]
 ; GFX1150-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1200-TRUE16-LABEL: frem_v2f16:
 ; GFX1200-TRUE16:       ; %bb.0:
 ; GFX1200-TRUE16-NEXT:    s_clause 0x1
 ; GFX1200-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1200-TRUE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x34
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
 ; GFX1200-TRUE16-NEXT:    s_clause 0x1
-; GFX1200-TRUE16-NEXT:    global_load_b32 v3, v2, s[2:3]
-; GFX1200-TRUE16-NEXT:    global_load_b32 v4, v2, s[4:5] offset:16
+; GFX1200-TRUE16-NEXT:    global_load_b32 v1, v0, s[2:3]
+; GFX1200-TRUE16-NEXT:    global_load_b32 v0, v0, s[6:7] offset:16
 ; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x1
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.h
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s4, v1
 ; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.h
-; GFX1200-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s4, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_and_b32 s5, s3, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s6, s2
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s5, s5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1200-TRUE16-NEXT:    s_cmp_ngt_f32 s6, s5
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB9_2
+; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s4
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s6, s5
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s7, -1, 0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, s4, v0.l, s7
+; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB9_3
+; GFX1200-TRUE16-NEXT:    s_branch .LBB9_8
+; GFX1200-TRUE16-NEXT:  .LBB9_2:
+; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT:  .LBB9_3: ; %frem.compute
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s6
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s6, v3
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX1200-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s5, s6, s5
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s5, s5, 11
+; GFX1200-TRUE16-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s5, s5, -11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s5, 11
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v5, -v4, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, v5, v1
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v5, -v4, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, v5, v1
-; GFX1200-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v3
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB9_5
+; GFX1200-TRUE16-NEXT:  ; %bb.6: ; %Flow55
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v4, s5
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1200-TRUE16-NEXT:  .LBB9_7: ; %frem.loop_exit
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v5.l
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s4
 ; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1200-TRUE16-NEXT:  .LBB9_8:
+; GFX1200-TRUE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1200-TRUE16-NEXT:    s_lshr_b32 s5, s3, 16
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s4, s6, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_and_b32 s7, s5, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s8, s4
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s7, s7
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-TRUE16-NEXT:    s_cmp_ngt_f32 s8, s7
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB9_10
+; GFX1200-TRUE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s6
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s8, s7
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s9, -1, 0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v2, v1
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, s6, v1.l, s9
+; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB9_11
+; GFX1200-TRUE16-NEXT:    s_branch .LBB9_16
+; GFX1200-TRUE16-NEXT:  .LBB9_10:
+; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1200-TRUE16-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s8
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s8, v4
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v6.l, v1.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.l
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX1200-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s7, s8, s7
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s7, s7, 11
+; GFX1200-TRUE16-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fmac_f16_e32 v5.l, v0.l, v6.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.l
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s7, s7, -11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s7, 11
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v6, -v4, v0, v3 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, v6, v1
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v6, -v4, v0, v3 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, v6, v1
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v3.l
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB9_13
+; GFX1200-TRUE16-NEXT:  ; %bb.14: ; %Flow
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, s7
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1200-TRUE16-NEXT:  .LBB9_15: ; %frem.loop_exit28
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v4.l, v1.l
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, v5
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fmac_f16_e32 v3.l, v0.l, v4.l
-; GFX1200-TRUE16-NEXT:    v_pack_b32_f16 v0, v3.l, v5.l
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s6
+; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1200-TRUE16-NEXT:  .LBB9_16: ; %Flow54
+; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s3, 0
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s2, s3
+; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s5, 0
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
+; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s3, s2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v1.l, s2
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX1200-TRUE16-NEXT:    global_store_b32 v2, v0, s[0:1]
 ; GFX1200-TRUE16-NEXT:    s_endpgm
 ;
@@ -2900,63 +6935,246 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX1200-FAKE16:       ; %bb.0:
 ; GFX1200-FAKE16-NEXT:    s_clause 0x1
 ; GFX1200-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
+; GFX1200-FAKE16-NEXT:    s_load_b64 s[6:7], s[4:5], 0x34
 ; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
 ; GFX1200-FAKE16-NEXT:    s_clause 0x1
 ; GFX1200-FAKE16-NEXT:    global_load_b32 v1, v0, s[2:3]
-; GFX1200-FAKE16-NEXT:    global_load_b32 v2, v0, s[4:5] offset:16
+; GFX1200-FAKE16-NEXT:    global_load_b32 v0, v0, s[6:7] offset:16
 ; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x1
-; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s4, v1
 ; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v3
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v4, v6
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX1200-FAKE16-NEXT:    s_and_b32 s2, s4, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_and_b32 s5, s3, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s6, s2
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s5, s5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1200-FAKE16-NEXT:    s_cmp_ngt_f32 s6, s5
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB9_2
+; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s6, s5
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, 0, s4
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s4, v0, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB9_3
+; GFX1200-FAKE16-NEXT:    s_branch .LBB9_8
+; GFX1200-FAKE16-NEXT:  .LBB9_2:
+; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1200-FAKE16-NEXT:  .LBB9_3: ; %frem.compute
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s5
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s6
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s6, v3
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v7, -v2, v4, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v4, v7, v6
+; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB9_7
+; GFX1200-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s5, s6, s5
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s5, s5, 11
+; GFX1200-FAKE16-NEXT:  .LBB9_5: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s5, s5, -11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s5, 11
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v7, -v2, v4, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v6, v7, v6
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB9_5
+; GFX1200-FAKE16-NEXT:  ; %bb.6: ; %Flow55
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, s5
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT:  .LBB9_7: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, v4
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v6, v4
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v4, v4, v5, v3
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v4, v4
-; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x8000, v4
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT:    v_fmac_f16_e32 v3, v4, v5
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v4, v1
-; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v5, v5
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s4
+; GFX1200-FAKE16-NEXT:  .LBB9_8:
+; GFX1200-FAKE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1200-FAKE16-NEXT:    s_lshr_b32 s5, s3, 16
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_and_b32 s4, s6, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_and_b32 s7, s5, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s8, s4
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s7, s7
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-FAKE16-NEXT:    s_cmp_ngt_f32 s8, s7
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB9_10
+; GFX1200-FAKE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s8, s7
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, 0, s6
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s6, v1, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB9_11
+; GFX1200-FAKE16-NEXT:    s_branch .LBB9_16
+; GFX1200-FAKE16-NEXT:  .LBB9_10:
+; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1200-FAKE16-NEXT:  .LBB9_11: ; %frem.compute19
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s7
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s8
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s8, v4
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v4, v5
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v4, v1 op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v4, v6, v5
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v4, v1 op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB9_15
+; GFX1200-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s7, s8, s7
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s7, s7, 11
+; GFX1200-FAKE16-NEXT:  .LBB9_13: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s7, s7, -11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s7, 11
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v6, v5
-; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v5, v4
-; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB9_13
+; GFX1200-FAKE16-NEXT:  ; %bb.14: ; %Flow
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, s7
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1200-FAKE16-NEXT:  .LBB9_15: ; %frem.loop_exit28
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, v5
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v4, v4, v2, v1
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v4, v4
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x8000, v4
-; GFX1200-FAKE16-NEXT:    v_fmac_f16_e32 v1, v4, v2
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s6
+; GFX1200-FAKE16-NEXT:  .LBB9_16: ; %Flow54
+; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s3, 0
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s2, 0x7c00
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, s3
+; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s5, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s4, 0x7c00
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x7e00, v1
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v3
-; GFX1200-FAKE16-NEXT:    global_store_b32 v0, v1, s[0:1]
+; GFX1200-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX1200-FAKE16-NEXT:    global_store_b32 v2, v0, s[0:1]
 ; GFX1200-FAKE16-NEXT:    s_endpgm
                         ptr addrspace(1) %in2) #0 {
    %gep2 = getelementptr <2 x half>, ptr addrspace(1) %in2, i32 4
@@ -2971,207 +7189,809 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; SI-LABEL: frem_v4f16:
 ; SI:       ; %bb.0:
 ; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
-; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s0, s8
-; SI-NEXT:    s_mov_b32 s1, s9
-; SI-NEXT:    s_mov_b32 s8, s10
-; SI-NEXT:    s_mov_b32 s9, s11
-; SI-NEXT:    s_mov_b32 s10, s2
-; SI-NEXT:    s_mov_b32 s11, s3
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_mov_b32 s7, s3
-; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; SI-NEXT:    s_mov_b32 s4, s10
+; SI-NEXT:    s_mov_b32 s5, s11
+; SI-NEXT:    s_mov_b32 s2, s6
+; SI-NEXT:    s_mov_b32 s3, s7
+; SI-NEXT:    buffer_load_dwordx2 v[3:4], off, s[4:7], 0
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_cvt_f32_f16_e32 v2, v0
-; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT:    v_cvt_f32_f16_e32 v3, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v2, v4
+; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v4
+; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
 ; SI-NEXT:    v_cvt_f32_f16_e32 v4, v1
-; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
-; SI-NEXT:    v_cvt_f32_f16_e32 v5, v0
-; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0 offset:32
+; SI-NEXT:    v_cvt_f32_f16_e32 v6, v3
+; SI-NEXT:    buffer_load_dwordx2 v[7:8], off, s[0:3], 0 offset:32
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_cvt_f32_f16_e32 v6, v0
-; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT:    v_cvt_f32_f16_e32 v7, v1
-; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v8
+; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
 ; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT:    v_div_scale_f32 v8, vcc, v5, v1, v5
-; SI-NEXT:    v_div_scale_f32 v9, s[4:5], v1, v1, v5
-; SI-NEXT:    v_rcp_f32_e32 v10, v9
+; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v7
+; SI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_and_b32_e32 v9, 0x7fffffff, v6
+; SI-NEXT:    v_and_b32_e32 v10, 0x7fffffff, v7
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v6|, |v7|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    v_cvt_f16_f32_e32 v8, v6
+; SI-NEXT:    s_cbranch_vccz .LBB10_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    v_bfi_b32 v11, s0, 0, v6
+; SI-NEXT:    v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v9, v10
+; SI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB10_3
+; SI-NEXT:    s_branch .LBB10_8
+; SI-NEXT:  .LBB10_2:
+; SI-NEXT:    ; implicit-def: $vgpr8
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB10_3: ; %frem.compute
+; SI-NEXT:    s_mov_b32 s3, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v9|, s3
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v9
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v8
+; SI-NEXT:    s_cselect_b32 s2, s0, 0
+; SI-NEXT:    v_frexp_mant_f32_e32 v8, v9
+; SI-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v9, v8, 11
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v10|, s3
+; SI-NEXT:    v_frexp_mant_f32_e32 v8, v10
+; SI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v10
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v10
+; SI-NEXT:    s_cselect_b32 s3, s0, 0
+; SI-NEXT:    s_add_i32 s0, s3, -1
+; SI-NEXT:    v_ldexp_f32_e64 v8, v8, 1
+; SI-NEXT:    s_not_b32 s1, s0
+; SI-NEXT:    s_add_i32 s1, s1, s2
+; SI-NEXT:    v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
+; SI-NEXT:    v_div_scale_f32 v11, s[4:5], v8, v8, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v12, v11
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
-; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
-; SI-NEXT:    v_mul_f32_e32 v11, v8, v10
-; SI-NEXT:    v_fma_f32 v12, -v9, v11, v8
-; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
-; SI-NEXT:    v_fma_f32 v8, -v9, v11, v8
+; SI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; SI-NEXT:    v_fma_f32 v12, v13, v12, v12
+; SI-NEXT:    v_mul_f32_e32 v13, v10, v12
+; SI-NEXT:    v_fma_f32 v14, -v11, v13, v10
+; SI-NEXT:    v_fma_f32 v13, v14, v12, v13
+; SI-NEXT:    v_fma_f32 v10, -v11, v13, v10
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
-; SI-NEXT:    v_div_fixup_f32 v8, v8, v1, v5
-; SI-NEXT:    v_trunc_f32_e32 v8, v8
-; SI-NEXT:    v_fma_f32 v1, -v8, v1, v5
-; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
-; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT:    v_div_scale_f32 v5, vcc, v4, v7, v4
-; SI-NEXT:    v_div_scale_f32 v8, s[4:5], v7, v7, v4
-; SI-NEXT:    v_rcp_f32_e32 v9, v8
+; SI-NEXT:    v_div_fmas_f32 v10, v10, v12, v13
+; SI-NEXT:    v_div_fixup_f32 v10, v10, v8, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s1, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB10_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s1, s2, s3
+; SI-NEXT:    s_add_i32 s1, s1, 11
+; SI-NEXT:  .LBB10_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v11, v9
+; SI-NEXT:    v_mul_f32_e32 v9, v11, v10
+; SI-NEXT:    v_rndne_f32_e32 v9, v9
+; SI-NEXT:    v_fma_f32 v9, -v9, v8, v11
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
+; SI-NEXT:    v_add_f32_e32 v12, v9, v8
+; SI-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, 11
+; SI-NEXT:    s_add_i32 s1, s1, -11
+; SI-NEXT:    s_cmp_gt_i32 s1, 11
+; SI-NEXT:    s_cbranch_scc1 .LBB10_5
+; SI-NEXT:  ; %bb.6: ; %Flow133
+; SI-NEXT:    v_mov_b32_e32 v9, v11
+; SI-NEXT:  .LBB10_7: ; %frem.loop_exit
+; SI-NEXT:    s_add_i32 s1, s1, -10
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, s1
+; SI-NEXT:    v_mul_f32_e32 v10, v9, v10
+; SI-NEXT:    v_rndne_f32_e32 v10, v10
+; SI-NEXT:    v_fma_f32 v9, -v10, v8, v9
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
+; SI-NEXT:    v_add_f32_e32 v8, v9, v8
+; SI-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v8, v8, s0
+; SI-NEXT:    v_cvt_f16_f32_e32 v8, v8
+; SI-NEXT:    v_cvt_f32_f16_e32 v8, v8
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v8, s0, v8, v6
+; SI-NEXT:  .LBB10_8:
+; SI-NEXT:    v_cvt_f16_f32_e32 v9, v4
+; SI-NEXT:    v_cvt_f16_f32_e32 v11, v5
+; SI-NEXT:    v_cvt_f32_f16_e64 v10, |v9|
+; SI-NEXT:    v_cvt_f32_f16_e64 v11, |v11|
+; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v10, v11
+; SI-NEXT:    s_cbranch_vccz .LBB10_10
+; SI-NEXT:  ; %bb.9: ; %frem.else20
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v12, s0, 0, v4
+; SI-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v10, v11
+; SI-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB10_11
+; SI-NEXT:    s_branch .LBB10_16
+; SI-NEXT:  .LBB10_10:
+; SI-NEXT:    ; implicit-def: $vgpr9
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB10_11: ; %frem.compute19
+; SI-NEXT:    s_mov_b32 s3, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v10|, s3
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v10
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v9
+; SI-NEXT:    s_cselect_b32 s2, s0, 0
+; SI-NEXT:    v_frexp_mant_f32_e32 v9, v10
+; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v10, v9, 11
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v11|, s3
+; SI-NEXT:    v_frexp_mant_f32_e32 v9, v11
+; SI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v11
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v11
+; SI-NEXT:    s_cselect_b32 s3, s0, 0
+; SI-NEXT:    s_add_i32 s0, s3, -1
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, 1
+; SI-NEXT:    s_not_b32 s1, s0
+; SI-NEXT:    s_add_i32 s1, s1, s2
+; SI-NEXT:    v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
+; SI-NEXT:    v_div_scale_f32 v12, s[4:5], v9, v9, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v13, v12
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
-; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
-; SI-NEXT:    v_mul_f32_e32 v10, v5, v9
-; SI-NEXT:    v_fma_f32 v11, -v8, v10, v5
-; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
-; SI-NEXT:    v_fma_f32 v5, -v8, v10, v5
+; SI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; SI-NEXT:    v_fma_f32 v13, v14, v13, v13
+; SI-NEXT:    v_mul_f32_e32 v14, v11, v13
+; SI-NEXT:    v_fma_f32 v15, -v12, v14, v11
+; SI-NEXT:    v_fma_f32 v14, v15, v13, v14
+; SI-NEXT:    v_fma_f32 v11, -v12, v14, v11
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v5, v5, v9, v10
-; SI-NEXT:    v_div_fixup_f32 v5, v5, v7, v4
-; SI-NEXT:    v_trunc_f32_e32 v5, v5
-; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
-; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; SI-NEXT:    v_or_b32_e32 v1, v4, v1
-; SI-NEXT:    v_div_scale_f32 v4, vcc, v3, v0, v3
-; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v0, v0, v3
-; SI-NEXT:    v_rcp_f32_e32 v7, v5
+; SI-NEXT:    v_div_fmas_f32 v11, v11, v13, v14
+; SI-NEXT:    v_div_fixup_f32 v11, v11, v9, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s1, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB10_15
+; SI-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; SI-NEXT:    s_sub_i32 s1, s2, s3
+; SI-NEXT:    s_add_i32 s1, s1, 11
+; SI-NEXT:  .LBB10_13: ; %frem.loop_body27
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v12, v10
+; SI-NEXT:    v_mul_f32_e32 v10, v12, v11
+; SI-NEXT:    v_rndne_f32_e32 v10, v10
+; SI-NEXT:    v_fma_f32 v10, -v10, v9, v12
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; SI-NEXT:    v_add_f32_e32 v13, v10, v9
+; SI-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, 11
+; SI-NEXT:    s_add_i32 s1, s1, -11
+; SI-NEXT:    s_cmp_gt_i32 s1, 11
+; SI-NEXT:    s_cbranch_scc1 .LBB10_13
+; SI-NEXT:  ; %bb.14: ; %Flow129
+; SI-NEXT:    v_mov_b32_e32 v10, v12
+; SI-NEXT:  .LBB10_15: ; %frem.loop_exit28
+; SI-NEXT:    s_add_i32 s1, s1, -10
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, s1
+; SI-NEXT:    v_mul_f32_e32 v11, v10, v11
+; SI-NEXT:    v_rndne_f32_e32 v11, v11
+; SI-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; SI-NEXT:    v_add_f32_e32 v9, v10, v9
+; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, s0
+; SI-NEXT:    v_cvt_f16_f32_e32 v9, v9
+; SI-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v9, s0, v9, v4
+; SI-NEXT:  .LBB10_16:
+; SI-NEXT:    v_cvt_f16_f32_e32 v10, v2
+; SI-NEXT:    v_cvt_f16_f32_e32 v12, v3
+; SI-NEXT:    v_cvt_f32_f16_e64 v11, |v10|
+; SI-NEXT:    v_cvt_f32_f16_e64 v12, |v12|
+; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v11, v12
+; SI-NEXT:    s_cbranch_vccz .LBB10_18
+; SI-NEXT:  ; %bb.17: ; %frem.else53
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v13, s0, 0, v2
+; SI-NEXT:    v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v11, v12
+; SI-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB10_19
+; SI-NEXT:    s_branch .LBB10_24
+; SI-NEXT:  .LBB10_18:
+; SI-NEXT:    ; implicit-def: $vgpr10
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB10_19: ; %frem.compute52
+; SI-NEXT:    s_mov_b32 s3, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v11|, s3
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v11
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v10
+; SI-NEXT:    s_cselect_b32 s2, s0, 0
+; SI-NEXT:    v_frexp_mant_f32_e32 v10, v11
+; SI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v11, v10, 11
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v12|, s3
+; SI-NEXT:    v_frexp_mant_f32_e32 v10, v12
+; SI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v12, v12
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v12
+; SI-NEXT:    s_cselect_b32 s3, s0, 0
+; SI-NEXT:    s_add_i32 s0, s3, -1
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, 1
+; SI-NEXT:    s_not_b32 s1, s0
+; SI-NEXT:    s_add_i32 s1, s1, s2
+; SI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
+; SI-NEXT:    v_div_scale_f32 v13, s[4:5], v10, v10, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v14, v13
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v8, -v5, v7, 1.0
-; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
-; SI-NEXT:    v_mul_f32_e32 v8, v4, v7
-; SI-NEXT:    v_fma_f32 v9, -v5, v8, v4
-; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
-; SI-NEXT:    v_fma_f32 v4, -v5, v8, v4
+; SI-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
+; SI-NEXT:    v_fma_f32 v14, v15, v14, v14
+; SI-NEXT:    v_mul_f32_e32 v15, v12, v14
+; SI-NEXT:    v_fma_f32 v16, -v13, v15, v12
+; SI-NEXT:    v_fma_f32 v15, v16, v14, v15
+; SI-NEXT:    v_fma_f32 v12, -v13, v15, v12
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
-; SI-NEXT:    v_div_fixup_f32 v4, v4, v0, v3
-; SI-NEXT:    v_trunc_f32_e32 v4, v4
-; SI-NEXT:    v_fma_f32 v0, -v4, v0, v3
-; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT:    v_div_scale_f32 v3, vcc, v2, v6, v2
-; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v6, v6, v2
-; SI-NEXT:    v_rcp_f32_e32 v5, v4
+; SI-NEXT:    v_div_fmas_f32 v12, v12, v14, v15
+; SI-NEXT:    v_div_fixup_f32 v12, v12, v10, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s1, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB10_23
+; SI-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; SI-NEXT:    s_sub_i32 s1, s2, s3
+; SI-NEXT:    s_add_i32 s1, s1, 11
+; SI-NEXT:  .LBB10_21: ; %frem.loop_body60
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v13, v11
+; SI-NEXT:    v_mul_f32_e32 v11, v13, v12
+; SI-NEXT:    v_rndne_f32_e32 v11, v11
+; SI-NEXT:    v_fma_f32 v11, -v11, v10, v13
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; SI-NEXT:    v_add_f32_e32 v14, v11, v10
+; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, 11
+; SI-NEXT:    s_add_i32 s1, s1, -11
+; SI-NEXT:    s_cmp_gt_i32 s1, 11
+; SI-NEXT:    s_cbranch_scc1 .LBB10_21
+; SI-NEXT:  ; %bb.22: ; %Flow125
+; SI-NEXT:    v_mov_b32_e32 v11, v13
+; SI-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; SI-NEXT:    s_add_i32 s1, s1, -10
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, s1
+; SI-NEXT:    v_mul_f32_e32 v12, v11, v12
+; SI-NEXT:    v_rndne_f32_e32 v12, v12
+; SI-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; SI-NEXT:    v_add_f32_e32 v10, v11, v10
+; SI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, s0
+; SI-NEXT:    v_cvt_f16_f32_e32 v10, v10
+; SI-NEXT:    v_cvt_f32_f16_e32 v10, v10
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v10, s0, v10, v2
+; SI-NEXT:  .LBB10_24:
+; SI-NEXT:    v_cvt_f16_f32_e32 v11, v0
+; SI-NEXT:    v_cvt_f16_f32_e32 v13, v1
+; SI-NEXT:    v_cvt_f32_f16_e64 v12, |v11|
+; SI-NEXT:    v_cvt_f32_f16_e64 v13, |v13|
+; SI-NEXT:    v_cmp_ngt_f32_e32 vcc, v12, v13
+; SI-NEXT:    s_cbranch_vccz .LBB10_26
+; SI-NEXT:  ; %bb.25: ; %frem.else86
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v14, s0, 0, v0
+; SI-NEXT:    v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT:    v_cmp_eq_f32_e32 vcc, v12, v13
+; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB10_27
+; SI-NEXT:    s_branch .LBB10_32
+; SI-NEXT:  .LBB10_26:
+; SI-NEXT:    ; implicit-def: $vgpr11
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB10_27: ; %frem.compute85
+; SI-NEXT:    s_mov_b32 s3, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v12|, s3
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v12
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v11
+; SI-NEXT:    s_cselect_b32 s2, s0, 0
+; SI-NEXT:    v_frexp_mant_f32_e32 v11, v12
+; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v12, v11, 11
+; SI-NEXT:    v_cmp_lt_f32_e64 vcc, |v13|, s3
+; SI-NEXT:    v_frexp_mant_f32_e32 v11, v13
+; SI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v13
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v13
+; SI-NEXT:    s_cselect_b32 s3, s0, 0
+; SI-NEXT:    s_add_i32 s0, s3, -1
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, 1
+; SI-NEXT:    s_not_b32 s1, s0
+; SI-NEXT:    s_add_i32 s1, s1, s2
+; SI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
+; SI-NEXT:    v_div_scale_f32 v14, s[4:5], v11, v11, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v15, v14
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
-; SI-NEXT:    v_fma_f32 v5, v7, v5, v5
-; SI-NEXT:    v_mul_f32_e32 v7, v3, v5
-; SI-NEXT:    v_fma_f32 v8, -v4, v7, v3
-; SI-NEXT:    v_fma_f32 v7, v8, v5, v7
-; SI-NEXT:    v_fma_f32 v3, -v4, v7, v3
+; SI-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
+; SI-NEXT:    v_fma_f32 v15, v16, v15, v15
+; SI-NEXT:    v_mul_f32_e32 v16, v13, v15
+; SI-NEXT:    v_fma_f32 v17, -v14, v16, v13
+; SI-NEXT:    v_fma_f32 v16, v17, v15, v16
+; SI-NEXT:    v_fma_f32 v13, -v14, v16, v13
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v7
-; SI-NEXT:    v_div_fixup_f32 v3, v3, v6, v2
-; SI-NEXT:    v_trunc_f32_e32 v3, v3
-; SI-NEXT:    v_fma_f32 v2, -v3, v6, v2
+; SI-NEXT:    v_div_fmas_f32 v13, v13, v15, v16
+; SI-NEXT:    v_div_fixup_f32 v13, v13, v11, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s1, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB10_31
+; SI-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; SI-NEXT:    s_sub_i32 s1, s2, s3
+; SI-NEXT:    s_add_i32 s1, s1, 11
+; SI-NEXT:  .LBB10_29: ; %frem.loop_body93
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v14, v12
+; SI-NEXT:    v_mul_f32_e32 v12, v14, v13
+; SI-NEXT:    v_rndne_f32_e32 v12, v12
+; SI-NEXT:    v_fma_f32 v12, -v12, v11, v14
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; SI-NEXT:    v_add_f32_e32 v15, v12, v11
+; SI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v12, v12, 11
+; SI-NEXT:    s_add_i32 s1, s1, -11
+; SI-NEXT:    s_cmp_gt_i32 s1, 11
+; SI-NEXT:    s_cbranch_scc1 .LBB10_29
+; SI-NEXT:  ; %bb.30: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v12, v14
+; SI-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; SI-NEXT:    s_add_i32 s1, s1, -10
+; SI-NEXT:    v_ldexp_f32_e64 v12, v12, s1
+; SI-NEXT:    v_mul_f32_e32 v13, v12, v13
+; SI-NEXT:    v_rndne_f32_e32 v13, v13
+; SI-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; SI-NEXT:    v_add_f32_e32 v11, v12, v11
+; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, s0
+; SI-NEXT:    v_cvt_f16_f32_e32 v11, v11
+; SI-NEXT:    v_cvt_f32_f16_e32 v11, v11
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_bfi_b32 v11, s0, v11, v0
+; SI-NEXT:  .LBB10_32: ; %Flow124
+; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v7
+; SI-NEXT:    v_cvt_f16_f32_e32 v7, v8
+; SI-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; SI-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; SI-NEXT:    v_and_b32_e32 v6, 0x7fff, v6
+; SI-NEXT:    s_movk_i32 s2, 0x7c00
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v6
+; SI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_mov_b32_e32 v6, 0x7fc00000
+; SI-NEXT:    v_cndmask_b32_e32 v7, v7, v6, vcc
+; SI-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; SI-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; SI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v5
+; SI-NEXT:    v_cvt_f16_f32_e32 v5, v9
+; SI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT:    v_and_b32_e32 v4, 0x7fff, v4
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v4
+; SI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v4, v5, v6, vcc
+; SI-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; SI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v3
+; SI-NEXT:    v_cvt_f16_f32_e32 v3, v10
+; SI-NEXT:    v_cvt_f32_f16_e32 v3, v3
 ; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT:    v_or_b32_e32 v0, v2, v0
-; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v2
+; SI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v2, v3, v6, vcc
+; SI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11
+; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v0
+; SI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v0, v1, v6, vcc
+; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT:    v_or_b32_e32 v1, v2, v0
+; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v4
+; SI-NEXT:    v_or_b32_e32 v0, v7, v0
+; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: frem_v4f16:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
-; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    s_mov_b32 s6, s2
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
+; CI-NEXT:    s_mov_b32 s7, 0xf000
+; CI-NEXT:    s_mov_b32 s6, -1
+; CI-NEXT:    s_mov_b32 s2, s6
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_mov_b32 s0, s8
-; CI-NEXT:    s_mov_b32 s1, s9
-; CI-NEXT:    s_mov_b32 s8, s10
-; CI-NEXT:    s_mov_b32 s9, s11
-; CI-NEXT:    s_mov_b32 s10, s2
-; CI-NEXT:    s_mov_b32 s11, s3
-; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; CI-NEXT:    s_mov_b32 s7, s3
+; CI-NEXT:    s_mov_b32 s4, s10
+; CI-NEXT:    s_mov_b32 s5, s11
+; CI-NEXT:    buffer_load_dwordx2 v[3:4], off, s[4:7], 0
+; CI-NEXT:    s_mov_b32 s3, s7
+; CI-NEXT:    buffer_load_dwordx2 v[7:8], off, s[0:3], 0 offset:32
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    s_waitcnt vmcnt(1)
+; CI-NEXT:    v_cvt_f32_f16_e32 v6, v3
+; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v3
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_cvt_f32_f16_e32 v2, v0
-; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; CI-NEXT:    v_cvt_f32_f16_e32 v3, v0
-; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v1
+; CI-NEXT:    v_lshrrev_b32_e32 v5, 16, v7
+; CI-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; CI-NEXT:    v_cvt_f32_f16_e32 v2, v4
+; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v4
 ; CI-NEXT:    v_cvt_f32_f16_e32 v4, v1
-; CI-NEXT:    v_cvt_f32_f16_e32 v5, v0
-; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0 offset:32
-; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_cvt_f32_f16_e32 v7, v1
-; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT:    v_cvt_f32_f16_e32 v6, v0
-; CI-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; CI-NEXT:    v_lshrrev_b32_e32 v1, 16, v8
 ; CI-NEXT:    v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v1, v1, v5
-; CI-NEXT:    v_div_scale_f32 v8, vcc, v5, v1, v5
-; CI-NEXT:    v_rcp_f32_e32 v10, v9
+; CI-NEXT:    v_cvt_f32_f16_e32 v3, v8
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; CI-NEXT:    v_cvt_f16_f32_e32 v8, v6
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v6|, |v7|
+; CI-NEXT:    v_and_b32_e32 v10, 0x7fffffff, v6
+; CI-NEXT:    v_and_b32_e32 v9, 0x7fffffff, v7
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB10_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    v_cvt_f32_f16_e32 v8, v8
+; CI-NEXT:    v_bfi_b32 v11, s0, 0, v6
+; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v10, v9
+; CI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
+; CI-NEXT:    s_cbranch_execz .LBB10_3
+; CI-NEXT:    s_branch .LBB10_8
+; CI-NEXT:  .LBB10_2:
+; CI-NEXT:    ; implicit-def: $vgpr8
+; CI-NEXT:  .LBB10_3: ; %frem.compute
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v10
+; CI-NEXT:    v_frexp_mant_f32_e32 v8, v10
+; CI-NEXT:    v_frexp_mant_f32_e32 v10, v9
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v9
+; CI-NEXT:    v_ldexp_f32_e64 v9, v10, 1
+; CI-NEXT:    v_div_scale_f32 v15, s[0:1], v9, v9, 1.0
+; CI-NEXT:    v_ldexp_f32_e64 v11, v8, 11
+; CI-NEXT:    v_add_i32_e32 v8, vcc, -1, v14
+; CI-NEXT:    v_not_b32_e32 v10, v8
+; CI-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v16, v15
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
-; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
-; CI-NEXT:    v_mul_f32_e32 v11, v8, v10
-; CI-NEXT:    v_fma_f32 v12, -v9, v11, v8
-; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
-; CI-NEXT:    v_fma_f32 v8, -v9, v11, v8
+; CI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
+; CI-NEXT:    v_fma_f32 v16, v17, v16, v16
+; CI-NEXT:    v_mul_f32_e32 v17, v12, v16
+; CI-NEXT:    v_fma_f32 v18, -v15, v17, v12
+; CI-NEXT:    v_fma_f32 v17, v18, v16, v17
+; CI-NEXT:    v_fma_f32 v12, -v15, v17, v12
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
-; CI-NEXT:    v_div_fixup_f32 v8, v8, v1, v5
-; CI-NEXT:    v_trunc_f32_e32 v8, v8
-; CI-NEXT:    v_fma_f32 v1, -v8, v1, v5
-; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v7, v7, v4
-; CI-NEXT:    v_div_scale_f32 v5, vcc, v4, v7, v4
-; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
-; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; CI-NEXT:    v_rcp_f32_e32 v9, v8
+; CI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v10
+; CI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB10_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v10, vcc, v13, v14
+; CI-NEXT:    v_add_i32_e32 v10, vcc, 11, v10
+; CI-NEXT:  .LBB10_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v13, v11
+; CI-NEXT:    v_mul_f32_e32 v11, v13, v12
+; CI-NEXT:    v_rndne_f32_e32 v11, v11
+; CI-NEXT:    v_fma_f32 v11, -v11, v9, v13
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; CI-NEXT:    v_add_f32_e32 v14, v11, v9
+; CI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; CI-NEXT:    v_add_i32_e32 v10, vcc, -11, v10
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v10
+; CI-NEXT:    v_ldexp_f32_e64 v11, v11, 11
+; CI-NEXT:    s_cbranch_vccnz .LBB10_5
+; CI-NEXT:  ; %bb.6: ; %Flow133
+; CI-NEXT:    v_mov_b32_e32 v11, v13
+; CI-NEXT:  .LBB10_7: ; %frem.loop_exit
+; CI-NEXT:    v_add_i32_e32 v10, vcc, -10, v10
+; CI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
+; CI-NEXT:    v_mul_f32_e32 v11, v10, v12
+; CI-NEXT:    v_rndne_f32_e32 v11, v11
+; CI-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; CI-NEXT:    v_add_f32_e32 v9, v10, v9
+; CI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v8, v9, v8
+; CI-NEXT:    v_cvt_f16_f32_e32 v8, v8
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_cvt_f32_f16_e32 v8, v8
+; CI-NEXT:    v_bfi_b32 v8, s0, v8, v6
+; CI-NEXT:  .LBB10_8:
+; CI-NEXT:    v_cvt_f16_f32_e32 v9, v4
+; CI-NEXT:    v_cvt_f16_f32_e32 v10, v5
+; CI-NEXT:    v_cvt_f32_f16_e64 v11, |v9|
+; CI-NEXT:    v_cvt_f32_f16_e64 v10, |v10|
+; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v11, v10
+; CI-NEXT:    s_cbranch_vccz .LBB10_10
+; CI-NEXT:  ; %bb.9: ; %frem.else20
+; CI-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_bfi_b32 v12, s0, 0, v4
+; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v11, v10
+; CI-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
+; CI-NEXT:    s_cbranch_execz .LBB10_11
+; CI-NEXT:    s_branch .LBB10_16
+; CI-NEXT:  .LBB10_10:
+; CI-NEXT:    ; implicit-def: $vgpr9
+; CI-NEXT:  .LBB10_11: ; %frem.compute19
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v11
+; CI-NEXT:    v_frexp_mant_f32_e32 v9, v11
+; CI-NEXT:    v_frexp_mant_f32_e32 v11, v10
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v10
+; CI-NEXT:    v_ldexp_f32_e64 v10, v11, 1
+; CI-NEXT:    v_div_scale_f32 v16, s[0:1], v10, v10, 1.0
+; CI-NEXT:    v_ldexp_f32_e64 v12, v9, 11
+; CI-NEXT:    v_add_i32_e32 v9, vcc, -1, v15
+; CI-NEXT:    v_not_b32_e32 v11, v9
+; CI-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
+; CI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v17, v16
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
-; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
-; CI-NEXT:    v_mul_f32_e32 v10, v5, v9
-; CI-NEXT:    v_fma_f32 v11, -v8, v10, v5
-; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
-; CI-NEXT:    v_fma_f32 v5, -v8, v10, v5
+; CI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
+; CI-NEXT:    v_fma_f32 v17, v18, v17, v17
+; CI-NEXT:    v_mul_f32_e32 v18, v13, v17
+; CI-NEXT:    v_fma_f32 v19, -v16, v18, v13
+; CI-NEXT:    v_fma_f32 v18, v19, v17, v18
+; CI-NEXT:    v_fma_f32 v13, -v16, v18, v13
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v5, v5, v9, v10
-; CI-NEXT:    v_div_fixup_f32 v5, v5, v7, v4
-; CI-NEXT:    v_trunc_f32_e32 v5, v5
-; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
-; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v0, v0, v3
-; CI-NEXT:    v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT:    v_or_b32_e32 v1, v4, v1
-; CI-NEXT:    v_div_scale_f32 v4, vcc, v3, v0, v3
-; CI-NEXT:    v_rcp_f32_e32 v7, v5
+; CI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v11
+; CI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB10_15
+; CI-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; CI-NEXT:    v_sub_i32_e32 v11, vcc, v14, v15
+; CI-NEXT:    v_add_i32_e32 v11, vcc, 11, v11
+; CI-NEXT:  .LBB10_13: ; %frem.loop_body27
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v14, v12
+; CI-NEXT:    v_mul_f32_e32 v12, v14, v13
+; CI-NEXT:    v_rndne_f32_e32 v12, v12
+; CI-NEXT:    v_fma_f32 v12, -v12, v10, v14
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; CI-NEXT:    v_add_f32_e32 v15, v12, v10
+; CI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
+; CI-NEXT:    v_add_i32_e32 v11, vcc, -11, v11
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v11
+; CI-NEXT:    v_ldexp_f32_e64 v12, v12, 11
+; CI-NEXT:    s_cbranch_vccnz .LBB10_13
+; CI-NEXT:  ; %bb.14: ; %Flow129
+; CI-NEXT:    v_mov_b32_e32 v12, v14
+; CI-NEXT:  .LBB10_15: ; %frem.loop_exit28
+; CI-NEXT:    v_add_i32_e32 v11, vcc, -10, v11
+; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
+; CI-NEXT:    v_mul_f32_e32 v12, v11, v13
+; CI-NEXT:    v_rndne_f32_e32 v12, v12
+; CI-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; CI-NEXT:    v_add_f32_e32 v10, v11, v10
+; CI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v9, v10, v9
+; CI-NEXT:    v_cvt_f16_f32_e32 v9, v9
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_cvt_f32_f16_e32 v9, v9
+; CI-NEXT:    v_bfi_b32 v9, s0, v9, v4
+; CI-NEXT:  .LBB10_16:
+; CI-NEXT:    v_cvt_f16_f32_e32 v10, v2
+; CI-NEXT:    v_cvt_f16_f32_e32 v11, v3
+; CI-NEXT:    v_cvt_f32_f16_e64 v12, |v10|
+; CI-NEXT:    v_cvt_f32_f16_e64 v11, |v11|
+; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v12, v11
+; CI-NEXT:    s_cbranch_vccz .LBB10_18
+; CI-NEXT:  ; %bb.17: ; %frem.else53
+; CI-NEXT:    v_cvt_f32_f16_e32 v10, v10
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_bfi_b32 v13, s0, 0, v2
+; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v12, v11
+; CI-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
+; CI-NEXT:    s_cbranch_execz .LBB10_19
+; CI-NEXT:    s_branch .LBB10_24
+; CI-NEXT:  .LBB10_18:
+; CI-NEXT:    ; implicit-def: $vgpr10
+; CI-NEXT:  .LBB10_19: ; %frem.compute52
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v12
+; CI-NEXT:    v_frexp_mant_f32_e32 v10, v12
+; CI-NEXT:    v_frexp_mant_f32_e32 v12, v11
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v11
+; CI-NEXT:    v_ldexp_f32_e64 v11, v12, 1
+; CI-NEXT:    v_div_scale_f32 v17, s[0:1], v11, v11, 1.0
+; CI-NEXT:    v_ldexp_f32_e64 v13, v10, 11
+; CI-NEXT:    v_add_i32_e32 v10, vcc, -1, v16
+; CI-NEXT:    v_not_b32_e32 v12, v10
+; CI-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v18, v17
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v8, -v5, v7, 1.0
-; CI-NEXT:    v_fma_f32 v7, v8, v7, v7
-; CI-NEXT:    v_mul_f32_e32 v8, v4, v7
-; CI-NEXT:    v_fma_f32 v9, -v5, v8, v4
-; CI-NEXT:    v_fma_f32 v8, v9, v7, v8
-; CI-NEXT:    v_fma_f32 v4, -v5, v8, v4
+; CI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
+; CI-NEXT:    v_fma_f32 v18, v19, v18, v18
+; CI-NEXT:    v_mul_f32_e32 v19, v14, v18
+; CI-NEXT:    v_fma_f32 v20, -v17, v19, v14
+; CI-NEXT:    v_fma_f32 v19, v20, v18, v19
+; CI-NEXT:    v_fma_f32 v14, -v17, v19, v14
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
-; CI-NEXT:    v_div_fixup_f32 v4, v4, v0, v3
-; CI-NEXT:    v_trunc_f32_e32 v4, v4
-; CI-NEXT:    v_fma_f32 v0, -v4, v0, v3
-; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v6, v6, v2
-; CI-NEXT:    v_div_scale_f32 v3, vcc, v2, v6, v2
-; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
-; CI-NEXT:    v_rcp_f32_e32 v5, v4
+; CI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v12
+; CI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB10_23
+; CI-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; CI-NEXT:    v_sub_i32_e32 v12, vcc, v15, v16
+; CI-NEXT:    v_add_i32_e32 v12, vcc, 11, v12
+; CI-NEXT:  .LBB10_21: ; %frem.loop_body60
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v15, v13
+; CI-NEXT:    v_mul_f32_e32 v13, v15, v14
+; CI-NEXT:    v_rndne_f32_e32 v13, v13
+; CI-NEXT:    v_fma_f32 v13, -v13, v11, v15
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; CI-NEXT:    v_add_f32_e32 v16, v13, v11
+; CI-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
+; CI-NEXT:    v_add_i32_e32 v12, vcc, -11, v12
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v12
+; CI-NEXT:    v_ldexp_f32_e64 v13, v13, 11
+; CI-NEXT:    s_cbranch_vccnz .LBB10_21
+; CI-NEXT:  ; %bb.22: ; %Flow125
+; CI-NEXT:    v_mov_b32_e32 v13, v15
+; CI-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; CI-NEXT:    v_add_i32_e32 v12, vcc, -10, v12
+; CI-NEXT:    v_ldexp_f32_e32 v12, v13, v12
+; CI-NEXT:    v_mul_f32_e32 v13, v12, v14
+; CI-NEXT:    v_rndne_f32_e32 v13, v13
+; CI-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; CI-NEXT:    v_add_f32_e32 v11, v12, v11
+; CI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
+; CI-NEXT:    v_cvt_f16_f32_e32 v10, v10
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_cvt_f32_f16_e32 v10, v10
+; CI-NEXT:    v_bfi_b32 v10, s0, v10, v2
+; CI-NEXT:  .LBB10_24:
+; CI-NEXT:    v_cvt_f16_f32_e32 v11, v0
+; CI-NEXT:    v_cvt_f16_f32_e32 v12, v1
+; CI-NEXT:    v_cvt_f32_f16_e64 v13, |v11|
+; CI-NEXT:    v_cvt_f32_f16_e64 v12, |v12|
+; CI-NEXT:    v_cmp_ngt_f32_e32 vcc, v13, v12
+; CI-NEXT:    s_cbranch_vccz .LBB10_26
+; CI-NEXT:  ; %bb.25: ; %frem.else86
+; CI-NEXT:    v_cvt_f32_f16_e32 v11, v11
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_bfi_b32 v14, s0, 0, v0
+; CI-NEXT:    v_cmp_eq_f32_e32 vcc, v13, v12
+; CI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; CI-NEXT:    s_cbranch_execz .LBB10_27
+; CI-NEXT:    s_branch .LBB10_32
+; CI-NEXT:  .LBB10_26:
+; CI-NEXT:    ; implicit-def: $vgpr11
+; CI-NEXT:  .LBB10_27: ; %frem.compute85
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v13
+; CI-NEXT:    v_frexp_mant_f32_e32 v11, v13
+; CI-NEXT:    v_frexp_mant_f32_e32 v13, v12
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v12
+; CI-NEXT:    v_ldexp_f32_e64 v12, v13, 1
+; CI-NEXT:    v_div_scale_f32 v18, s[0:1], v12, v12, 1.0
+; CI-NEXT:    v_ldexp_f32_e64 v14, v11, 11
+; CI-NEXT:    v_add_i32_e32 v11, vcc, -1, v17
+; CI-NEXT:    v_not_b32_e32 v13, v11
+; CI-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v19, v18
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
-; CI-NEXT:    v_fma_f32 v5, v7, v5, v5
-; CI-NEXT:    v_mul_f32_e32 v7, v3, v5
-; CI-NEXT:    v_fma_f32 v8, -v4, v7, v3
-; CI-NEXT:    v_fma_f32 v7, v8, v5, v7
-; CI-NEXT:    v_fma_f32 v3, -v4, v7, v3
+; CI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
+; CI-NEXT:    v_fma_f32 v19, v20, v19, v19
+; CI-NEXT:    v_mul_f32_e32 v20, v15, v19
+; CI-NEXT:    v_fma_f32 v21, -v18, v20, v15
+; CI-NEXT:    v_fma_f32 v20, v21, v19, v20
+; CI-NEXT:    v_fma_f32 v15, -v18, v20, v15
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v7
-; CI-NEXT:    v_div_fixup_f32 v3, v3, v6, v2
-; CI-NEXT:    v_trunc_f32_e32 v3, v3
-; CI-NEXT:    v_fma_f32 v2, -v3, v6, v2
+; CI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v13
+; CI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB10_31
+; CI-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; CI-NEXT:    v_sub_i32_e32 v13, vcc, v16, v17
+; CI-NEXT:    v_add_i32_e32 v13, vcc, 11, v13
+; CI-NEXT:  .LBB10_29: ; %frem.loop_body93
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v16, v14
+; CI-NEXT:    v_mul_f32_e32 v14, v16, v15
+; CI-NEXT:    v_rndne_f32_e32 v14, v14
+; CI-NEXT:    v_fma_f32 v14, -v14, v12, v16
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
+; CI-NEXT:    v_add_f32_e32 v17, v14, v12
+; CI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
+; CI-NEXT:    v_add_i32_e32 v13, vcc, -11, v13
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v13
+; CI-NEXT:    v_ldexp_f32_e64 v14, v14, 11
+; CI-NEXT:    s_cbranch_vccnz .LBB10_29
+; CI-NEXT:  ; %bb.30: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v14, v16
+; CI-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; CI-NEXT:    v_add_i32_e32 v13, vcc, -10, v13
+; CI-NEXT:    v_ldexp_f32_e32 v13, v14, v13
+; CI-NEXT:    v_mul_f32_e32 v14, v13, v15
+; CI-NEXT:    v_rndne_f32_e32 v14, v14
+; CI-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; CI-NEXT:    v_add_f32_e32 v12, v13, v12
+; CI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
+; CI-NEXT:    v_cvt_f16_f32_e32 v11, v11
+; CI-NEXT:    s_brev_b32 s0, -2
+; CI-NEXT:    v_cvt_f32_f16_e32 v11, v11
+; CI-NEXT:    v_bfi_b32 v11, s0, v11, v0
+; CI-NEXT:  .LBB10_32: ; %Flow124
+; CI-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; CI-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; CI-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; CI-NEXT:    s_movk_i32 s2, 0x7c00
+; CI-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; CI-NEXT:    v_cvt_f32_f16_e32 v5, v5
+; CI-NEXT:    v_and_b32_e32 v6, 0x7fff, v6
+; CI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v6
+; CI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v7
+; CI-NEXT:    v_cvt_f16_f32_e32 v7, v8
+; CI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; CI-NEXT:    v_mov_b32_e32 v6, 0x7fc00000
+; CI-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT:    v_cvt_f32_f16_e32 v7, v7
+; CI-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; CI-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v6, vcc
+; CI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v5
+; CI-NEXT:    v_cvt_f16_f32_e32 v5, v9
+; CI-NEXT:    v_and_b32_e32 v4, 0x7fff, v4
+; CI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v4
+; CI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; CI-NEXT:    v_cvt_f32_f16_e32 v5, v5
 ; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT:    v_or_b32_e32 v0, v2, v0
-; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT:    v_cndmask_b32_e32 v4, v5, v6, vcc
+; CI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v3
+; CI-NEXT:    v_cvt_f16_f32_e32 v3, v10
+; CI-NEXT:    v_and_b32_e32 v2, 0x7fff, v2
+; CI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v2
+; CI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; CI-NEXT:    v_cvt_f32_f16_e32 v3, v3
+; CI-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
+; CI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s2, v0
+; CI-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; CI-NEXT:    v_cndmask_b32_e32 v2, v3, v6, vcc
+; CI-NEXT:    v_cmp_nlg_f32_e32 vcc, 0, v1
+; CI-NEXT:    v_cvt_f16_f32_e32 v1, v11
+; CI-NEXT:    s_or_b64 vcc, s[0:1], vcc
+; CI-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; CI-NEXT:    v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT:    s_mov_b32 s11, 0xf000
+; CI-NEXT:    s_mov_b32 s10, -1
+; CI-NEXT:    v_cndmask_b32_e32 v0, v1, v6, vcc
+; CI-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
+; CI-NEXT:    v_or_b32_e32 v1, v2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v0, 16, v4
+; CI-NEXT:    v_or_b32_e32 v0, v7, v0
+; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: frem_v4f16:
@@ -3179,82 +7999,322 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_add_u32 s0, s4, 32
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    s_addc_u32 s1, s5, 0
-; VI-NEXT:    v_mov_b32_e32 v5, s1
-; VI-NEXT:    v_mov_b32_e32 v4, s0
-; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    s_add_u32 s2, s4, 32
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    s_addc_u32 s3, s5, 0
 ; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    v_mov_b32_e32 v3, s3
+; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
 ; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
 ; VI-NEXT:    s_waitcnt vmcnt(1)
-; VI-NEXT:    v_lshrrev_b32_e32 v8, 16, v5
-; VI-NEXT:    v_cvt_f32_f16_e32 v9, v8
+; VI-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
-; VI-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; VI-NEXT:    v_rcp_f32_e32 v10, v9
-; VI-NEXT:    v_mul_f32_e32 v11, v7, v10
-; VI-NEXT:    v_mad_f32 v12, -v9, v11, v7
-; VI-NEXT:    v_mac_f32_e32 v11, v12, v10
-; VI-NEXT:    v_mad_f32 v7, -v9, v11, v7
-; VI-NEXT:    v_mul_f32_e32 v7, v7, v10
-; VI-NEXT:    v_and_b32_e32 v7, 0xff800000, v7
-; VI-NEXT:    v_add_f32_e32 v7, v7, v11
-; VI-NEXT:    v_cvt_f16_f32_e32 v7, v7
-; VI-NEXT:    v_div_fixup_f16 v7, v7, v8, v6
-; VI-NEXT:    v_trunc_f16_e32 v7, v7
-; VI-NEXT:    v_fma_f16 v6, -v7, v8, v6
-; VI-NEXT:    v_cvt_f32_f16_e32 v8, v5
-; VI-NEXT:    v_cvt_f32_f16_e32 v7, v3
-; VI-NEXT:    v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT:    v_rcp_f32_e32 v9, v8
-; VI-NEXT:    v_mul_f32_e32 v10, v7, v9
-; VI-NEXT:    v_mad_f32 v11, -v8, v10, v7
-; VI-NEXT:    v_mac_f32_e32 v10, v11, v9
-; VI-NEXT:    v_mad_f32 v7, -v8, v10, v7
-; VI-NEXT:    v_mul_f32_e32 v7, v7, v9
-; VI-NEXT:    v_and_b32_e32 v7, 0xff800000, v7
-; VI-NEXT:    v_add_f32_e32 v7, v7, v10
+; VI-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
+; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
+; VI-NEXT:    s_cbranch_vccz .LBB10_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v4, s2, 0, v0
+; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
+; VI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
+; VI-NEXT:    s_cbranch_execz .LBB10_3
+; VI-NEXT:    s_branch .LBB10_8
+; VI-NEXT:  .LBB10_2:
+; VI-NEXT:    ; implicit-def: $vgpr4
+; VI-NEXT:  .LBB10_3: ; %frem.compute
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
+; VI-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; VI-NEXT:    v_frexp_mant_f32_e32 v6, v5
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
+; VI-NEXT:    v_ldexp_f32 v5, v6, 1
+; VI-NEXT:    v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
+; VI-NEXT:    v_ldexp_f32 v7, v4, 11
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -1, v10
+; VI-NEXT:    v_not_b32_e32 v6, v4
+; VI-NEXT:    v_add_u32_e32 v6, vcc, v6, v9
+; VI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v12, v11
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; VI-NEXT:    v_fma_f32 v12, v13, v12, v12
+; VI-NEXT:    v_mul_f32_e32 v13, v8, v12
+; VI-NEXT:    v_fma_f32 v14, -v11, v13, v8
+; VI-NEXT:    v_fma_f32 v13, v14, v12, v13
+; VI-NEXT:    v_fma_f32 v8, -v11, v13, v8
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
+; VI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB10_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v6, vcc, v9, v10
+; VI-NEXT:    v_add_u32_e32 v6, vcc, 11, v6
+; VI-NEXT:  .LBB10_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v9, v7
+; VI-NEXT:    v_mul_f32_e32 v7, v9, v8
+; VI-NEXT:    v_rndne_f32_e32 v7, v7
+; VI-NEXT:    v_fma_f32 v7, -v7, v5, v9
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; VI-NEXT:    v_add_f32_e32 v10, v7, v5
+; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
+; VI-NEXT:    v_add_u32_e32 v6, vcc, -11, v6
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
+; VI-NEXT:    v_ldexp_f32 v7, v7, 11
+; VI-NEXT:    s_cbranch_vccnz .LBB10_5
+; VI-NEXT:  ; %bb.6: ; %Flow133
+; VI-NEXT:    v_mov_b32_e32 v7, v9
+; VI-NEXT:  .LBB10_7: ; %frem.loop_exit
+; VI-NEXT:    v_add_u32_e32 v6, vcc, -10, v6
+; VI-NEXT:    v_ldexp_f32 v6, v7, v6
+; VI-NEXT:    v_mul_f32_e32 v7, v6, v8
+; VI-NEXT:    v_rndne_f32_e32 v7, v7
+; VI-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; VI-NEXT:    v_add_f32_e32 v5, v6, v5
+; VI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; VI-NEXT:    v_ldexp_f32 v4, v5, v4
+; VI-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v4, s2, v4, v0
+; VI-NEXT:  .LBB10_8:
+; VI-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; VI-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
+; VI-NEXT:    v_cvt_f32_f16_e64 v9, |v5|
+; VI-NEXT:    v_cvt_f32_f16_e64 v8, |v6|
+; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v9, v8
+; VI-NEXT:    s_cbranch_vccz .LBB10_10
+; VI-NEXT:  ; %bb.9: ; %frem.else20
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v7, s2, 0, v5
+; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v9, v8
+; VI-NEXT:    v_cndmask_b32_e32 v7, v5, v7, vcc
+; VI-NEXT:    s_cbranch_execz .LBB10_11
+; VI-NEXT:    s_branch .LBB10_16
+; VI-NEXT:  .LBB10_10:
+; VI-NEXT:    ; implicit-def: $vgpr7
+; VI-NEXT:  .LBB10_11: ; %frem.compute19
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
+; VI-NEXT:    v_frexp_mant_f32_e32 v7, v9
+; VI-NEXT:    v_frexp_mant_f32_e32 v9, v8
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
+; VI-NEXT:    v_ldexp_f32 v8, v9, 1
+; VI-NEXT:    v_div_scale_f32 v14, s[2:3], v8, v8, 1.0
+; VI-NEXT:    v_ldexp_f32 v10, v7, 11
+; VI-NEXT:    v_add_u32_e32 v7, vcc, -1, v13
+; VI-NEXT:    v_not_b32_e32 v9, v7
+; VI-NEXT:    v_add_u32_e32 v9, vcc, v9, v12
+; VI-NEXT:    v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v15, v14
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
+; VI-NEXT:    v_fma_f32 v15, v16, v15, v15
+; VI-NEXT:    v_mul_f32_e32 v16, v11, v15
+; VI-NEXT:    v_fma_f32 v17, -v14, v16, v11
+; VI-NEXT:    v_fma_f32 v16, v17, v15, v16
+; VI-NEXT:    v_fma_f32 v11, -v14, v16, v11
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v9
+; VI-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB10_15
+; VI-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; VI-NEXT:    v_sub_u32_e32 v9, vcc, v12, v13
+; VI-NEXT:    v_add_u32_e32 v9, vcc, 11, v9
+; VI-NEXT:  .LBB10_13: ; %frem.loop_body27
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v12, v10
+; VI-NEXT:    v_mul_f32_e32 v10, v12, v11
+; VI-NEXT:    v_rndne_f32_e32 v10, v10
+; VI-NEXT:    v_fma_f32 v10, -v10, v8, v12
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; VI-NEXT:    v_add_f32_e32 v13, v10, v8
+; VI-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
+; VI-NEXT:    v_add_u32_e32 v9, vcc, -11, v9
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v9
+; VI-NEXT:    v_ldexp_f32 v10, v10, 11
+; VI-NEXT:    s_cbranch_vccnz .LBB10_13
+; VI-NEXT:  ; %bb.14: ; %Flow129
+; VI-NEXT:    v_mov_b32_e32 v10, v12
+; VI-NEXT:  .LBB10_15: ; %frem.loop_exit28
+; VI-NEXT:    v_add_u32_e32 v9, vcc, -10, v9
+; VI-NEXT:    v_ldexp_f32 v9, v10, v9
+; VI-NEXT:    v_mul_f32_e32 v10, v9, v11
+; VI-NEXT:    v_rndne_f32_e32 v10, v10
+; VI-NEXT:    v_fma_f32 v9, -v10, v8, v9
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
+; VI-NEXT:    v_add_f32_e32 v8, v9, v8
+; VI-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; VI-NEXT:    v_ldexp_f32 v7, v8, v7
 ; VI-NEXT:    v_cvt_f16_f32_e32 v7, v7
-; VI-NEXT:    v_div_fixup_f16 v7, v7, v5, v3
-; VI-NEXT:    v_trunc_f16_e32 v7, v7
-; VI-NEXT:    v_fma_f16 v3, -v7, v5, v3
-; VI-NEXT:    v_lshrrev_b32_e32 v7, 16, v4
-; VI-NEXT:    v_cvt_f32_f16_e32 v8, v7
-; VI-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
-; VI-NEXT:    v_or_b32_e32 v3, v3, v6
-; VI-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; VI-NEXT:    v_rcp_f32_e32 v9, v8
-; VI-NEXT:    v_mul_f32_e32 v10, v6, v9
-; VI-NEXT:    v_mad_f32 v11, -v8, v10, v6
-; VI-NEXT:    v_mac_f32_e32 v10, v11, v9
-; VI-NEXT:    v_mad_f32 v6, -v8, v10, v6
-; VI-NEXT:    v_mul_f32_e32 v6, v6, v9
-; VI-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; VI-NEXT:    v_add_f32_e32 v6, v6, v10
-; VI-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; VI-NEXT:    v_div_fixup_f16 v6, v6, v7, v5
-; VI-NEXT:    v_trunc_f16_e32 v6, v6
-; VI-NEXT:    v_fma_f16 v5, -v6, v7, v5
-; VI-NEXT:    v_cvt_f32_f16_e32 v7, v4
-; VI-NEXT:    v_cvt_f32_f16_e32 v6, v2
-; VI-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT:    v_rcp_f32_e32 v8, v7
-; VI-NEXT:    v_mul_f32_e32 v9, v6, v8
-; VI-NEXT:    v_mad_f32 v10, -v7, v9, v6
-; VI-NEXT:    v_mac_f32_e32 v9, v10, v8
-; VI-NEXT:    v_mad_f32 v6, -v7, v9, v6
-; VI-NEXT:    v_mul_f32_e32 v6, v6, v8
-; VI-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; VI-NEXT:    v_add_f32_e32 v6, v6, v9
-; VI-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; VI-NEXT:    v_div_fixup_f16 v6, v6, v4, v2
-; VI-NEXT:    v_trunc_f16_e32 v6, v6
-; VI-NEXT:    v_fma_f16 v2, -v6, v4, v2
-; VI-NEXT:    v_or_b32_e32 v2, v2, v5
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v7, s2, v7, v5
+; VI-NEXT:  .LBB10_16:
+; VI-NEXT:    v_cvt_f32_f16_e64 v10, |v1|
+; VI-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
+; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v10, v9
+; VI-NEXT:    s_cbranch_vccz .LBB10_18
+; VI-NEXT:  ; %bb.17: ; %frem.else53
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v8, s2, 0, v1
+; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v10, v9
+; VI-NEXT:    v_cndmask_b32_e32 v8, v1, v8, vcc
+; VI-NEXT:    s_cbranch_execz .LBB10_19
+; VI-NEXT:    s_branch .LBB10_24
+; VI-NEXT:  .LBB10_18:
+; VI-NEXT:    ; implicit-def: $vgpr8
+; VI-NEXT:  .LBB10_19: ; %frem.compute52
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v10
+; VI-NEXT:    v_frexp_mant_f32_e32 v8, v10
+; VI-NEXT:    v_frexp_mant_f32_e32 v10, v9
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v9
+; VI-NEXT:    v_ldexp_f32 v9, v10, 1
+; VI-NEXT:    v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
+; VI-NEXT:    v_ldexp_f32 v11, v8, 11
+; VI-NEXT:    v_add_u32_e32 v8, vcc, -1, v14
+; VI-NEXT:    v_not_b32_e32 v10, v8
+; VI-NEXT:    v_add_u32_e32 v10, vcc, v10, v13
+; VI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v16, v15
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
+; VI-NEXT:    v_fma_f32 v16, v17, v16, v16
+; VI-NEXT:    v_mul_f32_e32 v17, v12, v16
+; VI-NEXT:    v_fma_f32 v18, -v15, v17, v12
+; VI-NEXT:    v_fma_f32 v17, v18, v16, v17
+; VI-NEXT:    v_fma_f32 v12, -v15, v17, v12
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v10
+; VI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB10_23
+; VI-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; VI-NEXT:    v_sub_u32_e32 v10, vcc, v13, v14
+; VI-NEXT:    v_add_u32_e32 v10, vcc, 11, v10
+; VI-NEXT:  .LBB10_21: ; %frem.loop_body60
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v13, v11
+; VI-NEXT:    v_mul_f32_e32 v11, v13, v12
+; VI-NEXT:    v_rndne_f32_e32 v11, v11
+; VI-NEXT:    v_fma_f32 v11, -v11, v9, v13
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; VI-NEXT:    v_add_f32_e32 v14, v11, v9
+; VI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; VI-NEXT:    v_add_u32_e32 v10, vcc, -11, v10
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v10
+; VI-NEXT:    v_ldexp_f32 v11, v11, 11
+; VI-NEXT:    s_cbranch_vccnz .LBB10_21
+; VI-NEXT:  ; %bb.22: ; %Flow125
+; VI-NEXT:    v_mov_b32_e32 v11, v13
+; VI-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; VI-NEXT:    v_add_u32_e32 v10, vcc, -10, v10
+; VI-NEXT:    v_ldexp_f32 v10, v11, v10
+; VI-NEXT:    v_mul_f32_e32 v11, v10, v12
+; VI-NEXT:    v_rndne_f32_e32 v11, v11
+; VI-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; VI-NEXT:    v_add_f32_e32 v9, v10, v9
+; VI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; VI-NEXT:    v_ldexp_f32 v8, v9, v8
+; VI-NEXT:    v_cvt_f16_f32_e32 v8, v8
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v8, s2, v8, v1
+; VI-NEXT:  .LBB10_24:
+; VI-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; VI-NEXT:    v_lshrrev_b32_e32 v10, 16, v3
+; VI-NEXT:    v_cvt_f32_f16_e64 v13, |v9|
+; VI-NEXT:    v_cvt_f32_f16_e64 v12, |v10|
+; VI-NEXT:    v_cmp_ngt_f32_e32 vcc, v13, v12
+; VI-NEXT:    s_cbranch_vccz .LBB10_26
+; VI-NEXT:  ; %bb.25: ; %frem.else86
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v11, s2, 0, v9
+; VI-NEXT:    v_cmp_eq_f32_e32 vcc, v13, v12
+; VI-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc
+; VI-NEXT:    s_cbranch_execz .LBB10_27
+; VI-NEXT:    s_branch .LBB10_32
+; VI-NEXT:  .LBB10_26:
+; VI-NEXT:    ; implicit-def: $vgpr11
+; VI-NEXT:  .LBB10_27: ; %frem.compute85
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v13
+; VI-NEXT:    v_frexp_mant_f32_e32 v11, v13
+; VI-NEXT:    v_frexp_mant_f32_e32 v13, v12
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v12
+; VI-NEXT:    v_ldexp_f32 v12, v13, 1
+; VI-NEXT:    v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
+; VI-NEXT:    v_ldexp_f32 v14, v11, 11
+; VI-NEXT:    v_add_u32_e32 v11, vcc, -1, v17
+; VI-NEXT:    v_not_b32_e32 v13, v11
+; VI-NEXT:    v_add_u32_e32 v13, vcc, v13, v16
+; VI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v19, v18
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; VI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
+; VI-NEXT:    v_fma_f32 v19, v20, v19, v19
+; VI-NEXT:    v_mul_f32_e32 v20, v15, v19
+; VI-NEXT:    v_fma_f32 v21, -v18, v20, v15
+; VI-NEXT:    v_fma_f32 v20, v21, v19, v20
+; VI-NEXT:    v_fma_f32 v15, -v18, v20, v15
+; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; VI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v13
+; VI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB10_31
+; VI-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; VI-NEXT:    v_sub_u32_e32 v13, vcc, v16, v17
+; VI-NEXT:    v_add_u32_e32 v13, vcc, 11, v13
+; VI-NEXT:  .LBB10_29: ; %frem.loop_body93
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v16, v14
+; VI-NEXT:    v_mul_f32_e32 v14, v16, v15
+; VI-NEXT:    v_rndne_f32_e32 v14, v14
+; VI-NEXT:    v_fma_f32 v14, -v14, v12, v16
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
+; VI-NEXT:    v_add_f32_e32 v17, v14, v12
+; VI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
+; VI-NEXT:    v_add_u32_e32 v13, vcc, -11, v13
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v13
+; VI-NEXT:    v_ldexp_f32 v14, v14, 11
+; VI-NEXT:    s_cbranch_vccnz .LBB10_29
+; VI-NEXT:  ; %bb.30: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v14, v16
+; VI-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; VI-NEXT:    v_add_u32_e32 v13, vcc, -10, v13
+; VI-NEXT:    v_ldexp_f32 v13, v14, v13
+; VI-NEXT:    v_mul_f32_e32 v14, v13, v15
+; VI-NEXT:    v_rndne_f32_e32 v14, v14
+; VI-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; VI-NEXT:    v_add_f32_e32 v12, v13, v12
+; VI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
+; VI-NEXT:    v_ldexp_f32 v11, v12, v11
+; VI-NEXT:    v_cvt_f16_f32_e32 v11, v11
+; VI-NEXT:    s_movk_i32 s2, 0x7fff
+; VI-NEXT:    v_bfi_b32 v11, s2, v11, v9
+; VI-NEXT:  .LBB10_32: ; %Flow124
+; VI-NEXT:    s_movk_i32 s4, 0x7c00
+; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v2
+; VI-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v0|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_mov_b32_e32 v2, 0x7e00
+; VI-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc
+; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v6
+; VI-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v5|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_cndmask_b32_sdwa v5, v2, v7, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v3
+; VI-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v1|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v3, v2, v8, vcc
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v10
+; VI-NEXT:    v_cmp_nge_f16_e64 s[0:1], |v9|, s4
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_cndmask_b32_sdwa v2, v2, v11, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v3, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT:    v_or_b32_sdwa v2, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; VI-NEXT:    s_endpgm
 ;
@@ -3264,73 +8324,316 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
-; GFX9-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
+; GFX9-NEXT:    global_load_dwordx2 v[2:3], v4, s[2:3]
+; GFX9-NEXT:    global_load_dwordx2 v[0:1], v4, s[6:7] offset:32
 ; GFX9-NEXT:    s_waitcnt vmcnt(1)
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v5, v1
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v6, |v2|
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v6, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 16, v3
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v9, v8
-; GFX9-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX9-NEXT:    v_rcp_f32_e32 v9, v9
-; GFX9-NEXT:    v_mul_f32_e32 v5, v5, v6
-; GFX9-NEXT:    v_mad_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mac_f32_e32 v5, v7, v6
-; GFX9-NEXT:    v_mad_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mul_f32_e32 v6, v7, v6
-; GFX9-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v5, |v0|
+; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v6, v5
+; GFX9-NEXT:    s_cbranch_vccz .LBB10_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v4, s2, 0, v2
+; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v6, v5
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB10_3
+; GFX9-NEXT:    s_branch .LBB10_8
+; GFX9-NEXT:  .LBB10_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr4
+; GFX9-NEXT:  .LBB10_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, v6
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v6, v5
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v5
+; GFX9-NEXT:    v_ldexp_f32 v5, v6, 1
+; GFX9-NEXT:    v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; GFX9-NEXT:    v_ldexp_f32 v7, v4, 11
+; GFX9-NEXT:    v_add_u32_e32 v4, -1, v10
+; GFX9-NEXT:    v_not_b32_e32 v6, v4
+; GFX9-NEXT:    v_add_u32_e32 v6, v6, v9
+; GFX9-NEXT:    v_rcp_f32_e32 v12, v11
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; GFX9-NEXT:    v_fma_f32 v12, v13, v12, v12
+; GFX9-NEXT:    v_mul_f32_e32 v13, v8, v12
+; GFX9-NEXT:    v_fma_f32 v14, -v11, v13, v8
+; GFX9-NEXT:    v_fma_f32 v13, v14, v12, v13
+; GFX9-NEXT:    v_fma_f32 v8, -v11, v13, v8
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v6
+; GFX9-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v6, v9, v10
+; GFX9-NEXT:    v_add_u32_e32 v6, 11, v6
+; GFX9-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v9, v7
+; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v8
+; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX9-NEXT:    v_fma_f32 v7, -v7, v5, v9
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; GFX9-NEXT:    v_add_f32_e32 v10, v7, v5
+; GFX9-NEXT:    v_add_u32_e32 v6, -11, v6
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v6
+; GFX9-NEXT:    v_ldexp_f32 v7, v7, 11
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow133
+; GFX9-NEXT:    v_mov_b32_e32 v7, v9
+; GFX9-NEXT:  .LBB10_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_add_u32_e32 v6, -10, v6
+; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
+; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v8
+; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX9-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
 ; GFX9-NEXT:    v_add_f32_e32 v5, v6, v5
-; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX9-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX9-NEXT:    v_mul_f32_e32 v7, v7, v9
-; GFX9-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
-; GFX9-NEXT:    v_mad_mix_f32 v10, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX9-NEXT:    v_mac_f32_e32 v7, v10, v9
-; GFX9-NEXT:    v_fma_f16 v5, -v5, v3, v1
-; GFX9-NEXT:    v_mad_mix_f32 v1, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mul_f32_e32 v1, v1, v9
-; GFX9-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX9-NEXT:    v_add_f32_e32 v1, v1, v7
-; GFX9-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v3, v0
-; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX9-NEXT:    v_div_fixup_f16 v1, v1, v8, v6
-; GFX9-NEXT:    v_trunc_f16_e32 v1, v1
-; GFX9-NEXT:    v_fma_f16 v1, -v1, v8, v6
-; GFX9-NEXT:    v_pack_b32_f16 v1, v5, v1
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v8, v7
-; GFX9-NEXT:    v_rcp_f32_e32 v5, v5
-; GFX9-NEXT:    v_rcp_f32_e32 v8, v8
-; GFX9-NEXT:    v_mul_f32_e32 v3, v3, v5
-; GFX9-NEXT:    v_mad_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mac_f32_e32 v3, v6, v5
-; GFX9-NEXT:    v_mad_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mul_f32_e32 v5, v6, v5
-; GFX9-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
-; GFX9-NEXT:    v_add_f32_e32 v3, v5, v3
-; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
-; GFX9-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; GFX9-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX9-NEXT:    v_mul_f32_e32 v6, v6, v8
-; GFX9-NEXT:    v_div_fixup_f16 v3, v3, v2, v0
-; GFX9-NEXT:    v_mad_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX9-NEXT:    v_mac_f32_e32 v6, v9, v8
-; GFX9-NEXT:    v_fma_f16 v3, -v3, v2, v0
-; GFX9-NEXT:    v_mad_mix_f32 v0, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX9-NEXT:    v_mul_f32_e32 v0, v0, v8
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
-; GFX9-NEXT:    v_add_f32_e32 v0, v0, v6
-; GFX9-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX9-NEXT:    v_div_fixup_f16 v0, v0, v7, v5
-; GFX9-NEXT:    v_trunc_f16_e32 v0, v0
-; GFX9-NEXT:    v_fma_f16 v0, -v0, v7, v5
-; GFX9-NEXT:    v_pack_b32_f16 v0, v3, v0
-; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v4, s2, v4, v2
+; GFX9-NEXT:  .LBB10_8:
+; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v8, |v5|
+; GFX9-NEXT:    v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v8, v7
+; GFX9-NEXT:    s_cbranch_vccz .LBB10_10
+; GFX9-NEXT:  ; %bb.9: ; %frem.else20
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v6, s2, 0, v5
+; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v8, v7
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB10_11
+; GFX9-NEXT:    s_branch .LBB10_16
+; GFX9-NEXT:  .LBB10_10:
+; GFX9-NEXT:    ; implicit-def: $vgpr6
+; GFX9-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v11, v8
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v6, v8
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v8, v7
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v12, v7
+; GFX9-NEXT:    v_ldexp_f32 v7, v8, 1
+; GFX9-NEXT:    v_div_scale_f32 v13, s[2:3], v7, v7, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v10, vcc, 1.0, v7, 1.0
+; GFX9-NEXT:    v_ldexp_f32 v9, v6, 11
+; GFX9-NEXT:    v_add_u32_e32 v6, -1, v12
+; GFX9-NEXT:    v_not_b32_e32 v8, v6
+; GFX9-NEXT:    v_add_u32_e32 v8, v8, v11
+; GFX9-NEXT:    v_rcp_f32_e32 v14, v13
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
+; GFX9-NEXT:    v_fma_f32 v14, v15, v14, v14
+; GFX9-NEXT:    v_mul_f32_e32 v15, v10, v14
+; GFX9-NEXT:    v_fma_f32 v16, -v13, v15, v10
+; GFX9-NEXT:    v_fma_f32 v15, v16, v14, v15
+; GFX9-NEXT:    v_fma_f32 v10, -v13, v15, v10
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v10, v10, v14, v15
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v8
+; GFX9-NEXT:    v_div_fixup_f32 v10, v10, v7, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v8, v11, v12
+; GFX9-NEXT:    v_add_u32_e32 v8, 11, v8
+; GFX9-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v11, v9
+; GFX9-NEXT:    v_mul_f32_e32 v9, v11, v10
+; GFX9-NEXT:    v_rndne_f32_e32 v9, v9
+; GFX9-NEXT:    v_fma_f32 v9, -v9, v7, v11
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
+; GFX9-NEXT:    v_add_f32_e32 v12, v9, v7
+; GFX9-NEXT:    v_add_u32_e32 v8, -11, v8
+; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v8
+; GFX9-NEXT:    v_ldexp_f32 v9, v9, 11
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_13
+; GFX9-NEXT:  ; %bb.14: ; %Flow129
+; GFX9-NEXT:    v_mov_b32_e32 v9, v11
+; GFX9-NEXT:  .LBB10_15: ; %frem.loop_exit28
+; GFX9-NEXT:    v_add_u32_e32 v8, -10, v8
+; GFX9-NEXT:    v_ldexp_f32 v8, v9, v8
+; GFX9-NEXT:    v_mul_f32_e32 v9, v8, v10
+; GFX9-NEXT:    v_rndne_f32_e32 v9, v9
+; GFX9-NEXT:    v_fma_f32 v8, -v9, v7, v8
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
+; GFX9-NEXT:    v_add_f32_e32 v7, v8, v7
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
+; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v6, s2, v6, v5
+; GFX9-NEXT:  .LBB10_16:
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v8, |v1|
+; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v9, v8
+; GFX9-NEXT:    s_cbranch_vccz .LBB10_18
+; GFX9-NEXT:  ; %bb.17: ; %frem.else53
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v7, s2, 0, v3
+; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v9, v8
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v3, v7, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB10_19
+; GFX9-NEXT:    s_branch .LBB10_24
+; GFX9-NEXT:  .LBB10_18:
+; GFX9-NEXT:    ; implicit-def: $vgpr7
+; GFX9-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v12, v9
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v7, v9
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v9, v8
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v13, v8
+; GFX9-NEXT:    v_ldexp_f32 v8, v9, 1
+; GFX9-NEXT:    v_div_scale_f32 v14, s[2:3], v8, v8, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v11, vcc, 1.0, v8, 1.0
+; GFX9-NEXT:    v_ldexp_f32 v10, v7, 11
+; GFX9-NEXT:    v_add_u32_e32 v7, -1, v13
+; GFX9-NEXT:    v_not_b32_e32 v9, v7
+; GFX9-NEXT:    v_add_u32_e32 v9, v9, v12
+; GFX9-NEXT:    v_rcp_f32_e32 v15, v14
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
+; GFX9-NEXT:    v_fma_f32 v15, v16, v15, v15
+; GFX9-NEXT:    v_mul_f32_e32 v16, v11, v15
+; GFX9-NEXT:    v_fma_f32 v17, -v14, v16, v11
+; GFX9-NEXT:    v_fma_f32 v16, v17, v15, v16
+; GFX9-NEXT:    v_fma_f32 v11, -v14, v16, v11
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v11, v11, v15, v16
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v9
+; GFX9-NEXT:    v_div_fixup_f32 v11, v11, v8, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX9-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v9, v12, v13
+; GFX9-NEXT:    v_add_u32_e32 v9, 11, v9
+; GFX9-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v12, v10
+; GFX9-NEXT:    v_mul_f32_e32 v10, v12, v11
+; GFX9-NEXT:    v_rndne_f32_e32 v10, v10
+; GFX9-NEXT:    v_fma_f32 v10, -v10, v8, v12
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; GFX9-NEXT:    v_add_f32_e32 v13, v10, v8
+; GFX9-NEXT:    v_add_u32_e32 v9, -11, v9
+; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v9
+; GFX9-NEXT:    v_ldexp_f32 v10, v10, 11
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_21
+; GFX9-NEXT:  ; %bb.22: ; %Flow125
+; GFX9-NEXT:    v_mov_b32_e32 v10, v12
+; GFX9-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; GFX9-NEXT:    v_add_u32_e32 v9, -10, v9
+; GFX9-NEXT:    v_ldexp_f32 v9, v10, v9
+; GFX9-NEXT:    v_mul_f32_e32 v10, v9, v11
+; GFX9-NEXT:    v_rndne_f32_e32 v10, v10
+; GFX9-NEXT:    v_fma_f32 v9, -v10, v8, v9
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
+; GFX9-NEXT:    v_add_f32_e32 v8, v9, v8
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; GFX9-NEXT:    v_ldexp_f32 v7, v8, v7
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v7, s2, v7, v3
+; GFX9-NEXT:  .LBB10_24:
+; GFX9-NEXT:    v_lshrrev_b32_e32 v8, 16, v3
+; GFX9-NEXT:    v_cvt_f32_f16_e64 v11, |v8|
+; GFX9-NEXT:    v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT:    v_cmp_ngt_f32_e32 vcc, v11, v10
+; GFX9-NEXT:    s_cbranch_vccz .LBB10_26
+; GFX9-NEXT:  ; %bb.25: ; %frem.else86
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v9, s2, 0, v8
+; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, v11, v10
+; GFX9-NEXT:    v_cndmask_b32_e32 v9, v8, v9, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB10_27
+; GFX9-NEXT:    s_branch .LBB10_32
+; GFX9-NEXT:  .LBB10_26:
+; GFX9-NEXT:    ; implicit-def: $vgpr9
+; GFX9-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v14, v11
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v9, v11
+; GFX9-NEXT:    v_frexp_mant_f32_e32 v11, v10
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v15, v10
+; GFX9-NEXT:    v_ldexp_f32 v10, v11, 1
+; GFX9-NEXT:    v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; GFX9-NEXT:    v_ldexp_f32 v12, v9, 11
+; GFX9-NEXT:    v_add_u32_e32 v9, -1, v15
+; GFX9-NEXT:    v_not_b32_e32 v11, v9
+; GFX9-NEXT:    v_add_u32_e32 v11, v11, v14
+; GFX9-NEXT:    v_rcp_f32_e32 v17, v16
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX9-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
+; GFX9-NEXT:    v_fma_f32 v17, v18, v17, v17
+; GFX9-NEXT:    v_mul_f32_e32 v18, v13, v17
+; GFX9-NEXT:    v_fma_f32 v19, -v16, v18, v13
+; GFX9-NEXT:    v_fma_f32 v18, v19, v17, v18
+; GFX9-NEXT:    v_fma_f32 v13, -v16, v18, v13
+; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX9-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 12, v11
+; GFX9-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX9-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v11, v14, v15
+; GFX9-NEXT:    v_add_u32_e32 v11, 11, v11
+; GFX9-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v14, v12
+; GFX9-NEXT:    v_mul_f32_e32 v12, v14, v13
+; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX9-NEXT:    v_fma_f32 v12, -v12, v10, v14
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; GFX9-NEXT:    v_add_f32_e32 v15, v12, v10
+; GFX9-NEXT:    v_add_u32_e32 v11, -11, v11
+; GFX9-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 11, v11
+; GFX9-NEXT:    v_ldexp_f32 v12, v12, 11
+; GFX9-NEXT:    s_cbranch_vccnz .LBB10_29
+; GFX9-NEXT:  ; %bb.30: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v12, v14
+; GFX9-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX9-NEXT:    v_add_u32_e32 v11, -10, v11
+; GFX9-NEXT:    v_ldexp_f32 v11, v12, v11
+; GFX9-NEXT:    v_mul_f32_e32 v12, v11, v13
+; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX9-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; GFX9-NEXT:    v_add_f32_e32 v10, v11, v10
+; GFX9-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; GFX9-NEXT:    v_ldexp_f32 v9, v10, v9
+; GFX9-NEXT:    v_cvt_f16_f32_e32 v9, v9
+; GFX9-NEXT:    s_movk_i32 s2, 0x7fff
+; GFX9-NEXT:    v_bfi_b32 v9, s2, v9, v8
+; GFX9-NEXT:  .LBB10_32: ; %Flow124
+; GFX9-NEXT:    s_movk_i32 s6, 0x7c00
+; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v0
+; GFX9-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v2|, s6
+; GFX9-NEXT:    v_mov_b32_e32 v10, 0
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x7e00
+; GFX9-NEXT:    v_cmp_lg_f16_sdwa s[2:3], v0, v10 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v5|, s6
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc
+; GFX9-NEXT:    s_and_b64 vcc, s[4:5], s[2:3]
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v6, vcc
+; GFX9-NEXT:    v_cmp_lg_f16_e32 vcc, 0, v1
+; GFX9-NEXT:    v_cmp_nge_f16_e64 s[2:3], |v3|, s6
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_cmp_lg_f16_sdwa s[2:3], v1, v10 src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT:    v_cmp_nge_f16_e64 s[4:5], |v8|, s6
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v2, v7, vcc
+; GFX9-NEXT:    s_and_b64 vcc, s[4:5], s[2:3]
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v9, vcc
+; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v3
+; GFX9-NEXT:    v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v4
+; GFX9-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
+; GFX9-NEXT:    global_store_dwordx2 v10, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: frem_v4f16:
@@ -3341,72 +8644,317 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
-; GFX10-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
+; GFX10-NEXT:    global_load_dwordx2 v[2:3], v4, s[2:3]
+; GFX10-NEXT:    global_load_dwordx2 v[0:1], v4, s[6:7] offset:32
 ; GFX10-NEXT:    s_waitcnt vmcnt(1)
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v1
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v6, |v2|
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v6, v3
-; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
-; GFX10-NEXT:    v_mul_f32_e32 v8, v5, v7
-; GFX10-NEXT:    v_mad_f32 v9, -v6, v8, v5
-; GFX10-NEXT:    v_mac_f32_e32 v8, v9, v7
-; GFX10-NEXT:    v_mad_f32 v5, -v6, v8, v5
-; GFX10-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX10-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
-; GFX10-NEXT:    v_add_f32_e32 v5, v5, v8
-; GFX10-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX10-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
-; GFX10-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX10-NEXT:    v_fma_f16 v5, -v5, v3, v1
-; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX10-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v7, v3
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v6, v1
-; GFX10-NEXT:    v_rcp_f32_e32 v8, v7
-; GFX10-NEXT:    v_mul_f32_e32 v9, v6, v8
-; GFX10-NEXT:    v_mad_f32 v10, -v7, v9, v6
-; GFX10-NEXT:    v_mac_f32_e32 v9, v10, v8
-; GFX10-NEXT:    v_mad_f32 v6, -v7, v9, v6
-; GFX10-NEXT:    v_mul_f32_e32 v6, v6, v8
-; GFX10-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX10-NEXT:    v_add_f32_e32 v6, v6, v9
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v5, |v0|
+; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX10-NEXT:    s_cbranch_vccz .LBB10_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, 0, v2
+; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX10-NEXT:    v_cndmask_b32_e32 v4, v2, v4, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB10_3
+; GFX10-NEXT:    s_branch .LBB10_8
+; GFX10-NEXT:  .LBB10_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr4
+; GFX10-NEXT:  .LBB10_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v8, v5
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v7, v6
+; GFX10-NEXT:    v_ldexp_f32 v6, v4, 11
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v4, v5
+; GFX10-NEXT:    v_ldexp_f32 v5, v8, 1
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v7
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX10-NEXT:    v_div_scale_f32 v9, s4, v5, v5, 1.0
+; GFX10-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX10-NEXT:    v_not_b32_e32 v8, v4
+; GFX10-NEXT:    v_add_nc_u32_e32 v8, v8, v7
+; GFX10-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v10
+; GFX10-NEXT:    v_mul_f32_e32 v11, v7, v10
+; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v7
+; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v10
+; GFX10-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
+; GFX10-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 11
+; GFX10-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v9, v6
+; GFX10-NEXT:    s_add_i32 s2, s2, -11
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX10-NEXT:    v_mul_f32_e32 v6, v9, v7
+; GFX10-NEXT:    v_rndne_f32_e32 v6, v6
+; GFX10-NEXT:    v_fma_f32 v6, -v6, v5, v9
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX10-NEXT:    v_add_f32_e32 v8, v6, v5
+; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v6, v6, 11
+; GFX10-NEXT:    s_cbranch_scc1 .LBB10_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow133
+; GFX10-NEXT:    v_mov_b32_e32 v8, s2
+; GFX10-NEXT:    v_mov_b32_e32 v6, v9
+; GFX10-NEXT:  .LBB10_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_add_nc_u32_e32 v8, -10, v8
+; GFX10-NEXT:    v_ldexp_f32 v6, v6, v8
+; GFX10-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX10-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX10-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX10-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v2
+; GFX10-NEXT:  .LBB10_8:
+; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
+; GFX10-NEXT:    v_cvt_f32_f16_sdwa v7, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v8, |v5|
+; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v8, v7
+; GFX10-NEXT:    s_cbranch_vccz .LBB10_10
+; GFX10-NEXT:  ; %bb.9: ; %frem.else20
+; GFX10-NEXT:    v_bfi_b32 v6, 0x7fff, 0, v5
+; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v8, v7
+; GFX10-NEXT:    v_cndmask_b32_e32 v6, v5, v6, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB10_11
+; GFX10-NEXT:    s_branch .LBB10_16
+; GFX10-NEXT:  .LBB10_10:
+; GFX10-NEXT:    ; implicit-def: $vgpr6
+; GFX10-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v6, v8
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v10, v7
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v9, v8
+; GFX10-NEXT:    v_ldexp_f32 v8, v6, 11
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v6, v7
+; GFX10-NEXT:    v_ldexp_f32 v7, v10, 1
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v9
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v6
+; GFX10-NEXT:    v_div_scale_f32 v11, s4, v7, v7, 1.0
+; GFX10-NEXT:    v_add_nc_u32_e32 v6, -1, v6
+; GFX10-NEXT:    v_rcp_f32_e32 v12, v11
+; GFX10-NEXT:    v_not_b32_e32 v10, v6
+; GFX10-NEXT:    v_add_nc_u32_e32 v10, v10, v9
+; GFX10-NEXT:    v_div_scale_f32 v9, vcc_lo, 1.0, v7, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v12, v13, v12
+; GFX10-NEXT:    v_mul_f32_e32 v13, v9, v12
+; GFX10-NEXT:    v_fma_f32 v14, -v11, v13, v9
+; GFX10-NEXT:    v_fmac_f32_e32 v13, v14, v12
+; GFX10-NEXT:    v_fma_f32 v9, -v11, v13, v9
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v9, v9, v12, v13
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v10
+; GFX10-NEXT:    v_div_fixup_f32 v9, v9, v7, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 11
+; GFX10-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v11, v8
+; GFX10-NEXT:    s_add_i32 s2, s2, -11
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX10-NEXT:    v_mul_f32_e32 v8, v11, v9
+; GFX10-NEXT:    v_rndne_f32_e32 v8, v8
+; GFX10-NEXT:    v_fma_f32 v8, -v8, v7, v11
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_add_f32_e32 v10, v8, v7
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v10, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v8, v8, 11
+; GFX10-NEXT:    s_cbranch_scc1 .LBB10_13
+; GFX10-NEXT:  ; %bb.14: ; %Flow129
+; GFX10-NEXT:    v_mov_b32_e32 v10, s2
+; GFX10-NEXT:    v_mov_b32_e32 v8, v11
+; GFX10-NEXT:  .LBB10_15: ; %frem.loop_exit28
+; GFX10-NEXT:    v_add_nc_u32_e32 v10, -10, v10
+; GFX10-NEXT:    v_ldexp_f32 v8, v8, v10
+; GFX10-NEXT:    v_mul_f32_e32 v9, v8, v9
+; GFX10-NEXT:    v_rndne_f32_e32 v9, v9
+; GFX10-NEXT:    v_fma_f32 v8, -v9, v7, v8
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_add_f32_e32 v7, v8, v7
+; GFX10-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v6, v7, v6
 ; GFX10-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GFX10-NEXT:    v_div_fixup_f16 v6, v6, v3, v1
-; GFX10-NEXT:    v_trunc_f16_e32 v6, v6
-; GFX10-NEXT:    v_fma_f16 v1, -v6, v3, v1
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v3, v0
-; GFX10-NEXT:    v_pack_b32_f16 v1, v5, v1
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
-; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
-; GFX10-NEXT:    v_mad_f32 v8, -v5, v7, v3
-; GFX10-NEXT:    v_mac_f32_e32 v7, v8, v6
-; GFX10-NEXT:    v_mad_f32 v3, -v5, v7, v3
-; GFX10-NEXT:    v_mul_f32_e32 v3, v3, v6
-; GFX10-NEXT:    v_and_b32_e32 v3, 0xff800000, v3
-; GFX10-NEXT:    v_add_f32_e32 v3, v3, v7
-; GFX10-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX10-NEXT:    v_div_fixup_f16 v3, v3, v2, v0
-; GFX10-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX10-NEXT:    v_fma_f16 v3, -v3, v2, v0
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX10-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v6, v2
-; GFX10-NEXT:    v_cvt_f32_f16_e32 v5, v0
-; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
-; GFX10-NEXT:    v_mul_f32_e32 v8, v5, v7
-; GFX10-NEXT:    v_mad_f32 v9, -v6, v8, v5
-; GFX10-NEXT:    v_mac_f32_e32 v8, v9, v7
-; GFX10-NEXT:    v_mad_f32 v5, -v6, v8, v5
-; GFX10-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX10-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
-; GFX10-NEXT:    v_add_f32_e32 v5, v5, v8
-; GFX10-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX10-NEXT:    v_div_fixup_f16 v5, v5, v2, v0
-; GFX10-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX10-NEXT:    v_fma_f16 v0, -v5, v2, v0
-; GFX10-NEXT:    v_pack_b32_f16 v0, v3, v0
+; GFX10-NEXT:    v_bfi_b32 v6, 0x7fff, v6, v5
+; GFX10-NEXT:  .LBB10_16:
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v8, |v1|
+; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v9, v8
+; GFX10-NEXT:    s_cbranch_vccz .LBB10_18
+; GFX10-NEXT:  ; %bb.17: ; %frem.else53
+; GFX10-NEXT:    v_bfi_b32 v7, 0x7fff, 0, v3
+; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
+; GFX10-NEXT:    v_cndmask_b32_e32 v7, v3, v7, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB10_19
+; GFX10-NEXT:    s_branch .LBB10_24
+; GFX10-NEXT:  .LBB10_18:
+; GFX10-NEXT:    ; implicit-def: $vgpr7
+; GFX10-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v7, v9
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v11, v8
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v10, v9
+; GFX10-NEXT:    v_ldexp_f32 v9, v7, 11
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v7, v8
+; GFX10-NEXT:    v_ldexp_f32 v8, v11, 1
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v10
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v7
+; GFX10-NEXT:    v_div_scale_f32 v12, s4, v8, v8, 1.0
+; GFX10-NEXT:    v_add_nc_u32_e32 v7, -1, v7
+; GFX10-NEXT:    v_rcp_f32_e32 v13, v12
+; GFX10-NEXT:    v_not_b32_e32 v11, v7
+; GFX10-NEXT:    v_add_nc_u32_e32 v11, v11, v10
+; GFX10-NEXT:    v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v13, v14, v13
+; GFX10-NEXT:    v_mul_f32_e32 v14, v10, v13
+; GFX10-NEXT:    v_fma_f32 v15, -v12, v14, v10
+; GFX10-NEXT:    v_fmac_f32_e32 v14, v15, v13
+; GFX10-NEXT:    v_fma_f32 v10, -v12, v14, v10
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v10, v10, v13, v14
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v11
+; GFX10-NEXT:    v_div_fixup_f32 v10, v10, v8, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX10-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 11
+; GFX10-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v12, v9
+; GFX10-NEXT:    s_add_i32 s2, s2, -11
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX10-NEXT:    v_mul_f32_e32 v9, v12, v10
+; GFX10-NEXT:    v_rndne_f32_e32 v9, v9
+; GFX10-NEXT:    v_fma_f32 v9, -v9, v8, v12
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX10-NEXT:    v_add_f32_e32 v11, v9, v8
+; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v9, v9, 11
+; GFX10-NEXT:    s_cbranch_scc1 .LBB10_21
+; GFX10-NEXT:  ; %bb.22: ; %Flow125
+; GFX10-NEXT:    v_mov_b32_e32 v11, s2
+; GFX10-NEXT:    v_mov_b32_e32 v9, v12
+; GFX10-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; GFX10-NEXT:    v_add_nc_u32_e32 v11, -10, v11
+; GFX10-NEXT:    v_ldexp_f32 v9, v9, v11
+; GFX10-NEXT:    v_mul_f32_e32 v10, v9, v10
+; GFX10-NEXT:    v_rndne_f32_e32 v10, v10
+; GFX10-NEXT:    v_fma_f32 v9, -v10, v8, v9
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX10-NEXT:    v_add_f32_e32 v8, v9, v8
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v7, v8, v7
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GFX10-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v3
+; GFX10-NEXT:  .LBB10_24:
+; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v3
+; GFX10-NEXT:    v_cvt_f32_f16_sdwa v10, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT:    v_cvt_f32_f16_e64 v11, |v8|
+; GFX10-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v11, v10
+; GFX10-NEXT:    s_cbranch_vccz .LBB10_26
+; GFX10-NEXT:  ; %bb.25: ; %frem.else86
+; GFX10-NEXT:    v_bfi_b32 v9, 0x7fff, 0, v8
+; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v9, v8, v9, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB10_27
+; GFX10-NEXT:    s_branch .LBB10_32
+; GFX10-NEXT:  .LBB10_26:
+; GFX10-NEXT:    ; implicit-def: $vgpr9
+; GFX10-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v9, v11
+; GFX10-NEXT:    v_frexp_mant_f32_e32 v13, v10
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v12, v11
+; GFX10-NEXT:    v_ldexp_f32 v11, v9, 11
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v9, v10
+; GFX10-NEXT:    v_ldexp_f32 v10, v13, 1
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v12
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v9
+; GFX10-NEXT:    v_div_scale_f32 v14, s4, v10, v10, 1.0
+; GFX10-NEXT:    v_add_nc_u32_e32 v9, -1, v9
+; GFX10-NEXT:    v_rcp_f32_e32 v15, v14
+; GFX10-NEXT:    v_not_b32_e32 v13, v9
+; GFX10-NEXT:    v_add_nc_u32_e32 v13, v13, v12
+; GFX10-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v10, 1.0
+; GFX10-NEXT:    s_denorm_mode 15
+; GFX10-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v15, v16, v15
+; GFX10-NEXT:    v_mul_f32_e32 v16, v12, v15
+; GFX10-NEXT:    v_fma_f32 v17, -v14, v16, v12
+; GFX10-NEXT:    v_fmac_f32_e32 v16, v17, v15
+; GFX10-NEXT:    v_fma_f32 v12, -v14, v16, v12
+; GFX10-NEXT:    s_denorm_mode 12
+; GFX10-NEXT:    v_div_fmas_f32 v12, v12, v15, v16
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v13
+; GFX10-NEXT:    v_div_fixup_f32 v12, v12, v10, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX10-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 11
+; GFX10-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v14, v11
+; GFX10-NEXT:    s_add_i32 s2, s2, -11
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX10-NEXT:    v_mul_f32_e32 v11, v14, v12
+; GFX10-NEXT:    v_rndne_f32_e32 v11, v11
+; GFX10-NEXT:    v_fma_f32 v11, -v11, v10, v14
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
+; GFX10-NEXT:    v_add_f32_e32 v13, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v11, v11, 11
+; GFX10-NEXT:    s_cbranch_scc1 .LBB10_29
+; GFX10-NEXT:  ; %bb.30: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v13, s2
+; GFX10-NEXT:    v_mov_b32_e32 v11, v14
+; GFX10-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX10-NEXT:    v_add_nc_u32_e32 v13, -10, v13
+; GFX10-NEXT:    v_ldexp_f32 v11, v11, v13
+; GFX10-NEXT:    v_mul_f32_e32 v12, v11, v12
+; GFX10-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX10-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
+; GFX10-NEXT:    v_add_f32_e32 v10, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v9, v10, v9
+; GFX10-NEXT:    v_cvt_f16_f32_e32 v9, v9
+; GFX10-NEXT:    v_bfi_b32 v9, 0x7fff, v9, v8
+; GFX10-NEXT:  .LBB10_32: ; %Flow124
+; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v2|
+; GFX10-NEXT:    v_cmp_nle_f16_e64 s3, 0x7c00, |v5|
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v4, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v4, 0
+; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v2
+; GFX10-NEXT:    v_cmp_lg_f16_sdwa s2, v0, v4 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX10-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v3|
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v6, vcc_lo
+; GFX10-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v1
+; GFX10-NEXT:    v_cmp_nle_f16_e64 s3, 0x7c00, |v8|
+; GFX10-NEXT:    v_lshl_or_b32 v0, v0, 16, v2
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cmp_lg_f16_sdwa s2, v1, v4 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v7, vcc_lo
+; GFX10-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX10-NEXT:    v_and_b32_e32 v3, 0xffff, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v9, vcc_lo
+; GFX10-NEXT:    v_lshl_or_b32 v1, v1, 16, v3
 ; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
@@ -3415,103 +8963,424 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
 ; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v5, 0
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-TRUE16-NEXT:    s_clause 0x1
-; GFX11-TRUE16-NEXT:    global_load_b64 v[1:2], v5, s[2:3]
-; GFX11-TRUE16-NEXT:    global_load_b64 v[3:4], v5, s[4:5] offset:32
+; GFX11-TRUE16-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX11-TRUE16-NEXT:    global_load_b64 v[2:3], v2, s[4:5] offset:32
 ; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0.l|
 ; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v4.l
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB10_2
+; GFX11-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v0.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, 0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v9, v8.l
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v7, v4
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, v0.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_3
+; GFX11-TRUE16-NEXT:    s_branch .LBB10_8
+; GFX11-TRUE16-NEXT:  .LBB10_2:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT:  .LBB10_3: ; %frem.compute
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v8, v5
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v4, 11
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, v5
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v5, v8, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v7
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v9, null, v5, v5, 1.0
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_not_b32_e32 v8, v4
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, v8, v7
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
+; GFX11-TRUE16-NEXT:    s_denorm_mode 15
 ; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v6
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v11, v7, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v12, -v9, v11, v7
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX11-TRUE16-NEXT:    s_denorm_mode 12
+; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX11-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v6
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v9, v7
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v6, -v6, v5, v9
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, v6, v5
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v7, v6
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v6, 11
+; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_5
+; GFX11-TRUE16-NEXT:  ; %bb.6: ; %Flow133
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v8, s2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v6, v9
+; GFX11-TRUE16-NEXT:  .LBB10_7: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, -10, v8
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v6, v6, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v5, v6, v5
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v7, v6
-; GFX11-TRUE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v6, v0
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v4.l, v4
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v5
+; GFX11-TRUE16-NEXT:  .LBB10_8:
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
 ; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v7, v6.l
-; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v4.l, v2.l
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v7, v7, v9
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v10, -v4, v7, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v4.l, v2.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v9, |v5.l|
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v8, |v6.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v9, v8
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB10_10
+; GFX11-TRUE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v7.l, v5.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v10.l, 0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v7, v10, v9
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v2, -v4, v7, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v4, v3.l
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v2, v2, v9
-; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v10, v7
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v7.l, v5.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_11
+; GFX11-TRUE16-NEXT:    s_branch .LBB10_16
+; GFX11-TRUE16-NEXT:  .LBB10_10:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-TRUE16-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v11, v8
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v9, v7, 11
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v8
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v8, v11, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v10
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v7
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v12, null, v8, v8, 1.0
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -1, v7
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v13, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_not_b32_e32 v11, v7
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, v11, v10
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
+; GFX11-TRUE16-NEXT:    s_denorm_mode 15
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff800000, v2
-; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, v2, v7
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v14, v10, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v15, -v12, v14, v10
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v12, v14, v10
+; GFX11-TRUE16-NEXT:    s_denorm_mode 12
+; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v10, v10, v13, v14
+; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v10, v10, v8, 1.0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX11-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, v9
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v9, v12, v10
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v9, v8, v12
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v11, v9, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v9, v9, 11
+; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_13
+; GFX11-TRUE16-NEXT:  ; %bb.14: ; %Flow129
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v11, s2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v9, v12
+; GFX11-TRUE16-NEXT:  .LBB10_15: ; %frem.loop_exit28
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v2
-; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v8.l, v6.l
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, -10, v11
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v9, v9, v11
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.h, -v0.h, v8.l, v6.l
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v8, v7.l
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.l, v0.h
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v1.l
-; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v8, v8
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v10, v9, v10
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v4
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v6, -v3, v0, v1 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v8, v9, v8
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v0, v6, v4
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v6, -v3, v0, v1 op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v7, v8, v7
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v7.l, v7
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v8
+; GFX11-TRUE16-NEXT:  .LBB10_16:
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v10, |v1.l|
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v9, |v3.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v10, v9
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB10_18
+; GFX11-TRUE16-NEXT:  ; %bb.17: ; %frem.else53
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v8.l, v1.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, 0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v10, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0x7fff, v11, v8
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v8.l, v1.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_19
+; GFX11-TRUE16-NEXT:    s_branch .LBB10_24
+; GFX11-TRUE16-NEXT:  .LBB10_18:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-TRUE16-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v8, v10
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v10, v8, 11
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v9
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v9, v12, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v11
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v8
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v13, null, v9, v9, 1.0
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v8, -1, v8
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v14, v13
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v4, v6, v4
-; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 0xff800000, v4
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, v4, v0
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v1
-; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e32 v6, v4.l
-; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v3.l, v1.l
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v6, v6, v8
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT:    v_not_b32_e32 v12, v8
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, v12, v11
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
+; GFX11-TRUE16-NEXT:    s_denorm_mode 15
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v14, v15, v14
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v15, v11, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v16, -v13, v15, v11
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v15, v16, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v11, -v13, v15, v11
+; GFX11-TRUE16-NEXT:    s_denorm_mode 12
+; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v11, v11, v14, v15
+; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX11-TRUE16-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v13, v10
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v10, v13, v11
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v10, v10
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v10, v9, v13
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, v10, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v10, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v10, v10, 11
+; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_21
+; GFX11-TRUE16-NEXT:  ; %bb.22: ; %Flow125
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v12, s2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v10, v13
+; GFX11-TRUE16-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v12, -10, v12
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v10, v10, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v11, v10, v11
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v11, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v9, v10, v9
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v8, v9, v8
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v8.l, v8
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v8, 0x7fff, v8, v9
+; GFX11-TRUE16-NEXT:  .LBB10_24:
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v3
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v9, -v3, v6, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.l, -v0.l, v3.l, v1.l
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v13, |v9.l|
+; GFX11-TRUE16-NEXT:    v_cvt_f32_f16_e64 v12, |v10.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v13, v12
+; GFX11-TRUE16-NEXT:    s_cbranch_vccz .LBB10_26
+; GFX11-TRUE16-NEXT:  ; %bb.25: ; %frem.else86
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v11.l, v9.l
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v14.l, 0
+; GFX11-TRUE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v13, v12
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v6, v9, v8
-; GFX11-TRUE16-NEXT:    v_fma_mix_f32 v1, -v3, v6, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0x7fff, v14, v11
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v11.l, v9.l, v11.l, vcc_lo
+; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB10_27
+; GFX11-TRUE16-NEXT:    s_branch .LBB10_32
+; GFX11-TRUE16-NEXT:  .LBB10_26:
+; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-TRUE16-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v11, v13
+; GFX11-TRUE16-NEXT:    v_frexp_mant_f32_e32 v15, v12
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v14, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v13, v11, 11
+; GFX11-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v12
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v12, v15, 1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s3, v11
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v16, null, v12, v12, 1.0
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v11, -1, v11
+; GFX11-TRUE16-NEXT:    v_rcp_f32_e32 v17, v16
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_not_b32_e32 v15, v11
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v15, v15, v14
+; GFX11-TRUE16-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
+; GFX11-TRUE16-NEXT:    s_denorm_mode 15
+; GFX11-TRUE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-TRUE16-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v1, v1, v8
-; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v17, v18, v17
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v18, v14, v17
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_add_f32_e32 v1, v1, v6
-; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.h, v1
+; GFX11-TRUE16-NEXT:    v_fma_f32 v19, -v16, v18, v14
+; GFX11-TRUE16-NEXT:    v_fmac_f32_e32 v18, v19, v17
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v14, -v16, v18, v14
+; GFX11-TRUE16-NEXT:    s_denorm_mode 12
+; GFX11-TRUE16-NEXT:    v_div_fmas_f32 v14, v14, v17, v18
+; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_div_fixup_f32 v14, v14, v12, 1.0
+; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX11-TRUE16-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX11-TRUE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-TRUE16-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX11-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v16, v13
+; GFX11-TRUE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-TRUE16-NEXT:    s_cmp_gt_i32 s2, 11
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_div_fixup_f16 v0.h, v0.h, v7.l, v4.l
-; GFX11-TRUE16-NEXT:    v_trunc_f16_e32 v0.h, v0.h
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v13, v16, v14
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v13, v13
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v13, -v13, v12, v16
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v15, v13, v12
 ; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_fma_f16 v0.h, -v0.h, v7.l, v4.l
-; GFX11-TRUE16-NEXT:    v_pack_b32_f16 v1, v0.l, v0.h
-; GFX11-TRUE16-NEXT:    global_store_b64 v5, v[1:2], s[0:1]
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v13, v13, 11
+; GFX11-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_29
+; GFX11-TRUE16-NEXT:  ; %bb.30: ; %Flow
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v15, s2
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v13, v16
+; GFX11-TRUE16-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v15, -10, v15
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v13, v13, v15
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_mul_f32_e32 v14, v13, v14
+; GFX11-TRUE16-NEXT:    v_rndne_f32_e32 v14, v14
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; GFX11-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT:    v_add_f32_e32 v12, v13, v12
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
+; GFX11-TRUE16-NEXT:    v_ldexp_f32 v11, v12, v11
+; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cvt_f16_f32_e32 v11.l, v11
+; GFX11-TRUE16-NEXT:    v_bfi_b32 v11, 0x7fff, v11, v12
+; GFX11-TRUE16-NEXT:  .LBB10_32: ; %Flow124
+; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
+; GFX11-TRUE16-NEXT:    s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v6.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v4.l, s2
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v5.l|
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT:    s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v2.l, 0x7e00, v7.l, s2
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
+; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v3, 0
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-TRUE16-NEXT:    s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v10.l
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v8.l, s2
+; GFX11-TRUE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v9.l|
+; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT:    s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT:    v_cndmask_b16 v4.l, 0x7e00, v11.l, s2
+; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
+; GFX11-TRUE16-NEXT:    global_store_b64 v3, v[0:1], s[0:1]
 ; GFX11-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX11-FAKE16-LABEL: frem_v4f16:
@@ -3519,556 +9388,2288 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX11-FAKE16-NEXT:    s_clause 0x1
 ; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-FAKE16-NEXT:    s_clause 0x1
-; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
+; GFX11-FAKE16-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX11-FAKE16-NEXT:    global_load_b64 v[2:3], v2, s[4:5] offset:32
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v1
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v6, |v0|
 ; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v3
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v3
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v9, v8
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v5, |v2|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v6, v5
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB10_2
+; GFX11-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, 0, v0
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v6, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_3
+; GFX11-FAKE16-NEXT:    s_branch .LBB10_8
+; GFX11-FAKE16-NEXT:  .LBB10_2:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr4
+; GFX11-FAKE16-NEXT:  .LBB10_3: ; %frem.compute
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, v6
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v8, v5
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v6
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v6, v4, 11
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, v5
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v5, v8, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v7
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v9, null, v5, v5, 1.0
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_not_b32_e32 v8, v4
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, v8, v7
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
+; GFX11-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v6
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v10
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v11, v7, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v12, -v9, v11, v7
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v11, v12, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX11-FAKE16-NEXT:    s_denorm_mode 12
+; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX11-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-FAKE16-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v6
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v5, v7, v6
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v6, v9, v7
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v6, v7, v6
-; GFX11-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v6, -v6, v5, v9
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, v6, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v6, v6, 11
+; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_5
+; GFX11-FAKE16-NEXT:  ; %bb.6: ; %Flow133
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v8, s2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v6, v9
+; GFX11-FAKE16-NEXT:  .LBB10_7: ; %frem.loop_exit
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, -10, v8
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v6, v6, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
 ; GFX11-FAKE16-NEXT:    v_add_f32_e32 v5, v6, v5
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
-; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v7, v7, v9
-; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v5, v5
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, v4, v0
+; GFX11-FAKE16-NEXT:  .LBB10_8:
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v10, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-FAKE16-NEXT:    v_fma_f16 v5, -v5, v3, v1
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v7, v10, v9
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v1, -v3, v7, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v3, v0
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v5|
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v8, |v6|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB10_10
+; GFX11-FAKE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v7, 0x7fff, 0, v5
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v9, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v7, v5, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_11
+; GFX11-FAKE16-NEXT:    s_branch .LBB10_16
+; GFX11-FAKE16-NEXT:  .LBB10_10:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr7
+; GFX11-FAKE16-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v7, v9
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v11, v8
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v10, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v9, v7, 11
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v7, v8
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v8, v11, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v10
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v12, null, v8, v8, 1.0
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -1, v7
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v13, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_not_b32_e32 v11, v7
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, v11, v10
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
+; GFX11-FAKE16-NEXT:    s_denorm_mode 15
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v14, v10, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v15, -v12, v14, v10
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v14, v15, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v12, v14, v10
+; GFX11-FAKE16-NEXT:    s_denorm_mode 12
+; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v10, v10, v13, v14
+; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v10, v10, v8, 1.0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX11-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-FAKE16-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, v9
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v9, v12, v10
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v9, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v9, v8, v12
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v11, v9, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v9, v9, 11
+; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_13
+; GFX11-FAKE16-NEXT:  ; %bb.14: ; %Flow129
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v11, s2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v9, v12
+; GFX11-FAKE16-NEXT:  .LBB10_15: ; %frem.loop_exit28
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v1, v1, v9
-; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_add_f32_e32 v1, v1, v7
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, -10, v11
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v9, v9, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v10, v9, v10
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v9, -v10, v8, v9
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v8, v9, v8
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v1, v1, v8, v6
-; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v1, v1
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_fma_f16 v1, -v1, v8, v6
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v7
-; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v1, v5, v1
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v8, v8
-; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v5, v5
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v7, v8, v7
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v7, 0x7fff, v7, v5
+; GFX11-FAKE16-NEXT:  .LBB10_16:
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v10, |v1|
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v9, |v3|
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v10, v9
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB10_18
+; GFX11-FAKE16-NEXT:  ; %bb.17: ; %frem.else53
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v8, 0x7fff, 0, v1
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v10, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v8, v1, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_19
+; GFX11-FAKE16-NEXT:    s_branch .LBB10_24
+; GFX11-FAKE16-NEXT:  .LBB10_18:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr8
+; GFX11-FAKE16-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v8, v10
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v12, v9
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v10, v8, 11
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v8, v9
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v9, v12, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v11
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v13, null, v9, v9, 1.0
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v8, -1, v8
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v14, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_not_b32_e32 v12, v8
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, v12, v11
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
+; GFX11-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v3, v3, v5
+; GFX11-FAKE16-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v3, v6, v5
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v14, v15, v14
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v15, v11, v14
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v6, -v2, v3, v0 op_sel_hi:[1,0,1]
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v5, v6, v5
+; GFX11-FAKE16-NEXT:    v_fma_f32 v16, -v13, v15, v11
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v15, v16, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v11, -v13, v15, v11
+; GFX11-FAKE16-NEXT:    s_denorm_mode 12
+; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v11, v11, v14, v15
+; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX11-FAKE16-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-FAKE16-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v13, v10
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xff800000, v5
-; GFX11-FAKE16-NEXT:    v_add_f32_e32 v3, v5, v3
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
-; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v3, v3, v2, v0
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v6, v6, v8
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v3, v3
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_fma_f16 v3, -v3, v2, v0
-; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v6, v9, v8
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v10, v13, v11
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v10, v10
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_fma_mix_f32 v0, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v0, v0, v8
+; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v10, v9, v13
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, v10, v9
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff800000, v0
-; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, v0, v6
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v10, v10, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v10, v10, 11
+; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_21
+; GFX11-FAKE16-NEXT:  ; %bb.22: ; %Flow125
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v12, s2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v10, v13
+; GFX11-FAKE16-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v12, -10, v12
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v10, v10, v12
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT:    v_div_fixup_f16 v0, v0, v7, v5
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v11, v10, v11
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v11, v11
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_trunc_f16_e32 v0, v0
-; GFX11-FAKE16-NEXT:    v_fma_f16 v0, -v0, v7, v5
+; GFX11-FAKE16-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v9, v10, v9
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v8, v9, v8
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v8, v8
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v8, 0x7fff, v8, v1
+; GFX11-FAKE16-NEXT:  .LBB10_24:
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
+; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v13, |v9|
+; GFX11-FAKE16-NEXT:    v_cvt_f32_f16_e64 v12, |v10|
 ; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_pack_b32_f16 v0, v3, v0
-; GFX11-FAKE16-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX11-FAKE16-NEXT:    v_cmp_ngt_f32_e32 vcc_lo, v13, v12
+; GFX11-FAKE16-NEXT:    s_cbranch_vccz .LBB10_26
+; GFX11-FAKE16-NEXT:  ; %bb.25: ; %frem.else86
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v11, 0x7fff, 0, v9
+; GFX11-FAKE16-NEXT:    v_cmp_eq_f32_e32 vcc_lo, v13, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v11, v9, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB10_27
+; GFX11-FAKE16-NEXT:    s_branch .LBB10_32
+; GFX11-FAKE16-NEXT:  .LBB10_26:
+; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr11
+; GFX11-FAKE16-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v11, v13
+; GFX11-FAKE16-NEXT:    v_frexp_mant_f32_e32 v15, v12
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v14, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v13, v11, 11
+; GFX11-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v11, v12
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v12, v15, 1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s3, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v16, null, v12, v12, 1.0
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v11, -1, v11
+; GFX11-FAKE16-NEXT:    v_rcp_f32_e32 v17, v16
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_not_b32_e32 v15, v11
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v15, v15, v14
+; GFX11-FAKE16-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
+; GFX11-FAKE16-NEXT:    s_denorm_mode 15
+; GFX11-FAKE16-NEXT:    s_waitcnt_depctr 0xfff
+; GFX11-FAKE16-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v17, v18, v17
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v18, v14, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v19, -v16, v18, v14
+; GFX11-FAKE16-NEXT:    v_fmac_f32_e32 v18, v19, v17
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v14, -v16, v18, v14
+; GFX11-FAKE16-NEXT:    s_denorm_mode 12
+; GFX11-FAKE16-NEXT:    v_div_fmas_f32 v14, v14, v17, v18
+; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT:    v_div_fixup_f32 v14, v14, v12, 1.0
+; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX11-FAKE16-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX11-FAKE16-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, 11
+; GFX11-FAKE16-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX11-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v16, v13
+; GFX11-FAKE16-NEXT:    s_add_i32 s2, s2, -11
+; GFX11-FAKE16-NEXT:    s_cmp_gt_i32 s2, 11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v13, v16, v14
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v13, v13
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v13, -v13, v12, v16
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v15, v13, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v13, v13, 11
+; GFX11-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_29
+; GFX11-FAKE16-NEXT:  ; %bb.30: ; %Flow
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v15, s2
+; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v13, v16
+; GFX11-FAKE16-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v15, -10, v15
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v13, v13, v15
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_mul_f32_e32 v14, v13, v14
+; GFX11-FAKE16-NEXT:    v_rndne_f32_e32 v14, v14
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; GFX11-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-FAKE16-NEXT:    v_add_f32_e32 v12, v13, v12
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
+; GFX11-FAKE16-NEXT:    v_ldexp_f32 v11, v12, v11
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_cvt_f16_f32_e32 v11, v11
+; GFX11-FAKE16-NEXT:    v_bfi_b32 v11, 0x7fff, v11, v9
+; GFX11-FAKE16-NEXT:  .LBB10_32: ; %Flow124
+; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v2
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v0|
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v5|
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v4, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v6
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v1|
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7e00, v7, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v3
+; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_nle_f16_e64 s2, 0x7c00, |v9|
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, 0x7e00, v8, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cmp_lg_f16_e32 vcc_lo, 0, v10
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x7e00, v11, vcc_lo
+; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
+; GFX11-FAKE16-NEXT:    global_store_b64 v3, v[0:1], s[0:1]
 ; GFX11-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1150-TRUE16-LABEL: frem_v4f16:
 ; GFX1150-TRUE16:       ; %bb.0:
 ; GFX1150-TRUE16-NEXT:    s_clause 0x1
 ; GFX1150-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, 0
+; GFX1150-TRUE16-NEXT:    s_load_b64 s[8:9], s[4:5], 0x34
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1150-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1150-TRUE16-NEXT:    s_clause 0x1
-; GFX1150-TRUE16-NEXT:    global_load_b64 v[2:3], v6, s[2:3]
-; GFX1150-TRUE16-NEXT:    global_load_b64 v[4:5], v6, s[4:5] offset:32
-; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.h
+; GFX1150-TRUE16-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
 ; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.h
-; GFX1150-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1150-TRUE16-NEXT:    global_load_b64 v[0:1], v2, s[8:9] offset:32
+; GFX1150-TRUE16-NEXT:    s_and_b32 s3, s5, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s8, s3
+; GFX1150-TRUE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX1150-TRUE16-NEXT:    s_and_b32 s6, s4, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s6, s6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT:    s_cmp_ngt_f32 s8, s6
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_2
+; GFX1150-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s5
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s8, s6
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s9, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, s5, v0.l, s9
+; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_3
+; GFX1150-TRUE16-NEXT:    s_branch .LBB10_8
+; GFX1150-TRUE16-NEXT:  .LBB10_2:
+; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1150-TRUE16-NEXT:  .LBB10_3: ; %frem.compute
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s8
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s8, v3
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s6, v0
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v0, v7, v1
+; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v1, v7, v1
-; GFX1150-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX1150-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT:    s_sub_i32 s6, s8, s6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_add_i32 s6, s6, 11
+; GFX1150-TRUE16-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1150-TRUE16-NEXT:    s_add_i32 s6, s6, -11
+; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s6, 11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_5
+; GFX1150-TRUE16-NEXT:  ; %bb.6: ; %Flow133
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v4, s6
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1150-TRUE16-NEXT:  .LBB10_7: ; %frem.loop_exit
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s5
 ; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1150-TRUE16-NEXT:  .LBB10_8:
+; GFX1150-TRUE16-NEXT:    s_lshr_b32 s8, s5, 16
+; GFX1150-TRUE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1150-TRUE16-NEXT:    s_and_b32 s5, s8, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_and_b32 s9, s6, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s10, s5
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_10
+; GFX1150-TRUE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s8
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s11, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v2, v1
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, s8, v1.l, s11
+; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_11
+; GFX1150-TRUE16-NEXT:    s_branch .LBB10_16
+; GFX1150-TRUE16-NEXT:  .LBB10_10:
+; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1150-TRUE16-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s10
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s10, v4
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s9, v1
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v8.l, v1.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.l
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX1150-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT:    s_sub_i32 s9, s10, s9
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_add_i32 s9, s9, 11
+; GFX1150-TRUE16-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1150-TRUE16-NEXT:    s_add_i32 s9, s9, -11
+; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s9, 11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_13
+; GFX1150-TRUE16-NEXT:  ; %bb.14: ; %Flow129
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, s9
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1150-TRUE16-NEXT:  .LBB10_15: ; %frem.loop_exit28
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, v5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s8
+; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fmac_f16_e32 v7.l, v0.l, v8.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1150-TRUE16-NEXT:  .LBB10_16:
+; GFX1150-TRUE16-NEXT:    s_and_b32 s8, s7, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_and_b32 s9, s2, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s10, s8
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_18
+; GFX1150-TRUE16-NEXT:  ; %bb.17: ; %frem.else53
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s7
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s11, -1, 0
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v8, -v4, v0, v2 op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v0, v8, v1
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v3, v2
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v2.l, s7, v2.l, s11
+; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_19
+; GFX1150-TRUE16-NEXT:    s_branch .LBB10_24
+; GFX1150-TRUE16-NEXT:  .LBB10_18:
+; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s10
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s10, v5
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s9, v2
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v8, -v4, v0, v2 op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v1, v8, v1
+; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v5.h
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
-; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX1150-TRUE16-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX1150-TRUE16-NEXT:    s_sub_i32 s9, s10, s9
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_add_i32 s9, s9, 11
+; GFX1150-TRUE16-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1150-TRUE16-NEXT:    s_add_i32 s9, s9, -11
+; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s9, 11
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v4.l, v0.h
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
-; GFX1150-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v4.l, v2.l
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.l, v7.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.h
-; GFX1150-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v5
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_21
+; GFX1150-TRUE16-NEXT:  ; %bb.22: ; %Flow125
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v6, s9
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1150-TRUE16-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v4, v6
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v4, -v5, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v0, v4, v1
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v4, -v5, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v1, v4, v1
-; GFX1150-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v7.l, v1.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v5.l
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, s7
+; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fmac_f16_e32 v4.l, v0.l, v7.l
-; GFX1150-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.l
-; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1150-TRUE16-NEXT:  .LBB10_24:
+; GFX1150-TRUE16-NEXT:    s_lshr_b32 s10, s7, 16
+; GFX1150-TRUE16-NEXT:    s_lshr_b32 s9, s2, 16
+; GFX1150-TRUE16-NEXT:    s_and_b32 s7, s10, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_and_b32 s11, s9, 0x7fff
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s12, s7
+; GFX1150-TRUE16-NEXT:    s_cvt_f32_f16 s11, s11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-TRUE16-NEXT:    s_cmp_ngt_f32 s12, s11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_26
+; GFX1150-TRUE16-NEXT:  ; %bb.25: ; %frem.else86
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v3.l, s10
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_eq_f32 s12, s11
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s13, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v4, v3
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v3.l, s10, v3.l, s13
+; GFX1150-TRUE16-NEXT:    s_cbranch_execz .LBB10_27
+; GFX1150-TRUE16-NEXT:    s_branch .LBB10_32
+; GFX1150-TRUE16-NEXT:  .LBB10_26:
+; GFX1150-TRUE16-NEXT:    ; implicit-def: $vgpr3
+; GFX1150-TRUE16-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, s11
+; GFX1150-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s12
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v3, 11
+; GFX1150-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s12, v6
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT:    v_readfirstlane_b32 s11, v3
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-TRUE16-NEXT:    v_rcp_f32_e32 v9, v8
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_not_b32_e32 v7, v3
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1150-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v0, v3 op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v0, v7, v1
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v0, v3 op_sel_hi:[1,0,1]
-; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v1, v7, v1
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
+; GFX1150-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1150-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1150-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX1150-TRUE16-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX1150-TRUE16-NEXT:    s_sub_i32 s11, s12, s11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_add_i32 s11, s11, 11
+; GFX1150-TRUE16-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX1150-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1150-TRUE16-NEXT:    s_add_i32 s11, s11, -11
+; GFX1150-TRUE16-NEXT:    s_cmp_gt_i32 s11, 11
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v5, v8, v6
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT:    v_fma_f32 v5, v5, v4, v8
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
-; GFX1150-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v5.l, v0.h
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
+; GFX1150-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_29
+; GFX1150-TRUE16-NEXT:  ; %bb.30: ; %Flow
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v7, s11
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1150-TRUE16-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v5, v5, v7
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
-; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1150-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1150-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v5.l, v3.l
-; GFX1150-TRUE16-NEXT:    v_pack_b32_f16 v3, v0.l, v4.l
-; GFX1150-TRUE16-NEXT:    global_store_b64 v6, v[2:3], s[0:1]
+; GFX1150-TRUE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1150-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
+; GFX1150-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1150-TRUE16-NEXT:    v_mov_b16_e32 v4.l, s10
+; GFX1150-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, v4
+; GFX1150-TRUE16-NEXT:  .LBB10_32: ; %Flow124
+; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s4, 0
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s3, 0x7c00
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    s_and_b32 s3, s3, s4
+; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s6, 0
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s3
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s5, 0x7c00
+; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    s_and_b32 s3, s4, s3
+; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s2, 0
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v4.l, 0x7e00, v1.l, s3
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s8, 0x7c00
+; GFX1150-TRUE16-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s3, s2
+; GFX1150-TRUE16-NEXT:    s_cmp_lg_f16 s9, 0
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v2.l, s2
+; GFX1150-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT:    s_cmp_nge_f16 s7, 0x7c00
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX1150-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-TRUE16-NEXT:    s_and_b32 s2, s3, s2
+; GFX1150-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT:    v_cndmask_b16 v3.l, 0x7e00, v3.l, s2
+; GFX1150-TRUE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX1150-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX1150-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1150-FAKE16-LABEL: frem_v4f16:
 ; GFX1150-FAKE16:       ; %bb.0:
 ; GFX1150-FAKE16-NEXT:    s_clause 0x1
 ; GFX1150-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1150-FAKE16-NEXT:    s_load_b64 s[8:9], s[4:5], 0x34
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1150-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1150-FAKE16-NEXT:    s_clause 0x1
-; GFX1150-FAKE16-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX1150-FAKE16-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
-; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(1)
-; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX1150-FAKE16-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
 ; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v7
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v8, v8
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v6, v6, v8
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1150-FAKE16-NEXT:    global_load_b64 v[0:1], v2, s[8:9] offset:32
+; GFX1150-FAKE16-NEXT:    s_and_b32 s3, s5, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s8, s3
+; GFX1150-FAKE16-NEXT:    s_waitcnt vmcnt(0)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX1150-FAKE16-NEXT:    s_and_b32 s6, s4, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s6, s6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-FAKE16-NEXT:    s_cmp_ngt_f32 s8, s6
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_2
+; GFX1150-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s8, s6
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, 0, s5
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s5, v0, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_3
+; GFX1150-FAKE16-NEXT:    s_branch .LBB10_8
+; GFX1150-FAKE16-NEXT:  .LBB10_2:
+; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1150-FAKE16-NEXT:  .LBB10_3: ; %frem.compute
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s8
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s8, v3
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s6, v0
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v6, v9, v8
+; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX1150-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-FAKE16-NEXT:    s_sub_i32 s6, s8, s6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_add_i32 s6, s6, 11
+; GFX1150-FAKE16-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1150-FAKE16-NEXT:    s_add_i32 s6, s6, -11
+; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s6, 11
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_5
+; GFX1150-FAKE16-NEXT:  ; %bb.6: ; %Flow133
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, s6
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1150-FAKE16-NEXT:  .LBB10_7: ; %frem.loop_exit
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, v4
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v8, v9, v8
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff800000, v8
-; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v6, v8, v6
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v6, v6, v7, v5
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s5
+; GFX1150-FAKE16-NEXT:  .LBB10_8:
+; GFX1150-FAKE16-NEXT:    s_lshr_b32 s8, s5, 16
+; GFX1150-FAKE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1150-FAKE16-NEXT:    s_and_b32 s5, s8, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_and_b32 s9, s6, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s10, s5
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-FAKE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_10
+; GFX1150-FAKE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, 0, s8
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s8, v1, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_11
+; GFX1150-FAKE16-NEXT:    s_branch .LBB10_16
+; GFX1150-FAKE16-NEXT:  .LBB10_10:
+; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1150-FAKE16-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s9
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s10
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s10, v4
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s9, v1
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v6, v6
-; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x8000, v6
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1150-FAKE16-NEXT:    v_fmac_f16_e32 v5, v6, v7
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v2
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v0
-; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v6, v6, v7
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v8, -v2, v6, v0 op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v6, v8, v7
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v8, -v2, v6, v0 op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v8, v7
-; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff800000, v7
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX1150-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1150-FAKE16-NEXT:    s_sub_i32 s9, s10, s9
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_add_i32 s9, s9, 11
+; GFX1150-FAKE16-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1150-FAKE16-NEXT:    s_add_i32 s9, s9, -11
+; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s9, 11
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_13
+; GFX1150-FAKE16-NEXT:  ; %bb.14: ; %Flow129
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, s9
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1150-FAKE16-NEXT:  .LBB10_15: ; %frem.loop_exit28
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, v5
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v6, v7, v6
-; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v6, v6, v2, v0
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v6, v6
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x8000, v6
-; GFX1150-FAKE16-NEXT:    v_fma_f16 v0, v6, v2, v0
-; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
-; GFX1150-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s8
+; GFX1150-FAKE16-NEXT:  .LBB10_16:
+; GFX1150-FAKE16-NEXT:    s_and_b32 s8, s7, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_and_b32 s9, s2, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s10, s8
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-FAKE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_18
+; GFX1150-FAKE16-NEXT:  ; %bb.17: ; %frem.else53
+; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, 0, s7
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v2, s7, v2, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_19
+; GFX1150-FAKE16-NEXT:    s_branch .LBB10_24
+; GFX1150-FAKE16-NEXT:  .LBB10_18:
+; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1150-FAKE16-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s10
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s10
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v5
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s10, v5
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s9, v2
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v8, -v3, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX1150-FAKE16-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX1150-FAKE16-NEXT:    s_sub_i32 s9, s10, s9
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_add_i32 s9, s9, 11
+; GFX1150-FAKE16-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1150-FAKE16-NEXT:    s_add_i32 s9, s9, -11
+; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s9, 11
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v5, v8, v7
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v8, -v3, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v7, v8, v7
-; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff800000, v7
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_21
+; GFX1150-FAKE16-NEXT:  ; %bb.22: ; %Flow125
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v6, s9
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1150-FAKE16-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v4, v6
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v5, v7, v5
-; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v5, v5, v6, v2
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v5, v5
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x8000, v5
-; GFX1150-FAKE16-NEXT:    v_fmac_f16_e32 v2, v5, v6
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v3
-; GFX1150-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v1
-; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v6
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s7
+; GFX1150-FAKE16-NEXT:  .LBB10_24:
+; GFX1150-FAKE16-NEXT:    s_lshr_b32 s10, s7, 16
+; GFX1150-FAKE16-NEXT:    s_lshr_b32 s9, s2, 16
+; GFX1150-FAKE16-NEXT:    s_and_b32 s7, s10, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_and_b32 s11, s9, 0x7fff
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s12, s7
+; GFX1150-FAKE16-NEXT:    s_cvt_f32_f16 s11, s11
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1150-FAKE16-NEXT:    s_cmp_ngt_f32 s12, s11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_26
+; GFX1150-FAKE16-NEXT:  ; %bb.25: ; %frem.else86
+; GFX1150-FAKE16-NEXT:    s_cmp_eq_f32 s12, s11
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, 0, s10
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, s10, v3, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cbranch_execz .LBB10_27
+; GFX1150-FAKE16-NEXT:    s_branch .LBB10_32
+; GFX1150-FAKE16-NEXT:  .LBB10_26:
+; GFX1150-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX1150-FAKE16-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, s11
+; GFX1150-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s12
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v3, 11
+; GFX1150-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s12, v6
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-FAKE16-NEXT:    v_readfirstlane_b32 s11, v3
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-FAKE16-NEXT:    v_rcp_f32_e32 v9, v8
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v5, v7, v6
+; GFX1150-FAKE16-NEXT:    v_not_b32_e32 v7, v3
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1150-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v6, v7, v6
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
+; GFX1150-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1150-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1150-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX1150-FAKE16-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX1150-FAKE16-NEXT:    s_sub_i32 s11, s12, s11
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    s_add_i32 s11, s11, 11
+; GFX1150-FAKE16-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX1150-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1150-FAKE16-NEXT:    s_add_i32 s11, s11, -11
+; GFX1150-FAKE16-NEXT:    s_cmp_gt_i32 s11, 11
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX1150-FAKE16-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v5, v8, v6
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x8000, v5
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-FAKE16-NEXT:    v_fma_f32 v5, v5, v4, v8
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
+; GFX1150-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_29
+; GFX1150-FAKE16-NEXT:  ; %bb.30: ; %Flow
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v7, s11
+; GFX1150-FAKE16-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1150-FAKE16-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v5, v5, v7
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1150-FAKE16-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-FAKE16-NEXT:    v_fmac_f16_e32 v1, v5, v3
-; GFX1150-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v2
-; GFX1150-FAKE16-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX1150-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1150-FAKE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-FAKE16-NEXT:    v_add_f32_e32 v4, v5, v4
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1150-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s10
+; GFX1150-FAKE16-NEXT:  .LBB10_32: ; %Flow124
+; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s4, 0
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s3, 0x7c00
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s4
+; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s6, 0
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s5, 0x7c00
+; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s4, s3
+; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s2, 0
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x7e00, v1, vcc_lo
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s8, 0x7c00
+; GFX1150-FAKE16-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1150-FAKE16-NEXT:    s_cmp_lg_f16 s9, 0
+; GFX1150-FAKE16-NEXT:    v_dual_cndmask_b32 v1, 0x7e00, v2 :: v_dual_mov_b32 v2, 0
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-FAKE16-NEXT:    s_cmp_nge_f16 s7, 0x7c00
+; GFX1150-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX1150-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1150-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v3, vcc_lo
+; GFX1150-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX1150-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX1150-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1200-TRUE16-LABEL: frem_v4f16:
 ; GFX1200-TRUE16:       ; %bb.0:
 ; GFX1200-TRUE16-NEXT:    s_clause 0x1
 ; GFX1200-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, 0
+; GFX1200-TRUE16-NEXT:    s_load_b64 s[8:9], s[4:5], 0x34
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1200-TRUE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1200-TRUE16-NEXT:    s_clause 0x1
-; GFX1200-TRUE16-NEXT:    global_load_b64 v[2:3], v6, s[2:3]
-; GFX1200-TRUE16-NEXT:    global_load_b64 v[4:5], v6, s[4:5] offset:32
-; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x1
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.h
+; GFX1200-TRUE16-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1200-TRUE16-NEXT:    global_load_b64 v[0:1], v2, s[8:9] offset:32
+; GFX1200-TRUE16-NEXT:    s_and_b32 s3, s5, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s8, s3
 ; GFX1200-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.h
-; GFX1200-TRUE16-NEXT:    v_lshrrev_b32_e32 v8, 16, v4
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX1200-TRUE16-NEXT:    s_and_b32 s6, s4, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s6, s6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1200-TRUE16-NEXT:    s_cmp_ngt_f32 s8, s6
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_2
+; GFX1200-TRUE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s5
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s8, s6
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s9, -1, 0
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, v7, v1
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, s5, v0.l, s9
+; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_3
+; GFX1200-TRUE16-NEXT:    s_branch .LBB10_8
+; GFX1200-TRUE16-NEXT:  .LBB10_2:
+; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1200-TRUE16-NEXT:  .LBB10_3: ; %frem.compute
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v0, s8
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s8, v3
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s6, v0
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v7, -v4, v0, v2 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, v7, v1
-; GFX1200-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v7.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v8.l, v1.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v4.l
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX1200-TRUE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s6, s8, s6
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s6, s6, 11
+; GFX1200-TRUE16-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fmac_f16_e32 v7.l, v0.l, v8.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v2.l
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s6, s6, -11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s6, 11
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v8, -v4, v0, v2 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, v8, v1
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_5
+; GFX1200-TRUE16-NEXT:  ; %bb.6: ; %Flow133
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v4, s6
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1200-TRUE16-NEXT:  .LBB10_7: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, v4
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v8, -v4, v0, v2 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, v8, v1
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v5.h
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s5
 ; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l
-; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1200-TRUE16-NEXT:  .LBB10_8:
+; GFX1200-TRUE16-NEXT:    s_lshr_b32 s8, s5, 16
+; GFX1200-TRUE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s5, s8, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_and_b32 s9, s6, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s10, s5
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-TRUE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_10
+; GFX1200-TRUE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, s8
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s11, -1, 0
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v4.l, v0.h
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v2, v1
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, s8, v1.l, s11
+; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_11
+; GFX1200-TRUE16-NEXT:    s_branch .LBB10_16
+; GFX1200-TRUE16-NEXT:  .LBB10_10:
+; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1200-TRUE16-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v1, s10
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s10, v4
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s9, v1
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v7, v6
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
-; GFX1200-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v4.l, v2.l
+; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX1200-TRUE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s9, s10, s9
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s9, s9, 11
+; GFX1200-TRUE16-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_pack_b32_f16 v2, v0.l, v7.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.h
-; GFX1200-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v5
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s9, s9, -11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s9, 11
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v4, -v5, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, v4, v1
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v4, -v5, v0, v3 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, v4, v1
-; GFX1200-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_13
+; GFX1200-TRUE16-NEXT:  ; %bb.14: ; %Flow129
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, s9
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1200-TRUE16-NEXT:  .LBB10_15: ; %frem.loop_exit28
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v4.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v7.l, v1.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v1, v5.l
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s8
+; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1200-TRUE16-NEXT:  .LBB10_16:
+; GFX1200-TRUE16-NEXT:    s_and_b32 s8, s7, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_and_b32 s9, s2, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s10, s8
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-TRUE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_18
+; GFX1200-TRUE16-NEXT:  ; %bb.17: ; %frem.else53
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v2.l, s7
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s11, -1, 0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v3, v2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v2.l, s7, v2.l, s11
+; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_19
+; GFX1200-TRUE16-NEXT:    s_branch .LBB10_24
+; GFX1200-TRUE16-NEXT:  .LBB10_18:
+; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v2, s10
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s10, v5
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s9, v2
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX1200-TRUE16-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s9, s10, s9
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s9, s9, 11
+; GFX1200-TRUE16-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s9, s9, -11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s9, 11
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_21
+; GFX1200-TRUE16-NEXT:  ; %bb.22: ; %Flow125
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v6, s9
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1200-TRUE16-NEXT:  .LBB10_23: ; %frem.loop_exit61
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v1, v1
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, s7
+; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v2.l, v2
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fmac_f16_e32 v4.l, v0.l, v7.l
-; GFX1200-TRUE16-NEXT:    v_cvt_f32_f16_e32 v0, v3.l
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v0, v0, v1
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1200-TRUE16-NEXT:  .LBB10_24:
+; GFX1200-TRUE16-NEXT:    s_lshr_b32 s10, s7, 16
+; GFX1200-TRUE16-NEXT:    s_lshr_b32 s9, s2, 16
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s7, s10, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_and_b32 s11, s9, 0x7fff
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s12, s7
+; GFX1200-TRUE16-NEXT:    s_cvt_f32_f16 s11, s11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-TRUE16-NEXT:    s_cmp_ngt_f32 s12, s11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc0 .LBB10_26
+; GFX1200-TRUE16-NEXT:  ; %bb.25: ; %frem.else86
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v3.l, s10
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v4.l, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_eq_f32 s12, s11
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s13, -1, 0
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v0, v3 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v0, v7, v1
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v4, v3
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v3.l, s10, v3.l, s13
+; GFX1200-TRUE16-NEXT:    s_cbranch_execz .LBB10_27
+; GFX1200-TRUE16-NEXT:    s_branch .LBB10_32
+; GFX1200-TRUE16-NEXT:  .LBB10_26:
+; GFX1200-TRUE16-NEXT:    ; implicit-def: $vgpr3
+; GFX1200-TRUE16-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v4, s11
+; GFX1200-TRUE16-NEXT:    v_frexp_mant_f32_e32 v3, s12
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v3, 11
+; GFX1200-TRUE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s12, v6
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT:    v_readfirstlane_b32 s11, v3
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-TRUE16-NEXT:    v_rcp_f32_e32 v9, v8
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_mix_f32 v7, -v5, v0, v3 op_sel_hi:[1,0,1]
-; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v1, v7, v1
+; GFX1200-TRUE16-NEXT:    v_not_b32_e32 v7, v3
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1200-TRUE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 15
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff800000, v1
-; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v0, v1, v0
-; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v3.l
-; GFX1200-TRUE16-NEXT:    v_div_fixup_f16 v0.l, v0.l, v5.l, v0.h
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
+; GFX1200-TRUE16-NEXT:    s_denorm_mode 12
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1200-TRUE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1200-TRUE16-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX1200-TRUE16-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX1200-TRUE16-NEXT:    s_sub_co_i32 s11, s12, s11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s11, s11, 11
+; GFX1200-TRUE16-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX1200-TRUE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_add_co_i32 s11, s11, -11
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_cmp_gt_i32 s11, 11
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v5, v8, v6
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_fma_f32 v5, v5, v4, v8
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v5, 11
+; GFX1200-TRUE16-NEXT:    s_cbranch_scc1 .LBB10_29
+; GFX1200-TRUE16-NEXT:  ; %bb.30: ; %Flow
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v7, s11
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1200-TRUE16-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v5, v5, v7
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_trunc_f16_e32 v0.l, v0.l
-; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v0, 0x8000, v0
+; GFX1200-TRUE16-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1200-TRUE16-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT:    v_fma_f16 v0.l, v0.l, v5.l, v3.l
-; GFX1200-TRUE16-NEXT:    v_pack_b32_f16 v3, v0.l, v4.l
-; GFX1200-TRUE16-NEXT:    global_store_b64 v6, v[2:3], s[0:1]
+; GFX1200-TRUE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1200-TRUE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-TRUE16-NEXT:    v_add_f32_e32 v4, v5, v4
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-TRUE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1200-TRUE16-NEXT:    v_mov_b16_e32 v4.l, s10
+; GFX1200-TRUE16-NEXT:    v_cvt_f16_f32_e32 v3.l, v3
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, v4
+; GFX1200-TRUE16-NEXT:  .LBB10_32: ; %Flow124
+; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s4, 0
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s3, 0x7c00
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s3, s3, s4
+; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s6, 0
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v0.l, 0x7e00, v0.l, s3
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s5, 0x7c00
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s3, s4, s3
+; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s2, 0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v4.l, 0x7e00, v1.l, s3
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s8, 0x7c00
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s3, s2
+; GFX1200-TRUE16-NEXT:    s_cmp_lg_f16 s9, 0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v1.l, 0x7e00, v2.l, s2
+; GFX1200-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT:    s_cmp_nge_f16 s7, 0x7c00
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX1200-TRUE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    s_and_b32 s2, s3, s2
+; GFX1200-TRUE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-TRUE16-NEXT:    v_cndmask_b16 v3.l, 0x7e00, v3.l, s2
+; GFX1200-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX1200-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX1200-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1200-FAKE16-LABEL: frem_v4f16:
 ; GFX1200-FAKE16:       ; %bb.0:
 ; GFX1200-FAKE16-NEXT:    s_clause 0x1
 ; GFX1200-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1200-FAKE16-NEXT:    s_load_b64 s[8:9], s[4:5], 0x34
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1200-FAKE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1200-FAKE16-NEXT:    s_clause 0x1
-; GFX1200-FAKE16-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX1200-FAKE16-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
-; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x1
-; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, 16, v0
+; GFX1200-FAKE16-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
 ; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v5
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v8, v7
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v8, v8
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v6, v6, v8
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s5, v0
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s7, v1
+; GFX1200-FAKE16-NEXT:    global_load_b64 v[0:1], v2, s[8:9] offset:32
+; GFX1200-FAKE16-NEXT:    s_and_b32 s3, s5, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s8, s3
+; GFX1200-FAKE16-NEXT:    s_wait_loadcnt 0x0
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s2, v1
+; GFX1200-FAKE16-NEXT:    s_and_b32 s6, s4, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s6, s6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1200-FAKE16-NEXT:    s_cmp_ngt_f32 s8, s6
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_2
+; GFX1200-FAKE16-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s8, s6
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, 0, s5
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, s5, v0, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_3
+; GFX1200-FAKE16-NEXT:    s_branch .LBB10_8
+; GFX1200-FAKE16-NEXT:  .LBB10_2:
+; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr0
+; GFX1200-FAKE16-NEXT:  .LBB10_3: ; %frem.compute
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s6
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v0, s8
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v0, 11
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s8, v3
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s6, v0
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v4, v0
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v5, v7, v3
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v6, v9, v8
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_7
+; GFX1200-FAKE16-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s6, s8, s6
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s6, s6, 11
+; GFX1200-FAKE16-NEXT:  .LBB10_5: ; %frem.loop_body
+; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s6, s6, -11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s6, 11
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v9, -v2, v6, v0 op_sel:[1,0,1] op_sel_hi:[1,0,1]
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v8, v9, v8
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_5
+; GFX1200-FAKE16-NEXT:  ; %bb.6: ; %Flow133
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, s6
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1200-FAKE16-NEXT:  .LBB10_7: ; %frem.loop_exit
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, v4
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v8, 0xff800000, v8
-; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v6, v8, v6
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v6, v6
-; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v6, v6, v7, v5
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v6, v6
-; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x8000, v6
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT:    v_fmac_f16_e32 v5, v6, v7
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v2
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v0
-; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, s5
+; GFX1200-FAKE16-NEXT:  .LBB10_8:
+; GFX1200-FAKE16-NEXT:    s_lshr_b32 s8, s5, 16
+; GFX1200-FAKE16-NEXT:    s_lshr_b32 s6, s4, 16
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_and_b32 s5, s8, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_and_b32 s9, s6, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s10, s5
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-FAKE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_10
+; GFX1200-FAKE16-NEXT:  ; %bb.9: ; %frem.else20
+; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, 0, s8
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v1, s8, v1, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_11
+; GFX1200-FAKE16-NEXT:    s_branch .LBB10_16
+; GFX1200-FAKE16-NEXT:  .LBB10_10:
+; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr1
+; GFX1200-FAKE16-NEXT:  .LBB10_11: ; %frem.compute19
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s9
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v1, s10
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v1, 11
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s10, v4
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s9, v1
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v5, v1
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v6, v6, v7
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v8, -v2, v6, v0 op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v6, v8, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_15
+; GFX1200-FAKE16-NEXT:  ; %bb.12: ; %frem.loop_body27.preheader
+; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s9, s10, s9
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s9, s9, 11
+; GFX1200-FAKE16-NEXT:  .LBB10_13: ; %frem.loop_body27
+; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s9, s9, -11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s9, 11
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v6, v8, v7
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v8, -v2, v6, v0 op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v8, v7
-; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff800000, v7
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_13
+; GFX1200-FAKE16-NEXT:  ; %bb.14: ; %Flow129
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, s9
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1200-FAKE16-NEXT:  .LBB10_15: ; %frem.loop_exit28
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, v5
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v6, v7, v6
-; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v6, v6, v2, v0
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v6, v6
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x8000, v6
-; GFX1200-FAKE16-NEXT:    v_fma_f16 v0, v6, v2, v0
-; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v3
-; GFX1200-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, s8
+; GFX1200-FAKE16-NEXT:  .LBB10_16:
+; GFX1200-FAKE16-NEXT:    s_and_b32 s8, s7, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_and_b32 s9, s2, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s10, s8
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s9, s9
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-FAKE16-NEXT:    s_cmp_ngt_f32 s10, s9
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_18
+; GFX1200-FAKE16-NEXT:  ; %bb.17: ; %frem.else53
+; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s10, s9
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, 0, s7
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v2, s7, v2, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_19
+; GFX1200-FAKE16-NEXT:    s_branch .LBB10_24
+; GFX1200-FAKE16-NEXT:  .LBB10_18:
+; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr2
+; GFX1200-FAKE16-NEXT:  .LBB10_19: ; %frem.compute52
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s9
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v2, s10
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v5, s10
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v5
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v7, v6
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v2
-; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v7, v7
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v2, 11
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s10, v5
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s9, v2
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v6, v2
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v7
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v8, -v3, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_23
+; GFX1200-FAKE16-NEXT:  ; %bb.20: ; %frem.loop_body60.preheader
+; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s9, s10, s9
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s9, s9, 11
+; GFX1200-FAKE16-NEXT:  .LBB10_21: ; %frem.loop_body60
+; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s9, s9, -11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s9, 11
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v4, v7, v5
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v5, v8, v7
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v8, -v3, v5, v1 op_sel:[1,0,1] op_sel_hi:[1,0,1]
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_21
+; GFX1200-FAKE16-NEXT:  ; %bb.22: ; %Flow125
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v6, s9
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1200-FAKE16-NEXT:  .LBB10_23: ; %frem.loop_exit61
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v7, v8, v7
-; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v7, 0xff800000, v7
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, s7
+; GFX1200-FAKE16-NEXT:  .LBB10_24:
+; GFX1200-FAKE16-NEXT:    s_lshr_b32 s10, s7, 16
+; GFX1200-FAKE16-NEXT:    s_lshr_b32 s9, s2, 16
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_and_b32 s7, s10, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_and_b32 s11, s9, 0x7fff
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s12, s7
+; GFX1200-FAKE16-NEXT:    s_cvt_f32_f16 s11, s11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_2)
+; GFX1200-FAKE16-NEXT:    s_cmp_ngt_f32 s12, s11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc0 .LBB10_26
+; GFX1200-FAKE16-NEXT:  ; %bb.25: ; %frem.else86
+; GFX1200-FAKE16-NEXT:    s_cmp_eq_f32 s12, s11
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, 0, s10
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, s10, v3, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cbranch_execz .LBB10_27
+; GFX1200-FAKE16-NEXT:    s_branch .LBB10_32
+; GFX1200-FAKE16-NEXT:  .LBB10_26:
+; GFX1200-FAKE16-NEXT:    ; implicit-def: $vgpr3
+; GFX1200-FAKE16-NEXT:  .LBB10_27: ; %frem.compute85
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v4, s11
+; GFX1200-FAKE16-NEXT:    v_frexp_mant_f32_e32 v3, s12
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v3, 11
+; GFX1200-FAKE16-NEXT:    v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s12, v6
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-FAKE16-NEXT:    v_readfirstlane_b32 s11, v3
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v9, v8
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v5, v7, v5
-; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX1200-FAKE16-NEXT:    v_not_b32_e32 v7, v3
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1200-FAKE16-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 15
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v9, v10, v9
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v5, v5, v6, v2
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v5, v5
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v11, -v8, v10, v6
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x8000, v5
-; GFX1200-FAKE16-NEXT:    v_fmac_f16_e32 v2, v5, v6
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v6, v3
-; GFX1200-FAKE16-NEXT:    v_cvt_f32_f16_e32 v5, v1
-; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v5, v6
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v10, v11, v9
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v6, -v8, v10, v6
+; GFX1200-FAKE16-NEXT:    s_denorm_mode 12
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-FAKE16-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1200-FAKE16-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1200-FAKE16-NEXT:    s_cbranch_vccnz .LBB10_31
+; GFX1200-FAKE16-NEXT:  ; %bb.28: ; %frem.loop_body93.preheader
+; GFX1200-FAKE16-NEXT:    s_sub_co_i32 s11, s12, s11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s11, s11, 11
+; GFX1200-FAKE16-NEXT:  .LBB10_29: ; %frem.loop_body93
+; GFX1200-FAKE16-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_add_co_i32 s11, s11, -11
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_cmp_gt_i32 s11, 11
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v5, v8, v6
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v5, v7, v6
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fma_mix_f32 v7, -v3, v5, v1 op_sel_hi:[1,0,1]
-; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v6, v7, v6
+; GFX1200-FAKE16-NEXT:    v_fma_f32 v5, v5, v4, v8
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v6, 0xff800000, v6
-; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v5, 11
+; GFX1200-FAKE16-NEXT:    s_cbranch_scc1 .LBB10_29
+; GFX1200-FAKE16-NEXT:  ; %bb.30: ; %Flow
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v7, s11
+; GFX1200-FAKE16-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1200-FAKE16-NEXT:  .LBB10_31: ; %frem.loop_exit94
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_add_nc_u32_e32 v7, -10, v7
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v5, v5, v7
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v5, v5
-; GFX1200-FAKE16-NEXT:    v_div_fixup_f16 v5, v5, v3, v1
+; GFX1200-FAKE16-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1200-FAKE16-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_trunc_f16_e32 v5, v5
-; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v5, 0x8000, v5
+; GFX1200-FAKE16-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1200-FAKE16-NEXT:    v_fmac_f32_e32 v5, v6, v4
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-FAKE16-NEXT:    v_add_f32_e32 v4, v5, v4
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffd
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
 ; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-FAKE16-NEXT:    v_fmac_f16_e32 v1, v5, v3
-; GFX1200-FAKE16-NEXT:    v_pack_b32_f16 v1, v1, v2
-; GFX1200-FAKE16-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX1200-FAKE16-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1200-FAKE16-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, s10
+; GFX1200-FAKE16-NEXT:  .LBB10_32: ; %Flow124
+; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s4, 0
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s3, 0x7c00
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s4
+; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s6, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7e00, v0, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s5, 0x7c00
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s4, s3
+; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s2, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v4, 0x7e00, v1, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s8, 0x7c00
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT:    v_lshl_or_b32 v0, v4, 16, v0
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1200-FAKE16-NEXT:    s_cmp_lg_f16 s9, 0
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    v_dual_cndmask_b32 v1, 0x7e00, v2 :: v_dual_mov_b32 v2, 0
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-FAKE16-NEXT:    s_cmp_nge_f16 s7, 0x7c00
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX1200-FAKE16-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-FAKE16-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1200-FAKE16-NEXT:    s_wait_alu 0xfffe
+; GFX1200-FAKE16-NEXT:    v_cndmask_b32_e32 v3, 0x7e00, v3, vcc_lo
+; GFX1200-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX1200-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX1200-FAKE16-NEXT:    s_endpgm
                         ptr addrspace(1) %in2) #0 {
    %gep2 = getelementptr <4 x half>, ptr addrspace(1) %in2, i32 4
@@ -4082,103 +11683,357 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
 define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
 ; SI-LABEL: frem_v2f32:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s0, s8
-; SI-NEXT:    s_mov_b32 s1, s9
-; SI-NEXT:    s_mov_b32 s8, s10
-; SI-NEXT:    s_mov_b32 s9, s11
-; SI-NEXT:    s_mov_b32 s10, s2
-; SI-NEXT:    s_mov_b32 s11, s3
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_mov_b32 s7, s3
+; SI-NEXT:    s_mov_b32 s8, s2
+; SI-NEXT:    s_mov_b32 s9, s3
+; SI-NEXT:    s_mov_b32 s6, s10
+; SI-NEXT:    s_mov_b32 s7, s11
 ; SI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
 ; SI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[4:7], 0 offset:32
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_div_scale_f32 v4, vcc, v1, v3, v1
-; SI-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; SI-NEXT:    v_rcp_f32_e32 v6, v5
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    s_cbranch_vccz .LBB11_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v4, s2, 0, v0
+; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; SI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB11_3
+; SI-NEXT:    s_branch .LBB11_8
+; SI-NEXT:  .LBB11_2:
+; SI-NEXT:    ; implicit-def: $vgpr4
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB11_3: ; %frem.compute
+; SI-NEXT:    s_mov_b32 s6, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v0|, s6
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v4, v0
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s4, v4
+; SI-NEXT:    s_cselect_b32 s4, s4, 0
+; SI-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; SI-NEXT:    v_cndmask_b32_e64 v4, |v0|, v4, s[2:3]
+; SI-NEXT:    v_ldexp_f32_e64 v5, v4, 12
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v2|, s6
+; SI-NEXT:    v_frexp_mant_f32_e64 v4, |v2|
+; SI-NEXT:    v_cndmask_b32_e64 v4, |v2|, v4, s[2:3]
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v6, v2
+; SI-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v6
+; SI-NEXT:    s_cselect_b32 s5, s2, 0
+; SI-NEXT:    s_add_i32 s2, s5, -1
+; SI-NEXT:    v_ldexp_f32_e64 v4, v4, 1
+; SI-NEXT:    s_not_b32 s3, s2
+; SI-NEXT:    s_add_i32 s3, s3, s4
+; SI-NEXT:    v_div_scale_f32 v6, vcc, 1.0, v4, 1.0
+; SI-NEXT:    v_div_scale_f32 v7, s[6:7], v4, v4, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v8, v7
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; SI-NEXT:    v_fma_f32 v6, v7, v6, v6
-; SI-NEXT:    v_mul_f32_e32 v7, v4, v6
-; SI-NEXT:    v_fma_f32 v8, -v5, v7, v4
-; SI-NEXT:    v_fma_f32 v7, v8, v6, v7
-; SI-NEXT:    v_fma_f32 v4, -v5, v7, v4
+; SI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; SI-NEXT:    v_fma_f32 v8, v9, v8, v8
+; SI-NEXT:    v_mul_f32_e32 v9, v6, v8
+; SI-NEXT:    v_fma_f32 v10, -v7, v9, v6
+; SI-NEXT:    v_fma_f32 v9, v10, v8, v9
+; SI-NEXT:    v_fma_f32 v6, -v7, v9, v6
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
-; SI-NEXT:    v_div_fixup_f32 v4, v4, v3, v1
-; SI-NEXT:    v_trunc_f32_e32 v4, v4
-; SI-NEXT:    v_fma_f32 v1, -v4, v3, v1
-; SI-NEXT:    v_div_scale_f32 v3, vcc, v0, v2, v0
-; SI-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
-; SI-NEXT:    v_rcp_f32_e32 v5, v4
+; SI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
+; SI-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s3, 13
+; SI-NEXT:    s_cbranch_scc1 .LBB11_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s3, s4, s5
+; SI-NEXT:    s_add_i32 s3, s3, 12
+; SI-NEXT:  .LBB11_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v7, v5
+; SI-NEXT:    v_mul_f32_e32 v5, v7, v6
+; SI-NEXT:    v_rndne_f32_e32 v5, v5
+; SI-NEXT:    v_fma_f32 v5, -v5, v4, v7
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT:    v_add_f32_e32 v8, v5, v4
+; SI-NEXT:    v_cndmask_b32_e32 v5, v5, v8, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, 12
+; SI-NEXT:    s_add_i32 s3, s3, -12
+; SI-NEXT:    s_cmp_gt_i32 s3, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB11_5
+; SI-NEXT:  ; %bb.6: ; %Flow51
+; SI-NEXT:    v_mov_b32_e32 v5, v7
+; SI-NEXT:  .LBB11_7: ; %frem.loop_exit
+; SI-NEXT:    s_add_i32 s3, s3, -11
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, s3
+; SI-NEXT:    v_mul_f32_e32 v6, v5, v6
+; SI-NEXT:    v_rndne_f32_e32 v6, v6
+; SI-NEXT:    v_fma_f32 v5, -v6, v4, v5
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v5
+; SI-NEXT:    v_add_f32_e32 v4, v5, v4
+; SI-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v4, v4, s2
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v4, s2, v4, v0
+; SI-NEXT:  .LBB11_8:
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    s_cbranch_vccz .LBB11_10
+; SI-NEXT:  ; %bb.9: ; %frem.else16
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v5, s2, 0, v1
+; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; SI-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB11_11
+; SI-NEXT:    s_branch .LBB11_16
+; SI-NEXT:  .LBB11_10:
+; SI-NEXT:    ; implicit-def: $vgpr5
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB11_11: ; %frem.compute15
+; SI-NEXT:    s_mov_b32 s6, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v1|, s6
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v5, v1
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s4, v5
+; SI-NEXT:    s_cselect_b32 s4, s4, 0
+; SI-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
+; SI-NEXT:    v_cndmask_b32_e64 v5, |v1|, v5, s[2:3]
+; SI-NEXT:    v_ldexp_f32_e64 v6, v5, 12
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v3|, s6
+; SI-NEXT:    v_frexp_mant_f32_e64 v5, |v3|
+; SI-NEXT:    v_cndmask_b32_e64 v5, |v3|, v5, s[2:3]
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v7, v3
+; SI-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v7
+; SI-NEXT:    s_cselect_b32 s5, s2, 0
+; SI-NEXT:    s_add_i32 s2, s5, -1
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, 1
+; SI-NEXT:    s_not_b32 s3, s2
+; SI-NEXT:    s_add_i32 s3, s3, s4
+; SI-NEXT:    v_div_scale_f32 v7, vcc, 1.0, v5, 1.0
+; SI-NEXT:    v_div_scale_f32 v8, s[6:7], v5, v5, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v9, v8
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
-; SI-NEXT:    v_fma_f32 v5, v6, v5, v5
-; SI-NEXT:    v_mul_f32_e32 v6, v3, v5
-; SI-NEXT:    v_fma_f32 v7, -v4, v6, v3
-; SI-NEXT:    v_fma_f32 v6, v7, v5, v6
-; SI-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
+; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
+; SI-NEXT:    v_mul_f32_e32 v10, v7, v9
+; SI-NEXT:    v_fma_f32 v11, -v8, v10, v7
+; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
+; SI-NEXT:    v_fma_f32 v7, -v8, v10, v7
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
-; SI-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
-; SI-NEXT:    v_trunc_f32_e32 v3, v3
-; SI-NEXT:    v_fma_f32 v0, -v3, v2, v0
+; SI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
+; SI-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s3, 13
+; SI-NEXT:    s_cbranch_scc1 .LBB11_15
+; SI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; SI-NEXT:    s_sub_i32 s3, s4, s5
+; SI-NEXT:    s_add_i32 s3, s3, 12
+; SI-NEXT:  .LBB11_13: ; %frem.loop_body23
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v8, v6
+; SI-NEXT:    v_mul_f32_e32 v6, v8, v7
+; SI-NEXT:    v_rndne_f32_e32 v6, v6
+; SI-NEXT:    v_fma_f32 v6, -v6, v5, v8
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; SI-NEXT:    v_add_f32_e32 v9, v6, v5
+; SI-NEXT:    v_cndmask_b32_e32 v6, v6, v9, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v6, v6, 12
+; SI-NEXT:    s_add_i32 s3, s3, -12
+; SI-NEXT:    s_cmp_gt_i32 s3, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB11_13
+; SI-NEXT:  ; %bb.14: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v6, v8
+; SI-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; SI-NEXT:    s_add_i32 s3, s3, -11
+; SI-NEXT:    v_ldexp_f32_e64 v6, v6, s3
+; SI-NEXT:    v_mul_f32_e32 v7, v6, v7
+; SI-NEXT:    v_rndne_f32_e32 v7, v7
+; SI-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; SI-NEXT:    v_add_f32_e32 v5, v6, v5
+; SI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v5, v5, s2
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v5, s2, v5, v1
+; SI-NEXT:  .LBB11_16: ; %Flow50
+; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
+; SI-NEXT:    s_mov_b32 s4, 0x7f800000
+; SI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; SI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; SI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
+; SI-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
+; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s4
+; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
 ; SI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: frem_v2f32:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    s_mov_b32 s6, s2
+; CI-NEXT:    s_mov_b32 s11, 0xf000
+; CI-NEXT:    s_mov_b32 s10, -1
+; CI-NEXT:    s_mov_b32 s6, s10
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_mov_b32 s0, s8
-; CI-NEXT:    s_mov_b32 s1, s9
-; CI-NEXT:    s_mov_b32 s8, s10
-; CI-NEXT:    s_mov_b32 s9, s11
-; CI-NEXT:    s_mov_b32 s10, s2
-; CI-NEXT:    s_mov_b32 s11, s3
-; CI-NEXT:    s_mov_b32 s7, s3
+; CI-NEXT:    s_mov_b32 s8, s2
+; CI-NEXT:    s_mov_b32 s9, s3
+; CI-NEXT:    s_mov_b32 s7, s11
 ; CI-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
 ; CI-NEXT:    buffer_load_dwordx2 v[2:3], off, s[4:7], 0 offset:32
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; CI-NEXT:    v_div_scale_f32 v4, vcc, v1, v3, v1
-; CI-NEXT:    v_rcp_f32_e32 v6, v5
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB11_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v4, s2, 0, v0
+; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; CI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
+; CI-NEXT:    s_cbranch_execz .LBB11_3
+; CI-NEXT:    s_branch .LBB11_8
+; CI-NEXT:  .LBB11_2:
+; CI-NEXT:    ; implicit-def: $vgpr4
+; CI-NEXT:  .LBB11_3: ; %frem.compute
+; CI-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
+; CI-NEXT:    v_ldexp_f32_e64 v5, v5, 1
+; CI-NEXT:    v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
+; CI-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
+; CI-NEXT:    v_ldexp_f32_e64 v7, v4, 12
+; CI-NEXT:    v_add_i32_e32 v4, vcc, -1, v10
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
+; CI-NEXT:    v_not_b32_e32 v6, v4
+; CI-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v12, v11
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; CI-NEXT:    v_fma_f32 v6, v7, v6, v6
-; CI-NEXT:    v_mul_f32_e32 v7, v4, v6
-; CI-NEXT:    v_fma_f32 v8, -v5, v7, v4
-; CI-NEXT:    v_fma_f32 v7, v8, v6, v7
-; CI-NEXT:    v_fma_f32 v4, -v5, v7, v4
+; CI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; CI-NEXT:    v_fma_f32 v12, v13, v12, v12
+; CI-NEXT:    v_mul_f32_e32 v13, v8, v12
+; CI-NEXT:    v_fma_f32 v14, -v11, v13, v8
+; CI-NEXT:    v_fma_f32 v13, v14, v12, v13
+; CI-NEXT:    v_fma_f32 v8, -v11, v13, v8
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v4, v4, v6, v7
-; CI-NEXT:    v_div_fixup_f32 v4, v4, v3, v1
-; CI-NEXT:    v_trunc_f32_e32 v4, v4
-; CI-NEXT:    v_fma_f32 v1, -v4, v3, v1
-; CI-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
-; CI-NEXT:    v_div_scale_f32 v3, vcc, v0, v2, v0
-; CI-NEXT:    v_rcp_f32_e32 v5, v4
+; CI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v6
+; CI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB11_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v6, vcc, v9, v10
+; CI-NEXT:    v_add_i32_e32 v6, vcc, 12, v6
+; CI-NEXT:  .LBB11_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v9, v7
+; CI-NEXT:    v_mul_f32_e32 v7, v9, v8
+; CI-NEXT:    v_rndne_f32_e32 v7, v7
+; CI-NEXT:    v_fma_f32 v7, -v7, v5, v9
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; CI-NEXT:    v_add_f32_e32 v10, v7, v5
+; CI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
+; CI-NEXT:    v_add_i32_e32 v6, vcc, -12, v6
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v6
+; CI-NEXT:    v_ldexp_f32_e64 v7, v7, 12
+; CI-NEXT:    s_cbranch_vccnz .LBB11_5
+; CI-NEXT:  ; %bb.6: ; %Flow51
+; CI-NEXT:    v_mov_b32_e32 v7, v9
+; CI-NEXT:  .LBB11_7: ; %frem.loop_exit
+; CI-NEXT:    v_add_i32_e32 v6, vcc, -11, v6
+; CI-NEXT:    v_ldexp_f32_e32 v6, v7, v6
+; CI-NEXT:    v_mul_f32_e32 v7, v6, v8
+; CI-NEXT:    v_rndne_f32_e32 v7, v7
+; CI-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; CI-NEXT:    v_add_f32_e32 v5, v6, v5
+; CI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v4, v5, v4
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v4, s2, v4, v0
+; CI-NEXT:  .LBB11_8:
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB11_10
+; CI-NEXT:  ; %bb.9: ; %frem.else16
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v5, s2, 0, v1
+; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; CI-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
+; CI-NEXT:    s_cbranch_execz .LBB11_11
+; CI-NEXT:    s_branch .LBB11_16
+; CI-NEXT:  .LBB11_10:
+; CI-NEXT:    ; implicit-def: $vgpr5
+; CI-NEXT:  .LBB11_11: ; %frem.compute15
+; CI-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
+; CI-NEXT:    v_ldexp_f32_e64 v6, v6, 1
+; CI-NEXT:    v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
+; CI-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
+; CI-NEXT:    v_ldexp_f32_e64 v8, v5, 12
+; CI-NEXT:    v_add_i32_e32 v5, vcc, -1, v11
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
+; CI-NEXT:    v_not_b32_e32 v7, v5
+; CI-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v13, v12
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
-; CI-NEXT:    v_fma_f32 v5, v6, v5, v5
-; CI-NEXT:    v_mul_f32_e32 v6, v3, v5
-; CI-NEXT:    v_fma_f32 v7, -v4, v6, v3
-; CI-NEXT:    v_fma_f32 v6, v7, v5, v6
-; CI-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; CI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; CI-NEXT:    v_fma_f32 v13, v14, v13, v13
+; CI-NEXT:    v_mul_f32_e32 v14, v9, v13
+; CI-NEXT:    v_fma_f32 v15, -v12, v14, v9
+; CI-NEXT:    v_fma_f32 v14, v15, v13, v14
+; CI-NEXT:    v_fma_f32 v9, -v12, v14, v9
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
-; CI-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
-; CI-NEXT:    v_trunc_f32_e32 v3, v3
-; CI-NEXT:    v_fma_f32 v0, -v3, v2, v0
+; CI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v7
+; CI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB11_15
+; CI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; CI-NEXT:    v_sub_i32_e32 v7, vcc, v10, v11
+; CI-NEXT:    v_add_i32_e32 v7, vcc, 12, v7
+; CI-NEXT:  .LBB11_13: ; %frem.loop_body23
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v10, v8
+; CI-NEXT:    v_mul_f32_e32 v8, v10, v9
+; CI-NEXT:    v_rndne_f32_e32 v8, v8
+; CI-NEXT:    v_fma_f32 v8, -v8, v6, v10
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
+; CI-NEXT:    v_add_f32_e32 v11, v8, v6
+; CI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
+; CI-NEXT:    v_add_i32_e32 v7, vcc, -12, v7
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v7
+; CI-NEXT:    v_ldexp_f32_e64 v8, v8, 12
+; CI-NEXT:    s_cbranch_vccnz .LBB11_13
+; CI-NEXT:  ; %bb.14: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v8, v10
+; CI-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; CI-NEXT:    v_add_i32_e32 v7, vcc, -11, v7
+; CI-NEXT:    v_ldexp_f32_e32 v7, v8, v7
+; CI-NEXT:    v_mul_f32_e32 v8, v7, v9
+; CI-NEXT:    v_rndne_f32_e32 v8, v8
+; CI-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; CI-NEXT:    v_add_f32_e32 v6, v7, v6
+; CI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v5, v6, v5
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v5, s2, v5, v1
+; CI-NEXT:  .LBB11_16: ; %Flow50
+; CI-NEXT:    s_mov_b32 s4, 0x7f800000
+; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
+; CI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; CI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; CI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
+; CI-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
+; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
+; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v1|, s4
+; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
 ; CI-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; CI-NEXT:    s_endpgm
 ;
@@ -4187,48 +12042,164 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    s_add_u32 s0, s4, 32
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    s_addc_u32 s1, s5, 0
-; VI-NEXT:    v_mov_b32_e32 v5, s1
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    s_add_u32 s2, s4, 32
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    s_addc_u32 s3, s5, 0
 ; VI-NEXT:    v_mov_b32_e32 v2, s2
 ; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    flat_load_dwordx2 v[0:1], v[0:1]
 ; VI-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
-; VI-NEXT:    flat_load_dwordx2 v[4:5], v[4:5]
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_div_scale_f32 v7, s[0:1], v5, v5, v3
-; VI-NEXT:    v_div_scale_f32 v6, vcc, v3, v5, v3
-; VI-NEXT:    v_rcp_f32_e32 v8, v7
+; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB11_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v4, s2, 0, v0
+; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; VI-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
+; VI-NEXT:    s_cbranch_execz .LBB11_3
+; VI-NEXT:    s_branch .LBB11_8
+; VI-NEXT:  .LBB11_2:
+; VI-NEXT:    ; implicit-def: $vgpr4
+; VI-NEXT:  .LBB11_3: ; %frem.compute
+; VI-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
+; VI-NEXT:    v_ldexp_f32 v5, v5, 1
+; VI-NEXT:    v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
+; VI-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
+; VI-NEXT:    v_ldexp_f32 v7, v4, 12
+; VI-NEXT:    v_add_u32_e32 v4, vcc, -1, v10
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
+; VI-NEXT:    v_not_b32_e32 v6, v4
+; VI-NEXT:    v_add_u32_e32 v6, vcc, v6, v9
+; VI-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v12, v11
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
-; VI-NEXT:    v_fma_f32 v8, v9, v8, v8
-; VI-NEXT:    v_mul_f32_e32 v9, v6, v8
-; VI-NEXT:    v_fma_f32 v10, -v7, v9, v6
-; VI-NEXT:    v_fma_f32 v9, v10, v8, v9
-; VI-NEXT:    v_fma_f32 v6, -v7, v9, v6
+; VI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; VI-NEXT:    v_fma_f32 v12, v13, v12, v12
+; VI-NEXT:    v_mul_f32_e32 v13, v8, v12
+; VI-NEXT:    v_fma_f32 v14, -v11, v13, v8
+; VI-NEXT:    v_fma_f32 v13, v14, v12, v13
+; VI-NEXT:    v_fma_f32 v8, -v11, v13, v8
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
-; VI-NEXT:    v_div_fixup_f32 v6, v6, v5, v3
-; VI-NEXT:    v_trunc_f32_e32 v6, v6
-; VI-NEXT:    v_fma_f32 v3, -v6, v5, v3
-; VI-NEXT:    v_div_scale_f32 v6, s[0:1], v4, v4, v2
-; VI-NEXT:    v_div_scale_f32 v5, vcc, v2, v4, v2
-; VI-NEXT:    v_rcp_f32_e32 v7, v6
+; VI-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v6
+; VI-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB11_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v6, vcc, v9, v10
+; VI-NEXT:    v_add_u32_e32 v6, vcc, 12, v6
+; VI-NEXT:  .LBB11_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v9, v7
+; VI-NEXT:    v_mul_f32_e32 v7, v9, v8
+; VI-NEXT:    v_rndne_f32_e32 v7, v7
+; VI-NEXT:    v_fma_f32 v7, -v7, v5, v9
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; VI-NEXT:    v_add_f32_e32 v10, v7, v5
+; VI-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
+; VI-NEXT:    v_add_u32_e32 v6, vcc, -12, v6
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v6
+; VI-NEXT:    v_ldexp_f32 v7, v7, 12
+; VI-NEXT:    s_cbranch_vccnz .LBB11_5
+; VI-NEXT:  ; %bb.6: ; %Flow51
+; VI-NEXT:    v_mov_b32_e32 v7, v9
+; VI-NEXT:  .LBB11_7: ; %frem.loop_exit
+; VI-NEXT:    v_add_u32_e32 v6, vcc, -11, v6
+; VI-NEXT:    v_ldexp_f32 v6, v7, v6
+; VI-NEXT:    v_mul_f32_e32 v7, v6, v8
+; VI-NEXT:    v_rndne_f32_e32 v7, v7
+; VI-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; VI-NEXT:    v_add_f32_e32 v5, v6, v5
+; VI-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; VI-NEXT:    v_ldexp_f32 v4, v5, v4
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v4, s2, v4, v0
+; VI-NEXT:  .LBB11_8:
+; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB11_10
+; VI-NEXT:  ; %bb.9: ; %frem.else16
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v5, s2, 0, v1
+; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; VI-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
+; VI-NEXT:    s_cbranch_execz .LBB11_11
+; VI-NEXT:    s_branch .LBB11_16
+; VI-NEXT:  .LBB11_10:
+; VI-NEXT:    ; implicit-def: $vgpr5
+; VI-NEXT:  .LBB11_11: ; %frem.compute15
+; VI-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
+; VI-NEXT:    v_ldexp_f32 v6, v6, 1
+; VI-NEXT:    v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
+; VI-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
+; VI-NEXT:    v_ldexp_f32 v8, v5, 12
+; VI-NEXT:    v_add_u32_e32 v5, vcc, -1, v11
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
+; VI-NEXT:    v_not_b32_e32 v7, v5
+; VI-NEXT:    v_add_u32_e32 v7, vcc, v7, v10
+; VI-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v13, v12
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; VI-NEXT:    v_fma_f32 v7, v8, v7, v7
-; VI-NEXT:    v_mul_f32_e32 v8, v5, v7
-; VI-NEXT:    v_fma_f32 v9, -v6, v8, v5
-; VI-NEXT:    v_fma_f32 v8, v9, v7, v8
-; VI-NEXT:    v_fma_f32 v5, -v6, v8, v5
+; VI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; VI-NEXT:    v_fma_f32 v13, v14, v13, v13
+; VI-NEXT:    v_mul_f32_e32 v14, v9, v13
+; VI-NEXT:    v_fma_f32 v15, -v12, v14, v9
+; VI-NEXT:    v_fma_f32 v14, v15, v13, v14
+; VI-NEXT:    v_fma_f32 v9, -v12, v14, v9
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; VI-NEXT:    v_div_fixup_f32 v5, v5, v4, v2
-; VI-NEXT:    v_trunc_f32_e32 v5, v5
-; VI-NEXT:    v_fma_f32 v2, -v5, v4, v2
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; VI-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v7
+; VI-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB11_15
+; VI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; VI-NEXT:    v_sub_u32_e32 v7, vcc, v10, v11
+; VI-NEXT:    v_add_u32_e32 v7, vcc, 12, v7
+; VI-NEXT:  .LBB11_13: ; %frem.loop_body23
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v10, v8
+; VI-NEXT:    v_mul_f32_e32 v8, v10, v9
+; VI-NEXT:    v_rndne_f32_e32 v8, v8
+; VI-NEXT:    v_fma_f32 v8, -v8, v6, v10
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
+; VI-NEXT:    v_add_f32_e32 v11, v8, v6
+; VI-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
+; VI-NEXT:    v_add_u32_e32 v7, vcc, -12, v7
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v7
+; VI-NEXT:    v_ldexp_f32 v8, v8, 12
+; VI-NEXT:    s_cbranch_vccnz .LBB11_13
+; VI-NEXT:  ; %bb.14: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v8, v10
+; VI-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; VI-NEXT:    v_add_u32_e32 v7, vcc, -11, v7
+; VI-NEXT:    v_ldexp_f32 v7, v8, v7
+; VI-NEXT:    v_mul_f32_e32 v8, v7, v9
+; VI-NEXT:    v_rndne_f32_e32 v8, v8
+; VI-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; VI-NEXT:    v_add_f32_e32 v6, v7, v6
+; VI-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; VI-NEXT:    v_ldexp_f32 v5, v6, v5
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v5, s2, v5, v1
+; VI-NEXT:  .LBB11_16: ; %Flow50
+; VI-NEXT:    s_mov_b32 s4, 0x7f800000
+; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
+; VI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
+; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
+; VI-NEXT:    v_mov_b32_e32 v6, s0
+; VI-NEXT:    v_mov_b32_e32 v7, s1
+; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
+; VI-NEXT:    v_cmp_nge_f32_e64 s[0:1], |v1|, s4
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
+; VI-NEXT:    flat_store_dwordx2 v[6:7], v[0:1]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: frem_v2f32:
@@ -4240,36 +12211,153 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX9-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
 ; GFX9-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_div_scale_f32 v6, s[2:3], v3, v3, v1
-; GFX9-NEXT:    v_div_scale_f32 v5, vcc, v1, v3, v1
-; GFX9-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v2|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB11_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v4, s2, 0, v0
+; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v2|
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB11_3
+; GFX9-NEXT:    s_branch .LBB11_8
+; GFX9-NEXT:  .LBB11_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr4
+; GFX9-NEXT:  .LBB11_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
+; GFX9-NEXT:    v_ldexp_f32 v5, v5, 1
+; GFX9-NEXT:    v_div_scale_f32 v11, s[2:3], v5, v5, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v8, vcc, 1.0, v5, 1.0
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v9, v0
+; GFX9-NEXT:    v_ldexp_f32 v7, v4, 12
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, -1, v10
+; GFX9-NEXT:    v_not_b32_e32 v6, v4
+; GFX9-NEXT:    v_add_u32_e32 v6, v6, v9
+; GFX9-NEXT:    v_rcp_f32_e32 v12, v11
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX9-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; GFX9-NEXT:    v_fma_f32 v7, v8, v7, v7
-; GFX9-NEXT:    v_mul_f32_e32 v8, v5, v7
-; GFX9-NEXT:    v_fma_f32 v9, -v6, v8, v5
-; GFX9-NEXT:    v_fma_f32 v8, v9, v7, v8
-; GFX9-NEXT:    v_fma_f32 v5, -v6, v8, v5
+; GFX9-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; GFX9-NEXT:    v_fma_f32 v12, v13, v12, v12
+; GFX9-NEXT:    v_mul_f32_e32 v13, v8, v12
+; GFX9-NEXT:    v_fma_f32 v14, -v11, v13, v8
+; GFX9-NEXT:    v_fma_f32 v13, v14, v12, v13
+; GFX9-NEXT:    v_fma_f32 v8, -v11, v13, v8
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; GFX9-NEXT:    v_div_fixup_f32 v5, v5, v3, v1
-; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX9-NEXT:    v_fma_f32 v1, -v5, v3, v1
-; GFX9-NEXT:    v_div_scale_f32 v5, s[2:3], v2, v2, v0
-; GFX9-NEXT:    v_div_scale_f32 v3, vcc, v0, v2, v0
-; GFX9-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX9-NEXT:    v_div_fmas_f32 v8, v8, v12, v13
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v6
+; GFX9-NEXT:    v_div_fixup_f32 v8, v8, v5, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB11_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v6, v9, v10
+; GFX9-NEXT:    v_add_u32_e32 v6, 12, v6
+; GFX9-NEXT:  .LBB11_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v9, v7
+; GFX9-NEXT:    v_mul_f32_e32 v7, v9, v8
+; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX9-NEXT:    v_fma_f32 v7, -v7, v5, v9
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; GFX9-NEXT:    v_add_f32_e32 v10, v7, v5
+; GFX9-NEXT:    v_add_u32_e32 v6, -12, v6
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v6
+; GFX9-NEXT:    v_ldexp_f32 v7, v7, 12
+; GFX9-NEXT:    s_cbranch_vccnz .LBB11_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow51
+; GFX9-NEXT:    v_mov_b32_e32 v7, v9
+; GFX9-NEXT:  .LBB11_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_add_u32_e32 v6, -11, v6
+; GFX9-NEXT:    v_ldexp_f32 v6, v7, v6
+; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v8
+; GFX9-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX9-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v6
+; GFX9-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX9-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v4, s2, v4, v0
+; GFX9-NEXT:  .LBB11_8:
+; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v3|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB11_10
+; GFX9-NEXT:  ; %bb.9: ; %frem.else16
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v5, s2, 0, v1
+; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v3|
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB11_11
+; GFX9-NEXT:    s_branch .LBB11_16
+; GFX9-NEXT:  .LBB11_10:
+; GFX9-NEXT:    ; implicit-def: $vgpr5
+; GFX9-NEXT:  .LBB11_11: ; %frem.compute15
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
+; GFX9-NEXT:    v_ldexp_f32 v6, v6, 1
+; GFX9-NEXT:    v_div_scale_f32 v12, s[2:3], v6, v6, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v9, vcc, 1.0, v6, 1.0
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v10, v1
+; GFX9-NEXT:    v_ldexp_f32 v8, v5, 12
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
+; GFX9-NEXT:    v_add_u32_e32 v5, -1, v11
+; GFX9-NEXT:    v_not_b32_e32 v7, v5
+; GFX9-NEXT:    v_add_u32_e32 v7, v7, v10
+; GFX9-NEXT:    v_rcp_f32_e32 v13, v12
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX9-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; GFX9-NEXT:    v_fma_f32 v6, v7, v6, v6
-; GFX9-NEXT:    v_mul_f32_e32 v7, v3, v6
-; GFX9-NEXT:    v_fma_f32 v8, -v5, v7, v3
-; GFX9-NEXT:    v_fma_f32 v7, v8, v6, v7
-; GFX9-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX9-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; GFX9-NEXT:    v_fma_f32 v13, v14, v13, v13
+; GFX9-NEXT:    v_mul_f32_e32 v14, v9, v13
+; GFX9-NEXT:    v_fma_f32 v15, -v12, v14, v9
+; GFX9-NEXT:    v_fma_f32 v14, v15, v13, v14
+; GFX9-NEXT:    v_fma_f32 v9, -v12, v14, v9
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
-; GFX9-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
-; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX9-NEXT:    v_fma_f32 v0, -v3, v2, v0
+; GFX9-NEXT:    v_div_fmas_f32 v9, v9, v13, v14
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v7
+; GFX9-NEXT:    v_div_fixup_f32 v9, v9, v6, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB11_15
+; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v7, v10, v11
+; GFX9-NEXT:    v_add_u32_e32 v7, 12, v7
+; GFX9-NEXT:  .LBB11_13: ; %frem.loop_body23
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v10, v8
+; GFX9-NEXT:    v_mul_f32_e32 v8, v10, v9
+; GFX9-NEXT:    v_rndne_f32_e32 v8, v8
+; GFX9-NEXT:    v_fma_f32 v8, -v8, v6, v10
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v8
+; GFX9-NEXT:    v_add_f32_e32 v11, v8, v6
+; GFX9-NEXT:    v_add_u32_e32 v7, -12, v7
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v11, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v7
+; GFX9-NEXT:    v_ldexp_f32 v8, v8, 12
+; GFX9-NEXT:    s_cbranch_vccnz .LBB11_13
+; GFX9-NEXT:  ; %bb.14: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v8, v10
+; GFX9-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; GFX9-NEXT:    v_add_u32_e32 v7, -11, v7
+; GFX9-NEXT:    v_ldexp_f32 v7, v8, v7
+; GFX9-NEXT:    v_mul_f32_e32 v8, v7, v9
+; GFX9-NEXT:    v_rndne_f32_e32 v8, v8
+; GFX9-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v7
+; GFX9-NEXT:    v_add_f32_e32 v6, v7, v6
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; GFX9-NEXT:    v_ldexp_f32 v5, v6, v5
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v5, s2, v5, v1
+; GFX9-NEXT:  .LBB11_16: ; %Flow50
+; GFX9-NEXT:    s_mov_b32 s4, 0x7f800000
+; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v2
+; GFX9-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
+; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v3
+; GFX9-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v1|, s4
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
 ; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
@@ -4284,37 +12372,154 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX10-NEXT:    global_load_dwordx2 v[0:1], v4, s[2:3]
 ; GFX10-NEXT:    global_load_dwordx2 v[2:3], v4, s[6:7] offset:32
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_div_scale_f32 v6, s2, v3, v3, v1
-; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, v1, v3, v1
-; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX10-NEXT:    v_cmp_ngt_f32_e64 s2, |v0|, |v2|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB11_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_bfi_b32 v4, 0x7fffffff, 0, v0
+; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
+; GFX10-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB11_3
+; GFX10-NEXT:    s_branch .LBB11_8
+; GFX10-NEXT:  .LBB11_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr4
+; GFX10-NEXT:  .LBB11_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
+; GFX10-NEXT:    v_ldexp_f32 v5, v5, 1
+; GFX10-NEXT:    v_ldexp_f32 v6, v4, 12
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v7
+; GFX10-NEXT:    v_div_scale_f32 v9, s4, v5, v5, 1.0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX10-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX10-NEXT:    v_not_b32_e32 v8, v4
+; GFX10-NEXT:    v_add_nc_u32_e32 v8, v8, v7
+; GFX10-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
 ; GFX10-NEXT:    s_denorm_mode 15
-; GFX10-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v7
-; GFX10-NEXT:    v_mul_f32_e32 v8, v5, v7
-; GFX10-NEXT:    v_fma_f32 v9, -v6, v8, v5
-; GFX10-NEXT:    v_fmac_f32_e32 v8, v9, v7
-; GFX10-NEXT:    v_fma_f32 v5, -v6, v8, v5
+; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v10
+; GFX10-NEXT:    v_mul_f32_e32 v11, v7, v10
+; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v7
+; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v10
+; GFX10-NEXT:    v_fma_f32 v7, -v9, v11, v7
 ; GFX10-NEXT:    s_denorm_mode 12
-; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v3, v1
-; GFX10-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX10-NEXT:    v_fma_f32 v1, -v5, v3, v1
-; GFX10-NEXT:    v_div_scale_f32 v5, s2, v2, v2, v0
-; GFX10-NEXT:    v_div_scale_f32 v3, vcc_lo, v0, v2, v0
-; GFX10-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX10-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v8
+; GFX10-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB11_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 12
+; GFX10-NEXT:  .LBB11_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v9, v6
+; GFX10-NEXT:    s_add_i32 s2, s2, -12
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX10-NEXT:    v_mul_f32_e32 v6, v9, v7
+; GFX10-NEXT:    v_rndne_f32_e32 v6, v6
+; GFX10-NEXT:    v_fma_f32 v6, -v6, v5, v9
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX10-NEXT:    v_add_f32_e32 v8, v6, v5
+; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v6, v6, 12
+; GFX10-NEXT:    s_cbranch_scc1 .LBB11_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow51
+; GFX10-NEXT:    v_mov_b32_e32 v8, s2
+; GFX10-NEXT:    v_mov_b32_e32 v6, v9
+; GFX10-NEXT:  .LBB11_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_add_nc_u32_e32 v8, -11, v8
+; GFX10-NEXT:    v_ldexp_f32 v6, v6, v8
+; GFX10-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX10-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX10-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX10-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX10-NEXT:    v_bfi_b32 v4, 0x7fffffff, v4, v0
+; GFX10-NEXT:  .LBB11_8:
+; GFX10-NEXT:    v_cmp_ngt_f32_e64 s2, |v1|, |v3|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB11_10
+; GFX10-NEXT:  ; %bb.9: ; %frem.else16
+; GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, 0, v1
+; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
+; GFX10-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB11_11
+; GFX10-NEXT:    s_branch .LBB11_16
+; GFX10-NEXT:  .LBB11_10:
+; GFX10-NEXT:    ; implicit-def: $vgpr5
+; GFX10-NEXT:  .LBB11_11: ; %frem.compute15
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
+; GFX10-NEXT:    v_ldexp_f32 v6, v6, 1
+; GFX10-NEXT:    v_ldexp_f32 v7, v5, 12
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX10-NEXT:    v_div_scale_f32 v10, s4, v6, v6, 1.0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v5
+; GFX10-NEXT:    v_add_nc_u32_e32 v5, -1, v5
+; GFX10-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX10-NEXT:    v_not_b32_e32 v9, v5
+; GFX10-NEXT:    v_add_nc_u32_e32 v9, v9, v8
+; GFX10-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
 ; GFX10-NEXT:    s_denorm_mode 15
-; GFX10-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; GFX10-NEXT:    v_fmac_f32_e32 v6, v7, v6
-; GFX10-NEXT:    v_mul_f32_e32 v7, v3, v6
-; GFX10-NEXT:    v_fma_f32 v8, -v5, v7, v3
-; GFX10-NEXT:    v_fmac_f32_e32 v7, v8, v6
-; GFX10-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX10-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v11
+; GFX10-NEXT:    v_mul_f32_e32 v12, v8, v11
+; GFX10-NEXT:    v_fma_f32 v13, -v10, v12, v8
+; GFX10-NEXT:    v_fmac_f32_e32 v12, v13, v11
+; GFX10-NEXT:    v_fma_f32 v8, -v10, v12, v8
 ; GFX10-NEXT:    s_denorm_mode 12
-; GFX10-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
-; GFX10-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
-; GFX10-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX10-NEXT:    v_fma_f32 v0, -v3, v2, v0
-; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX10-NEXT:    v_div_fmas_f32 v8, v8, v11, v12
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v9
+; GFX10-NEXT:    v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB11_15
+; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 12
+; GFX10-NEXT:  .LBB11_13: ; %frem.loop_body23
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v10, v7
+; GFX10-NEXT:    s_add_i32 s2, s2, -12
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX10-NEXT:    v_mul_f32_e32 v7, v10, v8
+; GFX10-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX10-NEXT:    v_fma_f32 v7, -v7, v6, v10
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX10-NEXT:    v_add_f32_e32 v9, v7, v6
+; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v7, v7, 12
+; GFX10-NEXT:    s_cbranch_scc1 .LBB11_13
+; GFX10-NEXT:  ; %bb.14: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v9, s2
+; GFX10-NEXT:    v_mov_b32_e32 v7, v10
+; GFX10-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; GFX10-NEXT:    v_add_nc_u32_e32 v9, -11, v9
+; GFX10-NEXT:    v_ldexp_f32 v7, v7, v9
+; GFX10-NEXT:    v_mul_f32_e32 v8, v7, v8
+; GFX10-NEXT:    v_rndne_f32_e32 v8, v8
+; GFX10-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX10-NEXT:    v_add_f32_e32 v6, v7, v6
+; GFX10-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v5, v6, v5
+; GFX10-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX10-NEXT:  .LBB11_16: ; %Flow50
+; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v2
+; GFX10-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v1|
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
+; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v3
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo
+; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: frem_v2f32:
@@ -4322,172 +12527,650 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX11-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
+; GFX11-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
+; GFX11-NEXT:    global_load_b64 v[2:3], v2, s[4:5] offset:32
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_div_scale_f32 v6, null, v3, v3, v1
-; GFX11-NEXT:    v_div_scale_f32 v5, vcc_lo, v1, v3, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s2, |v0|, |v2|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB11_2
+; GFX11-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-NEXT:    v_bfi_b32 v4, 0x7fffffff, 0, v0
+; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v2|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e32 v4, v0, v4, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB11_3
+; GFX11-NEXT:    s_branch .LBB11_8
+; GFX11-NEXT:  .LBB11_2:
+; GFX11-NEXT:    ; implicit-def: $vgpr4
+; GFX11-NEXT:  .LBB11_3: ; %frem.compute
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v5, |v2|
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v4, |v0|
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v7, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_ldexp_f32 v5, v5, 1
+; GFX11-NEXT:    v_ldexp_f32 v6, v4, 12
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v4, v2
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v7
+; GFX11-NEXT:    v_div_scale_f32 v9, null, v5, v5, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v4
+; GFX11-NEXT:    v_add_nc_u32_e32 v4, -1, v4
+; GFX11-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v8, v4
+; GFX11-NEXT:    v_add_nc_u32_e32 v8, v8, v7
+; GFX11-NEXT:    v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
 ; GFX11-NEXT:    s_denorm_mode 15
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; GFX11-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX11-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v8, v5, v7
-; GFX11-NEXT:    v_fma_f32 v9, -v6, v8, v5
+; GFX11-NEXT:    v_fmac_f32_e32 v10, v11, v10
+; GFX11-NEXT:    v_mul_f32_e32 v11, v7, v10
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v8, v9, v7
-; GFX11-NEXT:    v_fma_f32 v5, -v6, v8, v5
+; GFX11-NEXT:    v_fma_f32 v12, -v9, v11, v7
+; GFX11-NEXT:    v_fmac_f32_e32 v11, v12, v10
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v7, -v9, v11, v7
 ; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v8
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB11_7
+; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 12
+; GFX11-NEXT:  .LBB11_5: ; %frem.loop_body
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_mov_b32_e32 v9, v6
+; GFX11-NEXT:    s_add_i32 s2, s2, -12
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; GFX11-NEXT:    v_div_fixup_f32 v5, v5, v3, v1
+; GFX11-NEXT:    v_mul_f32_e32 v6, v9, v7
+; GFX11-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX11-NEXT:    v_fma_f32 v1, -v5, v3, v1
-; GFX11-NEXT:    v_div_scale_f32 v5, null, v2, v2, v0
-; GFX11-NEXT:    v_div_scale_f32 v3, vcc_lo, v0, v2, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX11-NEXT:    v_fma_f32 v6, -v6, v5, v9
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX11-NEXT:    v_add_f32_e32 v8, v6, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v6, v6, 12
+; GFX11-NEXT:    s_cbranch_scc1 .LBB11_5
+; GFX11-NEXT:  ; %bb.6: ; %Flow51
+; GFX11-NEXT:    v_mov_b32_e32 v8, s2
+; GFX11-NEXT:    v_mov_b32_e32 v6, v9
+; GFX11-NEXT:  .LBB11_7: ; %frem.loop_exit
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_add_nc_u32_e32 v8, -11, v8
+; GFX11-NEXT:    v_ldexp_f32 v6, v6, v8
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX11-NEXT:    v_rndne_f32_e32 v7, v7
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v6, -v7, v5, v6
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX11-NEXT:    v_add_f32_e32 v5, v6, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v4, v5, v4
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v4, 0x7fffffff, v4, v0
+; GFX11-NEXT:  .LBB11_8:
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s2, |v1|, |v3|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB11_10
+; GFX11-NEXT:  ; %bb.9: ; %frem.else16
+; GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, 0, v1
+; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v3|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e32 v5, v1, v5, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB11_11
+; GFX11-NEXT:    s_branch .LBB11_16
+; GFX11-NEXT:  .LBB11_10:
+; GFX11-NEXT:    ; implicit-def: $vgpr5
+; GFX11-NEXT:  .LBB11_11: ; %frem.compute15
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v6, |v3|
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v5, |v1|
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v8, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_ldexp_f32 v6, v6, 1
+; GFX11-NEXT:    v_ldexp_f32 v7, v5, 12
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v5, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v8
+; GFX11-NEXT:    v_div_scale_f32 v10, null, v6, v6, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v5
+; GFX11-NEXT:    v_add_nc_u32_e32 v5, -1, v5
+; GFX11-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v9, v5
+; GFX11-NEXT:    v_add_nc_u32_e32 v9, v9, v8
+; GFX11-NEXT:    v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
 ; GFX11-NEXT:    s_denorm_mode 15
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; GFX11-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX11-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v7, v3, v6
-; GFX11-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX11-NEXT:    v_fmac_f32_e32 v11, v12, v11
+; GFX11-NEXT:    v_mul_f32_e32 v12, v8, v11
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v7, v8, v6
-; GFX11-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX11-NEXT:    v_fma_f32 v13, -v10, v12, v8
+; GFX11-NEXT:    v_fmac_f32_e32 v12, v13, v11
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v8, -v10, v12, v8
 ; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    v_div_fmas_f32 v8, v8, v11, v12
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v9
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB11_15
+; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 12
+; GFX11-NEXT:  .LBB11_13: ; %frem.loop_body23
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_mov_b32_e32 v10, v7
+; GFX11-NEXT:    s_add_i32 s2, s2, -12
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
-; GFX11-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
+; GFX11-NEXT:    v_mul_f32_e32 v7, v10, v8
+; GFX11-NEXT:    v_rndne_f32_e32 v7, v7
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX11-NEXT:    v_fma_f32 v0, -v3, v2, v0
-; GFX11-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX11-NEXT:    v_fma_f32 v7, -v7, v6, v10
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-NEXT:    v_add_f32_e32 v9, v7, v6
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v7, v7, 12
+; GFX11-NEXT:    s_cbranch_scc1 .LBB11_13
+; GFX11-NEXT:  ; %bb.14: ; %Flow
+; GFX11-NEXT:    v_mov_b32_e32 v9, s2
+; GFX11-NEXT:    v_mov_b32_e32 v7, v10
+; GFX11-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_add_nc_u32_e32 v9, -11, v9
+; GFX11-NEXT:    v_ldexp_f32 v7, v7, v9
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v8, v7, v8
+; GFX11-NEXT:    v_rndne_f32_e32 v8, v8
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v7, -v8, v6, v7
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-NEXT:    v_add_f32_e32 v6, v7, v6
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v5, v6, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v5, 0x7fffffff, v5, v1
+; GFX11-NEXT:  .LBB11_16: ; %Flow50
+; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v2
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v1|
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
+; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v3
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x7fc00000, v5
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: frem_v2f32:
 ; GFX1150:       ; %bb.0:
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1150-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1150-NEXT:    s_load_b64 s[6:7], s[4:5], 0x34
+; GFX1150-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1150-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1150-NEXT:    s_clause 0x1
-; GFX1150-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX1150-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
+; GFX1150-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
 ; GFX1150-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-NEXT:    v_div_scale_f32 v6, null, v3, v3, v1
-; GFX1150-NEXT:    v_div_scale_f32 v5, vcc_lo, v1, v3, v1
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1150-NEXT:    v_rcp_f32_e32 v7, v6
-; GFX1150-NEXT:    s_denorm_mode 15
-; GFX1150-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v7
-; GFX1150-NEXT:    v_mul_f32_e32 v8, v5, v7
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v9, -v6, v8, v5
-; GFX1150-NEXT:    v_fmac_f32_e32 v8, v9, v7
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v5, -v6, v8, v5
-; GFX1150-NEXT:    s_denorm_mode 12
-; GFX1150-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fixup_f32 v5, v5, v3, v1
-; GFX1150-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1150-NEXT:    v_fma_f32 v1, v5, v3, v1
-; GFX1150-NEXT:    v_div_scale_f32 v5, null, v2, v2, v0
-; GFX1150-NEXT:    v_div_scale_f32 v3, vcc_lo, v0, v2, v0
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1150-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX1150-NEXT:    global_load_b64 v[1:2], v2, s[6:7] offset:32
+; GFX1150-NEXT:    v_readfirstlane_b32 s6, v0
+; GFX1150-NEXT:    s_and_b32 s3, s6, 0x7fffffff
+; GFX1150-NEXT:    s_waitcnt vmcnt(0)
+; GFX1150-NEXT:    v_readfirstlane_b32 s4, v1
+; GFX1150-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX1150-NEXT:    s_and_b32 s8, s4, 0x7fffffff
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_cmp_ngt_f32 s3, s8
+; GFX1150-NEXT:    s_cbranch_scc0 .LBB11_2
+; GFX1150-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-NEXT:    s_cmp_eq_f32 s3, s8
+; GFX1150-NEXT:    v_bfi_b32 v0, 0x7fffffff, 0, s6
+; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v0, s6, v0, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB11_3
+; GFX1150-NEXT:    s_branch .LBB11_8
+; GFX1150-NEXT:  .LBB11_2:
+; GFX1150-NEXT:    ; implicit-def: $vgpr0
+; GFX1150-NEXT:  .LBB11_3: ; %frem.compute
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s4|
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v0, |s6|
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1150-NEXT:    v_ldexp_f32 v2, v0, 12
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX1150-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_readfirstlane_b32 s8, v0
+; GFX1150-NEXT:    v_add_nc_u32_e32 v0, -1, v0
 ; GFX1150-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v4, v0
+; GFX1150-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
 ; GFX1150-NEXT:    s_denorm_mode 15
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1150-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1150-NEXT:    v_fmac_f32_e32 v6, v7, v6
-; GFX1150-NEXT:    v_mul_f32_e32 v7, v3, v6
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v7, v3, v6
 ; GFX1150-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v6
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
 ; GFX1150-NEXT:    v_fma_f32 v3, -v5, v7, v3
 ; GFX1150-NEXT:    s_denorm_mode 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
 ; GFX1150-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
+; GFX1150-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB11_7
+; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-NEXT:    s_sub_i32 s7, s7, s8
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s7, s7, 12
+; GFX1150-NEXT:  .LBB11_5: ; %frem.loop_body
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1150-NEXT:    s_add_i32 s7, s7, -12
+; GFX1150-NEXT:    s_cmp_gt_i32 s7, 12
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
-; GFX1150-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX1150-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1150-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 12
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB11_5
+; GFX1150-NEXT:  ; %bb.6: ; %Flow51
+; GFX1150-NEXT:    v_mov_b32_e32 v4, s7
+; GFX1150-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1150-NEXT:  .LBB11_7: ; %frem.loop_exit
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_add_nc_u32_e32 v4, -11, v4
+; GFX1150-NEXT:    v_ldexp_f32 v2, v2, v4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1150-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1150-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s6
+; GFX1150-NEXT:  .LBB11_8:
+; GFX1150-NEXT:    s_and_b32 s6, s5, 0x7fffffff
+; GFX1150-NEXT:    s_and_b32 s8, s2, 0x7fffffff
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_cmp_ngt_f32 s6, s8
+; GFX1150-NEXT:    s_cbranch_scc0 .LBB11_10
+; GFX1150-NEXT:  ; %bb.9: ; %frem.else16
+; GFX1150-NEXT:    s_cmp_eq_f32 s6, s8
+; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, 0, s5
+; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v1, s5, v1, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB11_11
+; GFX1150-NEXT:    s_branch .LBB11_16
+; GFX1150-NEXT:  .LBB11_10:
+; GFX1150-NEXT:    ; implicit-def: $vgpr1
+; GFX1150-NEXT:  .LBB11_11: ; %frem.compute15
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v2, |s2|
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s5|
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v4, s5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1150-NEXT:    v_ldexp_f32 v3, v1, 12
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v1, s2
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_readfirstlane_b32 s7, v4
+; GFX1150-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_readfirstlane_b32 s8, v1
+; GFX1150-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v5, v1
+; GFX1150-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1150-NEXT:    s_denorm_mode 15
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1150-NEXT:    v_fma_f32 v9, -v6, v8, v4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1150-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1150-NEXT:    s_denorm_mode 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
+; GFX1150-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB11_15
+; GFX1150-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX1150-NEXT:    s_sub_i32 s7, s7, s8
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s7, s7, 12
+; GFX1150-NEXT:  .LBB11_13: ; %frem.loop_body23
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1150-NEXT:    s_add_i32 s7, s7, -12
+; GFX1150-NEXT:    s_cmp_gt_i32 s7, 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1150-NEXT:    v_fmac_f32_e32 v0, v3, v2
-; GFX1150-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX1150-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v3, v3, 12
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB11_13
+; GFX1150-NEXT:  ; %bb.14: ; %Flow
+; GFX1150-NEXT:    v_mov_b32_e32 v5, s7
+; GFX1150-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1150-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_add_nc_u32_e32 v5, -11, v5
+; GFX1150-NEXT:    v_ldexp_f32 v3, v3, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1150-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s5
+; GFX1150-NEXT:  .LBB11_16: ; %Flow50
+; GFX1150-NEXT:    s_cmp_lg_f32 s4, 0
+; GFX1150-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1150-NEXT:    s_cmp_nge_f32 s3, 0x7f800000
+; GFX1150-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s3, s4
+; GFX1150-NEXT:    s_cmp_lg_f32 s2, 0
+; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
+; GFX1150-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-NEXT:    s_cmp_nge_f32 s6, 0x7f800000
+; GFX1150-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1150-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x7fc00000, v1
+; GFX1150-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
 ; GFX1200-LABEL: frem_v2f32:
 ; GFX1200:       ; %bb.0:
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1200-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1200-NEXT:    s_load_b64 s[6:7], s[4:5], 0x34
+; GFX1200-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1200-NEXT:    s_wait_kmcnt 0x0
-; GFX1200-NEXT:    s_clause 0x1
-; GFX1200-NEXT:    global_load_b64 v[0:1], v4, s[2:3]
-; GFX1200-NEXT:    global_load_b64 v[2:3], v4, s[4:5] offset:32
+; GFX1200-NEXT:    global_load_b64 v[0:1], v2, s[2:3]
 ; GFX1200-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-NEXT:    v_div_scale_f32 v6, null, v3, v3, v1
-; GFX1200-NEXT:    v_div_scale_f32 v5, vcc_lo, v1, v3, v1
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1200-NEXT:    v_rcp_f32_e32 v7, v6
-; GFX1200-NEXT:    s_denorm_mode 15
-; GFX1200-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v7
-; GFX1200-NEXT:    v_mul_f32_e32 v8, v5, v7
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v9, -v6, v8, v5
-; GFX1200-NEXT:    v_fmac_f32_e32 v8, v9, v7
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v5, -v6, v8, v5
-; GFX1200-NEXT:    s_denorm_mode 12
-; GFX1200-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fixup_f32 v5, v5, v3, v1
-; GFX1200-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-NEXT:    v_fma_f32 v1, v5, v3, v1
-; GFX1200-NEXT:    v_div_scale_f32 v5, null, v2, v2, v0
-; GFX1200-NEXT:    v_div_scale_f32 v3, vcc_lo, v0, v2, v0
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
+; GFX1200-NEXT:    v_readfirstlane_b32 s5, v1
+; GFX1200-NEXT:    global_load_b64 v[1:2], v2, s[6:7] offset:32
+; GFX1200-NEXT:    v_readfirstlane_b32 s6, v0
+; GFX1200-NEXT:    s_and_b32 s3, s6, 0x7fffffff
+; GFX1200-NEXT:    s_wait_loadcnt 0x0
+; GFX1200-NEXT:    v_readfirstlane_b32 s4, v1
+; GFX1200-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX1200-NEXT:    s_and_b32 s8, s4, 0x7fffffff
+; GFX1200-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT:    s_cmp_ngt_f32 s3, s8
+; GFX1200-NEXT:    s_cbranch_scc0 .LBB11_2
+; GFX1200-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-NEXT:    s_cmp_eq_f32 s3, s8
+; GFX1200-NEXT:    v_bfi_b32 v0, 0x7fffffff, 0, s6
+; GFX1200-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v0, s6, v0, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB11_3
+; GFX1200-NEXT:    s_branch .LBB11_8
+; GFX1200-NEXT:  .LBB11_2:
+; GFX1200-NEXT:    ; implicit-def: $vgpr0
+; GFX1200-NEXT:  .LBB11_3: ; %frem.compute
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s4|
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v0, |s6|
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1200-NEXT:    v_ldexp_f32 v2, v0, 12
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v0, s4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX1200-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_readfirstlane_b32 s8, v0
+; GFX1200-NEXT:    v_add_nc_u32_e32 v0, -1, v0
 ; GFX1200-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v4, v0
+; GFX1200-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
 ; GFX1200-NEXT:    s_denorm_mode 15
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1200-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1200-NEXT:    v_fmac_f32_e32 v6, v7, v6
-; GFX1200-NEXT:    v_mul_f32_e32 v7, v3, v6
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v7, v3, v6
 ; GFX1200-NEXT:    v_fma_f32 v8, -v5, v7, v3
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v6
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
 ; GFX1200-NEXT:    v_fma_f32 v3, -v5, v7, v3
 ; GFX1200-NEXT:    s_denorm_mode 12
 ; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
 ; GFX1200-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
+; GFX1200-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB11_7
+; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s7, s7, s8
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s7, s7, 12
+; GFX1200-NEXT:  .LBB11_5: ; %frem.loop_body
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s7, s7, -12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_gt_i32 s7, 12
+; GFX1200-NEXT:    v_mul_f32_e32 v2, v5, v3
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fixup_f32 v3, v3, v2, v0
-; GFX1200-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX1200-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1200-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 12
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB11_5
+; GFX1200-NEXT:  ; %bb.6: ; %Flow51
+; GFX1200-NEXT:    v_mov_b32_e32 v4, s7
+; GFX1200-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1200-NEXT:  .LBB11_7: ; %frem.loop_exit
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_add_nc_u32_e32 v4, -11, v4
+; GFX1200-NEXT:    v_ldexp_f32 v2, v2, v4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1200-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s6
+; GFX1200-NEXT:  .LBB11_8:
+; GFX1200-NEXT:    s_and_b32 s6, s5, 0x7fffffff
+; GFX1200-NEXT:    s_and_b32 s8, s2, 0x7fffffff
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_ngt_f32 s6, s8
+; GFX1200-NEXT:    s_cbranch_scc0 .LBB11_10
+; GFX1200-NEXT:  ; %bb.9: ; %frem.else16
+; GFX1200-NEXT:    s_cmp_eq_f32 s6, s8
+; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, 0, s5
+; GFX1200-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v1, s5, v1, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB11_11
+; GFX1200-NEXT:    s_branch .LBB11_16
+; GFX1200-NEXT:  .LBB11_10:
+; GFX1200-NEXT:    ; implicit-def: $vgpr1
+; GFX1200-NEXT:  .LBB11_11: ; %frem.compute15
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v2, |s2|
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s5|
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v4, s5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1200-NEXT:    v_ldexp_f32 v3, v1, 12
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v1, s2
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_readfirstlane_b32 s7, v4
+; GFX1200-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_readfirstlane_b32 s8, v1
+; GFX1200-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v5, v1
+; GFX1200-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-NEXT:    s_denorm_mode 15
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1200-NEXT:    v_fma_f32 v9, -v6, v8, v4
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1200-NEXT:    v_fma_f32 v4, -v6, v8, v4
+; GFX1200-NEXT:    s_denorm_mode 12
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
+; GFX1200-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB11_15
+; GFX1200-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s7, s7, s8
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s7, s7, 12
+; GFX1200-NEXT:  .LBB11_13: ; %frem.loop_body23
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s7, s7, -12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_gt_i32 s7, 12
+; GFX1200-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-NEXT:    v_fmac_f32_e32 v0, v3, v2
-; GFX1200-NEXT:    global_store_b64 v4, v[0:1], s[0:1]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-NEXT:    v_ldexp_f32 v3, v3, 12
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB11_13
+; GFX1200-NEXT:  ; %bb.14: ; %Flow
+; GFX1200-NEXT:    v_mov_b32_e32 v5, s7
+; GFX1200-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1200-NEXT:  .LBB11_15: ; %frem.loop_exit24
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_add_nc_u32_e32 v5, -11, v5
+; GFX1200-NEXT:    v_ldexp_f32 v3, v3, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1200-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s5
+; GFX1200-NEXT:  .LBB11_16: ; %Flow50
+; GFX1200-NEXT:    s_cmp_lg_f32 s4, 0
+; GFX1200-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1200-NEXT:    s_cmp_nge_f32 s3, 0x7f800000
+; GFX1200-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s3, s4
+; GFX1200-NEXT:    s_cmp_lg_f32 s2, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
+; GFX1200-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-NEXT:    s_cmp_nge_f32 s6, 0x7f800000
+; GFX1200-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0x7fc00000, v1
+; GFX1200-NEXT:    global_store_b64 v2, v[0:1], s[0:1]
 ; GFX1200-NEXT:    s_endpgm
                         ptr addrspace(1) %in2) #0 {
    %gep2 = getelementptr <2 x float>, ptr addrspace(1) %in2, i32 4
@@ -4501,163 +13184,671 @@ define amdgpu_kernel void @frem_v2f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in1,
 ; SI-LABEL: frem_v4f32:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; SI-NEXT:    s_mov_b32 s3, 0xf000
-; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s0, s8
-; SI-NEXT:    s_mov_b32 s1, s9
-; SI-NEXT:    s_mov_b32 s8, s10
-; SI-NEXT:    s_mov_b32 s9, s11
-; SI-NEXT:    s_mov_b32 s10, s2
-; SI-NEXT:    s_mov_b32 s11, s3
-; SI-NEXT:    s_mov_b32 s6, s2
-; SI-NEXT:    s_mov_b32 s7, s3
+; SI-NEXT:    s_mov_b32 s8, s2
+; SI-NEXT:    s_mov_b32 s9, s3
+; SI-NEXT:    s_mov_b32 s6, s10
+; SI-NEXT:    s_mov_b32 s7, s11
 ; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
 ; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_div_scale_f32 v8, vcc, v3, v7, v3
-; SI-NEXT:    v_div_scale_f32 v9, s[4:5], v7, v7, v3
-; SI-NEXT:    v_rcp_f32_e32 v10, v9
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    s_cbranch_vccz .LBB12_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v8, s2, 0, v0
+; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; SI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB12_3
+; SI-NEXT:    s_branch .LBB12_8
+; SI-NEXT:  .LBB12_2:
+; SI-NEXT:    ; implicit-def: $vgpr8
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB12_3: ; %frem.compute
+; SI-NEXT:    s_mov_b32 s6, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v0|, s6
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v8, v0
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s4, v8
+; SI-NEXT:    s_cselect_b32 s4, s4, 0
+; SI-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
+; SI-NEXT:    v_cndmask_b32_e64 v8, |v0|, v8, s[2:3]
+; SI-NEXT:    v_ldexp_f32_e64 v9, v8, 12
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v4|, s6
+; SI-NEXT:    v_frexp_mant_f32_e64 v8, |v4|
+; SI-NEXT:    v_cndmask_b32_e64 v8, |v4|, v8, s[2:3]
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v4
+; SI-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v10
+; SI-NEXT:    s_cselect_b32 s5, s2, 0
+; SI-NEXT:    s_add_i32 s2, s5, -1
+; SI-NEXT:    v_ldexp_f32_e64 v8, v8, 1
+; SI-NEXT:    s_not_b32 s3, s2
+; SI-NEXT:    s_add_i32 s3, s3, s4
+; SI-NEXT:    v_div_scale_f32 v10, vcc, 1.0, v8, 1.0
+; SI-NEXT:    v_div_scale_f32 v11, s[6:7], v8, v8, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v12, v11
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
-; SI-NEXT:    v_fma_f32 v10, v11, v10, v10
-; SI-NEXT:    v_mul_f32_e32 v11, v8, v10
-; SI-NEXT:    v_fma_f32 v12, -v9, v11, v8
-; SI-NEXT:    v_fma_f32 v11, v12, v10, v11
-; SI-NEXT:    v_fma_f32 v8, -v9, v11, v8
+; SI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
+; SI-NEXT:    v_fma_f32 v12, v13, v12, v12
+; SI-NEXT:    v_mul_f32_e32 v13, v10, v12
+; SI-NEXT:    v_fma_f32 v14, -v11, v13, v10
+; SI-NEXT:    v_fma_f32 v13, v14, v12, v13
+; SI-NEXT:    v_fma_f32 v10, -v11, v13, v10
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
-; SI-NEXT:    v_div_fixup_f32 v8, v8, v7, v3
-; SI-NEXT:    v_trunc_f32_e32 v8, v8
-; SI-NEXT:    v_fma_f32 v3, -v8, v7, v3
-; SI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
-; SI-NEXT:    v_div_scale_f32 v8, s[4:5], v6, v6, v2
-; SI-NEXT:    v_rcp_f32_e32 v9, v8
+; SI-NEXT:    v_div_fmas_f32 v10, v10, v12, v13
+; SI-NEXT:    v_div_fixup_f32 v10, v10, v8, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s3, 13
+; SI-NEXT:    s_cbranch_scc1 .LBB12_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s3, s4, s5
+; SI-NEXT:    s_add_i32 s3, s3, 12
+; SI-NEXT:  .LBB12_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v11, v9
+; SI-NEXT:    v_mul_f32_e32 v9, v11, v10
+; SI-NEXT:    v_rndne_f32_e32 v9, v9
+; SI-NEXT:    v_fma_f32 v9, -v9, v8, v11
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
+; SI-NEXT:    v_add_f32_e32 v12, v9, v8
+; SI-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, 12
+; SI-NEXT:    s_add_i32 s3, s3, -12
+; SI-NEXT:    s_cmp_gt_i32 s3, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB12_5
+; SI-NEXT:  ; %bb.6: ; %Flow125
+; SI-NEXT:    v_mov_b32_e32 v9, v11
+; SI-NEXT:  .LBB12_7: ; %frem.loop_exit
+; SI-NEXT:    s_add_i32 s3, s3, -11
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, s3
+; SI-NEXT:    v_mul_f32_e32 v10, v9, v10
+; SI-NEXT:    v_rndne_f32_e32 v10, v10
+; SI-NEXT:    v_fma_f32 v9, -v10, v8, v9
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v9
+; SI-NEXT:    v_add_f32_e32 v8, v9, v8
+; SI-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v8, v8, s2
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v8, s2, v8, v0
+; SI-NEXT:  .LBB12_8:
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    s_cbranch_vccz .LBB12_10
+; SI-NEXT:  ; %bb.9: ; %frem.else16
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v9, s2, 0, v1
+; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; SI-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB12_11
+; SI-NEXT:    s_branch .LBB12_16
+; SI-NEXT:  .LBB12_10:
+; SI-NEXT:    ; implicit-def: $vgpr9
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB12_11: ; %frem.compute15
+; SI-NEXT:    s_mov_b32 s6, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v1|, s6
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v9, v1
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s4, v9
+; SI-NEXT:    s_cselect_b32 s4, s4, 0
+; SI-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
+; SI-NEXT:    v_cndmask_b32_e64 v9, |v1|, v9, s[2:3]
+; SI-NEXT:    v_ldexp_f32_e64 v10, v9, 12
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v5|, s6
+; SI-NEXT:    v_frexp_mant_f32_e64 v9, |v5|
+; SI-NEXT:    v_cndmask_b32_e64 v9, |v5|, v9, s[2:3]
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v5
+; SI-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v11
+; SI-NEXT:    s_cselect_b32 s5, s2, 0
+; SI-NEXT:    s_add_i32 s2, s5, -1
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, 1
+; SI-NEXT:    s_not_b32 s3, s2
+; SI-NEXT:    s_add_i32 s3, s3, s4
+; SI-NEXT:    v_div_scale_f32 v11, vcc, 1.0, v9, 1.0
+; SI-NEXT:    v_div_scale_f32 v12, s[6:7], v9, v9, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v13, v12
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
-; SI-NEXT:    v_fma_f32 v9, v10, v9, v9
-; SI-NEXT:    v_mul_f32_e32 v10, v7, v9
-; SI-NEXT:    v_fma_f32 v11, -v8, v10, v7
-; SI-NEXT:    v_fma_f32 v10, v11, v9, v10
-; SI-NEXT:    v_fma_f32 v7, -v8, v10, v7
+; SI-NEXT:    v_fma_f32 v14, -v12, v13, 1.0
+; SI-NEXT:    v_fma_f32 v13, v14, v13, v13
+; SI-NEXT:    v_mul_f32_e32 v14, v11, v13
+; SI-NEXT:    v_fma_f32 v15, -v12, v14, v11
+; SI-NEXT:    v_fma_f32 v14, v15, v13, v14
+; SI-NEXT:    v_fma_f32 v11, -v12, v14, v11
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
-; SI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
-; SI-NEXT:    v_trunc_f32_e32 v7, v7
-; SI-NEXT:    v_fma_f32 v2, -v7, v6, v2
-; SI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
-; SI-NEXT:    v_div_scale_f32 v7, s[4:5], v5, v5, v1
-; SI-NEXT:    v_rcp_f32_e32 v8, v7
+; SI-NEXT:    v_div_fmas_f32 v11, v11, v13, v14
+; SI-NEXT:    v_div_fixup_f32 v11, v11, v9, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s3, 13
+; SI-NEXT:    s_cbranch_scc1 .LBB12_15
+; SI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; SI-NEXT:    s_sub_i32 s3, s4, s5
+; SI-NEXT:    s_add_i32 s3, s3, 12
+; SI-NEXT:  .LBB12_13: ; %frem.loop_body23
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v12, v10
+; SI-NEXT:    v_mul_f32_e32 v10, v12, v11
+; SI-NEXT:    v_rndne_f32_e32 v10, v10
+; SI-NEXT:    v_fma_f32 v10, -v10, v9, v12
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; SI-NEXT:    v_add_f32_e32 v13, v10, v9
+; SI-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, 12
+; SI-NEXT:    s_add_i32 s3, s3, -12
+; SI-NEXT:    s_cmp_gt_i32 s3, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB12_13
+; SI-NEXT:  ; %bb.14: ; %Flow121
+; SI-NEXT:    v_mov_b32_e32 v10, v12
+; SI-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; SI-NEXT:    s_add_i32 s3, s3, -11
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, s3
+; SI-NEXT:    v_mul_f32_e32 v11, v10, v11
+; SI-NEXT:    v_rndne_f32_e32 v11, v11
+; SI-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; SI-NEXT:    v_add_f32_e32 v9, v10, v9
+; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v9, v9, s2
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v9, s2, v9, v1
+; SI-NEXT:  .LBB12_16:
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    s_cbranch_vccz .LBB12_18
+; SI-NEXT:  ; %bb.17: ; %frem.else47
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v10, s2, 0, v2
+; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; SI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB12_19
+; SI-NEXT:    s_branch .LBB12_24
+; SI-NEXT:  .LBB12_18:
+; SI-NEXT:    ; implicit-def: $vgpr10
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB12_19: ; %frem.compute46
+; SI-NEXT:    s_mov_b32 s6, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v2|, s6
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v10, v2
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s4, v10
+; SI-NEXT:    s_cselect_b32 s4, s4, 0
+; SI-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
+; SI-NEXT:    v_cndmask_b32_e64 v10, |v2|, v10, s[2:3]
+; SI-NEXT:    v_ldexp_f32_e64 v11, v10, 12
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v6|, s6
+; SI-NEXT:    v_frexp_mant_f32_e64 v10, |v6|
+; SI-NEXT:    v_cndmask_b32_e64 v10, |v6|, v10, s[2:3]
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v12, v6
+; SI-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v12
+; SI-NEXT:    s_cselect_b32 s5, s2, 0
+; SI-NEXT:    s_add_i32 s2, s5, -1
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, 1
+; SI-NEXT:    s_not_b32 s3, s2
+; SI-NEXT:    s_add_i32 s3, s3, s4
+; SI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v10, 1.0
+; SI-NEXT:    v_div_scale_f32 v13, s[6:7], v10, v10, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v14, v13
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
-; SI-NEXT:    v_fma_f32 v8, v9, v8, v8
-; SI-NEXT:    v_mul_f32_e32 v9, v6, v8
-; SI-NEXT:    v_fma_f32 v10, -v7, v9, v6
-; SI-NEXT:    v_fma_f32 v9, v10, v8, v9
-; SI-NEXT:    v_fma_f32 v6, -v7, v9, v6
+; SI-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
+; SI-NEXT:    v_fma_f32 v14, v15, v14, v14
+; SI-NEXT:    v_mul_f32_e32 v15, v12, v14
+; SI-NEXT:    v_fma_f32 v16, -v13, v15, v12
+; SI-NEXT:    v_fma_f32 v15, v16, v14, v15
+; SI-NEXT:    v_fma_f32 v12, -v13, v15, v12
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
-; SI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
-; SI-NEXT:    v_trunc_f32_e32 v6, v6
-; SI-NEXT:    v_fma_f32 v1, -v6, v5, v1
-; SI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
-; SI-NEXT:    v_div_scale_f32 v6, s[4:5], v4, v4, v0
-; SI-NEXT:    v_rcp_f32_e32 v7, v6
+; SI-NEXT:    v_div_fmas_f32 v12, v12, v14, v15
+; SI-NEXT:    v_div_fixup_f32 v12, v12, v10, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s3, 13
+; SI-NEXT:    s_cbranch_scc1 .LBB12_23
+; SI-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; SI-NEXT:    s_sub_i32 s3, s4, s5
+; SI-NEXT:    s_add_i32 s3, s3, 12
+; SI-NEXT:  .LBB12_21: ; %frem.loop_body54
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v13, v11
+; SI-NEXT:    v_mul_f32_e32 v11, v13, v12
+; SI-NEXT:    v_rndne_f32_e32 v11, v11
+; SI-NEXT:    v_fma_f32 v11, -v11, v10, v13
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; SI-NEXT:    v_add_f32_e32 v14, v11, v10
+; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, 12
+; SI-NEXT:    s_add_i32 s3, s3, -12
+; SI-NEXT:    s_cmp_gt_i32 s3, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB12_21
+; SI-NEXT:  ; %bb.22: ; %Flow117
+; SI-NEXT:    v_mov_b32_e32 v11, v13
+; SI-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; SI-NEXT:    s_add_i32 s3, s3, -11
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, s3
+; SI-NEXT:    v_mul_f32_e32 v12, v11, v12
+; SI-NEXT:    v_rndne_f32_e32 v12, v12
+; SI-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; SI-NEXT:    v_add_f32_e32 v10, v11, v10
+; SI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v10, v10, s2
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v10, s2, v10, v2
+; SI-NEXT:  .LBB12_24:
+; SI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; SI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; SI-NEXT:    s_cbranch_vccz .LBB12_26
+; SI-NEXT:  ; %bb.25: ; %frem.else78
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v11, s2, 0, v3
+; SI-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; SI-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB12_27
+; SI-NEXT:    s_branch .LBB12_32
+; SI-NEXT:  .LBB12_26:
+; SI-NEXT:    ; implicit-def: $vgpr11
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB12_27: ; %frem.compute77
+; SI-NEXT:    s_mov_b32 s6, 0x7f800000
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v3|, s6
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v11, v3
+; SI-NEXT:    s_and_b64 s[4:5], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s4, v11
+; SI-NEXT:    s_cselect_b32 s4, s4, 0
+; SI-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
+; SI-NEXT:    v_cndmask_b32_e64 v11, |v3|, v11, s[2:3]
+; SI-NEXT:    v_ldexp_f32_e64 v12, v11, 12
+; SI-NEXT:    v_cmp_lt_f32_e64 s[2:3], |v7|, s6
+; SI-NEXT:    v_frexp_mant_f32_e64 v11, |v7|
+; SI-NEXT:    v_cndmask_b32_e64 v11, |v7|, v11, s[2:3]
+; SI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v7
+; SI-NEXT:    s_and_b64 s[2:3], s[2:3], exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v13
+; SI-NEXT:    s_cselect_b32 s5, s2, 0
+; SI-NEXT:    s_add_i32 s2, s5, -1
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, 1
+; SI-NEXT:    s_not_b32 s3, s2
+; SI-NEXT:    s_add_i32 s3, s3, s4
+; SI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v11, 1.0
+; SI-NEXT:    v_div_scale_f32 v14, s[6:7], v11, v11, 1.0
+; SI-NEXT:    v_rcp_f32_e32 v15, v14
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; SI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; SI-NEXT:    v_fma_f32 v7, v8, v7, v7
-; SI-NEXT:    v_mul_f32_e32 v8, v5, v7
-; SI-NEXT:    v_fma_f32 v9, -v6, v8, v5
-; SI-NEXT:    v_fma_f32 v8, v9, v7, v8
-; SI-NEXT:    v_fma_f32 v5, -v6, v8, v5
+; SI-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
+; SI-NEXT:    v_fma_f32 v15, v16, v15, v15
+; SI-NEXT:    v_mul_f32_e32 v16, v13, v15
+; SI-NEXT:    v_fma_f32 v17, -v14, v16, v13
+; SI-NEXT:    v_fma_f32 v16, v17, v15, v16
+; SI-NEXT:    v_fma_f32 v13, -v14, v16, v13
 ; SI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; SI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; SI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
-; SI-NEXT:    v_trunc_f32_e32 v5, v5
-; SI-NEXT:    v_fma_f32 v0, -v5, v4, v0
+; SI-NEXT:    v_div_fmas_f32 v13, v13, v15, v16
+; SI-NEXT:    v_div_fixup_f32 v13, v13, v11, 1.0
+; SI-NEXT:    s_cmp_lt_i32 s3, 13
+; SI-NEXT:    s_cbranch_scc1 .LBB12_31
+; SI-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; SI-NEXT:    s_sub_i32 s3, s4, s5
+; SI-NEXT:    s_add_i32 s3, s3, 12
+; SI-NEXT:  .LBB12_29: ; %frem.loop_body85
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v14, v12
+; SI-NEXT:    v_mul_f32_e32 v12, v14, v13
+; SI-NEXT:    v_rndne_f32_e32 v12, v12
+; SI-NEXT:    v_fma_f32 v12, -v12, v11, v14
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; SI-NEXT:    v_add_f32_e32 v15, v12, v11
+; SI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v12, v12, 12
+; SI-NEXT:    s_add_i32 s3, s3, -12
+; SI-NEXT:    s_cmp_gt_i32 s3, 12
+; SI-NEXT:    s_cbranch_scc1 .LBB12_29
+; SI-NEXT:  ; %bb.30: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v12, v14
+; SI-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; SI-NEXT:    s_add_i32 s3, s3, -11
+; SI-NEXT:    v_ldexp_f32_e64 v12, v12, s3
+; SI-NEXT:    v_mul_f32_e32 v13, v12, v13
+; SI-NEXT:    v_rndne_f32_e32 v13, v13
+; SI-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; SI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; SI-NEXT:    v_add_f32_e32 v11, v12, v11
+; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; SI-NEXT:    v_ldexp_f32_e64 v11, v11, s2
+; SI-NEXT:    s_brev_b32 s2, -2
+; SI-NEXT:    v_bfi_b32 v11, s2, v11, v3
+; SI-NEXT:  .LBB12_32: ; %Flow116
+; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
+; SI-NEXT:    s_mov_b32 s4, 0x7f800000
+; SI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; SI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; SI-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
+; SI-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc
+; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
+; SI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v1|, s4
+; SI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
+; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
+; SI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v2|, s4
+; SI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v2, v4, v10, vcc
+; SI-NEXT:    s_mov_b32 s3, 0xf000
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
+; SI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v3|, s4
+; SI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
 ; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: frem_v4f32:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    s_mov_b32 s6, s2
+; CI-NEXT:    s_mov_b32 s11, 0xf000
+; CI-NEXT:    s_mov_b32 s10, -1
+; CI-NEXT:    s_mov_b32 s6, s10
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_mov_b32 s0, s8
-; CI-NEXT:    s_mov_b32 s1, s9
-; CI-NEXT:    s_mov_b32 s8, s10
-; CI-NEXT:    s_mov_b32 s9, s11
-; CI-NEXT:    s_mov_b32 s10, s2
-; CI-NEXT:    s_mov_b32 s11, s3
-; CI-NEXT:    s_mov_b32 s7, s3
+; CI-NEXT:    s_mov_b32 s8, s2
+; CI-NEXT:    s_mov_b32 s9, s3
+; CI-NEXT:    s_mov_b32 s7, s11
 ; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
 ; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_div_scale_f32 v9, s[4:5], v7, v7, v3
-; CI-NEXT:    v_div_scale_f32 v8, vcc, v3, v7, v3
-; CI-NEXT:    v_rcp_f32_e32 v10, v9
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB12_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v8, s2, 0, v0
+; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; CI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
+; CI-NEXT:    s_cbranch_execz .LBB12_3
+; CI-NEXT:    s_branch .LBB12_8
+; CI-NEXT:  .LBB12_2:
+; CI-NEXT:    ; implicit-def: $vgpr8
+; CI-NEXT:  .LBB12_3: ; %frem.compute
+; CI-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
+; CI-NEXT:    v_ldexp_f32_e64 v9, v9, 1
+; CI-NEXT:    v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
+; CI-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
+; CI-NEXT:    v_ldexp_f32_e64 v11, v8, 12
+; CI-NEXT:    v_add_i32_e32 v8, vcc, -1, v14
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
+; CI-NEXT:    v_not_b32_e32 v10, v8
+; CI-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v16, v15
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
-; CI-NEXT:    v_fma_f32 v10, v11, v10, v10
-; CI-NEXT:    v_mul_f32_e32 v11, v8, v10
-; CI-NEXT:    v_fma_f32 v12, -v9, v11, v8
-; CI-NEXT:    v_fma_f32 v11, v12, v10, v11
-; CI-NEXT:    v_fma_f32 v8, -v9, v11, v8
+; CI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
+; CI-NEXT:    v_fma_f32 v16, v17, v16, v16
+; CI-NEXT:    v_mul_f32_e32 v17, v12, v16
+; CI-NEXT:    v_fma_f32 v18, -v15, v17, v12
+; CI-NEXT:    v_fma_f32 v17, v18, v16, v17
+; CI-NEXT:    v_fma_f32 v12, -v15, v17, v12
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v8, v8, v10, v11
-; CI-NEXT:    v_div_fixup_f32 v8, v8, v7, v3
-; CI-NEXT:    v_trunc_f32_e32 v8, v8
-; CI-NEXT:    v_fma_f32 v3, -v8, v7, v3
-; CI-NEXT:    v_div_scale_f32 v8, s[4:5], v6, v6, v2
-; CI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
-; CI-NEXT:    v_rcp_f32_e32 v9, v8
+; CI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v10
+; CI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB12_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v10, vcc, v13, v14
+; CI-NEXT:    v_add_i32_e32 v10, vcc, 12, v10
+; CI-NEXT:  .LBB12_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v13, v11
+; CI-NEXT:    v_mul_f32_e32 v11, v13, v12
+; CI-NEXT:    v_rndne_f32_e32 v11, v11
+; CI-NEXT:    v_fma_f32 v11, -v11, v9, v13
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; CI-NEXT:    v_add_f32_e32 v14, v11, v9
+; CI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; CI-NEXT:    v_add_i32_e32 v10, vcc, -12, v10
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v10
+; CI-NEXT:    v_ldexp_f32_e64 v11, v11, 12
+; CI-NEXT:    s_cbranch_vccnz .LBB12_5
+; CI-NEXT:  ; %bb.6: ; %Flow125
+; CI-NEXT:    v_mov_b32_e32 v11, v13
+; CI-NEXT:  .LBB12_7: ; %frem.loop_exit
+; CI-NEXT:    v_add_i32_e32 v10, vcc, -11, v10
+; CI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
+; CI-NEXT:    v_mul_f32_e32 v11, v10, v12
+; CI-NEXT:    v_rndne_f32_e32 v11, v11
+; CI-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; CI-NEXT:    v_add_f32_e32 v9, v10, v9
+; CI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v8, v9, v8
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v8, s2, v8, v0
+; CI-NEXT:  .LBB12_8:
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB12_10
+; CI-NEXT:  ; %bb.9: ; %frem.else16
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v9, s2, 0, v1
+; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; CI-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
+; CI-NEXT:    s_cbranch_execz .LBB12_11
+; CI-NEXT:    s_branch .LBB12_16
+; CI-NEXT:  .LBB12_10:
+; CI-NEXT:    ; implicit-def: $vgpr9
+; CI-NEXT:  .LBB12_11: ; %frem.compute15
+; CI-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
+; CI-NEXT:    v_ldexp_f32_e64 v10, v10, 1
+; CI-NEXT:    v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
+; CI-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
+; CI-NEXT:    v_ldexp_f32_e64 v12, v9, 12
+; CI-NEXT:    v_add_i32_e32 v9, vcc, -1, v15
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
+; CI-NEXT:    v_not_b32_e32 v11, v9
+; CI-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
+; CI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v17, v16
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
-; CI-NEXT:    v_fma_f32 v9, v10, v9, v9
-; CI-NEXT:    v_mul_f32_e32 v10, v7, v9
-; CI-NEXT:    v_fma_f32 v11, -v8, v10, v7
-; CI-NEXT:    v_fma_f32 v10, v11, v9, v10
-; CI-NEXT:    v_fma_f32 v7, -v8, v10, v7
+; CI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
+; CI-NEXT:    v_fma_f32 v17, v18, v17, v17
+; CI-NEXT:    v_mul_f32_e32 v18, v13, v17
+; CI-NEXT:    v_fma_f32 v19, -v16, v18, v13
+; CI-NEXT:    v_fma_f32 v18, v19, v17, v18
+; CI-NEXT:    v_fma_f32 v13, -v16, v18, v13
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v7, v7, v9, v10
-; CI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
-; CI-NEXT:    v_trunc_f32_e32 v7, v7
-; CI-NEXT:    v_fma_f32 v2, -v7, v6, v2
-; CI-NEXT:    v_div_scale_f32 v7, s[4:5], v5, v5, v1
-; CI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
-; CI-NEXT:    v_rcp_f32_e32 v8, v7
+; CI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v11
+; CI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB12_15
+; CI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; CI-NEXT:    v_sub_i32_e32 v11, vcc, v14, v15
+; CI-NEXT:    v_add_i32_e32 v11, vcc, 12, v11
+; CI-NEXT:  .LBB12_13: ; %frem.loop_body23
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v14, v12
+; CI-NEXT:    v_mul_f32_e32 v12, v14, v13
+; CI-NEXT:    v_rndne_f32_e32 v12, v12
+; CI-NEXT:    v_fma_f32 v12, -v12, v10, v14
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; CI-NEXT:    v_add_f32_e32 v15, v12, v10
+; CI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
+; CI-NEXT:    v_add_i32_e32 v11, vcc, -12, v11
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v11
+; CI-NEXT:    v_ldexp_f32_e64 v12, v12, 12
+; CI-NEXT:    s_cbranch_vccnz .LBB12_13
+; CI-NEXT:  ; %bb.14: ; %Flow121
+; CI-NEXT:    v_mov_b32_e32 v12, v14
+; CI-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; CI-NEXT:    v_add_i32_e32 v11, vcc, -11, v11
+; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
+; CI-NEXT:    v_mul_f32_e32 v12, v11, v13
+; CI-NEXT:    v_rndne_f32_e32 v12, v12
+; CI-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; CI-NEXT:    v_add_f32_e32 v10, v11, v10
+; CI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v9, v10, v9
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v9, s2, v9, v1
+; CI-NEXT:  .LBB12_16:
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB12_18
+; CI-NEXT:  ; %bb.17: ; %frem.else47
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v10, s2, 0, v2
+; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; CI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
+; CI-NEXT:    s_cbranch_execz .LBB12_19
+; CI-NEXT:    s_branch .LBB12_24
+; CI-NEXT:  .LBB12_18:
+; CI-NEXT:    ; implicit-def: $vgpr10
+; CI-NEXT:  .LBB12_19: ; %frem.compute46
+; CI-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
+; CI-NEXT:    v_ldexp_f32_e64 v11, v11, 1
+; CI-NEXT:    v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
+; CI-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
+; CI-NEXT:    v_ldexp_f32_e64 v13, v10, 12
+; CI-NEXT:    v_add_i32_e32 v10, vcc, -1, v16
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
+; CI-NEXT:    v_not_b32_e32 v12, v10
+; CI-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v18, v17
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
-; CI-NEXT:    v_fma_f32 v8, v9, v8, v8
-; CI-NEXT:    v_mul_f32_e32 v9, v6, v8
-; CI-NEXT:    v_fma_f32 v10, -v7, v9, v6
-; CI-NEXT:    v_fma_f32 v9, v10, v8, v9
-; CI-NEXT:    v_fma_f32 v6, -v7, v9, v6
+; CI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
+; CI-NEXT:    v_fma_f32 v18, v19, v18, v18
+; CI-NEXT:    v_mul_f32_e32 v19, v14, v18
+; CI-NEXT:    v_fma_f32 v20, -v17, v19, v14
+; CI-NEXT:    v_fma_f32 v19, v20, v18, v19
+; CI-NEXT:    v_fma_f32 v14, -v17, v19, v14
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v6, v6, v8, v9
-; CI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
-; CI-NEXT:    v_trunc_f32_e32 v6, v6
-; CI-NEXT:    v_fma_f32 v1, -v6, v5, v1
-; CI-NEXT:    v_div_scale_f32 v6, s[4:5], v4, v4, v0
-; CI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
-; CI-NEXT:    v_rcp_f32_e32 v7, v6
+; CI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v12
+; CI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB12_23
+; CI-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; CI-NEXT:    v_sub_i32_e32 v12, vcc, v15, v16
+; CI-NEXT:    v_add_i32_e32 v12, vcc, 12, v12
+; CI-NEXT:  .LBB12_21: ; %frem.loop_body54
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v15, v13
+; CI-NEXT:    v_mul_f32_e32 v13, v15, v14
+; CI-NEXT:    v_rndne_f32_e32 v13, v13
+; CI-NEXT:    v_fma_f32 v13, -v13, v11, v15
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; CI-NEXT:    v_add_f32_e32 v16, v13, v11
+; CI-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
+; CI-NEXT:    v_add_i32_e32 v12, vcc, -12, v12
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v12
+; CI-NEXT:    v_ldexp_f32_e64 v13, v13, 12
+; CI-NEXT:    s_cbranch_vccnz .LBB12_21
+; CI-NEXT:  ; %bb.22: ; %Flow117
+; CI-NEXT:    v_mov_b32_e32 v13, v15
+; CI-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; CI-NEXT:    v_add_i32_e32 v12, vcc, -11, v12
+; CI-NEXT:    v_ldexp_f32_e32 v12, v13, v12
+; CI-NEXT:    v_mul_f32_e32 v13, v12, v14
+; CI-NEXT:    v_rndne_f32_e32 v13, v13
+; CI-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; CI-NEXT:    v_add_f32_e32 v11, v12, v11
+; CI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v10, v11, v10
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v10, s2, v10, v2
+; CI-NEXT:  .LBB12_24:
+; CI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB12_26
+; CI-NEXT:  ; %bb.25: ; %frem.else78
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v11, s2, 0, v3
+; CI-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; CI-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
+; CI-NEXT:    s_cbranch_execz .LBB12_27
+; CI-NEXT:    s_branch .LBB12_32
+; CI-NEXT:  .LBB12_26:
+; CI-NEXT:    ; implicit-def: $vgpr11
+; CI-NEXT:  .LBB12_27: ; %frem.compute77
+; CI-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
+; CI-NEXT:    v_ldexp_f32_e64 v12, v12, 1
+; CI-NEXT:    v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
+; CI-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
+; CI-NEXT:    v_ldexp_f32_e64 v14, v11, 12
+; CI-NEXT:    v_add_i32_e32 v11, vcc, -1, v17
+; CI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
+; CI-NEXT:    v_not_b32_e32 v13, v11
+; CI-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; CI-NEXT:    v_rcp_f32_e32 v19, v18
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; CI-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
-; CI-NEXT:    v_fma_f32 v7, v8, v7, v7
-; CI-NEXT:    v_mul_f32_e32 v8, v5, v7
-; CI-NEXT:    v_fma_f32 v9, -v6, v8, v5
-; CI-NEXT:    v_fma_f32 v8, v9, v7, v8
-; CI-NEXT:    v_fma_f32 v5, -v6, v8, v5
+; CI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
+; CI-NEXT:    v_fma_f32 v19, v20, v19, v19
+; CI-NEXT:    v_mul_f32_e32 v20, v15, v19
+; CI-NEXT:    v_fma_f32 v21, -v18, v20, v15
+; CI-NEXT:    v_fma_f32 v20, v21, v19, v20
+; CI-NEXT:    v_fma_f32 v15, -v18, v20, v15
 ; CI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; CI-NEXT:    v_div_fmas_f32 v5, v5, v7, v8
-; CI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
-; CI-NEXT:    v_trunc_f32_e32 v5, v5
-; CI-NEXT:    v_fma_f32 v0, -v5, v4, v0
+; CI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v13
+; CI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB12_31
+; CI-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; CI-NEXT:    v_sub_i32_e32 v13, vcc, v16, v17
+; CI-NEXT:    v_add_i32_e32 v13, vcc, 12, v13
+; CI-NEXT:  .LBB12_29: ; %frem.loop_body85
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v16, v14
+; CI-NEXT:    v_mul_f32_e32 v14, v16, v15
+; CI-NEXT:    v_rndne_f32_e32 v14, v14
+; CI-NEXT:    v_fma_f32 v14, -v14, v12, v16
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
+; CI-NEXT:    v_add_f32_e32 v17, v14, v12
+; CI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
+; CI-NEXT:    v_add_i32_e32 v13, vcc, -12, v13
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v13
+; CI-NEXT:    v_ldexp_f32_e64 v14, v14, 12
+; CI-NEXT:    s_cbranch_vccnz .LBB12_29
+; CI-NEXT:  ; %bb.30: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v14, v16
+; CI-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; CI-NEXT:    v_add_i32_e32 v13, vcc, -11, v13
+; CI-NEXT:    v_ldexp_f32_e32 v13, v14, v13
+; CI-NEXT:    v_mul_f32_e32 v14, v13, v15
+; CI-NEXT:    v_rndne_f32_e32 v14, v14
+; CI-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; CI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; CI-NEXT:    v_add_f32_e32 v12, v13, v12
+; CI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
+; CI-NEXT:    v_ldexp_f32_e32 v11, v12, v11
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_bfi_b32 v11, s2, v11, v3
+; CI-NEXT:  .LBB12_32: ; %Flow116
+; CI-NEXT:    s_mov_b32 s4, 0x7f800000
+; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
+; CI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; CI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; CI-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
+; CI-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc
+; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
+; CI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v1|, s4
+; CI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; CI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
+; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
+; CI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v2|, s4
+; CI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; CI-NEXT:    v_cndmask_b32_e32 v2, v4, v10, vcc
+; CI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
+; CI-NEXT:    v_cmp_nge_f32_e64 s[4:5], |v3|, s4
+; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
 ; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; CI-NEXT:    s_endpgm
 ;
@@ -4666,78 +13857,308 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v8, s0
-; VI-NEXT:    s_add_u32 s0, s4, 64
-; VI-NEXT:    v_mov_b32_e32 v9, s1
-; VI-NEXT:    s_addc_u32 s1, s5, 0
-; VI-NEXT:    v_mov_b32_e32 v5, s1
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    s_add_u32 s2, s4, 64
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    s_addc_u32 s3, s5, 0
+; VI-NEXT:    v_mov_b32_e32 v5, s3
+; VI-NEXT:    v_mov_b32_e32 v4, s2
 ; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
 ; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_div_scale_f32 v11, s[0:1], v7, v7, v3
-; VI-NEXT:    v_div_scale_f32 v10, vcc, v3, v7, v3
-; VI-NEXT:    v_rcp_f32_e32 v12, v11
+; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB12_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v8, s2, 0, v0
+; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; VI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
+; VI-NEXT:    s_cbranch_execz .LBB12_3
+; VI-NEXT:    s_branch .LBB12_8
+; VI-NEXT:  .LBB12_2:
+; VI-NEXT:    ; implicit-def: $vgpr8
+; VI-NEXT:  .LBB12_3: ; %frem.compute
+; VI-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
+; VI-NEXT:    v_ldexp_f32 v9, v9, 1
+; VI-NEXT:    v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
+; VI-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
+; VI-NEXT:    v_ldexp_f32 v11, v8, 12
+; VI-NEXT:    v_add_u32_e32 v8, vcc, -1, v14
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
+; VI-NEXT:    v_not_b32_e32 v10, v8
+; VI-NEXT:    v_add_u32_e32 v10, vcc, v10, v13
+; VI-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v16, v15
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT:    v_fma_f32 v13, -v11, v12, 1.0
-; VI-NEXT:    v_fma_f32 v12, v13, v12, v12
-; VI-NEXT:    v_mul_f32_e32 v13, v10, v12
-; VI-NEXT:    v_fma_f32 v14, -v11, v13, v10
-; VI-NEXT:    v_fma_f32 v13, v14, v12, v13
-; VI-NEXT:    v_fma_f32 v10, -v11, v13, v10
+; VI-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
+; VI-NEXT:    v_fma_f32 v16, v17, v16, v16
+; VI-NEXT:    v_mul_f32_e32 v17, v12, v16
+; VI-NEXT:    v_fma_f32 v18, -v15, v17, v12
+; VI-NEXT:    v_fma_f32 v17, v18, v16, v17
+; VI-NEXT:    v_fma_f32 v12, -v15, v17, v12
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT:    v_div_fmas_f32 v10, v10, v12, v13
-; VI-NEXT:    v_div_fixup_f32 v10, v10, v7, v3
-; VI-NEXT:    v_trunc_f32_e32 v10, v10
-; VI-NEXT:    v_fma_f32 v3, -v10, v7, v3
-; VI-NEXT:    v_div_scale_f32 v10, s[0:1], v6, v6, v2
-; VI-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
-; VI-NEXT:    v_rcp_f32_e32 v11, v10
+; VI-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v10
+; VI-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB12_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v10, vcc, v13, v14
+; VI-NEXT:    v_add_u32_e32 v10, vcc, 12, v10
+; VI-NEXT:  .LBB12_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v13, v11
+; VI-NEXT:    v_mul_f32_e32 v11, v13, v12
+; VI-NEXT:    v_rndne_f32_e32 v11, v11
+; VI-NEXT:    v_fma_f32 v11, -v11, v9, v13
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; VI-NEXT:    v_add_f32_e32 v14, v11, v9
+; VI-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; VI-NEXT:    v_add_u32_e32 v10, vcc, -12, v10
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v10
+; VI-NEXT:    v_ldexp_f32 v11, v11, 12
+; VI-NEXT:    s_cbranch_vccnz .LBB12_5
+; VI-NEXT:  ; %bb.6: ; %Flow125
+; VI-NEXT:    v_mov_b32_e32 v11, v13
+; VI-NEXT:  .LBB12_7: ; %frem.loop_exit
+; VI-NEXT:    v_add_u32_e32 v10, vcc, -11, v10
+; VI-NEXT:    v_ldexp_f32 v10, v11, v10
+; VI-NEXT:    v_mul_f32_e32 v11, v10, v12
+; VI-NEXT:    v_rndne_f32_e32 v11, v11
+; VI-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; VI-NEXT:    v_add_f32_e32 v9, v10, v9
+; VI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; VI-NEXT:    v_ldexp_f32 v8, v9, v8
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v8, s2, v8, v0
+; VI-NEXT:  .LBB12_8:
+; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB12_10
+; VI-NEXT:  ; %bb.9: ; %frem.else16
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v9, s2, 0, v1
+; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; VI-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
+; VI-NEXT:    s_cbranch_execz .LBB12_11
+; VI-NEXT:    s_branch .LBB12_16
+; VI-NEXT:  .LBB12_10:
+; VI-NEXT:    ; implicit-def: $vgpr9
+; VI-NEXT:  .LBB12_11: ; %frem.compute15
+; VI-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
+; VI-NEXT:    v_ldexp_f32 v10, v10, 1
+; VI-NEXT:    v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
+; VI-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
+; VI-NEXT:    v_ldexp_f32 v12, v9, 12
+; VI-NEXT:    v_add_u32_e32 v9, vcc, -1, v15
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
+; VI-NEXT:    v_not_b32_e32 v11, v9
+; VI-NEXT:    v_add_u32_e32 v11, vcc, v11, v14
+; VI-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v17, v16
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
-; VI-NEXT:    v_fma_f32 v11, v12, v11, v11
-; VI-NEXT:    v_mul_f32_e32 v12, v7, v11
-; VI-NEXT:    v_fma_f32 v13, -v10, v12, v7
-; VI-NEXT:    v_fma_f32 v12, v13, v11, v12
-; VI-NEXT:    v_fma_f32 v7, -v10, v12, v7
+; VI-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
+; VI-NEXT:    v_fma_f32 v17, v18, v17, v17
+; VI-NEXT:    v_mul_f32_e32 v18, v13, v17
+; VI-NEXT:    v_fma_f32 v19, -v16, v18, v13
+; VI-NEXT:    v_fma_f32 v18, v19, v17, v18
+; VI-NEXT:    v_fma_f32 v13, -v16, v18, v13
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT:    v_div_fmas_f32 v7, v7, v11, v12
-; VI-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
-; VI-NEXT:    v_trunc_f32_e32 v7, v7
-; VI-NEXT:    v_fma_f32 v2, -v7, v6, v2
-; VI-NEXT:    v_div_scale_f32 v7, s[0:1], v5, v5, v1
-; VI-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
-; VI-NEXT:    v_rcp_f32_e32 v10, v7
+; VI-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v11
+; VI-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB12_15
+; VI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; VI-NEXT:    v_sub_u32_e32 v11, vcc, v14, v15
+; VI-NEXT:    v_add_u32_e32 v11, vcc, 12, v11
+; VI-NEXT:  .LBB12_13: ; %frem.loop_body23
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v14, v12
+; VI-NEXT:    v_mul_f32_e32 v12, v14, v13
+; VI-NEXT:    v_rndne_f32_e32 v12, v12
+; VI-NEXT:    v_fma_f32 v12, -v12, v10, v14
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; VI-NEXT:    v_add_f32_e32 v15, v12, v10
+; VI-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
+; VI-NEXT:    v_add_u32_e32 v11, vcc, -12, v11
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v11
+; VI-NEXT:    v_ldexp_f32 v12, v12, 12
+; VI-NEXT:    s_cbranch_vccnz .LBB12_13
+; VI-NEXT:  ; %bb.14: ; %Flow121
+; VI-NEXT:    v_mov_b32_e32 v12, v14
+; VI-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; VI-NEXT:    v_add_u32_e32 v11, vcc, -11, v11
+; VI-NEXT:    v_ldexp_f32 v11, v12, v11
+; VI-NEXT:    v_mul_f32_e32 v12, v11, v13
+; VI-NEXT:    v_rndne_f32_e32 v12, v12
+; VI-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; VI-NEXT:    v_add_f32_e32 v10, v11, v10
+; VI-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; VI-NEXT:    v_ldexp_f32 v9, v10, v9
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v9, s2, v9, v1
+; VI-NEXT:  .LBB12_16:
+; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB12_18
+; VI-NEXT:  ; %bb.17: ; %frem.else47
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v10, s2, 0, v2
+; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; VI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
+; VI-NEXT:    s_cbranch_execz .LBB12_19
+; VI-NEXT:    s_branch .LBB12_24
+; VI-NEXT:  .LBB12_18:
+; VI-NEXT:    ; implicit-def: $vgpr10
+; VI-NEXT:  .LBB12_19: ; %frem.compute46
+; VI-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
+; VI-NEXT:    v_ldexp_f32 v11, v11, 1
+; VI-NEXT:    v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
+; VI-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
+; VI-NEXT:    v_ldexp_f32 v13, v10, 12
+; VI-NEXT:    v_add_u32_e32 v10, vcc, -1, v16
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
+; VI-NEXT:    v_not_b32_e32 v12, v10
+; VI-NEXT:    v_add_u32_e32 v12, vcc, v12, v15
+; VI-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v18, v17
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT:    v_fma_f32 v11, -v7, v10, 1.0
-; VI-NEXT:    v_fma_f32 v10, v11, v10, v10
-; VI-NEXT:    v_mul_f32_e32 v11, v6, v10
-; VI-NEXT:    v_fma_f32 v12, -v7, v11, v6
-; VI-NEXT:    v_fma_f32 v11, v12, v10, v11
-; VI-NEXT:    v_fma_f32 v6, -v7, v11, v6
+; VI-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
+; VI-NEXT:    v_fma_f32 v18, v19, v18, v18
+; VI-NEXT:    v_mul_f32_e32 v19, v14, v18
+; VI-NEXT:    v_fma_f32 v20, -v17, v19, v14
+; VI-NEXT:    v_fma_f32 v19, v20, v18, v19
+; VI-NEXT:    v_fma_f32 v14, -v17, v19, v14
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT:    v_div_fmas_f32 v6, v6, v10, v11
-; VI-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
-; VI-NEXT:    v_trunc_f32_e32 v6, v6
-; VI-NEXT:    v_fma_f32 v1, -v6, v5, v1
-; VI-NEXT:    v_div_scale_f32 v6, s[0:1], v4, v4, v0
-; VI-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
-; VI-NEXT:    v_rcp_f32_e32 v7, v6
+; VI-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v12
+; VI-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB12_23
+; VI-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; VI-NEXT:    v_sub_u32_e32 v12, vcc, v15, v16
+; VI-NEXT:    v_add_u32_e32 v12, vcc, 12, v12
+; VI-NEXT:  .LBB12_21: ; %frem.loop_body54
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v15, v13
+; VI-NEXT:    v_mul_f32_e32 v13, v15, v14
+; VI-NEXT:    v_rndne_f32_e32 v13, v13
+; VI-NEXT:    v_fma_f32 v13, -v13, v11, v15
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; VI-NEXT:    v_add_f32_e32 v16, v13, v11
+; VI-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
+; VI-NEXT:    v_add_u32_e32 v12, vcc, -12, v12
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v12
+; VI-NEXT:    v_ldexp_f32 v13, v13, 12
+; VI-NEXT:    s_cbranch_vccnz .LBB12_21
+; VI-NEXT:  ; %bb.22: ; %Flow117
+; VI-NEXT:    v_mov_b32_e32 v13, v15
+; VI-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; VI-NEXT:    v_add_u32_e32 v12, vcc, -11, v12
+; VI-NEXT:    v_ldexp_f32 v12, v13, v12
+; VI-NEXT:    v_mul_f32_e32 v13, v12, v14
+; VI-NEXT:    v_rndne_f32_e32 v13, v13
+; VI-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; VI-NEXT:    v_add_f32_e32 v11, v12, v11
+; VI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; VI-NEXT:    v_ldexp_f32 v10, v11, v10
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v10, s2, v10, v2
+; VI-NEXT:  .LBB12_24:
+; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB12_26
+; VI-NEXT:  ; %bb.25: ; %frem.else78
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v11, s2, 0, v3
+; VI-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; VI-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
+; VI-NEXT:    s_cbranch_execz .LBB12_27
+; VI-NEXT:    s_branch .LBB12_32
+; VI-NEXT:  .LBB12_26:
+; VI-NEXT:    ; implicit-def: $vgpr11
+; VI-NEXT:  .LBB12_27: ; %frem.compute77
+; VI-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
+; VI-NEXT:    v_ldexp_f32 v12, v12, 1
+; VI-NEXT:    v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
+; VI-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
+; VI-NEXT:    v_ldexp_f32 v14, v11, 12
+; VI-NEXT:    v_add_u32_e32 v11, vcc, -1, v17
+; VI-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
+; VI-NEXT:    v_not_b32_e32 v13, v11
+; VI-NEXT:    v_add_u32_e32 v13, vcc, v13, v16
+; VI-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; VI-NEXT:    v_rcp_f32_e32 v19, v18
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; VI-NEXT:    v_fma_f32 v10, -v6, v7, 1.0
-; VI-NEXT:    v_fma_f32 v7, v10, v7, v7
-; VI-NEXT:    v_mul_f32_e32 v10, v5, v7
-; VI-NEXT:    v_fma_f32 v11, -v6, v10, v5
-; VI-NEXT:    v_fma_f32 v10, v11, v7, v10
-; VI-NEXT:    v_fma_f32 v5, -v6, v10, v5
+; VI-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
+; VI-NEXT:    v_fma_f32 v19, v20, v19, v19
+; VI-NEXT:    v_mul_f32_e32 v20, v15, v19
+; VI-NEXT:    v_fma_f32 v21, -v18, v20, v15
+; VI-NEXT:    v_fma_f32 v20, v21, v19, v20
+; VI-NEXT:    v_fma_f32 v15, -v18, v20, v15
 ; VI-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; VI-NEXT:    v_div_fmas_f32 v5, v5, v7, v10
-; VI-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
-; VI-NEXT:    v_trunc_f32_e32 v5, v5
-; VI-NEXT:    v_fma_f32 v0, -v5, v4, v0
-; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
+; VI-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v13
+; VI-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB12_31
+; VI-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; VI-NEXT:    v_sub_u32_e32 v13, vcc, v16, v17
+; VI-NEXT:    v_add_u32_e32 v13, vcc, 12, v13
+; VI-NEXT:  .LBB12_29: ; %frem.loop_body85
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v16, v14
+; VI-NEXT:    v_mul_f32_e32 v14, v16, v15
+; VI-NEXT:    v_rndne_f32_e32 v14, v14
+; VI-NEXT:    v_fma_f32 v14, -v14, v12, v16
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
+; VI-NEXT:    v_add_f32_e32 v17, v14, v12
+; VI-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
+; VI-NEXT:    v_add_u32_e32 v13, vcc, -12, v13
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v13
+; VI-NEXT:    v_ldexp_f32 v14, v14, 12
+; VI-NEXT:    s_cbranch_vccnz .LBB12_29
+; VI-NEXT:  ; %bb.30: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v14, v16
+; VI-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; VI-NEXT:    v_add_u32_e32 v13, vcc, -11, v13
+; VI-NEXT:    v_ldexp_f32 v13, v14, v13
+; VI-NEXT:    v_mul_f32_e32 v14, v13, v15
+; VI-NEXT:    v_rndne_f32_e32 v14, v14
+; VI-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; VI-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; VI-NEXT:    v_add_f32_e32 v12, v13, v12
+; VI-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
+; VI-NEXT:    v_ldexp_f32 v11, v12, v11
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_bfi_b32 v11, s2, v11, v3
+; VI-NEXT:  .LBB12_32: ; %Flow116
+; VI-NEXT:    s_mov_b32 s4, 0x7f800000
+; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
+; VI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_mov_b32_e32 v12, 0x7fc00000
+; VI-NEXT:    v_cndmask_b32_e32 v0, v12, v8, vcc
+; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
+; VI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v1|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v1, v12, v9, vcc
+; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
+; VI-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v2|, s4
+; VI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v2, v12, v10, vcc
+; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    v_mov_b32_e32 v5, s1
+; VI-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
+; VI-NEXT:    v_cmp_nge_f32_e64 s[0:1], |v3|, s4
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v3, v12, v11, vcc
+; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: frem_v4f32:
@@ -4749,67 +14170,298 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX9-NEXT:    global_load_dwordx4 v[0:3], v8, s[2:3]
 ; GFX9-NEXT:    global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_div_scale_f32 v10, s[2:3], v7, v7, v3
-; GFX9-NEXT:    v_div_scale_f32 v9, vcc, v3, v7, v3
-; GFX9-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v0|, |v4|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB12_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v8, s2, 0, v0
+; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v0|, |v4|
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB12_3
+; GFX9-NEXT:    s_branch .LBB12_8
+; GFX9-NEXT:  .LBB12_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr8
+; GFX9-NEXT:  .LBB12_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
+; GFX9-NEXT:    v_ldexp_f32 v9, v9, 1
+; GFX9-NEXT:    v_div_scale_f32 v15, s[2:3], v9, v9, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v12, vcc, 1.0, v9, 1.0
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v13, v0
+; GFX9-NEXT:    v_ldexp_f32 v11, v8, 12
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v14, v4
+; GFX9-NEXT:    v_add_u32_e32 v8, -1, v14
+; GFX9-NEXT:    v_not_b32_e32 v10, v8
+; GFX9-NEXT:    v_add_u32_e32 v10, v10, v13
+; GFX9-NEXT:    v_rcp_f32_e32 v16, v15
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX9-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
-; GFX9-NEXT:    v_fma_f32 v11, v12, v11, v11
-; GFX9-NEXT:    v_mul_f32_e32 v12, v9, v11
-; GFX9-NEXT:    v_fma_f32 v13, -v10, v12, v9
-; GFX9-NEXT:    v_fma_f32 v12, v13, v11, v12
-; GFX9-NEXT:    v_fma_f32 v9, -v10, v12, v9
+; GFX9-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
+; GFX9-NEXT:    v_fma_f32 v16, v17, v16, v16
+; GFX9-NEXT:    v_mul_f32_e32 v17, v12, v16
+; GFX9-NEXT:    v_fma_f32 v18, -v15, v17, v12
+; GFX9-NEXT:    v_fma_f32 v17, v18, v16, v17
+; GFX9-NEXT:    v_fma_f32 v12, -v15, v17, v12
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT:    v_div_fmas_f32 v9, v9, v11, v12
-; GFX9-NEXT:    v_div_fixup_f32 v9, v9, v7, v3
-; GFX9-NEXT:    v_trunc_f32_e32 v9, v9
-; GFX9-NEXT:    v_fma_f32 v3, -v9, v7, v3
-; GFX9-NEXT:    v_div_scale_f32 v9, s[2:3], v6, v6, v2
-; GFX9-NEXT:    v_div_scale_f32 v7, vcc, v2, v6, v2
-; GFX9-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX9-NEXT:    v_div_fmas_f32 v12, v12, v16, v17
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v10
+; GFX9-NEXT:    v_div_fixup_f32 v12, v12, v9, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v10, v13, v14
+; GFX9-NEXT:    v_add_u32_e32 v10, 12, v10
+; GFX9-NEXT:  .LBB12_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v13, v11
+; GFX9-NEXT:    v_mul_f32_e32 v11, v13, v12
+; GFX9-NEXT:    v_rndne_f32_e32 v11, v11
+; GFX9-NEXT:    v_fma_f32 v11, -v11, v9, v13
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; GFX9-NEXT:    v_add_f32_e32 v14, v11, v9
+; GFX9-NEXT:    v_add_u32_e32 v10, -12, v10
+; GFX9-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v10
+; GFX9-NEXT:    v_ldexp_f32 v11, v11, 12
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow125
+; GFX9-NEXT:    v_mov_b32_e32 v11, v13
+; GFX9-NEXT:  .LBB12_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_add_u32_e32 v10, -11, v10
+; GFX9-NEXT:    v_ldexp_f32 v10, v11, v10
+; GFX9-NEXT:    v_mul_f32_e32 v11, v10, v12
+; GFX9-NEXT:    v_rndne_f32_e32 v11, v11
+; GFX9-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v10
+; GFX9-NEXT:    v_add_f32_e32 v9, v10, v9
+; GFX9-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; GFX9-NEXT:    v_ldexp_f32 v8, v9, v8
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v8, s2, v8, v0
+; GFX9-NEXT:  .LBB12_8:
+; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v1|, |v5|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB12_10
+; GFX9-NEXT:  ; %bb.9: ; %frem.else16
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v9, s2, 0, v1
+; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v1|, |v5|
+; GFX9-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB12_11
+; GFX9-NEXT:    s_branch .LBB12_16
+; GFX9-NEXT:  .LBB12_10:
+; GFX9-NEXT:    ; implicit-def: $vgpr9
+; GFX9-NEXT:  .LBB12_11: ; %frem.compute15
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
+; GFX9-NEXT:    v_ldexp_f32 v10, v10, 1
+; GFX9-NEXT:    v_div_scale_f32 v16, s[2:3], v10, v10, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v13, vcc, 1.0, v10, 1.0
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v14, v1
+; GFX9-NEXT:    v_ldexp_f32 v12, v9, 12
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v15, v5
+; GFX9-NEXT:    v_add_u32_e32 v9, -1, v15
+; GFX9-NEXT:    v_not_b32_e32 v11, v9
+; GFX9-NEXT:    v_add_u32_e32 v11, v11, v14
+; GFX9-NEXT:    v_rcp_f32_e32 v17, v16
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX9-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
-; GFX9-NEXT:    v_fma_f32 v10, v11, v10, v10
-; GFX9-NEXT:    v_mul_f32_e32 v11, v7, v10
-; GFX9-NEXT:    v_fma_f32 v12, -v9, v11, v7
-; GFX9-NEXT:    v_fma_f32 v11, v12, v10, v11
-; GFX9-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX9-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
+; GFX9-NEXT:    v_fma_f32 v17, v18, v17, v17
+; GFX9-NEXT:    v_mul_f32_e32 v18, v13, v17
+; GFX9-NEXT:    v_fma_f32 v19, -v16, v18, v13
+; GFX9-NEXT:    v_fma_f32 v18, v19, v17, v18
+; GFX9-NEXT:    v_fma_f32 v13, -v16, v18, v13
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
-; GFX9-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
-; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
-; GFX9-NEXT:    v_fma_f32 v2, -v7, v6, v2
-; GFX9-NEXT:    v_div_scale_f32 v7, s[2:3], v5, v5, v1
-; GFX9-NEXT:    v_div_scale_f32 v6, vcc, v1, v5, v1
-; GFX9-NEXT:    v_rcp_f32_e32 v9, v7
+; GFX9-NEXT:    v_div_fmas_f32 v13, v13, v17, v18
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v11
+; GFX9-NEXT:    v_div_fixup_f32 v13, v13, v10, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_15
+; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v11, v14, v15
+; GFX9-NEXT:    v_add_u32_e32 v11, 12, v11
+; GFX9-NEXT:  .LBB12_13: ; %frem.loop_body23
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v14, v12
+; GFX9-NEXT:    v_mul_f32_e32 v12, v14, v13
+; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX9-NEXT:    v_fma_f32 v12, -v12, v10, v14
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; GFX9-NEXT:    v_add_f32_e32 v15, v12, v10
+; GFX9-NEXT:    v_add_u32_e32 v11, -12, v11
+; GFX9-NEXT:    v_cndmask_b32_e32 v12, v12, v15, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v11
+; GFX9-NEXT:    v_ldexp_f32 v12, v12, 12
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_13
+; GFX9-NEXT:  ; %bb.14: ; %Flow121
+; GFX9-NEXT:    v_mov_b32_e32 v12, v14
+; GFX9-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; GFX9-NEXT:    v_add_u32_e32 v11, -11, v11
+; GFX9-NEXT:    v_ldexp_f32 v11, v12, v11
+; GFX9-NEXT:    v_mul_f32_e32 v12, v11, v13
+; GFX9-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX9-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v11
+; GFX9-NEXT:    v_add_f32_e32 v10, v11, v10
+; GFX9-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; GFX9-NEXT:    v_ldexp_f32 v9, v10, v9
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v9, s2, v9, v1
+; GFX9-NEXT:  .LBB12_16:
+; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v2|, |v6|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB12_18
+; GFX9-NEXT:  ; %bb.17: ; %frem.else47
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v10, s2, 0, v2
+; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v2|, |v6|
+; GFX9-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB12_19
+; GFX9-NEXT:    s_branch .LBB12_24
+; GFX9-NEXT:  .LBB12_18:
+; GFX9-NEXT:    ; implicit-def: $vgpr10
+; GFX9-NEXT:  .LBB12_19: ; %frem.compute46
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
+; GFX9-NEXT:    v_ldexp_f32 v11, v11, 1
+; GFX9-NEXT:    v_div_scale_f32 v17, s[2:3], v11, v11, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v14, vcc, 1.0, v11, 1.0
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v15, v2
+; GFX9-NEXT:    v_ldexp_f32 v13, v10, 12
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v16, v6
+; GFX9-NEXT:    v_add_u32_e32 v10, -1, v16
+; GFX9-NEXT:    v_not_b32_e32 v12, v10
+; GFX9-NEXT:    v_add_u32_e32 v12, v12, v15
+; GFX9-NEXT:    v_rcp_f32_e32 v18, v17
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX9-NEXT:    v_fma_f32 v10, -v7, v9, 1.0
-; GFX9-NEXT:    v_fma_f32 v9, v10, v9, v9
-; GFX9-NEXT:    v_mul_f32_e32 v10, v6, v9
-; GFX9-NEXT:    v_fma_f32 v11, -v7, v10, v6
-; GFX9-NEXT:    v_fma_f32 v10, v11, v9, v10
-; GFX9-NEXT:    v_fma_f32 v6, -v7, v10, v6
+; GFX9-NEXT:    v_fma_f32 v19, -v17, v18, 1.0
+; GFX9-NEXT:    v_fma_f32 v18, v19, v18, v18
+; GFX9-NEXT:    v_mul_f32_e32 v19, v14, v18
+; GFX9-NEXT:    v_fma_f32 v20, -v17, v19, v14
+; GFX9-NEXT:    v_fma_f32 v19, v20, v18, v19
+; GFX9-NEXT:    v_fma_f32 v14, -v17, v19, v14
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
-; GFX9-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
-; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
-; GFX9-NEXT:    v_fma_f32 v1, -v6, v5, v1
-; GFX9-NEXT:    v_div_scale_f32 v6, s[2:3], v4, v4, v0
-; GFX9-NEXT:    v_div_scale_f32 v5, vcc, v0, v4, v0
-; GFX9-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX9-NEXT:    v_div_fmas_f32 v14, v14, v18, v19
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v12
+; GFX9-NEXT:    v_div_fixup_f32 v14, v14, v11, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_23
+; GFX9-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v12, v15, v16
+; GFX9-NEXT:    v_add_u32_e32 v12, 12, v12
+; GFX9-NEXT:  .LBB12_21: ; %frem.loop_body54
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v15, v13
+; GFX9-NEXT:    v_mul_f32_e32 v13, v15, v14
+; GFX9-NEXT:    v_rndne_f32_e32 v13, v13
+; GFX9-NEXT:    v_fma_f32 v13, -v13, v11, v15
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; GFX9-NEXT:    v_add_f32_e32 v16, v13, v11
+; GFX9-NEXT:    v_add_u32_e32 v12, -12, v12
+; GFX9-NEXT:    v_cndmask_b32_e32 v13, v13, v16, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v12
+; GFX9-NEXT:    v_ldexp_f32 v13, v13, 12
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_21
+; GFX9-NEXT:  ; %bb.22: ; %Flow117
+; GFX9-NEXT:    v_mov_b32_e32 v13, v15
+; GFX9-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; GFX9-NEXT:    v_add_u32_e32 v12, -11, v12
+; GFX9-NEXT:    v_ldexp_f32 v12, v13, v12
+; GFX9-NEXT:    v_mul_f32_e32 v13, v12, v14
+; GFX9-NEXT:    v_rndne_f32_e32 v13, v13
+; GFX9-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v12
+; GFX9-NEXT:    v_add_f32_e32 v11, v12, v11
+; GFX9-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; GFX9-NEXT:    v_ldexp_f32 v10, v11, v10
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v10, s2, v10, v2
+; GFX9-NEXT:  .LBB12_24:
+; GFX9-NEXT:    v_cmp_ngt_f32_e64 s[2:3], |v3|, |v7|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB12_26
+; GFX9-NEXT:  ; %bb.25: ; %frem.else78
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v11, s2, 0, v3
+; GFX9-NEXT:    v_cmp_eq_f32_e64 vcc, |v3|, |v7|
+; GFX9-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB12_27
+; GFX9-NEXT:    s_branch .LBB12_32
+; GFX9-NEXT:  .LBB12_26:
+; GFX9-NEXT:    ; implicit-def: $vgpr11
+; GFX9-NEXT:  .LBB12_27: ; %frem.compute77
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
+; GFX9-NEXT:    v_ldexp_f32 v12, v12, 1
+; GFX9-NEXT:    v_div_scale_f32 v18, s[2:3], v12, v12, 1.0
+; GFX9-NEXT:    v_div_scale_f32 v15, vcc, 1.0, v12, 1.0
+; GFX9-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v16, v3
+; GFX9-NEXT:    v_ldexp_f32 v14, v11, 12
+; GFX9-NEXT:    v_frexp_exp_i32_f32_e32 v17, v7
+; GFX9-NEXT:    v_add_u32_e32 v11, -1, v17
+; GFX9-NEXT:    v_not_b32_e32 v13, v11
+; GFX9-NEXT:    v_add_u32_e32 v13, v13, v16
+; GFX9-NEXT:    v_rcp_f32_e32 v19, v18
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX9-NEXT:    v_fma_f32 v9, -v6, v7, 1.0
-; GFX9-NEXT:    v_fma_f32 v7, v9, v7, v7
-; GFX9-NEXT:    v_mul_f32_e32 v9, v5, v7
-; GFX9-NEXT:    v_fma_f32 v10, -v6, v9, v5
-; GFX9-NEXT:    v_fma_f32 v9, v10, v7, v9
-; GFX9-NEXT:    v_fma_f32 v5, -v6, v9, v5
+; GFX9-NEXT:    v_fma_f32 v20, -v18, v19, 1.0
+; GFX9-NEXT:    v_fma_f32 v19, v20, v19, v19
+; GFX9-NEXT:    v_mul_f32_e32 v20, v15, v19
+; GFX9-NEXT:    v_fma_f32 v21, -v18, v20, v15
+; GFX9-NEXT:    v_fma_f32 v20, v21, v19, v20
+; GFX9-NEXT:    v_fma_f32 v15, -v18, v20, v15
 ; GFX9-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX9-NEXT:    v_div_fmas_f32 v5, v5, v7, v9
-; GFX9-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
-; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX9-NEXT:    v_fma_f32 v0, -v5, v4, v0
-; GFX9-NEXT:    global_store_dwordx4 v8, v[0:3], s[0:1]
+; GFX9-NEXT:    v_div_fmas_f32 v15, v15, v19, v20
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 13, v13
+; GFX9-NEXT:    v_div_fixup_f32 v15, v15, v12, 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_31
+; GFX9-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v13, v16, v17
+; GFX9-NEXT:    v_add_u32_e32 v13, 12, v13
+; GFX9-NEXT:  .LBB12_29: ; %frem.loop_body85
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v16, v14
+; GFX9-NEXT:    v_mul_f32_e32 v14, v16, v15
+; GFX9-NEXT:    v_rndne_f32_e32 v14, v14
+; GFX9-NEXT:    v_fma_f32 v14, -v14, v12, v16
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v14
+; GFX9-NEXT:    v_add_f32_e32 v17, v14, v12
+; GFX9-NEXT:    v_add_u32_e32 v13, -12, v13
+; GFX9-NEXT:    v_cndmask_b32_e32 v14, v14, v17, vcc
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 12, v13
+; GFX9-NEXT:    v_ldexp_f32 v14, v14, 12
+; GFX9-NEXT:    s_cbranch_vccnz .LBB12_29
+; GFX9-NEXT:  ; %bb.30: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v14, v16
+; GFX9-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; GFX9-NEXT:    v_add_u32_e32 v13, -11, v13
+; GFX9-NEXT:    v_ldexp_f32 v13, v14, v13
+; GFX9-NEXT:    v_mul_f32_e32 v14, v13, v15
+; GFX9-NEXT:    v_rndne_f32_e32 v14, v14
+; GFX9-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, 0, v13
+; GFX9-NEXT:    v_add_f32_e32 v12, v13, v12
+; GFX9-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
+; GFX9-NEXT:    v_ldexp_f32 v11, v12, v11
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_bfi_b32 v11, s2, v11, v3
+; GFX9-NEXT:  .LBB12_32: ; %Flow116
+; GFX9-NEXT:    s_mov_b32 s4, 0x7f800000
+; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v4
+; GFX9-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v0|, s4
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7fc00000
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v8, vcc
+; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v5
+; GFX9-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v1|, s4
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
+; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v6
+; GFX9-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v2|, s4
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v10, vcc
+; GFX9-NEXT:    v_cmp_lg_f32_e32 vcc, 0, v7
+; GFX9-NEXT:    v_cmp_nge_f32_e64 s[2:3], |v3|, s4
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
+; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: frem_v4f32:
@@ -4823,67 +14475,300 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX10-NEXT:    global_load_dwordx4 v[0:3], v8, s[2:3]
 ; GFX10-NEXT:    global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_div_scale_f32 v10, s2, v7, v7, v3
-; GFX10-NEXT:    v_div_scale_f32 v9, vcc_lo, v3, v7, v3
-; GFX10-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX10-NEXT:    v_cmp_ngt_f32_e64 s2, |v0|, |v4|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB12_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_bfi_b32 v8, 0x7fffffff, 0, v0
+; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB12_3
+; GFX10-NEXT:    s_branch .LBB12_8
+; GFX10-NEXT:  .LBB12_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr8
+; GFX10-NEXT:  .LBB12_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v11, v0
+; GFX10-NEXT:    v_ldexp_f32 v9, v9, 1
+; GFX10-NEXT:    v_ldexp_f32 v10, v8, 12
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v11
+; GFX10-NEXT:    v_div_scale_f32 v13, s4, v9, v9, 1.0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v8
+; GFX10-NEXT:    v_add_nc_u32_e32 v8, -1, v8
+; GFX10-NEXT:    v_rcp_f32_e32 v14, v13
+; GFX10-NEXT:    v_not_b32_e32 v12, v8
+; GFX10-NEXT:    v_add_nc_u32_e32 v12, v12, v11
+; GFX10-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
 ; GFX10-NEXT:    s_denorm_mode 15
-; GFX10-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
-; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v11
-; GFX10-NEXT:    v_mul_f32_e32 v12, v9, v11
-; GFX10-NEXT:    v_fma_f32 v13, -v10, v12, v9
-; GFX10-NEXT:    v_fmac_f32_e32 v12, v13, v11
-; GFX10-NEXT:    v_fma_f32 v9, -v10, v12, v9
+; GFX10-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v14, v15, v14
+; GFX10-NEXT:    v_mul_f32_e32 v15, v11, v14
+; GFX10-NEXT:    v_fma_f32 v16, -v13, v15, v11
+; GFX10-NEXT:    v_fmac_f32_e32 v15, v16, v14
+; GFX10-NEXT:    v_fma_f32 v11, -v13, v15, v11
 ; GFX10-NEXT:    s_denorm_mode 12
-; GFX10-NEXT:    v_div_fmas_f32 v9, v9, v11, v12
-; GFX10-NEXT:    v_div_fixup_f32 v9, v9, v7, v3
-; GFX10-NEXT:    v_trunc_f32_e32 v9, v9
-; GFX10-NEXT:    v_fma_f32 v3, -v9, v7, v3
-; GFX10-NEXT:    v_div_scale_f32 v9, s2, v6, v6, v2
-; GFX10-NEXT:    v_div_scale_f32 v7, vcc_lo, v2, v6, v2
-; GFX10-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX10-NEXT:    v_div_fmas_f32 v11, v11, v14, v15
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v12
+; GFX10-NEXT:    v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB12_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 12
+; GFX10-NEXT:  .LBB12_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v13, v10
+; GFX10-NEXT:    s_add_i32 s2, s2, -12
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX10-NEXT:    v_mul_f32_e32 v10, v13, v11
+; GFX10-NEXT:    v_rndne_f32_e32 v10, v10
+; GFX10-NEXT:    v_fma_f32 v10, -v10, v9, v13
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX10-NEXT:    v_add_f32_e32 v12, v10, v9
+; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v12, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v10, v10, 12
+; GFX10-NEXT:    s_cbranch_scc1 .LBB12_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow125
+; GFX10-NEXT:    v_mov_b32_e32 v12, s2
+; GFX10-NEXT:    v_mov_b32_e32 v10, v13
+; GFX10-NEXT:  .LBB12_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_add_nc_u32_e32 v12, -11, v12
+; GFX10-NEXT:    v_ldexp_f32 v10, v10, v12
+; GFX10-NEXT:    v_mul_f32_e32 v11, v10, v11
+; GFX10-NEXT:    v_rndne_f32_e32 v11, v11
+; GFX10-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX10-NEXT:    v_add_f32_e32 v9, v10, v9
+; GFX10-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v8, v9, v8
+; GFX10-NEXT:    v_bfi_b32 v8, 0x7fffffff, v8, v0
+; GFX10-NEXT:  .LBB12_8:
+; GFX10-NEXT:    v_cmp_ngt_f32_e64 s2, |v1|, |v5|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB12_10
+; GFX10-NEXT:  ; %bb.9: ; %frem.else16
+; GFX10-NEXT:    v_bfi_b32 v9, 0x7fffffff, 0, v1
+; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
+; GFX10-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB12_11
+; GFX10-NEXT:    s_branch .LBB12_16
+; GFX10-NEXT:  .LBB12_10:
+; GFX10-NEXT:    ; implicit-def: $vgpr9
+; GFX10-NEXT:  .LBB12_11: ; %frem.compute15
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v12, v1
+; GFX10-NEXT:    v_ldexp_f32 v10, v10, 1
+; GFX10-NEXT:    v_ldexp_f32 v11, v9, 12
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v9, v5
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v12
+; GFX10-NEXT:    v_div_scale_f32 v14, s4, v10, v10, 1.0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v9
+; GFX10-NEXT:    v_add_nc_u32_e32 v9, -1, v9
+; GFX10-NEXT:    v_rcp_f32_e32 v15, v14
+; GFX10-NEXT:    v_not_b32_e32 v13, v9
+; GFX10-NEXT:    v_add_nc_u32_e32 v13, v13, v12
+; GFX10-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v10, 1.0
 ; GFX10-NEXT:    s_denorm_mode 15
-; GFX10-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
-; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v10
-; GFX10-NEXT:    v_mul_f32_e32 v11, v7, v10
-; GFX10-NEXT:    v_fma_f32 v12, -v9, v11, v7
-; GFX10-NEXT:    v_fmac_f32_e32 v11, v12, v10
-; GFX10-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX10-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v15, v16, v15
+; GFX10-NEXT:    v_mul_f32_e32 v16, v12, v15
+; GFX10-NEXT:    v_fma_f32 v17, -v14, v16, v12
+; GFX10-NEXT:    v_fmac_f32_e32 v16, v17, v15
+; GFX10-NEXT:    v_fma_f32 v12, -v14, v16, v12
 ; GFX10-NEXT:    s_denorm_mode 12
-; GFX10-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
-; GFX10-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
-; GFX10-NEXT:    v_trunc_f32_e32 v7, v7
-; GFX10-NEXT:    v_fma_f32 v2, -v7, v6, v2
-; GFX10-NEXT:    v_div_scale_f32 v7, s2, v5, v5, v1
-; GFX10-NEXT:    v_div_scale_f32 v6, vcc_lo, v1, v5, v1
-; GFX10-NEXT:    v_rcp_f32_e32 v9, v7
+; GFX10-NEXT:    v_div_fmas_f32 v12, v12, v15, v16
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v13
+; GFX10-NEXT:    v_div_fixup_f32 v12, v12, v10, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB12_15
+; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 12
+; GFX10-NEXT:  .LBB12_13: ; %frem.loop_body23
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v14, v11
+; GFX10-NEXT:    s_add_i32 s2, s2, -12
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX10-NEXT:    v_mul_f32_e32 v11, v14, v12
+; GFX10-NEXT:    v_rndne_f32_e32 v11, v11
+; GFX10-NEXT:    v_fma_f32 v11, -v11, v10, v14
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
+; GFX10-NEXT:    v_add_f32_e32 v13, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v11, v11, 12
+; GFX10-NEXT:    s_cbranch_scc1 .LBB12_13
+; GFX10-NEXT:  ; %bb.14: ; %Flow121
+; GFX10-NEXT:    v_mov_b32_e32 v13, s2
+; GFX10-NEXT:    v_mov_b32_e32 v11, v14
+; GFX10-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; GFX10-NEXT:    v_add_nc_u32_e32 v13, -11, v13
+; GFX10-NEXT:    v_ldexp_f32 v11, v11, v13
+; GFX10-NEXT:    v_mul_f32_e32 v12, v11, v12
+; GFX10-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX10-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
+; GFX10-NEXT:    v_add_f32_e32 v10, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v9, v10, v9
+; GFX10-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
+; GFX10-NEXT:  .LBB12_16:
+; GFX10-NEXT:    v_cmp_ngt_f32_e64 s2, |v2|, |v6|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB12_18
+; GFX10-NEXT:  ; %bb.17: ; %frem.else47
+; GFX10-NEXT:    v_bfi_b32 v10, 0x7fffffff, 0, v2
+; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
+; GFX10-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB12_19
+; GFX10-NEXT:    s_branch .LBB12_24
+; GFX10-NEXT:  .LBB12_18:
+; GFX10-NEXT:    ; implicit-def: $vgpr10
+; GFX10-NEXT:  .LBB12_19: ; %frem.compute46
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v13, v2
+; GFX10-NEXT:    v_ldexp_f32 v11, v11, 1
+; GFX10-NEXT:    v_ldexp_f32 v12, v10, 12
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v10, v6
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v13
+; GFX10-NEXT:    v_div_scale_f32 v15, s4, v11, v11, 1.0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v10
+; GFX10-NEXT:    v_add_nc_u32_e32 v10, -1, v10
+; GFX10-NEXT:    v_rcp_f32_e32 v16, v15
+; GFX10-NEXT:    v_not_b32_e32 v14, v10
+; GFX10-NEXT:    v_add_nc_u32_e32 v14, v14, v13
+; GFX10-NEXT:    v_div_scale_f32 v13, vcc_lo, 1.0, v11, 1.0
 ; GFX10-NEXT:    s_denorm_mode 15
-; GFX10-NEXT:    v_fma_f32 v10, -v7, v9, 1.0
-; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v9
-; GFX10-NEXT:    v_mul_f32_e32 v10, v6, v9
-; GFX10-NEXT:    v_fma_f32 v11, -v7, v10, v6
-; GFX10-NEXT:    v_fmac_f32_e32 v10, v11, v9
-; GFX10-NEXT:    v_fma_f32 v6, -v7, v10, v6
+; GFX10-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v16, v17, v16
+; GFX10-NEXT:    v_mul_f32_e32 v17, v13, v16
+; GFX10-NEXT:    v_fma_f32 v18, -v15, v17, v13
+; GFX10-NEXT:    v_fmac_f32_e32 v17, v18, v16
+; GFX10-NEXT:    v_fma_f32 v13, -v15, v17, v13
 ; GFX10-NEXT:    s_denorm_mode 12
-; GFX10-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
-; GFX10-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
-; GFX10-NEXT:    v_trunc_f32_e32 v6, v6
-; GFX10-NEXT:    v_fma_f32 v1, -v6, v5, v1
-; GFX10-NEXT:    v_div_scale_f32 v6, s2, v4, v4, v0
-; GFX10-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v4, v0
-; GFX10-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX10-NEXT:    v_div_fmas_f32 v13, v13, v16, v17
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v14
+; GFX10-NEXT:    v_div_fixup_f32 v13, v13, v11, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB12_23
+; GFX10-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 12
+; GFX10-NEXT:  .LBB12_21: ; %frem.loop_body54
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v15, v12
+; GFX10-NEXT:    s_add_i32 s2, s2, -12
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX10-NEXT:    v_mul_f32_e32 v12, v15, v13
+; GFX10-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX10-NEXT:    v_fma_f32 v12, -v12, v11, v15
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
+; GFX10-NEXT:    v_add_f32_e32 v14, v12, v11
+; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v14, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v12, v12, 12
+; GFX10-NEXT:    s_cbranch_scc1 .LBB12_21
+; GFX10-NEXT:  ; %bb.22: ; %Flow117
+; GFX10-NEXT:    v_mov_b32_e32 v14, s2
+; GFX10-NEXT:    v_mov_b32_e32 v12, v15
+; GFX10-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; GFX10-NEXT:    v_add_nc_u32_e32 v14, -11, v14
+; GFX10-NEXT:    v_ldexp_f32 v12, v12, v14
+; GFX10-NEXT:    v_mul_f32_e32 v13, v12, v13
+; GFX10-NEXT:    v_rndne_f32_e32 v13, v13
+; GFX10-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
+; GFX10-NEXT:    v_add_f32_e32 v11, v12, v11
+; GFX10-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v10, v11, v10
+; GFX10-NEXT:    v_bfi_b32 v10, 0x7fffffff, v10, v2
+; GFX10-NEXT:  .LBB12_24:
+; GFX10-NEXT:    v_cmp_ngt_f32_e64 s2, |v3|, |v7|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB12_26
+; GFX10-NEXT:  ; %bb.25: ; %frem.else78
+; GFX10-NEXT:    v_bfi_b32 v11, 0x7fffffff, 0, v3
+; GFX10-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
+; GFX10-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB12_27
+; GFX10-NEXT:    s_branch .LBB12_32
+; GFX10-NEXT:  .LBB12_26:
+; GFX10-NEXT:    ; implicit-def: $vgpr11
+; GFX10-NEXT:  .LBB12_27: ; %frem.compute77
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
+; GFX10-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v14, v3
+; GFX10-NEXT:    v_ldexp_f32 v12, v12, 1
+; GFX10-NEXT:    v_ldexp_f32 v13, v11, 12
+; GFX10-NEXT:    v_frexp_exp_i32_f32_e32 v11, v7
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX10-NEXT:    v_div_scale_f32 v16, s4, v12, v12, 1.0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v11
+; GFX10-NEXT:    v_add_nc_u32_e32 v11, -1, v11
+; GFX10-NEXT:    v_rcp_f32_e32 v17, v16
+; GFX10-NEXT:    v_not_b32_e32 v15, v11
+; GFX10-NEXT:    v_add_nc_u32_e32 v15, v15, v14
+; GFX10-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
 ; GFX10-NEXT:    s_denorm_mode 15
-; GFX10-NEXT:    v_fma_f32 v9, -v6, v7, 1.0
-; GFX10-NEXT:    v_fmac_f32_e32 v7, v9, v7
-; GFX10-NEXT:    v_mul_f32_e32 v9, v5, v7
-; GFX10-NEXT:    v_fma_f32 v10, -v6, v9, v5
-; GFX10-NEXT:    v_fmac_f32_e32 v9, v10, v7
-; GFX10-NEXT:    v_fma_f32 v5, -v6, v9, v5
+; GFX10-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
+; GFX10-NEXT:    v_fmac_f32_e32 v17, v18, v17
+; GFX10-NEXT:    v_mul_f32_e32 v18, v14, v17
+; GFX10-NEXT:    v_fma_f32 v19, -v16, v18, v14
+; GFX10-NEXT:    v_fmac_f32_e32 v18, v19, v17
+; GFX10-NEXT:    v_fma_f32 v14, -v16, v18, v14
 ; GFX10-NEXT:    s_denorm_mode 12
-; GFX10-NEXT:    v_div_fmas_f32 v5, v5, v7, v9
-; GFX10-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
-; GFX10-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX10-NEXT:    v_fma_f32 v0, -v5, v4, v0
-; GFX10-NEXT:    global_store_dwordx4 v8, v[0:3], s[0:1]
+; GFX10-NEXT:    v_div_fmas_f32 v14, v14, v17, v18
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v15
+; GFX10-NEXT:    v_div_fixup_f32 v14, v14, v12, 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB12_31
+; GFX10-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 12
+; GFX10-NEXT:  .LBB12_29: ; %frem.loop_body85
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v16, v13
+; GFX10-NEXT:    s_add_i32 s2, s2, -12
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 12
+; GFX10-NEXT:    v_mul_f32_e32 v13, v16, v14
+; GFX10-NEXT:    v_rndne_f32_e32 v13, v13
+; GFX10-NEXT:    v_fma_f32 v13, -v13, v12, v16
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX10-NEXT:    v_add_f32_e32 v15, v13, v12
+; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v13, v13, 12
+; GFX10-NEXT:    s_cbranch_scc1 .LBB12_29
+; GFX10-NEXT:  ; %bb.30: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v15, s2
+; GFX10-NEXT:    v_mov_b32_e32 v13, v16
+; GFX10-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; GFX10-NEXT:    v_add_nc_u32_e32 v15, -11, v15
+; GFX10-NEXT:    v_ldexp_f32 v13, v13, v15
+; GFX10-NEXT:    v_mul_f32_e32 v14, v13, v14
+; GFX10-NEXT:    v_rndne_f32_e32 v14, v14
+; GFX10-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX10-NEXT:    v_add_f32_e32 v12, v13, v12
+; GFX10-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
+; GFX10-NEXT:    v_ldexp_f32 v11, v12, v11
+; GFX10-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
+; GFX10-NEXT:  .LBB12_32: ; %Flow116
+; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v4
+; GFX10-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
+; GFX10-NEXT:    v_mov_b32_e32 v4, 0
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v1|
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
+; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v5
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v2|
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
+; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v6
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v3|
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
+; GFX10-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v7
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v11, vcc_lo
+; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: frem_v4f32:
@@ -4891,97 +14776,386 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v8, 0
+; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b128 v[0:3], v8, s[2:3]
-; GFX11-NEXT:    global_load_b128 v[4:7], v8, s[4:5] offset:64
+; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
+; GFX11-NEXT:    global_load_b128 v[4:7], v4, s[4:5] offset:64
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_div_scale_f32 v10, null, v7, v7, v3
-; GFX11-NEXT:    v_div_scale_f32 v9, vcc_lo, v3, v7, v3
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s2, |v0|, |v4|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB12_2
+; GFX11-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-NEXT:    v_bfi_b32 v8, 0x7fffffff, 0, v0
+; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v0|, |v4|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB12_3
+; GFX11-NEXT:    s_branch .LBB12_8
+; GFX11-NEXT:  .LBB12_2:
+; GFX11-NEXT:    ; implicit-def: $vgpr8
+; GFX11-NEXT:  .LBB12_3: ; %frem.compute
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v9, |v4|
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v8, |v0|
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v11, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_ldexp_f32 v9, v9, 1
+; GFX11-NEXT:    v_ldexp_f32 v10, v8, 12
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v8, v4
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v11
+; GFX11-NEXT:    v_div_scale_f32 v13, null, v9, v9, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v8
+; GFX11-NEXT:    v_add_nc_u32_e32 v8, -1, v8
+; GFX11-NEXT:    v_rcp_f32_e32 v14, v13
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v12, v8
+; GFX11-NEXT:    v_add_nc_u32_e32 v12, v12, v11
+; GFX11-NEXT:    v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
 ; GFX11-NEXT:    s_denorm_mode 15
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
-; GFX11-NEXT:    v_fmac_f32_e32 v11, v12, v11
+; GFX11-NEXT:    v_fma_f32 v15, -v13, v14, 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v12, v9, v11
-; GFX11-NEXT:    v_fma_f32 v13, -v10, v12, v9
+; GFX11-NEXT:    v_fmac_f32_e32 v14, v15, v14
+; GFX11-NEXT:    v_mul_f32_e32 v15, v11, v14
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v12, v13, v11
-; GFX11-NEXT:    v_fma_f32 v9, -v10, v12, v9
+; GFX11-NEXT:    v_fma_f32 v16, -v13, v15, v11
+; GFX11-NEXT:    v_fmac_f32_e32 v15, v16, v14
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v11, -v13, v15, v11
 ; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    v_div_fmas_f32 v11, v11, v14, v15
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB12_7
+; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 12
+; GFX11-NEXT:  .LBB12_5: ; %frem.loop_body
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_mov_b32_e32 v13, v10
+; GFX11-NEXT:    s_add_i32 s2, s2, -12
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f32 v9, v9, v11, v12
-; GFX11-NEXT:    v_div_fixup_f32 v9, v9, v7, v3
+; GFX11-NEXT:    v_mul_f32_e32 v10, v13, v11
+; GFX11-NEXT:    v_rndne_f32_e32 v10, v10
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v9, v9
-; GFX11-NEXT:    v_fma_f32 v3, -v9, v7, v3
-; GFX11-NEXT:    v_div_scale_f32 v9, null, v6, v6, v2
-; GFX11-NEXT:    v_div_scale_f32 v7, vcc_lo, v2, v6, v2
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX11-NEXT:    v_fma_f32 v10, -v10, v9, v13
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-NEXT:    v_add_f32_e32 v12, v10, v9
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v10, v10, v12, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v10, v10, 12
+; GFX11-NEXT:    s_cbranch_scc1 .LBB12_5
+; GFX11-NEXT:  ; %bb.6: ; %Flow125
+; GFX11-NEXT:    v_mov_b32_e32 v12, s2
+; GFX11-NEXT:    v_mov_b32_e32 v10, v13
+; GFX11-NEXT:  .LBB12_7: ; %frem.loop_exit
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_add_nc_u32_e32 v12, -11, v12
+; GFX11-NEXT:    v_ldexp_f32 v10, v10, v12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v11, v10, v11
+; GFX11-NEXT:    v_rndne_f32_e32 v11, v11
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v10, -v11, v9, v10
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-NEXT:    v_add_f32_e32 v9, v10, v9
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v8, v9, v8
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v8, 0x7fffffff, v8, v0
+; GFX11-NEXT:  .LBB12_8:
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s2, |v1|, |v5|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB12_10
+; GFX11-NEXT:  ; %bb.9: ; %frem.else16
+; GFX11-NEXT:    v_bfi_b32 v9, 0x7fffffff, 0, v1
+; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v1|, |v5|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e32 v9, v1, v9, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB12_11
+; GFX11-NEXT:    s_branch .LBB12_16
+; GFX11-NEXT:  .LBB12_10:
+; GFX11-NEXT:    ; implicit-def: $vgpr9
+; GFX11-NEXT:  .LBB12_11: ; %frem.compute15
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v10, |v5|
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v9, |v1|
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v12, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_ldexp_f32 v10, v10, 1
+; GFX11-NEXT:    v_ldexp_f32 v11, v9, 12
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v9, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v12
+; GFX11-NEXT:    v_div_scale_f32 v14, null, v10, v10, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v9
+; GFX11-NEXT:    v_add_nc_u32_e32 v9, -1, v9
+; GFX11-NEXT:    v_rcp_f32_e32 v15, v14
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v13, v9
+; GFX11-NEXT:    v_add_nc_u32_e32 v13, v13, v12
+; GFX11-NEXT:    v_div_scale_f32 v12, vcc_lo, 1.0, v10, 1.0
 ; GFX11-NEXT:    s_denorm_mode 15
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
-; GFX11-NEXT:    v_fmac_f32_e32 v10, v11, v10
+; GFX11-NEXT:    v_fma_f32 v16, -v14, v15, 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v11, v7, v10
-; GFX11-NEXT:    v_fma_f32 v12, -v9, v11, v7
+; GFX11-NEXT:    v_fmac_f32_e32 v15, v16, v15
+; GFX11-NEXT:    v_mul_f32_e32 v16, v12, v15
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v11, v12, v10
-; GFX11-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX11-NEXT:    v_fma_f32 v17, -v14, v16, v12
+; GFX11-NEXT:    v_fmac_f32_e32 v16, v17, v15
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v12, -v14, v16, v12
 ; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    v_div_fmas_f32 v12, v12, v15, v16
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v13
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f32 v12, v12, v10, 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB12_15
+; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 12
+; GFX11-NEXT:  .LBB12_13: ; %frem.loop_body23
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_mov_b32_e32 v14, v11
+; GFX11-NEXT:    s_add_i32 s2, s2, -12
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
-; GFX11-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
+; GFX11-NEXT:    v_mul_f32_e32 v11, v14, v12
+; GFX11-NEXT:    v_rndne_f32_e32 v11, v11
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v7, v7
-; GFX11-NEXT:    v_fma_f32 v2, -v7, v6, v2
-; GFX11-NEXT:    v_div_scale_f32 v7, null, v5, v5, v1
-; GFX11-NEXT:    v_div_scale_f32 v6, vcc_lo, v1, v5, v1
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v9, v7
+; GFX11-NEXT:    v_fma_f32 v11, -v11, v10, v14
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
+; GFX11-NEXT:    v_add_f32_e32 v13, v11, v10
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v11, v11, v13, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v11, v11, 12
+; GFX11-NEXT:    s_cbranch_scc1 .LBB12_13
+; GFX11-NEXT:  ; %bb.14: ; %Flow121
+; GFX11-NEXT:    v_mov_b32_e32 v13, s2
+; GFX11-NEXT:    v_mov_b32_e32 v11, v14
+; GFX11-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_add_nc_u32_e32 v13, -11, v13
+; GFX11-NEXT:    v_ldexp_f32 v11, v11, v13
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v12, v11, v12
+; GFX11-NEXT:    v_rndne_f32_e32 v12, v12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v11, -v12, v10, v11
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v11
+; GFX11-NEXT:    v_add_f32_e32 v10, v11, v10
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v9, v10, v9
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
+; GFX11-NEXT:  .LBB12_16:
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s2, |v2|, |v6|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB12_18
+; GFX11-NEXT:  ; %bb.17: ; %frem.else47
+; GFX11-NEXT:    v_bfi_b32 v10, 0x7fffffff, 0, v2
+; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v2|, |v6|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB12_19
+; GFX11-NEXT:    s_branch .LBB12_24
+; GFX11-NEXT:  .LBB12_18:
+; GFX11-NEXT:    ; implicit-def: $vgpr10
+; GFX11-NEXT:  .LBB12_19: ; %frem.compute46
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v11, |v6|
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v10, |v2|
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v13, v2
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_ldexp_f32 v11, v11, 1
+; GFX11-NEXT:    v_ldexp_f32 v12, v10, 12
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v10, v6
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v13
+; GFX11-NEXT:    v_div_scale_f32 v15, null, v11, v11, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v10
+; GFX11-NEXT:    v_add_nc_u32_e32 v10, -1, v10
+; GFX11-NEXT:    v_rcp_f32_e32 v16, v15
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v14, v10
+; GFX11-NEXT:    v_add_nc_u32_e32 v14, v14, v13
+; GFX11-NEXT:    v_div_scale_f32 v13, vcc_lo, 1.0, v11, 1.0
 ; GFX11-NEXT:    s_denorm_mode 15
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f32 v10, -v7, v9, 1.0
-; GFX11-NEXT:    v_fmac_f32_e32 v9, v10, v9
+; GFX11-NEXT:    v_fma_f32 v17, -v15, v16, 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v10, v6, v9
-; GFX11-NEXT:    v_fma_f32 v11, -v7, v10, v6
+; GFX11-NEXT:    v_fmac_f32_e32 v16, v17, v16
+; GFX11-NEXT:    v_mul_f32_e32 v17, v13, v16
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v10, v11, v9
-; GFX11-NEXT:    v_fma_f32 v6, -v7, v10, v6
+; GFX11-NEXT:    v_fma_f32 v18, -v15, v17, v13
+; GFX11-NEXT:    v_fmac_f32_e32 v17, v18, v16
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v13, -v15, v17, v13
 ; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    v_div_fmas_f32 v13, v13, v16, v17
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v14
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f32 v13, v13, v11, 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB12_23
+; GFX11-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 12
+; GFX11-NEXT:  .LBB12_21: ; %frem.loop_body54
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_mov_b32_e32 v15, v12
+; GFX11-NEXT:    s_add_i32 s2, s2, -12
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
-; GFX11-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
+; GFX11-NEXT:    v_mul_f32_e32 v12, v15, v13
+; GFX11-NEXT:    v_rndne_f32_e32 v12, v12
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v6, v6
-; GFX11-NEXT:    v_fma_f32 v1, -v6, v5, v1
-; GFX11-NEXT:    v_div_scale_f32 v6, null, v4, v4, v0
-; GFX11-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v4, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX11-NEXT:    v_fma_f32 v12, -v12, v11, v15
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
+; GFX11-NEXT:    v_add_f32_e32 v14, v12, v11
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v12, v12, v14, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v12, v12, 12
+; GFX11-NEXT:    s_cbranch_scc1 .LBB12_21
+; GFX11-NEXT:  ; %bb.22: ; %Flow117
+; GFX11-NEXT:    v_mov_b32_e32 v14, s2
+; GFX11-NEXT:    v_mov_b32_e32 v12, v15
+; GFX11-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_add_nc_u32_e32 v14, -11, v14
+; GFX11-NEXT:    v_ldexp_f32 v12, v12, v14
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v13, v12, v13
+; GFX11-NEXT:    v_rndne_f32_e32 v13, v13
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v12, -v13, v11, v12
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v12
+; GFX11-NEXT:    v_add_f32_e32 v11, v12, v11
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v10, v11, v10
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v10, 0x7fffffff, v10, v2
+; GFX11-NEXT:  .LBB12_24:
+; GFX11-NEXT:    v_cmp_ngt_f32_e64 s2, |v3|, |v7|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB12_26
+; GFX11-NEXT:  ; %bb.25: ; %frem.else78
+; GFX11-NEXT:    v_bfi_b32 v11, 0x7fffffff, 0, v3
+; GFX11-NEXT:    v_cmp_eq_f32_e64 vcc_lo, |v3|, |v7|
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e32 v11, v3, v11, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB12_27
+; GFX11-NEXT:    s_branch .LBB12_32
+; GFX11-NEXT:  .LBB12_26:
+; GFX11-NEXT:    ; implicit-def: $vgpr11
+; GFX11-NEXT:  .LBB12_27: ; %frem.compute77
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v12, |v7|
+; GFX11-NEXT:    v_frexp_mant_f32_e64 v11, |v3|
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v14, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_ldexp_f32 v12, v12, 1
+; GFX11-NEXT:    v_ldexp_f32 v13, v11, 12
+; GFX11-NEXT:    v_frexp_exp_i32_f32_e32 v11, v7
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX11-NEXT:    v_div_scale_f32 v16, null, v12, v12, 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v11
+; GFX11-NEXT:    v_add_nc_u32_e32 v11, -1, v11
+; GFX11-NEXT:    v_rcp_f32_e32 v17, v16
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v15, v11
+; GFX11-NEXT:    v_add_nc_u32_e32 v15, v15, v14
+; GFX11-NEXT:    v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
 ; GFX11-NEXT:    s_denorm_mode 15
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f32 v9, -v6, v7, 1.0
-; GFX11-NEXT:    v_fmac_f32_e32 v7, v9, v7
+; GFX11-NEXT:    v_fma_f32 v18, -v16, v17, 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f32_e32 v9, v5, v7
-; GFX11-NEXT:    v_fma_f32 v10, -v6, v9, v5
+; GFX11-NEXT:    v_fmac_f32_e32 v17, v18, v17
+; GFX11-NEXT:    v_mul_f32_e32 v18, v14, v17
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fmac_f32_e32 v9, v10, v7
-; GFX11-NEXT:    v_fma_f32 v5, -v6, v9, v5
+; GFX11-NEXT:    v_fma_f32 v19, -v16, v18, v14
+; GFX11-NEXT:    v_fmac_f32_e32 v18, v19, v17
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v14, -v16, v18, v14
 ; GFX11-NEXT:    s_denorm_mode 12
+; GFX11-NEXT:    v_div_fmas_f32 v14, v14, v17, v18
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v15
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f32 v14, v14, v12, 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB12_31
+; GFX11-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 12
+; GFX11-NEXT:  .LBB12_29: ; %frem.loop_body85
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_mov_b32_e32 v16, v13
+; GFX11-NEXT:    s_add_i32 s2, s2, -12
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 12
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f32 v5, v5, v7, v9
-; GFX11-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
+; GFX11-NEXT:    v_mul_f32_e32 v13, v16, v14
+; GFX11-NEXT:    v_rndne_f32_e32 v13, v13
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX11-NEXT:    v_fma_f32 v0, -v5, v4, v0
-; GFX11-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX11-NEXT:    v_fma_f32 v13, -v13, v12, v16
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-NEXT:    v_add_f32_e32 v15, v13, v12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v13, v13, 12
+; GFX11-NEXT:    s_cbranch_scc1 .LBB12_29
+; GFX11-NEXT:  ; %bb.30: ; %Flow
+; GFX11-NEXT:    v_mov_b32_e32 v15, s2
+; GFX11-NEXT:    v_mov_b32_e32 v13, v16
+; GFX11-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_add_nc_u32_e32 v15, -11, v15
+; GFX11-NEXT:    v_ldexp_f32 v13, v13, v15
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f32_e32 v14, v13, v14
+; GFX11-NEXT:    v_rndne_f32_e32 v14, v14
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f32 v13, -v14, v12, v13
+; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-NEXT:    v_add_f32_e32 v12, v13, v12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc_lo
+; GFX11-NEXT:    v_ldexp_f32 v11, v12, v11
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
+; GFX11-NEXT:  .LBB12_32: ; %Flow116
+; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v4
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v0|
+; GFX11-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v1|
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
+; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v5
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v2|
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v9, vcc_lo
+; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v6
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_cmp_nle_f32_e64 s2, 0x7f800000, |v3|
+; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v10, vcc_lo
+; GFX11-NEXT:    v_cmp_lg_f32_e32 vcc_lo, 0, v7
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v11, vcc_lo
+; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: frem_v4f32:
@@ -4989,101 +15163,426 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1150-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-NEXT:    v_mov_b32_e32 v8, 0
+; GFX1150-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX1150-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX1150-NEXT:    s_clause 0x1
-; GFX1150-NEXT:    global_load_b128 v[0:3], v8, s[2:3]
-; GFX1150-NEXT:    global_load_b128 v[4:7], v8, s[4:5] offset:64
+; GFX1150-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
 ; GFX1150-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-NEXT:    v_div_scale_f32 v10, null, v7, v7, v3
-; GFX1150-NEXT:    v_div_scale_f32 v9, vcc_lo, v3, v7, v3
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1150-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX1150-NEXT:    v_readfirstlane_b32 s10, v1
+; GFX1150-NEXT:    v_readfirstlane_b32 s9, v2
+; GFX1150-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX1150-NEXT:    global_load_b128 v[1:4], v4, s[4:5] offset:64
+; GFX1150-NEXT:    v_readfirstlane_b32 s8, v0
+; GFX1150-NEXT:    s_and_b32 s5, s8, 0x7fffffff
+; GFX1150-NEXT:    s_waitcnt vmcnt(0)
+; GFX1150-NEXT:    v_readfirstlane_b32 s6, v1
+; GFX1150-NEXT:    v_readfirstlane_b32 s4, v2
+; GFX1150-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX1150-NEXT:    v_readfirstlane_b32 s2, v4
+; GFX1150-NEXT:    s_and_b32 s12, s6, 0x7fffffff
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_cmp_ngt_f32 s5, s12
+; GFX1150-NEXT:    s_cbranch_scc0 .LBB12_2
+; GFX1150-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-NEXT:    s_cmp_eq_f32 s5, s12
+; GFX1150-NEXT:    v_bfi_b32 v0, 0x7fffffff, 0, s8
+; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v0, s8, v0, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB12_3
+; GFX1150-NEXT:    s_branch .LBB12_8
+; GFX1150-NEXT:  .LBB12_2:
+; GFX1150-NEXT:    ; implicit-def: $vgpr0
+; GFX1150-NEXT:  .LBB12_3: ; %frem.compute
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s6|
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v0, |s8|
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1150-NEXT:    v_ldexp_f32 v2, v0, 12
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_readfirstlane_b32 s11, v3
+; GFX1150-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_readfirstlane_b32 s12, v0
+; GFX1150-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v4, v0
+; GFX1150-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
 ; GFX1150-NEXT:    s_denorm_mode 15
-; GFX1150-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-NEXT:    v_fmac_f32_e32 v6, v7, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1150-NEXT:    v_fma_f32 v8, -v5, v7, v3
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fmac_f32_e32 v11, v12, v11
-; GFX1150-NEXT:    v_mul_f32_e32 v12, v9, v11
+; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1150-NEXT:    v_fma_f32 v3, -v5, v7, v3
+; GFX1150-NEXT:    s_denorm_mode 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
+; GFX1150-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB12_7
+; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-NEXT:    s_sub_i32 s11, s11, s12
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s11, s11, 12
+; GFX1150-NEXT:  .LBB12_5: ; %frem.loop_body
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1150-NEXT:    s_add_i32 s11, s11, -12
+; GFX1150-NEXT:    s_cmp_gt_i32 s11, 12
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v13, -v10, v12, v9
-; GFX1150-NEXT:    v_fmac_f32_e32 v12, v13, v11
+; GFX1150-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1150-NEXT:    v_rndne_f32_e32 v2, v2
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-NEXT:    v_fma_f32 v2, v2, v1, v5
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v9, -v10, v12, v9
-; GFX1150-NEXT:    s_denorm_mode 12
-; GFX1150-NEXT:    v_div_fmas_f32 v9, v9, v11, v12
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 12
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB12_5
+; GFX1150-NEXT:  ; %bb.6: ; %Flow125
+; GFX1150-NEXT:    v_mov_b32_e32 v4, s11
+; GFX1150-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1150-NEXT:  .LBB12_7: ; %frem.loop_exit
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_add_nc_u32_e32 v4, -11, v4
+; GFX1150-NEXT:    v_ldexp_f32 v2, v2, v4
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fixup_f32 v9, v9, v7, v3
-; GFX1150-NEXT:    v_trunc_f32_e32 v9, v9
+; GFX1150-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_xor_b32_e32 v9, 0x80000000, v9
-; GFX1150-NEXT:    v_fma_f32 v3, v9, v7, v3
-; GFX1150-NEXT:    v_div_scale_f32 v9, null, v6, v6, v2
-; GFX1150-NEXT:    v_div_scale_f32 v7, vcc_lo, v2, v6, v2
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1150-NEXT:    v_rcp_f32_e32 v10, v9
+; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-NEXT:    v_fmac_f32_e32 v2, v3, v1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1150-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1150-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s8
+; GFX1150-NEXT:  .LBB12_8:
+; GFX1150-NEXT:    s_and_b32 s8, s10, 0x7fffffff
+; GFX1150-NEXT:    s_and_b32 s12, s4, 0x7fffffff
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_cmp_ngt_f32 s8, s12
+; GFX1150-NEXT:    s_cbranch_scc0 .LBB12_10
+; GFX1150-NEXT:  ; %bb.9: ; %frem.else16
+; GFX1150-NEXT:    s_cmp_eq_f32 s8, s12
+; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, 0, s10
+; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v1, s10, v1, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB12_11
+; GFX1150-NEXT:    s_branch .LBB12_16
+; GFX1150-NEXT:  .LBB12_10:
+; GFX1150-NEXT:    ; implicit-def: $vgpr1
+; GFX1150-NEXT:  .LBB12_11: ; %frem.compute15
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v2, |s4|
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v1, |s10|
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1150-NEXT:    v_ldexp_f32 v3, v1, 12
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v1, s4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_readfirstlane_b32 s11, v4
+; GFX1150-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_readfirstlane_b32 s12, v1
+; GFX1150-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v5, v1
+; GFX1150-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
 ; GFX1150-NEXT:    s_denorm_mode 15
-; GFX1150-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-NEXT:    v_fmac_f32_e32 v7, v8, v7
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fmac_f32_e32 v10, v11, v10
-; GFX1150-NEXT:    v_mul_f32_e32 v11, v7, v10
+; GFX1150-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1150-NEXT:    v_fma_f32 v9, -v6, v8, v4
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v12, -v9, v11, v7
-; GFX1150-NEXT:    v_fmac_f32_e32 v11, v12, v10
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX1150-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1150-NEXT:    v_fma_f32 v4, -v6, v8, v4
 ; GFX1150-NEXT:    s_denorm_mode 12
-; GFX1150-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
+; GFX1150-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB12_15
+; GFX1150-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX1150-NEXT:    s_sub_i32 s11, s11, s12
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s11, s11, 12
+; GFX1150-NEXT:  .LBB12_13: ; %frem.loop_body23
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1150-NEXT:    s_add_i32 s11, s11, -12
+; GFX1150-NEXT:    s_cmp_gt_i32 s11, 12
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
-; GFX1150-NEXT:    v_trunc_f32_e32 v7, v7
+; GFX1150-NEXT:    v_mul_f32_e32 v3, v6, v4
+; GFX1150-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_xor_b32_e32 v7, 0x80000000, v7
-; GFX1150-NEXT:    v_fma_f32 v2, v7, v6, v2
-; GFX1150-NEXT:    v_div_scale_f32 v7, null, v5, v5, v1
-; GFX1150-NEXT:    v_div_scale_f32 v6, vcc_lo, v1, v5, v1
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1150-NEXT:    v_rcp_f32_e32 v9, v7
+; GFX1150-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v3, v3, 12
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB12_13
+; GFX1150-NEXT:  ; %bb.14: ; %Flow121
+; GFX1150-NEXT:    v_mov_b32_e32 v5, s11
+; GFX1150-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1150-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_add_nc_u32_e32 v5, -11, v5
+; GFX1150-NEXT:    v_ldexp_f32 v3, v3, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1150-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1150-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1150-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s10
+; GFX1150-NEXT:  .LBB12_16:
+; GFX1150-NEXT:    s_and_b32 s10, s9, 0x7fffffff
+; GFX1150-NEXT:    s_and_b32 s12, s3, 0x7fffffff
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_cmp_ngt_f32 s10, s12
+; GFX1150-NEXT:    s_cbranch_scc0 .LBB12_18
+; GFX1150-NEXT:  ; %bb.17: ; %frem.else47
+; GFX1150-NEXT:    s_cmp_eq_f32 s10, s12
+; GFX1150-NEXT:    v_bfi_b32 v2, 0x7fffffff, 0, s9
+; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v2, s9, v2, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB12_19
+; GFX1150-NEXT:    s_branch .LBB12_24
+; GFX1150-NEXT:  .LBB12_18:
+; GFX1150-NEXT:    ; implicit-def: $vgpr2
+; GFX1150-NEXT:  .LBB12_19: ; %frem.compute46
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v3, |s3|
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v2, |s9|
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1150-NEXT:    v_ldexp_f32 v4, v2, 12
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v2, s3
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_readfirstlane_b32 s11, v5
+; GFX1150-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_readfirstlane_b32 s12, v2
+; GFX1150-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v6, v2
+; GFX1150-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
 ; GFX1150-NEXT:    s_denorm_mode 15
-; GFX1150-NEXT:    v_fma_f32 v10, -v7, v9, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1150-NEXT:    v_fma_f32 v10, -v7, v9, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1150-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1150-NEXT:    s_denorm_mode 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
+; GFX1150-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB12_23
+; GFX1150-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; GFX1150-NEXT:    s_sub_i32 s11, s11, s12
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s11, s11, 12
+; GFX1150-NEXT:  .LBB12_21: ; %frem.loop_body54
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1150-NEXT:    s_add_i32 s11, s11, -12
+; GFX1150-NEXT:    s_cmp_gt_i32 s11, 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1150-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1150-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v4, v4, 12
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB12_21
+; GFX1150-NEXT:  ; %bb.22: ; %Flow117
+; GFX1150-NEXT:    v_mov_b32_e32 v6, s11
+; GFX1150-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1150-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_add_nc_u32_e32 v6, -11, v6
+; GFX1150-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1150-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1150-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1150-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, s9
+; GFX1150-NEXT:  .LBB12_24:
+; GFX1150-NEXT:    s_and_b32 s9, s7, 0x7fffffff
+; GFX1150-NEXT:    s_and_b32 s12, s2, 0x7fffffff
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_cmp_ngt_f32 s9, s12
+; GFX1150-NEXT:    s_cbranch_scc0 .LBB12_26
+; GFX1150-NEXT:  ; %bb.25: ; %frem.else78
+; GFX1150-NEXT:    s_cmp_eq_f32 s9, s12
+; GFX1150-NEXT:    v_bfi_b32 v3, 0x7fffffff, 0, s7
+; GFX1150-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v3, s7, v3, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB12_27
+; GFX1150-NEXT:    s_branch .LBB12_32
+; GFX1150-NEXT:  .LBB12_26:
+; GFX1150-NEXT:    ; implicit-def: $vgpr3
+; GFX1150-NEXT:  .LBB12_27: ; %frem.compute77
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v4, |s2|
+; GFX1150-NEXT:    v_frexp_mant_f32_e64 v3, |s7|
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v6, s7
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1150-NEXT:    v_ldexp_f32 v5, v3, 12
+; GFX1150-NEXT:    v_frexp_exp_i32_f32_e32 v3, s2
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_readfirstlane_b32 s11, v6
+; GFX1150-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_readfirstlane_b32 s12, v3
+; GFX1150-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-NEXT:    v_rcp_f32_e32 v9, v8
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v7, v3
+; GFX1150-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1150-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1150-NEXT:    s_denorm_mode 15
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
 ; GFX1150-NEXT:    v_fmac_f32_e32 v9, v10, v9
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1150-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1150-NEXT:    v_fma_f32 v11, -v8, v10, v6
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v11, -v7, v10, v6
 ; GFX1150-NEXT:    v_fmac_f32_e32 v10, v11, v9
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v6, -v7, v10, v6
+; GFX1150-NEXT:    v_fma_f32 v6, -v8, v10, v6
 ; GFX1150-NEXT:    s_denorm_mode 12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
 ; GFX1150-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
+; GFX1150-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB12_31
+; GFX1150-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; GFX1150-NEXT:    s_sub_i32 s11, s11, s12
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s11, s11, 12
+; GFX1150-NEXT:  .LBB12_29: ; %frem.loop_body85
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1150-NEXT:    s_add_i32 s11, s11, -12
+; GFX1150-NEXT:    s_cmp_gt_i32 s11, 12
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
-; GFX1150-NEXT:    v_trunc_f32_e32 v6, v6
+; GFX1150-NEXT:    v_mul_f32_e32 v5, v8, v6
+; GFX1150-NEXT:    v_rndne_f32_e32 v5, v5
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
-; GFX1150-NEXT:    v_fma_f32 v1, v6, v5, v1
-; GFX1150-NEXT:    v_div_scale_f32 v6, null, v4, v4, v0
-; GFX1150-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v4, v0
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1150-NEXT:    v_rcp_f32_e32 v7, v6
-; GFX1150-NEXT:    s_denorm_mode 15
-; GFX1150-NEXT:    v_fma_f32 v9, -v6, v7, 1.0
+; GFX1150-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-NEXT:    v_fma_f32 v5, v5, v4, v8
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1150-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_ldexp_f32 v5, v5, 12
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB12_29
+; GFX1150-NEXT:  ; %bb.30: ; %Flow
+; GFX1150-NEXT:    v_mov_b32_e32 v7, s11
+; GFX1150-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1150-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_add_nc_u32_e32 v7, -11, v7
+; GFX1150-NEXT:    v_ldexp_f32 v5, v5, v7
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fmac_f32_e32 v7, v9, v7
-; GFX1150-NEXT:    v_mul_f32_e32 v9, v5, v7
+; GFX1150-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1150-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v10, -v6, v9, v5
-; GFX1150-NEXT:    v_fmac_f32_e32 v9, v10, v7
+; GFX1150-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1150-NEXT:    v_fmac_f32_e32 v5, v6, v4
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f32 v5, -v6, v9, v5
-; GFX1150-NEXT:    s_denorm_mode 12
-; GFX1150-NEXT:    v_div_fmas_f32 v5, v5, v7, v9
+; GFX1150-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-NEXT:    v_add_f32_e32 v4, v5, v4
+; GFX1150-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
-; GFX1150-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1150-NEXT:    v_fmac_f32_e32 v0, v5, v4
-; GFX1150-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX1150-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1150-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s7
+; GFX1150-NEXT:  .LBB12_32: ; %Flow116
+; GFX1150-NEXT:    s_cmp_lg_f32 s6, 0
+; GFX1150-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1150-NEXT:    s_cselect_b32 s6, -1, 0
+; GFX1150-NEXT:    s_cmp_nge_f32 s5, 0x7f800000
+; GFX1150-NEXT:    s_cselect_b32 s5, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s5, s6
+; GFX1150-NEXT:    s_cmp_lg_f32 s4, 0
+; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
+; GFX1150-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1150-NEXT:    s_cmp_nge_f32 s8, 0x7f800000
+; GFX1150-NEXT:    s_cselect_b32 s5, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s5, s4
+; GFX1150-NEXT:    s_cmp_lg_f32 s3, 0
+; GFX1150-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
+; GFX1150-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-NEXT:    s_cmp_nge_f32 s10, 0x7f800000
+; GFX1150-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s4, s3
+; GFX1150-NEXT:    s_cmp_lg_f32 s2, 0
+; GFX1150-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
+; GFX1150-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1150-NEXT:    s_cmp_nge_f32 s9, 0x7f800000
+; GFX1150-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1150-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
+; GFX1150-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
 ; GFX1200-LABEL: frem_v4f32:
@@ -5091,104 +15590,448 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1200-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-NEXT:    v_mov_b32_e32 v8, 0
+; GFX1200-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX1200-NEXT:    s_wait_kmcnt 0x0
-; GFX1200-NEXT:    s_clause 0x1
-; GFX1200-NEXT:    global_load_b128 v[0:3], v8, s[2:3]
-; GFX1200-NEXT:    global_load_b128 v[4:7], v8, s[4:5] offset:64
+; GFX1200-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
 ; GFX1200-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-NEXT:    v_div_scale_f32 v10, null, v7, v7, v3
-; GFX1200-NEXT:    v_div_scale_f32 v9, vcc_lo, v3, v7, v3
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1200-NEXT:    v_rcp_f32_e32 v11, v10
+; GFX1200-NEXT:    v_readfirstlane_b32 s10, v1
+; GFX1200-NEXT:    v_readfirstlane_b32 s9, v2
+; GFX1200-NEXT:    v_readfirstlane_b32 s7, v3
+; GFX1200-NEXT:    global_load_b128 v[1:4], v4, s[4:5] offset:64
+; GFX1200-NEXT:    v_readfirstlane_b32 s8, v0
+; GFX1200-NEXT:    s_and_b32 s5, s8, 0x7fffffff
+; GFX1200-NEXT:    s_wait_loadcnt 0x0
+; GFX1200-NEXT:    v_readfirstlane_b32 s6, v1
+; GFX1200-NEXT:    v_readfirstlane_b32 s4, v2
+; GFX1200-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX1200-NEXT:    v_readfirstlane_b32 s2, v4
+; GFX1200-NEXT:    s_and_b32 s12, s6, 0x7fffffff
+; GFX1200-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT:    s_cmp_ngt_f32 s5, s12
+; GFX1200-NEXT:    s_cbranch_scc0 .LBB12_2
+; GFX1200-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-NEXT:    s_cmp_eq_f32 s5, s12
+; GFX1200-NEXT:    v_bfi_b32 v0, 0x7fffffff, 0, s8
+; GFX1200-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v0, s8, v0, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB12_3
+; GFX1200-NEXT:    s_branch .LBB12_8
+; GFX1200-NEXT:  .LBB12_2:
+; GFX1200-NEXT:    ; implicit-def: $vgpr0
+; GFX1200-NEXT:  .LBB12_3: ; %frem.compute
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s6|
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v0, |s8|
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_ldexp_f32 v1, v1, 1
+; GFX1200-NEXT:    v_ldexp_f32 v2, v0, 12
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_readfirstlane_b32 s11, v3
+; GFX1200-NEXT:    v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_readfirstlane_b32 s12, v0
+; GFX1200-NEXT:    v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v4, v0
+; GFX1200-NEXT:    v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-NEXT:    v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
 ; GFX1200-NEXT:    s_denorm_mode 15
-; GFX1200-NEXT:    v_fma_f32 v12, -v10, v11, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-NEXT:    v_fmac_f32_e32 v6, v7, v6
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fmac_f32_e32 v11, v12, v11
-; GFX1200-NEXT:    v_mul_f32_e32 v12, v9, v11
+; GFX1200-NEXT:    v_mul_f32_e32 v7, v3, v6
+; GFX1200-NEXT:    v_fma_f32 v8, -v5, v7, v3
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v13, -v10, v12, v9
-; GFX1200-NEXT:    v_fmac_f32_e32 v12, v13, v11
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v9, -v10, v12, v9
+; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v6
+; GFX1200-NEXT:    v_fma_f32 v3, -v5, v7, v3
 ; GFX1200-NEXT:    s_denorm_mode 12
-; GFX1200-NEXT:    v_div_fmas_f32 v9, v9, v11, v12
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v4
+; GFX1200-NEXT:    v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB12_7
+; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s11, s11, s12
+; GFX1200-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, 12
+; GFX1200-NEXT:  .LBB12_5: ; %frem.loop_body
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT:    v_mov_b32_e32 v5, v2
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, -12
+; GFX1200-NEXT:    s_cmp_gt_i32 s11, 12
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fixup_f32 v9, v9, v7, v3
-; GFX1200-NEXT:    v_trunc_f32_e32 v9, v9
+; GFX1200-NEXT:    v_mul_f32_e32 v2, v5, v3
+; GFX1200-NEXT:    v_rndne_f32_e32 v2, v2
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_xor_b32_e32 v9, 0x80000000, v9
-; GFX1200-NEXT:    v_fma_f32 v3, v9, v7, v3
-; GFX1200-NEXT:    v_div_scale_f32 v9, null, v6, v6, v2
-; GFX1200-NEXT:    v_div_scale_f32 v7, vcc_lo, v2, v6, v2
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1200-NEXT:    v_rcp_f32_e32 v10, v9
-; GFX1200-NEXT:    s_denorm_mode 15
-; GFX1200-NEXT:    v_fma_f32 v11, -v9, v10, 1.0
+; GFX1200-NEXT:    v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-NEXT:    v_fma_f32 v2, v2, v1, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-NEXT:    v_add_f32_e32 v4, v2, v1
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 12
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB12_5
+; GFX1200-NEXT:  ; %bb.6: ; %Flow125
+; GFX1200-NEXT:    v_mov_b32_e32 v4, s11
+; GFX1200-NEXT:    v_mov_b32_e32 v2, v5
+; GFX1200-NEXT:  .LBB12_7: ; %frem.loop_exit
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_add_nc_u32_e32 v4, -11, v4
+; GFX1200-NEXT:    v_ldexp_f32 v2, v2, v4
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fmac_f32_e32 v10, v11, v10
-; GFX1200-NEXT:    v_mul_f32_e32 v11, v7, v10
+; GFX1200-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v12, -v9, v11, v7
-; GFX1200-NEXT:    v_fmac_f32_e32 v11, v12, v10
+; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-NEXT:    v_fmac_f32_e32 v2, v3, v1
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v7, -v9, v11, v7
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-NEXT:    v_add_f32_e32 v1, v2, v1
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v0, v1, v0
+; GFX1200-NEXT:    v_bfi_b32 v0, 0x7fffffff, v0, s8
+; GFX1200-NEXT:  .LBB12_8:
+; GFX1200-NEXT:    s_and_b32 s8, s10, 0x7fffffff
+; GFX1200-NEXT:    s_and_b32 s12, s4, 0x7fffffff
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_ngt_f32 s8, s12
+; GFX1200-NEXT:    s_cbranch_scc0 .LBB12_10
+; GFX1200-NEXT:  ; %bb.9: ; %frem.else16
+; GFX1200-NEXT:    s_cmp_eq_f32 s8, s12
+; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, 0, s10
+; GFX1200-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v1, s10, v1, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB12_11
+; GFX1200-NEXT:    s_branch .LBB12_16
+; GFX1200-NEXT:  .LBB12_10:
+; GFX1200-NEXT:    ; implicit-def: $vgpr1
+; GFX1200-NEXT:  .LBB12_11: ; %frem.compute15
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v2, |s4|
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v1, |s10|
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_ldexp_f32 v2, v2, 1
+; GFX1200-NEXT:    v_ldexp_f32 v3, v1, 12
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v1, s4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_readfirstlane_b32 s11, v4
+; GFX1200-NEXT:    v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_readfirstlane_b32 s12, v1
+; GFX1200-NEXT:    v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-NEXT:    v_rcp_f32_e32 v7, v6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v5, v1
+; GFX1200-NEXT:    v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-NEXT:    v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
+; GFX1200-NEXT:    s_denorm_mode 15
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-NEXT:    v_fmac_f32_e32 v7, v8, v7
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v8, v4, v7
+; GFX1200-NEXT:    v_fma_f32 v9, -v6, v8, v4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fmac_f32_e32 v8, v9, v7
+; GFX1200-NEXT:    v_fma_f32 v4, -v6, v8, v4
 ; GFX1200-NEXT:    s_denorm_mode 12
 ; GFX1200-NEXT:    s_wait_alu 0xfffd
-; GFX1200-NEXT:    v_div_fmas_f32 v7, v7, v10, v11
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v5
+; GFX1200-NEXT:    v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB12_15
+; GFX1200-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s11, s11, s12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, 12
+; GFX1200-NEXT:  .LBB12_13: ; %frem.loop_body23
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_mov_b32_e32 v6, v3
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, -12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_gt_i32 s11, 12
+; GFX1200-NEXT:    v_mul_f32_e32 v3, v6, v4
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fixup_f32 v7, v7, v6, v2
-; GFX1200-NEXT:    v_trunc_f32_e32 v7, v7
+; GFX1200-NEXT:    v_rndne_f32_e32 v3, v3
+; GFX1200-NEXT:    v_xor_b32_e32 v3, 0x80000000, v3
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_xor_b32_e32 v7, 0x80000000, v7
-; GFX1200-NEXT:    v_fma_f32 v2, v7, v6, v2
-; GFX1200-NEXT:    v_div_scale_f32 v7, null, v5, v5, v1
-; GFX1200-NEXT:    v_div_scale_f32 v6, vcc_lo, v1, v5, v1
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1200-NEXT:    v_rcp_f32_e32 v9, v7
+; GFX1200-NEXT:    v_fma_f32 v3, v3, v2, v6
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-NEXT:    v_add_f32_e32 v5, v3, v2
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-NEXT:    v_ldexp_f32 v3, v3, 12
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB12_13
+; GFX1200-NEXT:  ; %bb.14: ; %Flow121
+; GFX1200-NEXT:    v_mov_b32_e32 v5, s11
+; GFX1200-NEXT:    v_mov_b32_e32 v3, v6
+; GFX1200-NEXT:  .LBB12_15: ; %frem.loop_exit24
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_add_nc_u32_e32 v5, -11, v5
+; GFX1200-NEXT:    v_ldexp_f32 v3, v3, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v4, v3, v4
+; GFX1200-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-NEXT:    v_fmac_f32_e32 v3, v4, v2
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-NEXT:    v_add_f32_e32 v2, v3, v2
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v1, v2, v1
+; GFX1200-NEXT:    v_bfi_b32 v1, 0x7fffffff, v1, s10
+; GFX1200-NEXT:  .LBB12_16:
+; GFX1200-NEXT:    s_and_b32 s10, s9, 0x7fffffff
+; GFX1200-NEXT:    s_and_b32 s12, s3, 0x7fffffff
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_ngt_f32 s10, s12
+; GFX1200-NEXT:    s_cbranch_scc0 .LBB12_18
+; GFX1200-NEXT:  ; %bb.17: ; %frem.else47
+; GFX1200-NEXT:    s_cmp_eq_f32 s10, s12
+; GFX1200-NEXT:    v_bfi_b32 v2, 0x7fffffff, 0, s9
+; GFX1200-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v2, s9, v2, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB12_19
+; GFX1200-NEXT:    s_branch .LBB12_24
+; GFX1200-NEXT:  .LBB12_18:
+; GFX1200-NEXT:    ; implicit-def: $vgpr2
+; GFX1200-NEXT:  .LBB12_19: ; %frem.compute46
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v3, |s3|
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v2, |s9|
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v5, s9
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_ldexp_f32 v3, v3, 1
+; GFX1200-NEXT:    v_ldexp_f32 v4, v2, 12
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v2, s3
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_readfirstlane_b32 s11, v5
+; GFX1200-NEXT:    v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_readfirstlane_b32 s12, v2
+; GFX1200-NEXT:    v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-NEXT:    v_rcp_f32_e32 v8, v7
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v6, v2
+; GFX1200-NEXT:    v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-NEXT:    v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
 ; GFX1200-NEXT:    s_denorm_mode 15
-; GFX1200-NEXT:    v_fma_f32 v10, -v7, v9, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-NEXT:    v_fmac_f32_e32 v8, v9, v8
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v9, v5, v8
+; GFX1200-NEXT:    v_fma_f32 v10, -v7, v9, v5
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fmac_f32_e32 v9, v10, v8
+; GFX1200-NEXT:    v_fma_f32 v5, -v7, v9, v5
+; GFX1200-NEXT:    s_denorm_mode 12
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v6
+; GFX1200-NEXT:    v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB12_23
+; GFX1200-NEXT:  ; %bb.20: ; %frem.loop_body54.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s11, s11, s12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, 12
+; GFX1200-NEXT:  .LBB12_21: ; %frem.loop_body54
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_mov_b32_e32 v7, v4
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, -12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_gt_i32 s11, 12
+; GFX1200-NEXT:    v_mul_f32_e32 v4, v7, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_rndne_f32_e32 v4, v4
+; GFX1200-NEXT:    v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v4, v4, v3, v7
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-NEXT:    v_add_f32_e32 v6, v4, v3
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-NEXT:    v_ldexp_f32 v4, v4, 12
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB12_21
+; GFX1200-NEXT:  ; %bb.22: ; %Flow117
+; GFX1200-NEXT:    v_mov_b32_e32 v6, s11
+; GFX1200-NEXT:    v_mov_b32_e32 v4, v7
+; GFX1200-NEXT:  .LBB12_23: ; %frem.loop_exit55
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_add_nc_u32_e32 v6, -11, v6
+; GFX1200-NEXT:    v_ldexp_f32 v4, v4, v6
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX1200-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-NEXT:    v_fmac_f32_e32 v4, v5, v3
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-NEXT:    v_add_f32_e32 v3, v4, v3
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f32 v2, v3, v2
+; GFX1200-NEXT:    v_bfi_b32 v2, 0x7fffffff, v2, s9
+; GFX1200-NEXT:  .LBB12_24:
+; GFX1200-NEXT:    s_and_b32 s9, s7, 0x7fffffff
+; GFX1200-NEXT:    s_and_b32 s12, s2, 0x7fffffff
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_ngt_f32 s9, s12
+; GFX1200-NEXT:    s_cbranch_scc0 .LBB12_26
+; GFX1200-NEXT:  ; %bb.25: ; %frem.else78
+; GFX1200-NEXT:    s_cmp_eq_f32 s9, s12
+; GFX1200-NEXT:    v_bfi_b32 v3, 0x7fffffff, 0, s7
+; GFX1200-NEXT:    s_cselect_b32 vcc_lo, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v3, s7, v3, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB12_27
+; GFX1200-NEXT:    s_branch .LBB12_32
+; GFX1200-NEXT:  .LBB12_26:
+; GFX1200-NEXT:    ; implicit-def: $vgpr3
+; GFX1200-NEXT:  .LBB12_27: ; %frem.compute77
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v4, |s2|
+; GFX1200-NEXT:    v_frexp_mant_f32_e64 v3, |s7|
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v6, s7
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_ldexp_f32 v4, v4, 1
+; GFX1200-NEXT:    v_ldexp_f32 v5, v3, 12
+; GFX1200-NEXT:    v_frexp_exp_i32_f32_e32 v3, s2
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_readfirstlane_b32 s11, v6
+; GFX1200-NEXT:    v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_readfirstlane_b32 s12, v3
+; GFX1200-NEXT:    v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-NEXT:    v_rcp_f32_e32 v9, v8
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v7, v3
+; GFX1200-NEXT:    v_add_nc_u32_e32 v7, v7, v6
+; GFX1200-NEXT:    v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
+; GFX1200-NEXT:    s_denorm_mode 15
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f32 v10, -v8, v9, 1.0
 ; GFX1200-NEXT:    v_fmac_f32_e32 v9, v10, v9
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
 ; GFX1200-NEXT:    v_mul_f32_e32 v10, v6, v9
+; GFX1200-NEXT:    v_fma_f32 v11, -v8, v10, v6
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v11, -v7, v10, v6
 ; GFX1200-NEXT:    v_fmac_f32_e32 v10, v11, v9
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v6, -v7, v10, v6
+; GFX1200-NEXT:    v_fma_f32 v6, -v8, v10, v6
 ; GFX1200-NEXT:    s_denorm_mode 12
 ; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
 ; GFX1200-NEXT:    v_div_fmas_f32 v6, v6, v9, v10
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 13, v7
+; GFX1200-NEXT:    v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB12_31
+; GFX1200-NEXT:  ; %bb.28: ; %frem.loop_body85.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s11, s11, s12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, 12
+; GFX1200-NEXT:  .LBB12_29: ; %frem.loop_body85
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_mov_b32_e32 v8, v5
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s11, s11, -12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_gt_i32 s11, 12
+; GFX1200-NEXT:    v_mul_f32_e32 v5, v8, v6
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fixup_f32 v6, v6, v5, v1
-; GFX1200-NEXT:    v_trunc_f32_e32 v6, v6
+; GFX1200-NEXT:    v_rndne_f32_e32 v5, v5
+; GFX1200-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
-; GFX1200-NEXT:    v_fma_f32 v1, v6, v5, v1
-; GFX1200-NEXT:    v_div_scale_f32 v6, null, v4, v4, v0
-; GFX1200-NEXT:    v_div_scale_f32 v5, vcc_lo, v0, v4, v0
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(TRANS32_DEP_1)
-; GFX1200-NEXT:    v_rcp_f32_e32 v7, v6
-; GFX1200-NEXT:    s_denorm_mode 15
-; GFX1200-NEXT:    v_fma_f32 v9, -v6, v7, 1.0
+; GFX1200-NEXT:    v_fma_f32 v5, v5, v4, v8
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-NEXT:    v_add_f32_e32 v7, v5, v4
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1200-NEXT:    v_ldexp_f32 v5, v5, 12
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB12_29
+; GFX1200-NEXT:  ; %bb.30: ; %Flow
+; GFX1200-NEXT:    v_mov_b32_e32 v7, s11
+; GFX1200-NEXT:    v_mov_b32_e32 v5, v8
+; GFX1200-NEXT:  .LBB12_31: ; %frem.loop_exit86
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_add_nc_u32_e32 v7, -11, v7
+; GFX1200-NEXT:    v_ldexp_f32 v5, v5, v7
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fmac_f32_e32 v7, v9, v7
-; GFX1200-NEXT:    v_mul_f32_e32 v9, v5, v7
+; GFX1200-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX1200-NEXT:    v_rndne_f32_e32 v6, v6
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v10, -v6, v9, v5
-; GFX1200-NEXT:    v_fmac_f32_e32 v9, v10, v7
+; GFX1200-NEXT:    v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1200-NEXT:    v_fmac_f32_e32 v5, v6, v4
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f32 v5, -v6, v9, v5
-; GFX1200-NEXT:    s_denorm_mode 12
+; GFX1200-NEXT:    v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-NEXT:    v_add_f32_e32 v4, v5, v4
 ; GFX1200-NEXT:    s_wait_alu 0xfffd
-; GFX1200-NEXT:    v_div_fmas_f32 v5, v5, v7, v9
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fixup_f32 v5, v5, v4, v0
-; GFX1200-NEXT:    v_trunc_f32_e32 v5, v5
+; GFX1200-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-NEXT:    v_fmac_f32_e32 v0, v5, v4
-; GFX1200-NEXT:    global_store_b128 v8, v[0:3], s[0:1]
+; GFX1200-NEXT:    v_ldexp_f32 v3, v4, v3
+; GFX1200-NEXT:    v_bfi_b32 v3, 0x7fffffff, v3, s7
+; GFX1200-NEXT:  .LBB12_32: ; %Flow116
+; GFX1200-NEXT:    s_cmp_lg_f32 s6, 0
+; GFX1200-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1200-NEXT:    s_cselect_b32 s6, -1, 0
+; GFX1200-NEXT:    s_cmp_nge_f32 s5, 0x7f800000
+; GFX1200-NEXT:    s_cselect_b32 s5, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s5, s6
+; GFX1200-NEXT:    s_cmp_lg_f32 s4, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
+; GFX1200-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1200-NEXT:    s_cmp_nge_f32 s8, 0x7f800000
+; GFX1200-NEXT:    s_cselect_b32 s5, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s5, s4
+; GFX1200-NEXT:    s_cmp_lg_f32 s3, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
+; GFX1200-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-NEXT:    s_cmp_nge_f32 s10, 0x7f800000
+; GFX1200-NEXT:    s_cselect_b32 s4, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s4, s3
+; GFX1200-NEXT:    s_cmp_lg_f32 s2, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
+; GFX1200-NEXT:    s_cselect_b32 s2, -1, 0
+; GFX1200-NEXT:    s_cmp_nge_f32 s9, 0x7f800000
+; GFX1200-NEXT:    s_cselect_b32 s3, -1, 0
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s3, s2
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
+; GFX1200-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX1200-NEXT:    s_endpgm
                         ptr addrspace(1) %in2) #0 {
    %gep2 = getelementptr <4 x float>, ptr addrspace(1) %in2, i32 4
@@ -5202,131 +16045,431 @@ define amdgpu_kernel void @frem_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
 define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
 ; SI-LABEL: frem_v2f64:
 ; SI:       ; %bb.0:
-; SI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT:    s_load_dwordx2 s[8:9], s[4:5], 0xd
+; SI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0xd
 ; SI-NEXT:    s_mov_b32 s7, 0xf000
 ; SI-NEXT:    s_mov_b32 s6, -1
 ; SI-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-NEXT:    s_mov_b32 s4, s0
-; SI-NEXT:    s_mov_b32 s5, s1
-; SI-NEXT:    s_mov_b32 s0, s2
-; SI-NEXT:    s_mov_b32 s1, s3
+; SI-NEXT:    s_mov_b32 s4, s10
+; SI-NEXT:    s_mov_b32 s5, s11
 ; SI-NEXT:    s_mov_b32 s2, s6
 ; SI-NEXT:    s_mov_b32 s3, s7
-; SI-NEXT:    s_mov_b32 s10, s6
-; SI-NEXT:    s_mov_b32 s11, s7
-; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0
-; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:64
+; SI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:64
 ; SI-NEXT:    s_waitcnt vmcnt(0)
-; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[6:7], v[6:7], v[2:3]
-; SI-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; SI-NEXT:    v_div_scale_f64 v[12:13], s[0:1], v[2:3], v[6:7], v[2:3]
-; SI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
-; SI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], v[12:13]
-; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v9
-; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v3, v13
+; SI-NEXT:    v_cmp_ngt_f64_e64 s[0:1], |v[0:1]|, |v[4:5]|
+; SI-NEXT:    s_and_b64 vcc, exec, s[0:1]
+; SI-NEXT:    s_cbranch_vccz .LBB13_2
+; SI-NEXT:  ; %bb.1: ; %frem.else
+; SI-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; SI-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
+; SI-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB13_3
+; SI-NEXT:    s_branch .LBB13_8
+; SI-NEXT:  .LBB13_2:
+; SI-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB13_3: ; %frem.compute
+; SI-NEXT:    s_brev_b32 s5, -2
+; SI-NEXT:    v_and_b32_e32 v10, 0x7fffffff, v1
+; SI-NEXT:    s_mov_b32 s0, 0
+; SI-NEXT:    s_mov_b32 s1, 0x7ff00000
+; SI-NEXT:    v_cmp_lt_f64_e64 vcc, |v[0:1]|, s[0:1]
+; SI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; SI-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v8, v0, v8, vcc
+; SI-NEXT:    v_frexp_exp_i32_f64_e32 v10, v[0:1]
+; SI-NEXT:    s_and_b64 s[2:3], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v10
+; SI-NEXT:    s_cselect_b32 s3, s2, 0
+; SI-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; SI-NEXT:    v_and_b32_e32 v12, 0x7fffffff, v5
+; SI-NEXT:    v_cmp_lt_f64_e64 vcc, |v[4:5]|, s[0:1]
+; SI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; SI-NEXT:    v_cndmask_b32_e32 v9, v12, v9, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v8, v4, v8, vcc
+; SI-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[4:5]
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v12
+; SI-NEXT:    s_cselect_b32 s7, s0, 0
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_add_i32 s4, s7, -1
+; SI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
+; SI-NEXT:    s_not_b32 s0, s4
+; SI-NEXT:    s_add_i32 s6, s0, s3
+; SI-NEXT:    v_div_scale_f64 v[12:13], s[0:1], v[8:9], v[8:9], 1.0
+; SI-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; SI-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; SI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; SI-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; SI-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
+; SI-NEXT:    v_div_scale_f64 v[16:17], s[0:1], 1.0, v[8:9], 1.0
+; SI-NEXT:    v_mul_f64 v[18:19], v[16:17], v[14:15]
+; SI-NEXT:    v_fma_f64 v[20:21], -v[12:13], v[18:19], v[16:17]
+; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v9, v13
+; SI-NEXT:    s_mov_b32 s0, 0x3ff00000
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s0, v17
 ; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
-; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_div_fmas_f64 v[8:9], v[16:17], v[10:11], v[14:15]
-; SI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
-; SI-NEXT:    v_readfirstlane_b32 s0, v8
-; SI-NEXT:    v_readfirstlane_b32 s1, v9
-; SI-NEXT:    s_bfe_u32 s2, s1, 0xb0014
-; SI-NEXT:    s_add_i32 s10, s2, 0xfffffc01
-; SI-NEXT:    s_mov_b32 s3, 0xfffff
-; SI-NEXT:    s_mov_b32 s2, s6
-; SI-NEXT:    s_lshr_b64 s[8:9], s[2:3], s10
-; SI-NEXT:    s_andn2_b64 s[8:9], s[0:1], s[8:9]
-; SI-NEXT:    s_and_b32 s11, s1, 0x80000000
-; SI-NEXT:    s_cmp_lt_i32 s10, 0
-; SI-NEXT:    s_cselect_b32 s8, 0, s8
-; SI-NEXT:    s_cselect_b32 s9, s11, s9
-; SI-NEXT:    s_cmp_gt_i32 s10, 51
-; SI-NEXT:    s_cselect_b32 s1, s1, s9
-; SI-NEXT:    s_cselect_b32 s0, s0, s8
-; SI-NEXT:    v_fma_f64 v[2:3], -s[0:1], v[6:7], v[2:3]
-; SI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[0:1]
-; SI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
-; SI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; SI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; SI-NEXT:    v_div_scale_f64 v[10:11], s[0:1], v[0:1], v[4:5], v[0:1]
-; SI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
-; SI-NEXT:    v_fma_f64 v[14:15], -v[6:7], v[12:13], v[10:11]
-; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v7
-; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v11
+; SI-NEXT:    s_nop 0
+; SI-NEXT:    v_div_fmas_f64 v[12:13], v[20:21], v[14:15], v[18:19]
+; SI-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; SI-NEXT:    s_cmp_lt_i32 s6, 27
+; SI-NEXT:    s_cbranch_scc1 .LBB13_7
+; SI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; SI-NEXT:    s_sub_i32 s0, s3, s7
+; SI-NEXT:    s_add_i32 s6, s0, 26
+; SI-NEXT:    s_mov_b32 s3, 0x432fffff
+; SI-NEXT:    v_mov_b32_e32 v18, 0x43300000
+; SI-NEXT:    v_mov_b32_e32 v14, 0
+; SI-NEXT:  .LBB13_5: ; %frem.loop_body
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v17, v11
+; SI-NEXT:    v_mov_b32_e32 v16, v10
+; SI-NEXT:    v_mul_f64 v[10:11], v[16:17], v[12:13]
+; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[10:11]|, s[2:3]
+; SI-NEXT:    v_bfi_b32 v15, s5, v18, v11
+; SI-NEXT:    v_add_f64 v[19:20], v[10:11], v[14:15]
+; SI-NEXT:    v_add_f64 v[19:20], v[19:20], -v[14:15]
+; SI-NEXT:    v_cndmask_b32_e32 v11, v20, v11, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v10, v19, v10, vcc
+; SI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[16:17]
+; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; SI-NEXT:    v_add_f64 v[19:20], v[10:11], v[8:9]
+; SI-NEXT:    v_cndmask_b32_e32 v11, v11, v20, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v10, v10, v19, vcc
+; SI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; SI-NEXT:    s_sub_i32 s6, s6, 26
+; SI-NEXT:    s_cmp_gt_i32 s6, 26
+; SI-NEXT:    s_cbranch_scc1 .LBB13_5
+; SI-NEXT:  ; %bb.6: ; %Flow51
+; SI-NEXT:    v_mov_b32_e32 v10, v16
+; SI-NEXT:    v_mov_b32_e32 v11, v17
+; SI-NEXT:  .LBB13_7: ; %frem.loop_exit
+; SI-NEXT:    s_sub_i32 s0, s6, 25
+; SI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], s0
+; SI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[12:13]
+; SI-NEXT:    s_mov_b32 s0, -1
+; SI-NEXT:    s_mov_b32 s1, 0x432fffff
+; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[12:13]|, s[0:1]
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_mov_b32_e32 v14, 0x43300000
+; SI-NEXT:    v_bfi_b32 v15, s0, v14, v13
+; SI-NEXT:    v_mov_b32_e32 v14, 0
+; SI-NEXT:    v_add_f64 v[16:17], v[12:13], v[14:15]
+; SI-NEXT:    v_add_f64 v[14:15], v[16:17], -v[14:15]
+; SI-NEXT:    v_cndmask_b32_e32 v13, v15, v13, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v12, v14, v12, vcc
+; SI-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; SI-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
+; SI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; SI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], s4
+; SI-NEXT:    v_bfi_b32 v9, s0, v9, v1
+; SI-NEXT:  .LBB13_8:
+; SI-NEXT:    v_cmp_ngt_f64_e64 s[0:1], |v[2:3]|, |v[6:7]|
+; SI-NEXT:    s_and_b64 vcc, exec, s[0:1]
+; SI-NEXT:    s_cbranch_vccz .LBB13_10
+; SI-NEXT:  ; %bb.9: ; %frem.else16
+; SI-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; SI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; SI-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
+; SI-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
+; SI-NEXT:    s_mov_b64 vcc, exec
+; SI-NEXT:    s_cbranch_execz .LBB13_11
+; SI-NEXT:    s_branch .LBB13_16
+; SI-NEXT:  .LBB13_10:
+; SI-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; SI-NEXT:    s_mov_b64 vcc, 0
+; SI-NEXT:  .LBB13_11: ; %frem.compute15
+; SI-NEXT:    s_brev_b32 s5, -2
+; SI-NEXT:    v_and_b32_e32 v12, 0x7fffffff, v3
+; SI-NEXT:    s_mov_b32 s0, 0
+; SI-NEXT:    s_mov_b32 s1, 0x7ff00000
+; SI-NEXT:    v_cmp_lt_f64_e64 vcc, |v[2:3]|, s[0:1]
+; SI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; SI-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v10, v2, v10, vcc
+; SI-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[2:3]
+; SI-NEXT:    s_and_b64 s[2:3], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s2, v12
+; SI-NEXT:    s_cselect_b32 s3, s2, 0
+; SI-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; SI-NEXT:    v_and_b32_e32 v14, 0x7fffffff, v7
+; SI-NEXT:    v_cmp_lt_f64_e64 vcc, |v[6:7]|, s[0:1]
+; SI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; SI-NEXT:    v_cndmask_b32_e32 v11, v14, v11, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v10, v6, v10, vcc
+; SI-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[6:7]
+; SI-NEXT:    s_and_b64 s[0:1], vcc, exec
+; SI-NEXT:    v_readfirstlane_b32 s0, v14
+; SI-NEXT:    s_cselect_b32 s7, s0, 0
+; SI-NEXT:    s_mov_b32 s2, -1
+; SI-NEXT:    s_add_i32 s4, s7, -1
+; SI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; SI-NEXT:    s_not_b32 s0, s4
+; SI-NEXT:    s_add_i32 s6, s0, s3
+; SI-NEXT:    v_div_scale_f64 v[14:15], s[0:1], v[10:11], v[10:11], 1.0
+; SI-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
+; SI-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
+; SI-NEXT:    v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
+; SI-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], 1.0
+; SI-NEXT:    v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
+; SI-NEXT:    v_div_scale_f64 v[18:19], s[0:1], 1.0, v[10:11], 1.0
+; SI-NEXT:    v_mul_f64 v[20:21], v[18:19], v[16:17]
+; SI-NEXT:    v_fma_f64 v[22:23], -v[14:15], v[20:21], v[18:19]
+; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v11, v15
+; SI-NEXT:    s_mov_b32 s0, 0x3ff00000
+; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], s0, v19
 ; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
-; SI-NEXT:    s_nop 1
-; SI-NEXT:    v_div_fmas_f64 v[6:7], v[14:15], v[8:9], v[12:13]
-; SI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
-; SI-NEXT:    v_readfirstlane_b32 s0, v6
-; SI-NEXT:    v_readfirstlane_b32 s1, v7
-; SI-NEXT:    s_bfe_u32 s8, s1, 0xb0014
-; SI-NEXT:    s_addk_i32 s8, 0xfc01
-; SI-NEXT:    s_lshr_b64 s[2:3], s[2:3], s8
-; SI-NEXT:    s_andn2_b64 s[2:3], s[0:1], s[2:3]
-; SI-NEXT:    s_and_b32 s9, s1, 0x80000000
-; SI-NEXT:    s_cmp_lt_i32 s8, 0
-; SI-NEXT:    s_cselect_b32 s2, 0, s2
-; SI-NEXT:    s_cselect_b32 s3, s9, s3
-; SI-NEXT:    s_cmp_gt_i32 s8, 51
-; SI-NEXT:    s_cselect_b32 s1, s1, s3
-; SI-NEXT:    s_cselect_b32 s0, s0, s2
-; SI-NEXT:    v_fma_f64 v[0:1], -s[0:1], v[4:5], v[0:1]
-; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT:    s_nop 0
+; SI-NEXT:    v_div_fmas_f64 v[14:15], v[22:23], v[16:17], v[20:21]
+; SI-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; SI-NEXT:    s_cmp_lt_i32 s6, 27
+; SI-NEXT:    s_cbranch_scc1 .LBB13_15
+; SI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; SI-NEXT:    s_sub_i32 s0, s3, s7
+; SI-NEXT:    s_add_i32 s6, s0, 26
+; SI-NEXT:    s_mov_b32 s3, 0x432fffff
+; SI-NEXT:    v_mov_b32_e32 v20, 0x43300000
+; SI-NEXT:    v_mov_b32_e32 v16, 0
+; SI-NEXT:  .LBB13_13: ; %frem.loop_body23
+; SI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; SI-NEXT:    v_mov_b32_e32 v19, v13
+; SI-NEXT:    v_mov_b32_e32 v18, v12
+; SI-NEXT:    v_mul_f64 v[12:13], v[18:19], v[14:15]
+; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[12:13]|, s[2:3]
+; SI-NEXT:    v_bfi_b32 v17, s5, v20, v13
+; SI-NEXT:    v_add_f64 v[21:22], v[12:13], v[16:17]
+; SI-NEXT:    v_add_f64 v[21:22], v[21:22], -v[16:17]
+; SI-NEXT:    v_cndmask_b32_e32 v13, v22, v13, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v12, v21, v12, vcc
+; SI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[18:19]
+; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; SI-NEXT:    v_add_f64 v[21:22], v[12:13], v[10:11]
+; SI-NEXT:    v_cndmask_b32_e32 v13, v13, v22, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v12, v12, v21, vcc
+; SI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; SI-NEXT:    s_sub_i32 s6, s6, 26
+; SI-NEXT:    s_cmp_gt_i32 s6, 26
+; SI-NEXT:    s_cbranch_scc1 .LBB13_13
+; SI-NEXT:  ; %bb.14: ; %Flow
+; SI-NEXT:    v_mov_b32_e32 v12, v18
+; SI-NEXT:    v_mov_b32_e32 v13, v19
+; SI-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; SI-NEXT:    s_sub_i32 s0, s6, 25
+; SI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], s0
+; SI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[14:15]
+; SI-NEXT:    s_mov_b32 s0, -1
+; SI-NEXT:    s_mov_b32 s1, 0x432fffff
+; SI-NEXT:    v_cmp_gt_f64_e64 vcc, |v[14:15]|, s[0:1]
+; SI-NEXT:    s_brev_b32 s0, -2
+; SI-NEXT:    v_mov_b32_e32 v16, 0x43300000
+; SI-NEXT:    v_bfi_b32 v17, s0, v16, v15
+; SI-NEXT:    v_mov_b32_e32 v16, 0
+; SI-NEXT:    v_add_f64 v[18:19], v[14:15], v[16:17]
+; SI-NEXT:    v_add_f64 v[16:17], v[18:19], -v[16:17]
+; SI-NEXT:    v_cndmask_b32_e32 v15, v17, v15, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
+; SI-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; SI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; SI-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
+; SI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
+; SI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], s4
+; SI-NEXT:    v_bfi_b32 v11, s0, v11, v3
+; SI-NEXT:  .LBB13_16: ; %Flow50
+; SI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
+; SI-NEXT:    s_mov_b32 s0, 0
+; SI-NEXT:    s_mov_b32 s1, 0x7ff00000
+; SI-NEXT:    v_cmp_nge_f64_e64 s[2:3], |v[0:1]|, s[0:1]
+; SI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; SI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
+; SI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
+; SI-NEXT:    s_mov_b32 s11, 0xf000
+; SI-NEXT:    s_mov_b32 s10, -1
+; SI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
+; SI-NEXT:    v_cmp_nge_f64_e64 s[0:1], |v[2:3]|, s[0:1]
+; SI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; SI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
+; SI-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
+; SI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; SI-NEXT:    s_endpgm
 ;
 ; CI-LABEL: frem_v2f64:
 ; CI:       ; %bb.0:
-; CI-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x9
+; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; CI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0xd
-; CI-NEXT:    s_mov_b32 s3, 0xf000
-; CI-NEXT:    s_mov_b32 s2, -1
-; CI-NEXT:    s_mov_b32 s6, s2
+; CI-NEXT:    s_mov_b32 s11, 0xf000
+; CI-NEXT:    s_mov_b32 s10, -1
+; CI-NEXT:    s_mov_b32 s6, s10
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
-; CI-NEXT:    s_mov_b32 s0, s8
-; CI-NEXT:    s_mov_b32 s1, s9
-; CI-NEXT:    s_mov_b32 s8, s10
-; CI-NEXT:    s_mov_b32 s9, s11
-; CI-NEXT:    s_mov_b32 s10, s2
-; CI-NEXT:    s_mov_b32 s11, s3
-; CI-NEXT:    s_mov_b32 s7, s3
+; CI-NEXT:    s_mov_b32 s8, s2
+; CI-NEXT:    s_mov_b32 s9, s3
+; CI-NEXT:    s_mov_b32 s7, s11
 ; CI-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
 ; CI-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:64
 ; CI-NEXT:    s_waitcnt vmcnt(0)
-; CI-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[6:7], v[6:7], v[2:3]
-; CI-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; CI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; CI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; CI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; CI-NEXT:    v_div_scale_f64 v[12:13], vcc, v[2:3], v[6:7], v[2:3]
-; CI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
-; CI-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
+; CI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB13_2
+; CI-NEXT:  ; %bb.1: ; %frem.else
+; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; CI-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; CI-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
+; CI-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
+; CI-NEXT:    s_cbranch_execz .LBB13_3
+; CI-NEXT:    s_branch .LBB13_8
+; CI-NEXT:  .LBB13_2:
+; CI-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; CI-NEXT:  .LBB13_3: ; %frem.compute
+; CI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; CI-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
+; CI-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
+; CI-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; CI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; CI-NEXT:    v_add_i32_e32 v16, vcc, -1, v15
+; CI-NEXT:    v_not_b32_e32 v12, v16
+; CI-NEXT:    v_add_i32_e32 v17, vcc, v12, v14
+; CI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
+; CI-NEXT:    v_div_scale_f64 v[12:13], s[2:3], v[8:9], v[8:9], 1.0
+; CI-NEXT:    v_rcp_f64_e32 v[18:19], v[12:13]
+; CI-NEXT:    v_fma_f64 v[20:21], -v[12:13], v[18:19], 1.0
+; CI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
+; CI-NEXT:    v_fma_f64 v[20:21], -v[12:13], v[18:19], 1.0
+; CI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
+; CI-NEXT:    v_div_scale_f64 v[20:21], vcc, 1.0, v[8:9], 1.0
+; CI-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
+; CI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
 ; CI-NEXT:    s_nop 1
-; CI-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
-; CI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
-; CI-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
-; CI-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
-; CI-NEXT:    v_div_scale_f64 v[6:7], s[4:5], v[4:5], v[4:5], v[0:1]
-; CI-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
-; CI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; CI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; CI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; CI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; CI-NEXT:    v_div_scale_f64 v[10:11], vcc, v[0:1], v[4:5], v[0:1]
-; CI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
-; CI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
+; CI-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[18:19], v[22:23]
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v17
+; CI-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB13_7
+; CI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; CI-NEXT:    v_sub_i32_e32 v14, vcc, v14, v15
+; CI-NEXT:    v_add_i32_e32 v17, vcc, 26, v14
+; CI-NEXT:  .LBB13_5: ; %frem.loop_body
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v15, v11
+; CI-NEXT:    v_mov_b32_e32 v14, v10
+; CI-NEXT:    v_mul_f64 v[10:11], v[14:15], v[12:13]
+; CI-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
+; CI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; CI-NEXT:    v_add_f64 v[18:19], v[10:11], v[8:9]
+; CI-NEXT:    v_cndmask_b32_e32 v11, v11, v19, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v10, v10, v18, vcc
+; CI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; CI-NEXT:    v_subrev_i32_e32 v17, vcc, 26, v17
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v17
+; CI-NEXT:    s_cbranch_vccnz .LBB13_5
+; CI-NEXT:  ; %bb.6: ; %Flow51
+; CI-NEXT:    v_mov_b32_e32 v10, v14
+; CI-NEXT:    v_mov_b32_e32 v11, v15
+; CI-NEXT:  .LBB13_7: ; %frem.loop_exit
+; CI-NEXT:    v_subrev_i32_e32 v14, vcc, 25, v17
+; CI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v14
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[12:13]
+; CI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; CI-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; CI-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
+; CI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; CI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
+; CI-NEXT:    v_bfi_b32 v9, s2, v9, v1
+; CI-NEXT:  .LBB13_8:
+; CI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
+; CI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; CI-NEXT:    s_cbranch_vccz .LBB13_10
+; CI-NEXT:  ; %bb.9: ; %frem.else16
+; CI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; CI-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; CI-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
+; CI-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
+; CI-NEXT:    s_cbranch_execz .LBB13_11
+; CI-NEXT:    s_branch .LBB13_16
+; CI-NEXT:  .LBB13_10:
+; CI-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; CI-NEXT:  .LBB13_11: ; %frem.compute15
+; CI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; CI-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
+; CI-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
+; CI-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; CI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; CI-NEXT:    v_add_i32_e32 v18, vcc, -1, v17
+; CI-NEXT:    v_not_b32_e32 v14, v18
+; CI-NEXT:    v_add_i32_e32 v19, vcc, v14, v16
+; CI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; CI-NEXT:    v_div_scale_f64 v[14:15], s[2:3], v[10:11], v[10:11], 1.0
+; CI-NEXT:    v_rcp_f64_e32 v[20:21], v[14:15]
+; CI-NEXT:    v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
+; CI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
+; CI-NEXT:    v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
+; CI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
+; CI-NEXT:    v_div_scale_f64 v[22:23], vcc, 1.0, v[10:11], 1.0
+; CI-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
+; CI-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[24:25], v[22:23]
 ; CI-NEXT:    s_nop 1
-; CI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
-; CI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
-; CI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; CI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
+; CI-NEXT:    v_div_fmas_f64 v[14:15], v[14:15], v[20:21], v[24:25]
+; CI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v19
+; CI-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; CI-NEXT:    s_cbranch_vccnz .LBB13_15
+; CI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; CI-NEXT:    v_sub_i32_e32 v16, vcc, v16, v17
+; CI-NEXT:    v_add_i32_e32 v19, vcc, 26, v16
+; CI-NEXT:  .LBB13_13: ; %frem.loop_body23
+; CI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CI-NEXT:    v_mov_b32_e32 v17, v13
+; CI-NEXT:    v_mov_b32_e32 v16, v12
+; CI-NEXT:    v_mul_f64 v[12:13], v[16:17], v[14:15]
+; CI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; CI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; CI-NEXT:    v_add_f64 v[20:21], v[12:13], v[10:11]
+; CI-NEXT:    v_cndmask_b32_e32 v13, v13, v21, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v12, v12, v20, vcc
+; CI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; CI-NEXT:    v_subrev_i32_e32 v19, vcc, 26, v19
+; CI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v19
+; CI-NEXT:    s_cbranch_vccnz .LBB13_13
+; CI-NEXT:  ; %bb.14: ; %Flow
+; CI-NEXT:    v_mov_b32_e32 v12, v16
+; CI-NEXT:    v_mov_b32_e32 v13, v17
+; CI-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; CI-NEXT:    v_subrev_i32_e32 v16, vcc, 25, v19
+; CI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v16
+; CI-NEXT:    s_brev_b32 s2, -2
+; CI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[14:15]
+; CI-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
+; CI-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; CI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; CI-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
+; CI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
+; CI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
+; CI-NEXT:    v_bfi_b32 v11, s2, v11, v3
+; CI-NEXT:  .LBB13_16: ; %Flow50
+; CI-NEXT:    s_mov_b32 s4, 0
+; CI-NEXT:    s_mov_b32 s5, 0x7ff00000
+; CI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
+; CI-NEXT:    v_cmp_nge_f64_e64 s[2:3], |v[0:1]|, s[4:5]
+; CI-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
+; CI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[2:3]|, s[4:5]
+; CI-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; CI-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
+; CI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
+; CI-NEXT:    s_mov_b32 s3, 0xf000
+; CI-NEXT:    s_mov_b32 s2, -1
+; CI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; CI-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
+; CI-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
 ; CI-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; CI-NEXT:    s_endpgm
 ;
@@ -5335,86 +16478,341 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x34
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v8, s0
-; VI-NEXT:    s_add_u32 s0, s4, 64
-; VI-NEXT:    v_mov_b32_e32 v9, s1
-; VI-NEXT:    s_addc_u32 s1, s5, 0
-; VI-NEXT:    v_mov_b32_e32 v5, s1
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    s_add_u32 s2, s4, 64
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    s_addc_u32 s3, s5, 0
+; VI-NEXT:    v_mov_b32_e32 v5, s3
+; VI-NEXT:    v_mov_b32_e32 v4, s2
 ; VI-NEXT:    flat_load_dwordx4 v[0:3], v[0:1]
 ; VI-NEXT:    flat_load_dwordx4 v[4:7], v[4:5]
 ; VI-NEXT:    s_waitcnt vmcnt(0)
-; VI-NEXT:    v_div_scale_f64 v[10:11], s[0:1], v[6:7], v[6:7], v[2:3]
-; VI-NEXT:    v_rcp_f64_e32 v[12:13], v[10:11]
-; VI-NEXT:    v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
-; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
-; VI-NEXT:    v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
-; VI-NEXT:    v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
-; VI-NEXT:    v_div_scale_f64 v[14:15], vcc, v[2:3], v[6:7], v[2:3]
-; VI-NEXT:    v_mul_f64 v[16:17], v[14:15], v[12:13]
-; VI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
+; VI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB13_2
+; VI-NEXT:  ; %bb.1: ; %frem.else
+; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; VI-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; VI-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
+; VI-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
+; VI-NEXT:    s_cbranch_execz .LBB13_3
+; VI-NEXT:    s_branch .LBB13_8
+; VI-NEXT:  .LBB13_2:
+; VI-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; VI-NEXT:  .LBB13_3: ; %frem.compute
+; VI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; VI-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
+; VI-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
+; VI-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; VI-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; VI-NEXT:    v_add_u32_e32 v16, vcc, -1, v15
+; VI-NEXT:    v_not_b32_e32 v12, v16
+; VI-NEXT:    v_add_u32_e32 v17, vcc, v12, v14
+; VI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
+; VI-NEXT:    v_div_scale_f64 v[12:13], s[2:3], v[8:9], v[8:9], 1.0
+; VI-NEXT:    v_rcp_f64_e32 v[18:19], v[12:13]
+; VI-NEXT:    v_fma_f64 v[20:21], -v[12:13], v[18:19], 1.0
+; VI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
+; VI-NEXT:    v_fma_f64 v[20:21], -v[12:13], v[18:19], 1.0
+; VI-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
+; VI-NEXT:    v_div_scale_f64 v[20:21], vcc, 1.0, v[8:9], 1.0
+; VI-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
+; VI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
 ; VI-NEXT:    s_nop 1
-; VI-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
-; VI-NEXT:    v_div_fixup_f64 v[10:11], v[10:11], v[6:7], v[2:3]
-; VI-NEXT:    v_trunc_f64_e32 v[10:11], v[10:11]
-; VI-NEXT:    v_fma_f64 v[2:3], -v[10:11], v[6:7], v[2:3]
-; VI-NEXT:    v_div_scale_f64 v[6:7], s[0:1], v[4:5], v[4:5], v[0:1]
-; VI-NEXT:    v_rcp_f64_e32 v[10:11], v[6:7]
-; VI-NEXT:    v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
-; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; VI-NEXT:    v_fma_f64 v[12:13], -v[6:7], v[10:11], 1.0
-; VI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; VI-NEXT:    v_div_scale_f64 v[12:13], vcc, v[0:1], v[4:5], v[0:1]
-; VI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
-; VI-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[14:15], v[12:13]
+; VI-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[18:19], v[22:23]
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v17
+; VI-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB13_7
+; VI-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; VI-NEXT:    v_sub_u32_e32 v14, vcc, v14, v15
+; VI-NEXT:    v_add_u32_e32 v17, vcc, 26, v14
+; VI-NEXT:  .LBB13_5: ; %frem.loop_body
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v15, v11
+; VI-NEXT:    v_mov_b32_e32 v14, v10
+; VI-NEXT:    v_mul_f64 v[10:11], v[14:15], v[12:13]
+; VI-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
+; VI-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; VI-NEXT:    v_add_f64 v[18:19], v[10:11], v[8:9]
+; VI-NEXT:    v_cndmask_b32_e32 v11, v11, v19, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v10, v10, v18, vcc
+; VI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; VI-NEXT:    v_subrev_u32_e32 v17, vcc, 26, v17
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v17
+; VI-NEXT:    s_cbranch_vccnz .LBB13_5
+; VI-NEXT:  ; %bb.6: ; %Flow51
+; VI-NEXT:    v_mov_b32_e32 v10, v14
+; VI-NEXT:    v_mov_b32_e32 v11, v15
+; VI-NEXT:  .LBB13_7: ; %frem.loop_exit
+; VI-NEXT:    v_subrev_u32_e32 v14, vcc, 25, v17
+; VI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v14
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[12:13]
+; VI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; VI-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; VI-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
+; VI-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; VI-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
+; VI-NEXT:    v_bfi_b32 v9, s2, v9, v1
+; VI-NEXT:  .LBB13_8:
+; VI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
+; VI-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; VI-NEXT:    s_cbranch_vccz .LBB13_10
+; VI-NEXT:  ; %bb.9: ; %frem.else16
+; VI-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; VI-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; VI-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
+; VI-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
+; VI-NEXT:    s_cbranch_execz .LBB13_11
+; VI-NEXT:    s_branch .LBB13_16
+; VI-NEXT:  .LBB13_10:
+; VI-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; VI-NEXT:  .LBB13_11: ; %frem.compute15
+; VI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; VI-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
+; VI-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
+; VI-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; VI-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; VI-NEXT:    v_add_u32_e32 v18, vcc, -1, v17
+; VI-NEXT:    v_not_b32_e32 v14, v18
+; VI-NEXT:    v_add_u32_e32 v19, vcc, v14, v16
+; VI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; VI-NEXT:    v_div_scale_f64 v[14:15], s[2:3], v[10:11], v[10:11], 1.0
+; VI-NEXT:    v_rcp_f64_e32 v[20:21], v[14:15]
+; VI-NEXT:    v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
+; VI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
+; VI-NEXT:    v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
+; VI-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
+; VI-NEXT:    v_div_scale_f64 v[22:23], vcc, 1.0, v[10:11], 1.0
+; VI-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
+; VI-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[24:25], v[22:23]
 ; VI-NEXT:    s_nop 1
-; VI-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[10:11], v[14:15]
-; VI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
-; VI-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; VI-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
-; VI-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]
+; VI-NEXT:    v_div_fmas_f64 v[14:15], v[14:15], v[20:21], v[24:25]
+; VI-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v19
+; VI-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; VI-NEXT:    s_cbranch_vccnz .LBB13_15
+; VI-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; VI-NEXT:    v_sub_u32_e32 v16, vcc, v16, v17
+; VI-NEXT:    v_add_u32_e32 v19, vcc, 26, v16
+; VI-NEXT:  .LBB13_13: ; %frem.loop_body23
+; VI-NEXT:    ; =>This Inner Loop Header: Depth=1
+; VI-NEXT:    v_mov_b32_e32 v17, v13
+; VI-NEXT:    v_mov_b32_e32 v16, v12
+; VI-NEXT:    v_mul_f64 v[12:13], v[16:17], v[14:15]
+; VI-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; VI-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; VI-NEXT:    v_add_f64 v[20:21], v[12:13], v[10:11]
+; VI-NEXT:    v_cndmask_b32_e32 v13, v13, v21, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v12, v12, v20, vcc
+; VI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; VI-NEXT:    v_subrev_u32_e32 v19, vcc, 26, v19
+; VI-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v19
+; VI-NEXT:    s_cbranch_vccnz .LBB13_13
+; VI-NEXT:  ; %bb.14: ; %Flow
+; VI-NEXT:    v_mov_b32_e32 v12, v16
+; VI-NEXT:    v_mov_b32_e32 v13, v17
+; VI-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; VI-NEXT:    v_subrev_u32_e32 v16, vcc, 25, v19
+; VI-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v16
+; VI-NEXT:    s_brev_b32 s2, -2
+; VI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[14:15]
+; VI-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
+; VI-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; VI-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; VI-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
+; VI-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
+; VI-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
+; VI-NEXT:    v_bfi_b32 v11, s2, v11, v3
+; VI-NEXT:  .LBB13_16: ; %Flow50
+; VI-NEXT:    s_mov_b32 s2, 0
+; VI-NEXT:    s_mov_b32 s3, 0x7ff00000
+; VI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
+; VI-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[0:1]|, s[2:3]
+; VI-NEXT:    v_mov_b32_e32 v12, 0x7ff80000
+; VI-NEXT:    v_mov_b32_e32 v4, s0
+; VI-NEXT:    v_mov_b32_e32 v5, s1
+; VI-NEXT:    v_cmp_nge_f64_e64 s[0:1], |v[2:3]|, s[2:3]
+; VI-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v1, v12, v9, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
+; VI-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
+; VI-NEXT:    s_and_b64 vcc, s[0:1], vcc
+; VI-NEXT:    v_cndmask_b32_e32 v3, v12, v11, vcc
+; VI-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
+; VI-NEXT:    flat_store_dwordx4 v[4:5], v[0:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: frem_v2f64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX9-NEXT:    v_mov_b32_e32 v16, 0
+; GFX9-NEXT:    v_mov_b32_e32 v8, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_load_dwordx4 v[0:3], v16, s[2:3]
-; GFX9-NEXT:    global_load_dwordx4 v[4:7], v16, s[6:7] offset:64
+; GFX9-NEXT:    global_load_dwordx4 v[0:3], v8, s[2:3]
+; GFX9-NEXT:    global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_div_scale_f64 v[8:9], s[2:3], v[6:7], v[6:7], v[2:3]
-; GFX9-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX9-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX9-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX9-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX9-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX9-NEXT:    v_div_scale_f64 v[12:13], vcc, v[2:3], v[6:7], v[2:3]
-; GFX9-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
+; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[0:1]|, |v[4:5]|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB13_2
+; GFX9-NEXT:  ; %bb.1: ; %frem.else
+; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[0:1]|, |v[4:5]|
+; GFX9-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB13_3
+; GFX9-NEXT:    s_branch .LBB13_8
+; GFX9-NEXT:  .LBB13_2:
+; GFX9-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; GFX9-NEXT:  .LBB13_3: ; %frem.compute
+; GFX9-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[4:5]
+; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[0:1]
+; GFX9-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX9-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; GFX9-NEXT:    v_add_u32_e32 v16, -1, v15
+; GFX9-NEXT:    v_not_b32_e32 v12, v16
+; GFX9-NEXT:    v_add_u32_e32 v17, v12, v14
+; GFX9-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
+; GFX9-NEXT:    v_div_scale_f64 v[12:13], s[2:3], v[8:9], v[8:9], 1.0
+; GFX9-NEXT:    v_rcp_f64_e32 v[18:19], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[20:21], -v[12:13], v[18:19], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[20:21], -v[12:13], v[18:19], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
+; GFX9-NEXT:    v_div_scale_f64 v[20:21], vcc, 1.0, v[8:9], 1.0
+; GFX9-NEXT:    v_mul_f64 v[22:23], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[22:23], v[20:21]
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
-; GFX9-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
-; GFX9-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
-; GFX9-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
-; GFX9-NEXT:    v_div_scale_f64 v[6:7], s[2:3], v[4:5], v[4:5], v[0:1]
-; GFX9-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX9-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX9-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; GFX9-NEXT:    v_div_scale_f64 v[10:11], vcc, v[0:1], v[4:5], v[0:1]
-; GFX9-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
-; GFX9-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
+; GFX9-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[18:19], v[22:23]
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v17
+; GFX9-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB13_7
+; GFX9-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v14, v14, v15
+; GFX9-NEXT:    v_add_u32_e32 v17, 26, v14
+; GFX9-NEXT:  .LBB13_5: ; %frem.loop_body
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v15, v11
+; GFX9-NEXT:    v_mov_b32_e32 v14, v10
+; GFX9-NEXT:    v_mul_f64 v[10:11], v[14:15], v[12:13]
+; GFX9-NEXT:    v_subrev_u32_e32 v17, 26, v17
+; GFX9-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; GFX9-NEXT:    v_add_f64 v[18:19], v[10:11], v[8:9]
+; GFX9-NEXT:    v_cndmask_b32_e32 v11, v11, v19, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v18, vcc
+; GFX9-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v17
+; GFX9-NEXT:    s_cbranch_vccnz .LBB13_5
+; GFX9-NEXT:  ; %bb.6: ; %Flow51
+; GFX9-NEXT:    v_mov_b32_e32 v10, v14
+; GFX9-NEXT:    v_mov_b32_e32 v11, v15
+; GFX9-NEXT:  .LBB13_7: ; %frem.loop_exit
+; GFX9-NEXT:    v_subrev_u32_e32 v14, 25, v17
+; GFX9-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX9-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[10:11]
+; GFX9-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
+; GFX9-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX9-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
+; GFX9-NEXT:    v_bfi_b32 v9, s2, v9, v1
+; GFX9-NEXT:  .LBB13_8:
+; GFX9-NEXT:    v_cmp_ngt_f64_e64 s[2:3], |v[2:3]|, |v[6:7]|
+; GFX9-NEXT:    s_and_b64 vcc, exec, s[2:3]
+; GFX9-NEXT:    s_cbranch_vccz .LBB13_10
+; GFX9-NEXT:  ; %bb.9: ; %frem.else16
+; GFX9-NEXT:    v_cmp_eq_f64_e64 vcc, |v[2:3]|, |v[6:7]|
+; GFX9-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; GFX9-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
+; GFX9-NEXT:    s_cbranch_execz .LBB13_11
+; GFX9-NEXT:    s_branch .LBB13_16
+; GFX9-NEXT:  .LBB13_10:
+; GFX9-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; GFX9-NEXT:  .LBB13_11: ; %frem.compute15
+; GFX9-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v17, v[6:7]
+; GFX9-NEXT:    v_frexp_exp_i32_f64_e32 v16, v[2:3]
+; GFX9-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX9-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; GFX9-NEXT:    v_add_u32_e32 v18, -1, v17
+; GFX9-NEXT:    v_not_b32_e32 v14, v18
+; GFX9-NEXT:    v_add_u32_e32 v19, v14, v16
+; GFX9-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; GFX9-NEXT:    v_div_scale_f64 v[14:15], s[2:3], v[10:11], v[10:11], 1.0
+; GFX9-NEXT:    v_rcp_f64_e32 v[20:21], v[14:15]
+; GFX9-NEXT:    v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
+; GFX9-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
+; GFX9-NEXT:    v_fma_f64 v[22:23], -v[14:15], v[20:21], 1.0
+; GFX9-NEXT:    v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
+; GFX9-NEXT:    v_div_scale_f64 v[22:23], vcc, 1.0, v[10:11], 1.0
+; GFX9-NEXT:    v_mul_f64 v[24:25], v[22:23], v[20:21]
+; GFX9-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[24:25], v[22:23]
 ; GFX9-NEXT:    s_nop 1
-; GFX9-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
-; GFX9-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
-; GFX9-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; GFX9-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
-; GFX9-NEXT:    global_store_dwordx4 v16, v[0:3], s[0:1]
+; GFX9-NEXT:    v_div_fmas_f64 v[14:15], v[14:15], v[20:21], v[24:25]
+; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 27, v19
+; GFX9-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX9-NEXT:    s_cbranch_vccnz .LBB13_15
+; GFX9-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX9-NEXT:    v_sub_u32_e32 v16, v16, v17
+; GFX9-NEXT:    v_add_u32_e32 v19, 26, v16
+; GFX9-NEXT:  .LBB13_13: ; %frem.loop_body23
+; GFX9-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-NEXT:    v_mov_b32_e32 v17, v13
+; GFX9-NEXT:    v_mov_b32_e32 v16, v12
+; GFX9-NEXT:    v_mul_f64 v[12:13], v[16:17], v[14:15]
+; GFX9-NEXT:    v_subrev_u32_e32 v19, 26, v19
+; GFX9-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; GFX9-NEXT:    v_add_f64 v[20:21], v[12:13], v[10:11]
+; GFX9-NEXT:    v_cndmask_b32_e32 v13, v13, v21, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v12, v12, v20, vcc
+; GFX9-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX9-NEXT:    v_cmp_lt_i32_e32 vcc, 26, v19
+; GFX9-NEXT:    s_cbranch_vccnz .LBB13_13
+; GFX9-NEXT:  ; %bb.14: ; %Flow
+; GFX9-NEXT:    v_mov_b32_e32 v12, v16
+; GFX9-NEXT:    v_mov_b32_e32 v13, v17
+; GFX9-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; GFX9-NEXT:    v_subrev_u32_e32 v16, 25, v19
+; GFX9-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v16
+; GFX9-NEXT:    s_brev_b32 s2, -2
+; GFX9-NEXT:    v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX9-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX9-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX9-NEXT:    v_cmp_gt_f64_e32 vcc, 0, v[12:13]
+; GFX9-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
+; GFX9-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
+; GFX9-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
+; GFX9-NEXT:    v_bfi_b32 v11, s2, v11, v3
+; GFX9-NEXT:  .LBB13_16: ; %Flow50
+; GFX9-NEXT:    s_mov_b32 s2, 0
+; GFX9-NEXT:    s_mov_b32 s3, 0x7ff00000
+; GFX9-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[4:5]
+; GFX9-NEXT:    v_cmp_nge_f64_e64 s[4:5], |v[0:1]|, s[2:3]
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0x7ff80000
+; GFX9-NEXT:    v_cmp_nge_f64_e64 s[2:3], |v[2:3]|, s[2:3]
+; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    s_and_b64 vcc, s[4:5], vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v9, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc
+; GFX9-NEXT:    v_cmp_lg_f64_e32 vcc, 0, v[6:7]
+; GFX9-NEXT:    s_and_b64 vcc, s[2:3], vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v11, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc
+; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[0:1]
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: frem_v2f64:
@@ -5422,39 +16820,168 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX10-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
-; GFX10-NEXT:    v_mov_b32_e32 v16, 0
+; GFX10-NEXT:    v_mov_b32_e32 v8, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
-; GFX10-NEXT:    global_load_dwordx4 v[0:3], v16, s[2:3]
-; GFX10-NEXT:    global_load_dwordx4 v[4:7], v16, s[6:7] offset:64
+; GFX10-NEXT:    global_load_dwordx4 v[0:3], v8, s[2:3]
+; GFX10-NEXT:    global_load_dwordx4 v[4:7], v8, s[6:7] offset:64
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_div_scale_f64 v[8:9], s2, v[6:7], v[6:7], v[2:3]
-; GFX10-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX10-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX10-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX10-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX10-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX10-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[6:7], v[2:3]
-; GFX10-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
-; GFX10-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
-; GFX10-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
-; GFX10-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
-; GFX10-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
-; GFX10-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
-; GFX10-NEXT:    v_div_scale_f64 v[6:7], s2, v[4:5], v[4:5], v[0:1]
-; GFX10-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
-; GFX10-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX10-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; GFX10-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX10-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; GFX10-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[4:5], v[0:1]
-; GFX10-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
-; GFX10-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
-; GFX10-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
-; GFX10-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
-; GFX10-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; GFX10-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
-; GFX10-NEXT:    global_store_dwordx4 v16, v[0:3], s[0:1]
+; GFX10-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB13_2
+; GFX10-NEXT:  ; %bb.1: ; %frem.else
+; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX10-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; GFX10-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB13_3
+; GFX10-NEXT:    s_branch .LBB13_8
+; GFX10-NEXT:  .LBB13_2:
+; GFX10-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; GFX10-NEXT:  .LBB13_3: ; %frem.compute
+; GFX10-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX10-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX10-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; GFX10-NEXT:    v_add_nc_u32_e32 v16, -1, v13
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v13
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v12
+; GFX10-NEXT:    v_not_b32_e32 v13, v16
+; GFX10-NEXT:    v_add_nc_u32_e32 v17, v13, v12
+; GFX10-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
+; GFX10-NEXT:    v_div_scale_f64 v[12:13], s4, v[8:9], v[8:9], 1.0
+; GFX10-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX10-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX10-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX10-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX10-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX10-NEXT:    v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
+; GFX10-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
+; GFX10-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX10-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
+; GFX10-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB13_7
+; GFX10-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 26
+; GFX10-NEXT:  .LBB13_5: ; %frem.loop_body
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v15, v11
+; GFX10-NEXT:    v_mov_b32_e32 v14, v10
+; GFX10-NEXT:    s_sub_i32 s2, s2, 26
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX10-NEXT:    v_mul_f64 v[10:11], v[14:15], v[12:13]
+; GFX10-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX10-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX10-NEXT:    v_add_f64 v[17:18], v[10:11], v[8:9]
+; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v18, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v17, vcc_lo
+; GFX10-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX10-NEXT:    s_cbranch_scc1 .LBB13_5
+; GFX10-NEXT:  ; %bb.6: ; %Flow51
+; GFX10-NEXT:    v_mov_b32_e32 v10, v14
+; GFX10-NEXT:    v_mov_b32_e32 v17, s2
+; GFX10-NEXT:    v_mov_b32_e32 v11, v15
+; GFX10-NEXT:  .LBB13_7: ; %frem.loop_exit
+; GFX10-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
+; GFX10-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX10-NEXT:    v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX10-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX10-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX10-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
+; GFX10-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc_lo
+; GFX10-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
+; GFX10-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
+; GFX10-NEXT:  .LBB13_8:
+; GFX10-NEXT:    v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX10-NEXT:    s_cbranch_vccz .LBB13_10
+; GFX10-NEXT:  ; %bb.9: ; %frem.else16
+; GFX10-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX10-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; GFX10-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX10-NEXT:    s_cbranch_execz .LBB13_11
+; GFX10-NEXT:    s_branch .LBB13_16
+; GFX10-NEXT:  .LBB13_10:
+; GFX10-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; GFX10-NEXT:  .LBB13_11: ; %frem.compute15
+; GFX10-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX10-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX10-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX10-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; GFX10-NEXT:    v_add_nc_u32_e32 v18, -1, v15
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v15
+; GFX10-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX10-NEXT:    v_not_b32_e32 v15, v18
+; GFX10-NEXT:    v_add_nc_u32_e32 v19, v15, v14
+; GFX10-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; GFX10-NEXT:    v_div_scale_f64 v[14:15], s4, v[10:11], v[10:11], 1.0
+; GFX10-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
+; GFX10-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX10-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
+; GFX10-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX10-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
+; GFX10-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
+; GFX10-NEXT:    v_mul_f64 v[22:23], v[20:21], v[16:17]
+; GFX10-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
+; GFX10-NEXT:    v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
+; GFX10-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX10-NEXT:    s_cbranch_vccnz .LBB13_15
+; GFX10-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX10-NEXT:    s_sub_i32 s2, s2, s3
+; GFX10-NEXT:    s_add_i32 s2, s2, 26
+; GFX10-NEXT:  .LBB13_13: ; %frem.loop_body23
+; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX10-NEXT:    v_mov_b32_e32 v17, v13
+; GFX10-NEXT:    v_mov_b32_e32 v16, v12
+; GFX10-NEXT:    s_sub_i32 s2, s2, 26
+; GFX10-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX10-NEXT:    v_mul_f64 v[12:13], v[16:17], v[14:15]
+; GFX10-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX10-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX10-NEXT:    v_add_f64 v[19:20], v[12:13], v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v20, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v19, vcc_lo
+; GFX10-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX10-NEXT:    s_cbranch_scc1 .LBB13_13
+; GFX10-NEXT:  ; %bb.14: ; %Flow
+; GFX10-NEXT:    v_mov_b32_e32 v12, v16
+; GFX10-NEXT:    v_mov_b32_e32 v19, s2
+; GFX10-NEXT:    v_mov_b32_e32 v13, v17
+; GFX10-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; GFX10-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
+; GFX10-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v16
+; GFX10-NEXT:    v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX10-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX10-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX10-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX10-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e32 v11, v13, v11, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc_lo
+; GFX10-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
+; GFX10-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
+; GFX10-NEXT:  .LBB13_16: ; %Flow50
+; GFX10-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
+; GFX10-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX10-NEXT:    v_mov_b32_e32 v4, 0
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[2:3]|
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX10-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
+; GFX10-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v11, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc_lo
+; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1]
 ; GFX10-NEXT:    s_endpgm
 ;
 ; GFX11-LABEL: frem_v2f64:
@@ -5462,51 +16989,200 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX11-NEXT:    s_clause 0x1
 ; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-NEXT:    v_mov_b32_e32 v16, 0
+; GFX11-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-NEXT:    s_clause 0x1
-; GFX11-NEXT:    global_load_b128 v[0:3], v16, s[2:3]
-; GFX11-NEXT:    global_load_b128 v[4:7], v16, s[4:5] offset:64
+; GFX11-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
+; GFX11-NEXT:    global_load_b128 v[4:7], v4, s[4:5] offset:64
 ; GFX11-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-NEXT:    v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX11-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB13_2
+; GFX11-NEXT:  ; %bb.1: ; %frem.else
+; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX11-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB13_3
+; GFX11-NEXT:    s_branch .LBB13_8
+; GFX11-NEXT:  .LBB13_2:
+; GFX11-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; GFX11-NEXT:  .LBB13_3: ; %frem.compute
+; GFX11-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX11-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; GFX11-NEXT:    v_add_nc_u32_e32 v16, -1, v13
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v13
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v12
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v13, v16
+; GFX11-NEXT:    v_add_nc_u32_e32 v17, v13, v12
+; GFX11-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
+; GFX11-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX11-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
+; GFX11-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX11-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX11-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[6:7], v[2:3]
+; GFX11-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX11-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX11-NEXT:    v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
+; GFX11-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
-; GFX11-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
+; GFX11-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX11-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB13_7
+; GFX11-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 26
+; GFX11-NEXT:    .p2align 6
+; GFX11-NEXT:  .LBB13_5: ; %frem.loop_body
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
+; GFX11-NEXT:    s_sub_i32 s2, s2, 26
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 26
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
-; GFX11-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
+; GFX11-NEXT:    v_mul_f64 v[10:11], v[14:15], v[12:13]
+; GFX11-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
-; GFX11-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
-; GFX11-NEXT:    v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[0:1]
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
+; GFX11-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT:    v_add_f64 v[17:18], v[10:11], v[8:9]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
+; GFX11-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX11-NEXT:    s_cbranch_scc1 .LBB13_5
+; GFX11-NEXT:  ; %bb.6: ; %Flow51
+; GFX11-NEXT:    v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
+; GFX11-NEXT:    v_mov_b32_e32 v11, v15
+; GFX11-NEXT:  .LBB13_7: ; %frem.loop_exit
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
+; GFX11-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX11-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX11-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
+; GFX11-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
+; GFX11-NEXT:  .LBB13_8:
+; GFX11-NEXT:    v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX11-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX11-NEXT:    s_cbranch_vccz .LBB13_10
+; GFX11-NEXT:  ; %bb.9: ; %frem.else16
+; GFX11-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX11-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX11-NEXT:    s_cbranch_execz .LBB13_11
+; GFX11-NEXT:    s_branch .LBB13_16
+; GFX11-NEXT:  .LBB13_10:
+; GFX11-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; GFX11-NEXT:  .LBB13_11: ; %frem.compute15
+; GFX11-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX11-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX11-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; GFX11-NEXT:    v_add_nc_u32_e32 v18, -1, v15
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v15
+; GFX11-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_not_b32_e32 v15, v18
+; GFX11-NEXT:    v_add_nc_u32_e32 v19, v15, v14
+; GFX11-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
+; GFX11-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
 ; GFX11-NEXT:    s_waitcnt_depctr 0xfff
-; GFX11-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX11-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
+; GFX11-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
+; GFX11-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
+; GFX11-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
+; GFX11-NEXT:    v_mul_f64 v[22:23], v[20:21], v[16:17]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
+; GFX11-NEXT:    v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX11-NEXT:    s_cbranch_vccnz .LBB13_15
+; GFX11-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX11-NEXT:    s_sub_i32 s2, s2, s3
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    s_add_i32 s2, s2, 26
+; GFX11-NEXT:    .p2align 6
+; GFX11-NEXT:  .LBB13_13: ; %frem.loop_body23
+; GFX11-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
+; GFX11-NEXT:    s_sub_i32 s2, s2, 26
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 26
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX11-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; GFX11-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[4:5], v[0:1]
+; GFX11-NEXT:    v_mul_f64 v[12:13], v[16:17], v[14:15]
+; GFX11-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
-; GFX11-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
+; GFX11-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX11-NEXT:    v_add_f64 v[19:20], v[12:13], v[10:11]
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
-; GFX11-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
+; GFX11-NEXT:    v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
+; GFX11-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX11-NEXT:    s_cbranch_scc1 .LBB13_13
+; GFX11-NEXT:  ; %bb.14: ; %Flow
+; GFX11-NEXT:    v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
+; GFX11-NEXT:    v_mov_b32_e32 v13, v17
+; GFX11-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
+; GFX11-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v16
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; GFX11-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
-; GFX11-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
+; GFX11-NEXT:    v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX11-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX11-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX11-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10
+; GFX11-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
+; GFX11-NEXT:  .LBB13_16: ; %Flow50
+; GFX11-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
+; GFX11-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX11-NEXT:    v_mov_b32_e32 v4, 0
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[2:3]|
+; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX11-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
+; GFX11-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v11, vcc_lo
+; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc_lo
+; GFX11-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX11-NEXT:    s_endpgm
 ;
 ; GFX1150-LABEL: frem_v2f64:
@@ -5514,50 +17190,198 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX1150-NEXT:    s_clause 0x1
 ; GFX1150-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1150-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1150-NEXT:    v_mov_b32_e32 v16, 0
+; GFX1150-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX1150-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1150-NEXT:    s_clause 0x1
-; GFX1150-NEXT:    global_load_b128 v[0:3], v16, s[2:3]
-; GFX1150-NEXT:    global_load_b128 v[4:7], v16, s[4:5] offset:64
+; GFX1150-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
+; GFX1150-NEXT:    global_load_b128 v[4:7], v4, s[4:5] offset:64
 ; GFX1150-NEXT:    s_waitcnt vmcnt(0)
-; GFX1150-NEXT:    v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3]
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1150-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX1150-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT:    s_cbranch_vccz .LBB13_2
+; GFX1150-NEXT:  ; %bb.1: ; %frem.else
+; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1150-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX1150-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB13_3
+; GFX1150-NEXT:    s_branch .LBB13_8
+; GFX1150-NEXT:  .LBB13_2:
+; GFX1150-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; GFX1150-NEXT:  .LBB13_3: ; %frem.compute
+; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; GFX1150-NEXT:    v_add_nc_u32_e32 v16, -1, v13
+; GFX1150-NEXT:    v_readfirstlane_b32 s3, v13
+; GFX1150-NEXT:    v_readfirstlane_b32 s2, v12
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v13, v16
+; GFX1150-NEXT:    v_add_nc_u32_e32 v17, v13, v12
+; GFX1150-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX1150-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[6:7], v[2:3]
-; GFX1150-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
+; GFX1150-NEXT:    v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
+; GFX1150-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1150-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
-; GFX1150-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
+; GFX1150-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1150-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX1150-NEXT:    v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
-; GFX1150-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
-; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
-; GFX1150-NEXT:    v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[0:1]
-; GFX1150-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
+; GFX1150-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
+; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
+; GFX1150-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB13_7
+; GFX1150-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1150-NEXT:    s_sub_i32 s2, s2, s3
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s2, s2, 26
+; GFX1150-NEXT:    .p2align 6
+; GFX1150-NEXT:  .LBB13_5: ; %frem.loop_body
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
+; GFX1150-NEXT:    s_sub_i32 s2, s2, 26
+; GFX1150-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f64 v[10:11], v[14:15], v[12:13]
+; GFX1150-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX1150-NEXT:    v_add_f64 v[17:18], v[10:11], v[8:9]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
+; GFX1150-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB13_5
+; GFX1150-NEXT:  ; %bb.6: ; %Flow51
+; GFX1150-NEXT:    v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
+; GFX1150-NEXT:    v_mov_b32_e32 v11, v15
+; GFX1150-NEXT:  .LBB13_7: ; %frem.loop_exit
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
+; GFX1150-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f64 v[12:13], v[10:11], v[12:13]
+; GFX1150-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX1150-NEXT:    v_add_f64 v[8:9], v[10:11], v[8:9]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
+; GFX1150-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
+; GFX1150-NEXT:  .LBB13_8:
+; GFX1150-NEXT:    v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX1150-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX1150-NEXT:    s_cbranch_vccz .LBB13_10
+; GFX1150-NEXT:  ; %bb.9: ; %frem.else16
+; GFX1150-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1150-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1150-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX1150-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX1150-NEXT:    s_cbranch_execz .LBB13_11
+; GFX1150-NEXT:    s_branch .LBB13_16
+; GFX1150-NEXT:  .LBB13_10:
+; GFX1150-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; GFX1150-NEXT:  .LBB13_11: ; %frem.compute15
+; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX1150-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1150-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX1150-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; GFX1150-NEXT:    v_add_nc_u32_e32 v18, -1, v15
+; GFX1150-NEXT:    v_readfirstlane_b32 s3, v15
+; GFX1150-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_not_b32_e32 v15, v18
+; GFX1150-NEXT:    v_add_nc_u32_e32 v19, v15, v14
+; GFX1150-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
+; GFX1150-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
 ; GFX1150-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX1150-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
+; GFX1150-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1150-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1150-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
+; GFX1150-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_mul_f64 v[22:23], v[20:21], v[16:17]
+; GFX1150-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-NEXT:    v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX1150-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
+; GFX1150-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX1150-NEXT:    s_cbranch_vccnz .LBB13_15
+; GFX1150-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX1150-NEXT:    s_sub_i32 s2, s2, s3
+; GFX1150-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1150-NEXT:    s_add_i32 s2, s2, 26
+; GFX1150-NEXT:    .p2align 6
+; GFX1150-NEXT:  .LBB13_13: ; %frem.loop_body23
+; GFX1150-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1150-NEXT:    v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
+; GFX1150-NEXT:    s_sub_i32 s2, s2, 26
+; GFX1150-NEXT:    s_cmp_gt_i32 s2, 26
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX1150-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; GFX1150-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[4:5], v[0:1]
+; GFX1150-NEXT:    v_mul_f64 v[12:13], v[16:17], v[14:15]
+; GFX1150-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
-; GFX1150-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
+; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1150-NEXT:    v_add_f64 v[19:20], v[12:13], v[10:11]
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
-; GFX1150-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
+; GFX1150-NEXT:    v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
+; GFX1150-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX1150-NEXT:    s_cbranch_scc1 .LBB13_13
+; GFX1150-NEXT:  ; %bb.14: ; %Flow
+; GFX1150-NEXT:    v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
+; GFX1150-NEXT:    v_mov_b32_e32 v13, v17
+; GFX1150-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
+; GFX1150-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v16
 ; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; GFX1150-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
-; GFX1150-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
+; GFX1150-NEXT:    v_mul_f64 v[14:15], v[12:13], v[14:15]
+; GFX1150-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX1150-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1150-NEXT:    v_add_f64 v[10:11], v[12:13], v[10:11]
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-NEXT:    v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10
+; GFX1150-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
+; GFX1150-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
+; GFX1150-NEXT:  .LBB13_16: ; %Flow50
+; GFX1150-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
+; GFX1150-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX1150-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX1150-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[2:3]|
+; GFX1150-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX1150-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX1150-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1150-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX1150-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v11, vcc_lo
+; GFX1150-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc_lo
+; GFX1150-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX1150-NEXT:    s_endpgm
 ;
 ; GFX1200-LABEL: frem_v2f64:
@@ -5565,51 +17389,208 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; GFX1200-NEXT:    s_clause 0x1
 ; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX1200-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
-; GFX1200-NEXT:    v_mov_b32_e32 v16, 0
+; GFX1200-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX1200-NEXT:    s_wait_kmcnt 0x0
 ; GFX1200-NEXT:    s_clause 0x1
-; GFX1200-NEXT:    global_load_b128 v[0:3], v16, s[2:3]
-; GFX1200-NEXT:    global_load_b128 v[4:7], v16, s[4:5] offset:64
+; GFX1200-NEXT:    global_load_b128 v[0:3], v4, s[2:3]
+; GFX1200-NEXT:    global_load_b128 v[4:7], v4, s[4:5] offset:64
 ; GFX1200-NEXT:    s_wait_loadcnt 0x0
-; GFX1200-NEXT:    v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3]
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX1200-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s2, |v[0:1]|, |v[4:5]|
+; GFX1200-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT:    s_cbranch_vccz .LBB13_2
+; GFX1200-NEXT:  ; %bb.1: ; %frem.else
+; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[0:1]|, |v[4:5]|
+; GFX1200-NEXT:    v_and_b32_e32 v8, 0x80000000, v1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v9, v1, v8, vcc_lo
+; GFX1200-NEXT:    v_cndmask_b32_e64 v8, v0, 0, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB13_3
+; GFX1200-NEXT:    s_branch .LBB13_8
+; GFX1200-NEXT:  .LBB13_2:
+; GFX1200-NEXT:    ; implicit-def: $vgpr8_vgpr9
+; GFX1200-NEXT:  .LBB13_3: ; %frem.compute
+; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[0:1]|
+; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v13, v[4:5]
+; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v12, v[0:1]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_ldexp_f64 v[10:11], v[8:9], 26
+; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[8:9], |v[4:5]|
+; GFX1200-NEXT:    v_add_nc_u32_e32 v16, -1, v13
+; GFX1200-NEXT:    v_readfirstlane_b32 s3, v13
+; GFX1200-NEXT:    v_readfirstlane_b32 s2, v12
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v13, v16
+; GFX1200-NEXT:    v_add_nc_u32_e32 v17, v13, v12
+; GFX1200-NEXT:    v_ldexp_f64 v[8:9], v[8:9], 1
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX1200-NEXT:    v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[6:7], v[2:3]
-; GFX1200-NEXT:    v_mul_f64_e32 v[14:15], v[12:13], v[10:11]
+; GFX1200-NEXT:    v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], 1.0
+; GFX1200-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1200-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
-; GFX1200-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
+; GFX1200-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[14:15], 1.0
+; GFX1200-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX1200-NEXT:    v_div_scale_f64 v[18:19], vcc_lo, 1.0, v[8:9], 1.0
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
-; GFX1200-NEXT:    v_trunc_f64_e32 v[8:9], v[8:9]
-; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[2:3], -v[8:9], v[6:7], v[2:3]
-; GFX1200-NEXT:    v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[0:1]
-; GFX1200-NEXT:    v_rcp_f64_e32 v[8:9], v[6:7]
+; GFX1200-NEXT:    v_mul_f64_e32 v[20:21], v[18:19], v[14:15]
+; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[20:21], v[18:19]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[20:21]
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v17
+; GFX1200-NEXT:    v_div_fixup_f64 v[12:13], v[12:13], v[8:9], 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB13_7
+; GFX1200-NEXT:  ; %bb.4: ; %frem.loop_body.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s2, s2, s3
+; GFX1200-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT:    s_add_co_i32 s2, s2, 26
+; GFX1200-NEXT:  .LBB13_5: ; %frem.loop_body
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-NEXT:    v_dual_mov_b32 v15, v11 :: v_dual_mov_b32 v14, v10
+; GFX1200-NEXT:    s_sub_co_i32 s2, s2, 26
+; GFX1200-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f64_e32 v[10:11], v[14:15], v[12:13]
+; GFX1200-NEXT:    v_rndne_f64_e32 v[10:11], v[10:11]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[8:9], v[14:15]
+; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX1200-NEXT:    v_add_f64_e32 v[17:18], v[10:11], v[8:9]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_dual_cndmask_b32 v11, v11, v18 :: v_dual_cndmask_b32 v10, v10, v17
+; GFX1200-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 26
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB13_5
+; GFX1200-NEXT:  ; %bb.6: ; %Flow51
+; GFX1200-NEXT:    v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v10, v14
+; GFX1200-NEXT:    v_mov_b32_e32 v11, v15
+; GFX1200-NEXT:  .LBB13_7: ; %frem.loop_exit
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_subrev_nc_u32_e32 v14, 25, v17
+; GFX1200-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v14
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_mul_f64_e32 v[12:13], v[10:11], v[12:13]
+; GFX1200-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[12:13], v[8:9], v[10:11]
+; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[10:11]
+; GFX1200-NEXT:    v_add_f64_e32 v[8:9], v[10:11], v[8:9]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v8, v10, v8
+; GFX1200-NEXT:    v_ldexp_f64 v[8:9], v[8:9], v16
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_bfi_b32 v9, 0x7fffffff, v9, v1
+; GFX1200-NEXT:  .LBB13_8:
+; GFX1200-NEXT:    v_cmp_ngt_f64_e64 s2, |v[2:3]|, |v[6:7]|
+; GFX1200-NEXT:    s_and_b32 vcc_lo, exec_lo, s2
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cbranch_vccz .LBB13_10
+; GFX1200-NEXT:  ; %bb.9: ; %frem.else16
+; GFX1200-NEXT:    v_cmp_eq_f64_e64 vcc_lo, |v[2:3]|, |v[6:7]|
+; GFX1200-NEXT:    v_and_b32_e32 v10, 0x80000000, v3
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT:    v_cndmask_b32_e32 v11, v3, v10, vcc_lo
+; GFX1200-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc_lo
+; GFX1200-NEXT:    s_cbranch_execz .LBB13_11
+; GFX1200-NEXT:    s_branch .LBB13_16
+; GFX1200-NEXT:  .LBB13_10:
+; GFX1200-NEXT:    ; implicit-def: $vgpr10_vgpr11
+; GFX1200-NEXT:  .LBB13_11: ; %frem.compute15
+; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[2:3]|
+; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v15, v[6:7]
+; GFX1200-NEXT:    v_frexp_exp_i32_f64_e32 v14, v[2:3]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT:    v_ldexp_f64 v[12:13], v[10:11], 26
+; GFX1200-NEXT:    v_frexp_mant_f64_e64 v[10:11], |v[6:7]|
+; GFX1200-NEXT:    v_add_nc_u32_e32 v18, -1, v15
+; GFX1200-NEXT:    v_readfirstlane_b32 s3, v15
+; GFX1200-NEXT:    v_readfirstlane_b32 s2, v14
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_not_b32_e32 v15, v18
+; GFX1200-NEXT:    v_add_nc_u32_e32 v19, v15, v14
+; GFX1200-NEXT:    v_ldexp_f64 v[10:11], v[10:11], 1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_div_scale_f64 v[14:15], null, v[10:11], v[10:11], 1.0
+; GFX1200-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
 ; GFX1200-NEXT:    s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX1200-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
+; GFX1200-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1200-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
-; GFX1200-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
-; GFX1200-NEXT:    v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[4:5], v[0:1]
+; GFX1200-NEXT:    v_fma_f64 v[20:21], -v[14:15], v[16:17], 1.0
+; GFX1200-NEXT:    v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
+; GFX1200-NEXT:    v_div_scale_f64 v[20:21], vcc_lo, 1.0, v[10:11], 1.0
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_mul_f64_e32 v[12:13], v[10:11], v[8:9]
-; GFX1200-NEXT:    v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
+; GFX1200-NEXT:    v_mul_f64_e32 v[22:23], v[20:21], v[16:17]
+; GFX1200-NEXT:    v_fma_f64 v[14:15], -v[14:15], v[22:23], v[20:21]
 ; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_div_fmas_f64 v[14:15], v[14:15], v[16:17], v[22:23]
+; GFX1200-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 27, v19
+; GFX1200-NEXT:    v_div_fixup_f64 v[14:15], v[14:15], v[10:11], 1.0
+; GFX1200-NEXT:    s_cbranch_vccnz .LBB13_15
+; GFX1200-NEXT:  ; %bb.12: ; %frem.loop_body23.preheader
+; GFX1200-NEXT:    s_sub_co_i32 s2, s2, s3
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_add_co_i32 s2, s2, 26
+; GFX1200-NEXT:  .LBB13_13: ; %frem.loop_body23
+; GFX1200-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1200-NEXT:    v_dual_mov_b32 v17, v13 :: v_dual_mov_b32 v16, v12
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_sub_co_i32 s2, s2, 26
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    s_cmp_gt_i32 s2, 26
+; GFX1200-NEXT:    v_mul_f64_e32 v[12:13], v[16:17], v[14:15]
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
-; GFX1200-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
+; GFX1200-NEXT:    v_rndne_f64_e32 v[12:13], v[12:13]
+; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[12:13], v[10:11], v[16:17]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1200-NEXT:    v_add_f64_e32 v[19:20], v[12:13], v[10:11]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    v_dual_cndmask_b32 v13, v13, v20 :: v_dual_cndmask_b32 v12, v12, v19
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_ldexp_f64 v[12:13], v[12:13], 26
+; GFX1200-NEXT:    s_cbranch_scc1 .LBB13_13
+; GFX1200-NEXT:  ; %bb.14: ; %Flow
+; GFX1200-NEXT:    v_dual_mov_b32 v19, s2 :: v_dual_mov_b32 v12, v16
+; GFX1200-NEXT:    v_mov_b32_e32 v13, v17
+; GFX1200-NEXT:  .LBB13_15: ; %frem.loop_exit24
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_subrev_nc_u32_e32 v16, 25, v19
+; GFX1200-NEXT:    v_ldexp_f64 v[12:13], v[12:13], v16
 ; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-NEXT:    v_trunc_f64_e32 v[6:7], v[6:7]
-; GFX1200-NEXT:    v_fma_f64 v[0:1], -v[6:7], v[4:5], v[0:1]
-; GFX1200-NEXT:    global_store_b128 v16, v[0:3], s[0:1]
+; GFX1200-NEXT:    v_mul_f64_e32 v[14:15], v[12:13], v[14:15]
+; GFX1200-NEXT:    v_rndne_f64_e32 v[14:15], v[14:15]
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[10:11], v[12:13]
+; GFX1200-NEXT:    v_cmp_gt_f64_e32 vcc_lo, 0, v[12:13]
+; GFX1200-NEXT:    v_add_f64_e32 v[10:11], v[12:13], v[10:11]
+; GFX1200-NEXT:    s_wait_alu 0xfffd
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-NEXT:    v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v12, v10
+; GFX1200-NEXT:    v_ldexp_f64 v[10:11], v[10:11], v18
+; GFX1200-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-NEXT:    v_bfi_b32 v11, 0x7fffffff, v11, v3
+; GFX1200-NEXT:  .LBB13_16: ; %Flow50
+; GFX1200-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[4:5]
+; GFX1200-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[0:1]|
+; GFX1200-NEXT:    v_mov_b32_e32 v4, 0
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX1200-NEXT:    v_cmp_nle_f64_e64 s2, 0x7ff00000, |v[2:3]|
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v1, 0x7ff80000, v9, vcc_lo
+; GFX1200-NEXT:    v_cndmask_b32_e32 v0, 0, v8, vcc_lo
+; GFX1200-NEXT:    v_cmp_lg_f64_e32 vcc_lo, 0, v[6:7]
+; GFX1200-NEXT:    s_and_b32 vcc_lo, s2, vcc_lo
+; GFX1200-NEXT:    s_wait_alu 0xfffe
+; GFX1200-NEXT:    v_cndmask_b32_e32 v3, 0x7ff80000, v11, vcc_lo
+; GFX1200-NEXT:    v_cndmask_b32_e32 v2, 0, v10, vcc_lo
+; GFX1200-NEXT:    global_store_b128 v4, v[0:3], s[0:1]
 ; GFX1200-NEXT:    s_endpgm
                         ptr addrspace(1) %in2) #0 {
    %gep2 = getelementptr <2 x double>, ptr addrspace(1) %in2, i32 4