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| author | Craig Topper <craig.topper@sifive.com> | 2023-07-25 08:54:57 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-07-25 08:54:59 -0700 |
| commit | 12832c1773f520563601c85bd1163fc3e734d3e6 (patch) | |
| tree | 95e828a12f74d08d9186c8607e2710b5ee42e7eb /llvm/lib/TextAPI/TextAPIError.cpp | |
| parent | 94ee052509d5dc40d1b29d7c121ebf883084a216 (diff) | |
[RISCV] Add isAllocatable=0 to VCSR register class.
This avoids creating an unnecessary register pressure set.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D156196
Diffstat (limited to 'llvm/lib/TextAPI/TextAPIError.cpp')
0 files changed, 0 insertions, 0 deletions
