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| author | Peter Collingbourne <peter@pcc.me.uk> | 2025-07-18 13:26:00 -0700 |
|---|---|---|
| committer | Peter Collingbourne <peter@pcc.me.uk> | 2025-07-18 13:26:00 -0700 |
| commit | 9bf3524731070cadc6175707314f3b6ca37190d5 (patch) | |
| tree | 86dcab7604336b01ae938fe81062c29ff69efba8 /llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | |
| parent | 3a84c15cc13b6daf8e812592898ab6c7f19091a9 (diff) | |
| parent | 4f43f0606c3d7e1ce6d069583b5e59f036e112ce (diff) | |
Created using spr 1.3.6-beta.1
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 2723229859a5..64f9e3eb8d86 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2806,7 +2806,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, CASE_OPERAND_UIMM(7) CASE_OPERAND_UIMM(8) CASE_OPERAND_UIMM(9) - CASE_OPERAND_UIMM(10) + CASE_OPERAND_UIMM(10) CASE_OPERAND_UIMM(12) CASE_OPERAND_UIMM(16) CASE_OPERAND_UIMM(20) @@ -2823,6 +2823,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_UIMM5_NONZERO: Ok = isUInt<5>(Imm) && (Imm != 0); break; + case RISCVOp::OPERAND_UIMM5_GT3: + Ok = isUInt<5>(Imm) && (Imm > 3); + break; case RISCVOp::OPERAND_UIMM5_PLUS1: Ok = (isUInt<5>(Imm) && (Imm != 0)) || (Imm == 32); break; @@ -4809,6 +4812,8 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) { return true; if (RHS.isImm() && RHS.getImm() == RISCV::VLMaxSentinel) return true; + if (LHS.isImm() && LHS.getImm() == 0) + return true; if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel) return false; if (!LHS.isImm() || !RHS.isImm()) |