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authorMingming Liu <mingmingl@google.com>2025-09-10 15:25:31 -0700
committerGitHub <noreply@github.com>2025-09-10 15:25:31 -0700
commit1417dafa1db9cb1b2b09438aa9f53ea5ab6e36e2 (patch)
tree57f4b1f313c8cf74eed8819870f39c36ea263c68 /llvm/lib/Target/PowerPC
parent898b813bc8a6d0276bf0f4769f5f2f64b34e632d (diff)
parentb8cefcb601ddaa18482555c4ff363c01a270c2fe (diff)
Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/CMakeLists.txt2
-rw-r--r--llvm/lib/Target/PowerPC/PPC.h4
-rw-r--r--llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp12
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp44
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.h5
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstr64Bit.td52
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrAltivec.td15
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrFormats.td948
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrFuture.td190
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td809
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.cpp47
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.h4
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td98
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrMMA.td108
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrP10.td479
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrSPE.td54
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrVSX.td72
-rw-r--r--llvm/lib/Target/PowerPC/PPCSubtarget.cpp21
-rw-r--r--llvm/lib/Target/PowerPC/PPCSubtarget.h16
-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetMachine.cpp4
-rw-r--r--llvm/lib/Target/PowerPC/PPCVSXCopy.cpp159
-rw-r--r--llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp182
-rw-r--r--llvm/lib/Target/PowerPC/README_P9.txt18
23 files changed, 1805 insertions, 1538 deletions
diff --git a/llvm/lib/Target/PowerPC/CMakeLists.txt b/llvm/lib/Target/PowerPC/CMakeLists.txt
index 1e39f01fd7aa..2182039e0eef 100644
--- a/llvm/lib/Target/PowerPC/CMakeLists.txt
+++ b/llvm/lib/Target/PowerPC/CMakeLists.txt
@@ -49,7 +49,7 @@ add_llvm_target(PowerPCCodeGen
PPCTargetTransformInfo.cpp
PPCTOCRegDeps.cpp
PPCTLSDynamicCall.cpp
- PPCVSXCopy.cpp
+ PPCVSXWACCCopy.cpp
PPCReduceCRLogicals.cpp
PPCVSXFMAMutate.cpp
PPCVSXSwapRemoval.cpp
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index 124dac458431..a7cd5cde16b4 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -39,7 +39,7 @@ class ModulePass;
FunctionPass *createPPCLoopInstrFormPrepPass(PPCTargetMachine &TM);
FunctionPass *createPPCTOCRegDepsPass();
FunctionPass *createPPCEarlyReturnPass();
- FunctionPass *createPPCVSXCopyPass();
+ FunctionPass *createPPCVSXWACCCopyPass();
FunctionPass *createPPCVSXFMAMutatePass();
FunctionPass *createPPCVSXSwapRemovalPass();
FunctionPass *createPPCReduceCRLogicalsPass();
@@ -64,7 +64,7 @@ class ModulePass;
void initializePPCLoopInstrFormPrepPass(PassRegistry&);
void initializePPCTOCRegDepsPass(PassRegistry&);
void initializePPCEarlyReturnPass(PassRegistry&);
- void initializePPCVSXCopyPass(PassRegistry&);
+ void initializePPCVSXWACCCopyPass(PassRegistry &);
void initializePPCVSXFMAMutatePass(PassRegistry&);
void initializePPCVSXSwapRemovalPass(PassRegistry&);
void initializePPCReduceCRLogicalsPass(PassRegistry&);
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 2ab2c147be0e..023fd147535e 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -920,10 +920,6 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
assert(!Subtarget->isAIXABI() &&
"AIX does not support patchable function entry!");
- // PATCHABLE_FUNCTION_ENTER on little endian is for XRAY support which is
- // handled in PPCLinuxAsmPrinter.
- if (MAI->isLittleEndian())
- return;
const Function &F = MF->getFunction();
unsigned Num = 0;
(void)F.getFnAttribute("patchable-function-entry")
@@ -1789,7 +1785,13 @@ void PPCLinuxAsmPrinter::emitInstruction(const MachineInstr *MI) {
// Update compiler-rt/lib/xray/xray_powerpc64.cc accordingly when number
// of instructions change.
// XRAY is only supported on PPC Linux little endian.
- if (!MAI->isLittleEndian())
+ const Function &F = MF->getFunction();
+ unsigned Num = 0;
+ (void)F.getFnAttribute("patchable-function-entry")
+ .getValueAsString()
+ .getAsInteger(10, Num);
+
+ if (!MAI->isLittleEndian() || Num)
break;
MCSymbol *BeginOfSled = OutContext.createTempSymbol();
MCSymbol *EndOfSled = OutContext.createTempSymbol();
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 7022e9e9dae9..fa104e4f69d7 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1693,6 +1693,8 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
case PPCISD::XXPERM:
return "PPCISD::XXPERM";
case PPCISD::VECSHL: return "PPCISD::VECSHL";
+ case PPCISD::VSRQ:
+ return "PPCISD::VSRQ";
case PPCISD::CMPB: return "PPCISD::CMPB";
case PPCISD::Hi: return "PPCISD::Hi";
case PPCISD::Lo: return "PPCISD::Lo";
@@ -2696,7 +2698,7 @@ bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
if (!isa<ConstantSDNode>(N))
return false;
- Imm = (int64_t)cast<ConstantSDNode>(N)->getSExtValue();
+ Imm = cast<ConstantSDNode>(N)->getSExtValue();
return isInt<34>(Imm);
}
bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
@@ -11274,6 +11276,24 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getMergeValues(RetOps, dl);
}
+ case Intrinsic::ppc_mma_build_dmr: {
+ SmallVector<SDValue, 8> Pairs;
+ SmallVector<SDValue, 8> Chains;
+ for (int i = 1; i < 9; i += 2) {
+ SDValue Hi = Op.getOperand(i);
+ SDValue Lo = Op.getOperand(i + 1);
+ if (Hi->getOpcode() == ISD::LOAD)
+ Chains.push_back(Hi.getValue(1));
+ if (Lo->getOpcode() == ISD::LOAD)
+ Chains.push_back(Lo.getValue(1));
+ Pairs.push_back(
+ DAG.getNode(PPCISD::PAIR_BUILD, dl, MVT::v256i1, {Hi, Lo}));
+ }
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
+ SDValue Value = DMFInsert1024(Pairs, SDLoc(Op), DAG);
+ return DAG.getMergeValues({Value, TF}, dl);
+ }
+
case Intrinsic::ppc_mma_dmxxextfdmr512: {
assert(Subtarget.isISAFuture() && "dmxxextfdmr512 requires ISA Future");
auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(2));
@@ -11610,6 +11630,10 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
Op.getOperand(0)),
0);
}
+ case Intrinsic::ppc_mma_disassemble_dmr: {
+ return DAG.getStore(DAG.getEntryNode(), DL, Op.getOperand(ArgStart + 2),
+ Op.getOperand(ArgStart + 1), MachinePointerInfo());
+ }
default:
break;
}
@@ -12099,6 +12123,24 @@ SDValue PPCTargetLowering::LowerDMFVectorLoad(SDValue Op,
return DAG.getMergeValues({DmrPValue, TF}, dl);
}
+SDValue PPCTargetLowering::DMFInsert1024(const SmallVectorImpl<SDValue> &Pairs,
+ const SDLoc &dl,
+ SelectionDAG &DAG) const {
+ SDValue Lo(DAG.getMachineNode(PPC::DMXXINSTDMR512, dl, MVT::v512i1, Pairs[0],
+ Pairs[1]),
+ 0);
+ SDValue LoSub = DAG.getTargetConstant(PPC::sub_wacc_lo, dl, MVT::i32);
+ SDValue Hi(DAG.getMachineNode(PPC::DMXXINSTDMR512_HI, dl, MVT::v512i1,
+ Pairs[2], Pairs[3]),
+ 0);
+ SDValue HiSub = DAG.getTargetConstant(PPC::sub_wacc_hi, dl, MVT::i32);
+ SDValue RC = DAG.getTargetConstant(PPC::DMRRCRegClassID, dl, MVT::i32);
+
+ return SDValue(DAG.getMachineNode(PPC::REG_SEQUENCE, dl, MVT::v1024i1,
+ {RC, Lo, LoSub, Hi, HiSub}),
+ 0);
+}
+
SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
SelectionDAG &DAG) const {
SDLoc dl(Op);
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 559d58309692..669430550f4e 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -498,6 +498,9 @@ namespace llvm {
/// SETBCR - The ISA 3.1 (P10) SETBCR instruction.
SETBCR,
+ /// VSRQ - The ISA 3.1 (P10) Vector Shift right quadword instruction
+ VSRQ,
+
// NOTE: The nodes below may require PC-Rel specific patterns if the
// address could be PC-Relative. When adding new nodes below, consider
// whether or not the address can be PC-Relative and add the corresponding
@@ -1345,6 +1348,8 @@ namespace llvm {
SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDMFVectorLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDMFVectorStore(SDValue Op, SelectionDAG &DAG) const;
+ SDValue DMFInsert1024(const SmallVectorImpl<SDValue> &Pairs,
+ const SDLoc &dl, SelectionDAG &DAG) const;
SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
CallingConv::ID CallConv, bool isVarArg,
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index fd2084398c85..269d30318bca 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1095,8 +1095,7 @@ let hasSideEffects = 0 in {
defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA),
(ins g8rc:$RAi, g8rc:$RS, u6imm:$SH, u6imm:$MBE),
"rldimi", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI,
- []>, isPPC64, RegConstraint<"$RAi = $RA">,
- NoEncode<"$RAi">;
+ []>, isPPC64, RegConstraint<"$RAi = $RA">;
// Rotate instructions.
defm RLDCL : MDSForm_1r<30, 8,
@@ -1156,7 +1155,7 @@ defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA),
(ins g8rc:$RAi, g8rc:$RS, u5imm:$SH, u5imm:$MB,
u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",
IIC_IntRotate, []>, PPC970_DGroup_Cracked,
- RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">;
+ RegConstraint<"$RAi = $RA">;
let isSelect = 1 in
def ISEL8 : AForm_4<31, 15,
@@ -1313,21 +1312,18 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memri $D, $RA):$addr),
"lhau $RST, $addr", IIC_LdStLHAU,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
// NO LWAU!
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lhaux $RST, $addr", IIC_LdStLHAUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lwaux $RST, $addr", IIC_LdStLHAUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">, isPPC64;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64;
}
}
@@ -1366,34 +1362,28 @@ let mayLoad = 1, hasSideEffects = 0 in {
def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memri $D, $RA):$addr),
"lbzu $RST, $addr", IIC_LdStLoadUpd,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memri $D, $RA):$addr),
"lhzu $RST, $addr", IIC_LdStLoadUpd,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memri $D, $RA):$addr),
"lwzu $RST, $addr", IIC_LdStLoadUpd,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lbzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lhzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lwzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
}
}
} // Interpretation64Bit
@@ -1445,14 +1435,12 @@ let mayLoad = 1, hasSideEffects = 0 in {
def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrix $D, $RA):$addr),
"ldu $RST, $addr", IIC_LdStLDU,
- []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64;
def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"ldux $RST, $addr", IIC_LdStLDUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">, isPPC64;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64;
}
let mayLoad = 1, hasNoSchedulingInfo = 1 in {
@@ -1718,45 +1706,41 @@ let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
"stbu $RST, $addr", IIC_LdStSTU, []>,
- RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$addr.reg = $ea_res">;
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
"sthu $RST, $addr", IIC_LdStSTU, []>,
- RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$addr.reg = $ea_res">;
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr),
"stwu $RST, $addr", IIC_LdStSTU, []>,
- RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$addr.reg = $ea_res">;
def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stbux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$RST, (memrr $RA, $RB):$addr),
"sthux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stwux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
} // Interpretation64Bit
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$RST, (memrix $D, $RA):$addr),
"stdu $RST, $addr", IIC_LdStSTU, []>,
- RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">,
+ RegConstraint<"$addr.reg = $ea_res">,
isPPC64;
def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res),
(ins g8rc:$RST, (memrr $RA, $RB):$addr),
"stdux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked, isPPC64;
}
@@ -2000,7 +1984,7 @@ def : Pat<(int_ppc_darnraw), (DARN 2)>;
class X_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
InstrItinClass itin, list<dag> pattern>
- : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB, u1imm:$L),
+ : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$RA, ty:$RB),
!strconcat(opc, " $RA, $RB"), itin, pattern>{
let L = 1;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 79fe12e8e4b4..97d5e2896323 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -261,6 +261,13 @@ def immEQOneV : PatLeaf<(build_vector), [{
return C->isOne();
return false;
}]>;
+
+def VSRVSRO : PatFrag<(ops node:$input, node:$shift),
+ (int_ppc_altivec_vsr
+ (int_ppc_altivec_vsro node:$input, node:$shift),
+ node:$shift),
+ [{ return N->getOperand(1).hasOneUse(); }]>;
+
//===----------------------------------------------------------------------===//
// Helpers for defining instructions that directly correspond to intrinsics.
@@ -1471,13 +1478,13 @@ def VINSERTB : VXForm_1<781, (outs vrrc:$VD),
"vinsertb $VD, $VB, $VA", IIC_VecGeneral,
[(set v16i8:$VD, (PPCvecinsert v16i8:$VDi, v16i8:$VB,
imm32SExt16:$VA))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VINSERTH : VXForm_1<845, (outs vrrc:$VD),
(ins vrrc:$VDi, u4imm:$VA, vrrc:$VB),
"vinserth $VD, $VB, $VA", IIC_VecGeneral,
[(set v8i16:$VD, (PPCvecinsert v8i16:$VDi, v8i16:$VB,
imm32SExt16:$VA))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
@@ -1569,7 +1576,7 @@ def VRLWMI : VXForm_1<133, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),
[(set v4i32:$VD,
(int_ppc_altivec_vrlwmi v4i32:$VA, v4i32:$VB,
v4i32:$VDi))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm",
[(set v2i64:$VD,
(int_ppc_altivec_vrldnm v2i64:$VA,
@@ -1579,7 +1586,7 @@ def VRLDMI : VXForm_1<197, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi),
[(set v2i64:$VD,
(int_ppc_altivec_vrldmi v2i64:$VA, v2i64:$VB,
v2i64:$VDi))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
// Vector Shift Left/Right
def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index b4b475b470a5..fba1c6609dba 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -18,7 +18,7 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
bit PPC64 = 0; // Default value, override with isPPC64
let Namespace = "PPC";
- let Inst{0-5} = opcode;
+ let Inst{0...5} = opcode;
let OutOperandList = OOL;
let InOperandList = IOL;
let AsmString = asmstr;
@@ -34,7 +34,7 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
let TSFlags{0} = PPC970_First;
let TSFlags{1} = PPC970_Single;
let TSFlags{2} = PPC970_Cracked;
- let TSFlags{5-3} = PPC970_Unit;
+ let TSFlags{5...3} = PPC970_Unit;
// Indicate that this instruction is of type X-Form Load or Store
bits<1> XFormMemOp = 0;
@@ -99,8 +99,8 @@ class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
bit PPC64 = 0; // Default value, override with isPPC64
let Namespace = "PPC";
- let Inst{0-5} = opcode1;
- let Inst{32-37} = opcode2;
+ let Inst{0...5} = opcode1;
+ let Inst{32...37} = opcode2;
let OutOperandList = OOL;
let InOperandList = IOL;
let AsmString = asmstr;
@@ -116,7 +116,7 @@ class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
let TSFlags{0} = PPC970_First;
let TSFlags{1} = PPC970_Single;
let TSFlags{2} = PPC970_Cracked;
- let TSFlags{5-3} = PPC970_Unit;
+ let TSFlags{5...3} = PPC970_Unit;
// Fields used for relation models.
string BaseName = "";
@@ -135,7 +135,7 @@ class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
bits<24> LI;
- let Inst{6-29} = LI;
+ let Inst{6...29} = LI;
let Inst{30} = aa;
let Inst{31} = lk;
}
@@ -148,12 +148,12 @@ class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
bits<14> BD;
bits<5> BI;
- let BI{0-1} = BIBO{5-6};
- let BI{2-4} = CR{0-2};
+ let BI{0...1} = BIBO{5...6};
+ let BI{2...4} = CR{0...2};
- let Inst{6-10} = BIBO{4-0};
- let Inst{11-15} = BI;
- let Inst{16-29} = BD;
+ let Inst{6...10} = BIBO{4...0};
+ let Inst{11...15} = BI;
+ let Inst{16...29} = BD;
let Inst{30} = aa;
let Inst{31} = lk;
}
@@ -161,8 +161,8 @@ class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
string asmstr>
: BForm<opcode, aa, lk, OOL, IOL, asmstr> {
- let BIBO{4-0} = bo;
- let BIBO{6-5} = 0;
+ let BIBO{4...0} = bo;
+ let BIBO{6...5} = 0;
let CR = 0;
}
@@ -171,9 +171,9 @@ class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
: I<opcode, OOL, IOL, asmstr, IIC_BrB> {
bits<14> BD;
- let Inst{6-10} = bo;
- let Inst{11-15} = bi;
- let Inst{16-29} = BD;
+ let Inst{6...10} = bo;
+ let Inst{11...15} = bi;
+ let Inst{16...29} = BD;
let Inst{30} = aa;
let Inst{31} = lk;
}
@@ -185,9 +185,9 @@ class BForm_3<bits<6> opcode, bit aa, bit lk,
bits<5> BI;
bits<14> BD;
- let Inst{6-10} = BO;
- let Inst{11-15} = BI;
- let Inst{16-29} = BD;
+ let Inst{6...10} = BO;
+ let Inst{11...15} = BI;
+ let Inst{16...29} = BD;
let Inst{30} = aa;
let Inst{31} = lk;
}
@@ -200,10 +200,10 @@ class BForm_3_at<bits<6> opcode, bit aa, bit lk,
bits<5> BI;
bits<14> BD;
- let Inst{6-8} = BO{4-2};
- let Inst{9-10} = at;
- let Inst{11-15} = BI;
- let Inst{16-29} = BD;
+ let Inst{6...8} = BO{4...2};
+ let Inst{9...10} = at;
+ let Inst{11...15} = BI;
+ let Inst{16...29} = BD;
let Inst{30} = aa;
let Inst{31} = lk;
}
@@ -215,9 +215,9 @@ BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
bits<5> BI;
bits<14> BD;
- let Inst{6-10} = bo;
- let Inst{11-15} = BI;
- let Inst{16-29} = BD;
+ let Inst{6...10} = bo;
+ let Inst{11...15} = BI;
+ let Inst{16...29} = BD;
let Inst{30} = aa;
let Inst{31} = lk;
}
@@ -231,7 +231,7 @@ class SCForm<bits<6> opcode, bits<1> xo1, bits<1> xo2,
let Pattern = pattern;
- let Inst{20-26} = LEV;
+ let Inst{20...26} = LEV;
let Inst{30} = xo1;
let Inst{31} = xo2;
}
@@ -246,9 +246,9 @@ class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RST;
- let Inst{11-15} = RA;
- let Inst{16-31} = D;
+ let Inst{6...10} = RST;
+ let Inst{11...15} = RA;
+ let Inst{16...31} = D;
}
class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -273,9 +273,9 @@ class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RST;
- let Inst{11-15} = 0;
- let Inst{16-31} = D;
+ let Inst{6...10} = RST;
+ let Inst{11...15} = 0;
+ let Inst{16...31} = D;
}
class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -287,9 +287,9 @@ class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RST;
- let Inst{11-15} = RA;
- let Inst{16-31} = D;
+ let Inst{6...10} = RST;
+ let Inst{11...15} = RA;
+ let Inst{16...31} = D;
}
class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -321,13 +321,13 @@ class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
let Pattern = pattern;
bits<24> LI;
- let Inst{6-29} = LI;
+ let Inst{6...29} = LI;
let Inst{30} = aa;
let Inst{31} = lk;
- let Inst{38-42} = RST;
- let Inst{43-47} = RA;
- let Inst{48-63} = D;
+ let Inst{38...42} = RST;
+ let Inst{43...47} = RA;
+ let Inst{48...63} = D;
}
// This is used to emit BL8+NOP.
@@ -349,11 +349,11 @@ class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
bits<5> RA;
bits<16> D;
- let Inst{6-8} = BF;
+ let Inst{6...8} = BF;
let Inst{9} = 0;
let Inst{10} = L;
- let Inst{11-15} = RA;
- let Inst{16-31} = D;
+ let Inst{11...15} = RA;
+ let Inst{16...31} = D;
}
class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -383,10 +383,10 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RST;
- let Inst{11-15} = RA;
- let Inst{16-29} = D;
- let Inst{30-31} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...15} = RA;
+ let Inst{16...29} = D;
+ let Inst{30...31} = xo;
}
// ISA V3.0B 1.6.6 DX-Form
@@ -398,10 +398,10 @@ class DXForm<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = D{5-1}; // d1
- let Inst{16-25} = D{15-6}; // d0
- let Inst{26-30} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = D{5...1}; // d1
+ let Inst{16...25} = D{15...6}; // d0
+ let Inst{26...30} = xo;
let Inst{31} = D{0}; // d2
}
@@ -415,11 +415,11 @@ class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = RA;
- let Inst{16-27} = DQ;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = RA;
+ let Inst{16...27} = DQ;
let Inst{28} = XT{5};
- let Inst{29-31} = xo;
+ let Inst{29...31} = xo;
}
class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
@@ -431,10 +431,10 @@ class DQForm_RTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
bits<12> DQ;
let Pattern = pattern;
- let Inst{6-10} = RTp{4-0};
- let Inst{11-15} = RA;
- let Inst{16-27} = DQ;
- let Inst{28-31} = xo;
+ let Inst{6...10} = RTp{4...0};
+ let Inst{11...15} = RA;
+ let Inst{16...27} = DQ;
+ let Inst{28...31} = xo;
}
// 1.7.6 X-Form
@@ -449,10 +449,10 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asms
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RST;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -475,7 +475,7 @@ class XForm_tlbilx<bits<10> xo, dag OOL, dag IOL, string asmstr,
class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> {
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
}
// This is the same as XForm_base_r3xo, but the first two operands are swapped
@@ -490,10 +490,10 @@ class XForm_base_r3xo_swapped
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RST;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -528,10 +528,10 @@ class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RST;
- let Inst{11-15} = RA;
+ let Inst{6...10} = RST;
+ let Inst{11...15} = RA;
let Inst{20} = WS;
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -570,12 +570,12 @@ class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RA;
bits<5> RB;
- let Inst{6-8} = BF;
+ let Inst{6...8} = BF;
let Inst{9} = 0;
let Inst{10} = L;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -587,10 +587,10 @@ class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RB;
let Inst{6} = 0;
- let Inst{7-10} = CT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{7...10} = CT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -600,9 +600,9 @@ class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RS;
bits<4> SR;
- let Inst{6-10} = RS;
- let Inst{12-15} = SR;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RS;
+ let Inst{12...15} = SR;
+ let Inst{21...30} = xo;
}
class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
@@ -610,8 +610,8 @@ class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
: I<opcode, OOL, IOL, asmstr, itin> {
bits<5> MO;
- let Inst{6-10} = MO;
- let Inst{21-30} = xo;
+ let Inst{6...10} = MO;
+ let Inst{21...30} = xo;
}
class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
@@ -620,9 +620,9 @@ class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RS;
bits<5> RB;
- let Inst{6-10} = RS;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RS;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
}
class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
@@ -631,9 +631,9 @@ class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RS;
bits<1> L;
- let Inst{6-10} = RS;
+ let Inst{6...10} = RS;
let Inst{15} = L;
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
}
class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
@@ -649,11 +649,11 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RA;
bits<5> RB;
- let Inst{6-8} = BF;
- let Inst{9-10} = 0;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -673,10 +673,10 @@ class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = FRT;
- let Inst{11-15} = FRA;
- let Inst{16-20} = FRB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = FRT;
+ let Inst{11...15} = FRA;
+ let Inst{16...20} = FRB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -696,11 +696,11 @@ class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = FRT;
- let Inst{11-15} = FRA;
- let Inst{16-20} = FRB;
- let Inst{21-24} = tttt;
- let Inst{25-30} = xo;
+ let Inst{6...10} = FRT;
+ let Inst{11...15} = FRA;
+ let Inst{16...20} = FRB;
+ let Inst{21...24} = tttt;
+ let Inst{25...30} = xo;
let Inst{31} = 0;
}
@@ -708,10 +708,10 @@ class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
let Pattern = pattern;
- let Inst{6-10} = 31;
- let Inst{11-15} = 0;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...10} = 31;
+ let Inst{11...15} = 0;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -721,11 +721,11 @@ class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bits<2> L;
let Pattern = pattern;
- let Inst{6-8} = 0;
- let Inst{9-10} = L;
- let Inst{11-15} = 0;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...8} = 0;
+ let Inst{9...10} = L;
+ let Inst{11...15} = 0;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -736,12 +736,12 @@ class XForm_IMM2_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bits<2> PL;
let Pattern = pattern;
- let Inst{6-8} = 0;
- let Inst{9-10} = L;
- let Inst{11-13} = 0;
- let Inst{14-15} = PL;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...8} = 0;
+ let Inst{9...10} = L;
+ let Inst{11...13} = 0;
+ let Inst{14...15} = PL;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -752,12 +752,12 @@ class XForm_IMM3_IMM2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bits<2> SC;
let Pattern = pattern;
- let Inst{6-7} = 0;
- let Inst{8-10} = L;
- let Inst{11-13} = 0;
- let Inst{14-15} = SC;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...7} = 0;
+ let Inst{8...10} = L;
+ let Inst{11...13} = 0;
+ let Inst{14...15} = SC;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -803,9 +803,9 @@ class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RST;
- let Inst{11-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
@@ -816,9 +816,9 @@ class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = FM;
- let Inst{11-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...10} = FM;
+ let Inst{11...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -828,11 +828,11 @@ class XForm_44<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RT;
bits<3> BFA;
- let Inst{6-10} = RT;
- let Inst{11-13} = BFA;
- let Inst{14-15} = 0;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...13} = BFA;
+ let Inst{14...15} = 0;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -842,11 +842,11 @@ class XForm_45<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RT;
bits<2> L;
- let Inst{6-10} = RT;
- let Inst{11-13} = 0;
- let Inst{14-15} = L;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...13} = 0;
+ let Inst{14...15} = L;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -856,11 +856,11 @@ class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let Pattern = pattern;
- let Inst{6-10} = RST;
- let Inst{11-12} = xo1;
- let Inst{13-15} = xo2;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...12} = xo1;
+ let Inst{13...15} = xo2;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -871,11 +871,11 @@ class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
let Pattern = pattern;
bits<5> FRB;
- let Inst{6-10} = RST;
- let Inst{11-12} = xo1;
- let Inst{13-15} = xo2;
- let Inst{16-20} = FRB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...12} = xo1;
+ let Inst{13...15} = xo2;
+ let Inst{16...20} = FRB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -886,12 +886,12 @@ class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
let Pattern = pattern;
bits<3> DRM;
- let Inst{6-10} = RST;
- let Inst{11-12} = xo1;
- let Inst{13-15} = xo2;
- let Inst{16-17} = 0;
- let Inst{18-20} = DRM;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...12} = xo1;
+ let Inst{13...15} = xo2;
+ let Inst{16...17} = 0;
+ let Inst{18...20} = DRM;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -902,12 +902,12 @@ class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
let Pattern = pattern;
bits<2> RM;
- let Inst{6-10} = RST;
- let Inst{11-12} = xo1;
- let Inst{13-15} = xo2;
- let Inst{16-18} = 0;
- let Inst{19-20} = RM;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RST;
+ let Inst{11...12} = xo1;
+ let Inst{13...15} = xo2;
+ let Inst{16...18} = 0;
+ let Inst{19...20} = RM;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -934,10 +934,10 @@ class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bit RC = 1;
- let Inst{6-9} = 0;
+ let Inst{6...9} = 0;
let Inst{10} = R;
- let Inst{11-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{11...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -949,8 +949,8 @@ class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bit RC = 1;
let Inst{6} = A;
- let Inst{7-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{7...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -961,10 +961,10 @@ class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{7-9} = 0;
+ let Inst{7...9} = 0;
let Inst{10} = L;
- let Inst{11-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{11...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -975,9 +975,9 @@ class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0;
- let Inst{6-8} = BF;
- let Inst{9-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -992,12 +992,12 @@ class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = BF;
+ let Inst{6...8} = BF;
let Inst{9} = 0;
let Inst{10} = L;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1011,11 +1011,11 @@ class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = BF;
- let Inst{9-10} = 0;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1035,10 +1035,10 @@ class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = BF;
- let Inst{9-15} = DCMX;
- let Inst{16-20} = VB;
- let Inst{21-30} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...15} = DCMX;
+ let Inst{16...20} = VB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1050,10 +1050,10 @@ class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-12} = 0;
- let Inst{13-20} = IMM8;
- let Inst{21-30} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...12} = 0;
+ let Inst{13...20} = IMM8;
+ let Inst{21...30} = xo;
let Inst{31} = XT{5};
}
@@ -1092,10 +1092,10 @@ class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = XT{5};
}
@@ -1117,10 +1117,10 @@ class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = 0;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = 0;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = XT{5};
}
@@ -1133,10 +1133,10 @@ class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-8} = CR;
- let Inst{9-15} = 0;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...8} = CR;
+ let Inst{9...15} = 0;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = 0;
}
@@ -1150,11 +1150,11 @@ class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-13} = 0;
- let Inst{14-15} = D;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...13} = 0;
+ let Inst{14...15} = D;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = XT{5};
}
@@ -1168,10 +1168,10 @@ class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = UIM5;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = UIM5;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = XT{5};
}
@@ -1185,10 +1185,10 @@ class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = xo2;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = xo2;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = 0;
}
@@ -1202,10 +1202,10 @@ class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = xo2;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = xo2;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = XT{5};
}
@@ -1219,10 +1219,10 @@ class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = BF;
- let Inst{9-15} = DCMX;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...15} = DCMX;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = 0;
}
@@ -1237,12 +1237,12 @@ class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = DCMX{4-0};
- let Inst{16-20} = XB{4-0};
- let Inst{21-24} = xo1;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = DCMX{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...24} = xo1;
let Inst{25} = DCMX{6};
- let Inst{26-28} = xo2;
+ let Inst{26...28} = xo2;
let Inst{29} = DCMX{5};
let Inst{30} = XB{5};
let Inst{31} = XT{5};
@@ -1257,10 +1257,10 @@ class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = D{4-0}; // D
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = D{4...0}; // D
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = D{5}; // DX
}
@@ -1273,11 +1273,11 @@ class XForm_BF3_UIM6_FRB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = BF;
+ let Inst{6...8} = BF;
let Inst{9} = 0;
- let Inst{10-15} = UIM;
- let Inst{16-20} = FRB;
- let Inst{21-30} = xo;
+ let Inst{10...15} = UIM;
+ let Inst{16...20} = FRB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1292,11 +1292,11 @@ class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asms
bit RC = 0; // set by isRecordForm
- let Inst{6 - 10} = FRT;
- let Inst{11 - 12} = SP;
- let Inst{13 - 15} = 0;
- let Inst{16 - 20} = FRB;
- let Inst{21 - 30} = xo;
+ let Inst{6...10} = FRT;
+ let Inst{11...12} = SP;
+ let Inst{13...15} = 0;
+ let Inst{16...20} = FRB;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -1311,11 +1311,11 @@ class XForm_S1_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bit RC = 0; // set by isRecordForm
- let Inst{6 - 10} = FRT;
+ let Inst{6...10} = FRT;
let Inst{11} = S;
- let Inst{12 - 15} = 0;
- let Inst{16 - 20} = FRB;
- let Inst{21 - 30} = xo;
+ let Inst{12...15} = 0;
+ let Inst{16...20} = FRB;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -1328,10 +1328,10 @@ class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = XA{4-0};
- let Inst{16-20} = XB{4-0};
- let Inst{21-28} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...28} = xo;
let Inst{29} = XA{5};
let Inst{30} = XB{5};
let Inst{31} = XT{5};
@@ -1353,11 +1353,11 @@ class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-8} = CR;
- let Inst{9-10} = 0;
- let Inst{11-15} = XA{4-0};
- let Inst{16-20} = XB{4-0};
- let Inst{21-28} = xo;
+ let Inst{6...8} = CR;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...28} = xo;
let Inst{29} = XA{5};
let Inst{30} = XB{5};
let Inst{31} = 0;
@@ -1373,12 +1373,12 @@ class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = XA{4-0};
- let Inst{16-20} = XB{4-0};
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
let Inst{21} = 0;
- let Inst{22-23} = D;
- let Inst{24-28} = xo;
+ let Inst{22...23} = D;
+ let Inst{24...28} = xo;
let Inst{29} = XA{5};
let Inst{30} = XB{5};
let Inst{31} = XT{5};
@@ -1395,11 +1395,11 @@ class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = XA{4-0};
- let Inst{16-20} = XB{4-0};
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
let Inst{21} = RC;
- let Inst{22-28} = xo;
+ let Inst{22...28} = xo;
let Inst{29} = XA{5};
let Inst{30} = XB{5};
let Inst{31} = XT{5};
@@ -1415,11 +1415,11 @@ class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = XA{4-0};
- let Inst{16-20} = XB{4-0};
- let Inst{21-25} = XC{4-0};
- let Inst{26-27} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...25} = XC{4...0};
+ let Inst{26...27} = xo;
let Inst{28} = XC{5};
let Inst{29} = XA{5};
let Inst{30} = XB{5};
@@ -1435,10 +1435,10 @@ class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = immfield;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = immfield;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1451,10 +1451,10 @@ class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = TH;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = TH;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1469,11 +1469,11 @@ class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
let Inst{6} = T;
- let Inst{7-8} = 0;
- let Inst{9-10} = STRM;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{7...8} = 0;
+ let Inst{9...10} = STRM;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1487,10 +1487,10 @@ class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = CRD;
- let Inst{11-15} = CRA;
- let Inst{16-20} = CRB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = CRD;
+ let Inst{11...15} = CRA;
+ let Inst{16...20} = CRB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1527,10 +1527,10 @@ class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = CRD;
- let Inst{11-15} = CRD;
- let Inst{16-20} = CRD;
- let Inst{21-30} = xo;
+ let Inst{6...10} = CRD;
+ let Inst{11...15} = CRD;
+ let Inst{16...20} = CRD;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1543,11 +1543,11 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asm
let Pattern = pattern;
- let Inst{6-10} = BO;
- let Inst{11-15} = BI;
- let Inst{16-18} = 0;
- let Inst{19-20} = BH;
- let Inst{21-30} = xo;
+ let Inst{6...10} = BO;
+ let Inst{11...15} = BI;
+ let Inst{16...18} = 0;
+ let Inst{19...20} = BH;
+ let Inst{21...30} = xo;
let Inst{31} = lk;
}
@@ -1557,9 +1557,9 @@ class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
bits<3> CR;
- let BO = BIBO{4-0};
- let BI{0-1} = BIBO{5-6};
- let BI{2-4} = CR{0-2};
+ let BO = BIBO{4...0};
+ let BI{0...1} = BIBO{5...6};
+ let BI{2...4} = CR{0...2};
let BH = 0;
}
@@ -1584,12 +1584,12 @@ class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<3> BF;
bits<3> BFA;
- let Inst{6-8} = BF;
- let Inst{9-10} = 0;
- let Inst{11-13} = BFA;
- let Inst{14-15} = 0;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...10} = 0;
+ let Inst{11...13} = BFA;
+ let Inst{14...15} = 0;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1602,13 +1602,13 @@ class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0;
- let Inst{6-8} = BF;
- let Inst{9-10} = 0;
- let Inst{11-14} = 0;
+ let Inst{6...8} = BF;
+ let Inst{9...10} = 0;
+ let Inst{11...14} = 0;
let Inst{15} = W;
- let Inst{16-19} = U;
+ let Inst{16...19} = U;
let Inst{20} = 0;
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -1619,9 +1619,9 @@ class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-19} = 0;
+ let Inst{6...19} = 0;
let Inst{20} = S;
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1640,17 +1640,17 @@ class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
let Pattern = pattern;
- let Inst{6-10} = BO;
- let Inst{11-15} = BI;
- let Inst{16-18} = 0;
- let Inst{19-20} = BH;
- let Inst{21-30} = xo1;
+ let Inst{6...10} = BO;
+ let Inst{11...15} = BI;
+ let Inst{16...18} = 0;
+ let Inst{19...20} = BH;
+ let Inst{21...30} = xo1;
let Inst{31} = lk;
- let Inst{38-42} = RST;
- let Inst{43-47} = RA;
- let Inst{48-61} = D;
- let Inst{62-63} = xo2;
+ let Inst{38...42} = RST;
+ let Inst{43...47} = RA;
+ let Inst{48...61} = D;
+ let Inst{62...63} = xo2;
}
class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
@@ -1677,16 +1677,16 @@ class XLForm_2_ext_and_DForm_1<bits<6> opcode1, bits<10> xo1, bits<5> bo,
let Pattern = pattern;
- let Inst{6-10} = bo;
- let Inst{11-15} = bi;
- let Inst{16-18} = 0;
- let Inst{19-20} = 0; // Unused (BH)
- let Inst{21-30} = xo1;
+ let Inst{6...10} = bo;
+ let Inst{11...15} = bi;
+ let Inst{16...18} = 0;
+ let Inst{19...20} = 0; // Unused (BH)
+ let Inst{21...30} = xo1;
let Inst{31} = lk;
- let Inst{38-42} = RST;
- let Inst{43-47} = RA;
- let Inst{48-63} = D;
+ let Inst{38...42} = RST;
+ let Inst{43...47} = RA;
+ let Inst{48...63} = D;
}
// 1.7.8 XFX-Form
@@ -1696,7 +1696,7 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RST;
bits<10> SPR;
- let Inst{6-10} = RST;
+ let Inst{6...10} = RST;
let Inst{11} = SPR{4};
let Inst{12} = SPR{3};
let Inst{13} = SPR{2};
@@ -1707,7 +1707,7 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{18} = SPR{7};
let Inst{19} = SPR{6};
let Inst{20} = SPR{5};
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1722,9 +1722,9 @@ class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
: I<opcode, OOL, IOL, asmstr, itin> {
bits<5> RT;
- let Inst{6-10} = RT;
- let Inst{11-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1735,9 +1735,9 @@ class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<10> imm;
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-20} = imm;
- let Inst{21-30} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...20} = imm;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1747,11 +1747,11 @@ class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<8> FXM;
bits<5> RST;
- let Inst{6-10} = RST;
+ let Inst{6...10} = RST;
let Inst{11} = 0;
- let Inst{12-19} = FXM;
+ let Inst{12...19} = FXM;
let Inst{20} = 0;
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1761,11 +1761,11 @@ class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
bits<5> RST;
bits<8> FXM;
- let Inst{6-10} = RST;
+ let Inst{6...10} = RST;
let Inst{11} = 1;
- let Inst{12-19} = FXM;
+ let Inst{12...19} = FXM;
let Inst{20} = 0;
- let Inst{21-30} = xo;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -1782,10 +1782,10 @@ class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
let Inst{6} = 0;
- let Inst{7-14} = FM;
+ let Inst{7...14} = FM;
let Inst{15} = 0;
- let Inst{16-20} = RT;
- let Inst{21-30} = xo;
+ let Inst{16...20} = RT;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -1801,10 +1801,10 @@ class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
let Inst{6} = L;
- let Inst{7-14} = FLM;
+ let Inst{7...14} = FLM;
let Inst{15} = W;
- let Inst{16-20} = FRB;
- let Inst{21-30} = xo;
+ let Inst{16...20} = FRB;
+ let Inst{21...30} = xo;
let Inst{31} = RC;
}
@@ -1819,10 +1819,10 @@ class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
let Pattern = pattern;
- let Inst{6-10} = RS;
- let Inst{11-15} = RA;
- let Inst{16-20} = SH{4,3,2,1,0};
- let Inst{21-29} = xo;
+ let Inst{6...10} = RS;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = SH{4,3,2,1,0};
+ let Inst{21...29} = xo;
let Inst{30} = SH{5};
let Inst{31} = RC;
}
@@ -1839,11 +1839,11 @@ class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asms
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
let Inst{21} = oe;
- let Inst{22-30} = xo;
+ let Inst{22...30} = xo;
let Inst{31} = RC;
}
@@ -1866,11 +1866,11 @@ class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = FRT;
- let Inst{11-15} = FRA;
- let Inst{16-20} = FRB;
- let Inst{21-25} = FRC;
- let Inst{26-30} = xo;
+ let Inst{6...10} = FRT;
+ let Inst{11...15} = FRA;
+ let Inst{16...20} = FRB;
+ let Inst{21...25} = FRC;
+ let Inst{26...30} = xo;
let Inst{31} = RC;
}
@@ -1896,11 +1896,11 @@ class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-25} = COND;
- let Inst{26-30} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...25} = COND;
+ let Inst{26...30} = xo;
let Inst{31} = 0;
}
@@ -1918,11 +1918,11 @@ class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RS;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-25} = MB;
- let Inst{26-30} = ME;
+ let Inst{6...10} = RS;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...25} = MB;
+ let Inst{26...30} = ME;
let Inst{31} = RC;
}
@@ -1939,11 +1939,11 @@ class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RS;
- let Inst{11-15} = RA;
- let Inst{16-20} = SH;
- let Inst{21-25} = MB;
- let Inst{26-30} = ME;
+ let Inst{6...10} = RS;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = SH;
+ let Inst{21...25} = MB;
+ let Inst{26...30} = ME;
let Inst{31} = RC;
}
@@ -1960,11 +1960,11 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RS;
- let Inst{11-15} = RA;
- let Inst{16-20} = SH{4,3,2,1,0};
- let Inst{21-26} = MBE{4,3,2,1,0,5};
- let Inst{27-29} = xo;
+ let Inst{6...10} = RS;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = SH{4,3,2,1,0};
+ let Inst{21...26} = MBE{4,3,2,1,0,5};
+ let Inst{27...29} = xo;
let Inst{30} = SH{5};
let Inst{31} = RC;
}
@@ -1981,11 +1981,11 @@ class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RS;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-26} = MBE{4,3,2,1,0,5};
- let Inst{27-30} = xo;
+ let Inst{6...10} = RS;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...26} = MBE{4,3,2,1,0,5};
+ let Inst{27...30} = xo;
let Inst{31} = RC;
}
@@ -2003,11 +2003,11 @@ class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-25} = RC;
- let Inst{26-31} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...25} = RC;
+ let Inst{26...31} = xo;
}
// VAForm_1a - DABC ordering.
@@ -2021,11 +2021,11 @@ class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-25} = RC;
- let Inst{26-31} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...25} = RC;
+ let Inst{26...31} = xo;
}
class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
@@ -2038,12 +2038,12 @@ class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
let Inst{21} = 0;
- let Inst{22-25} = SH;
- let Inst{26-31} = xo;
+ let Inst{22...25} = SH;
+ let Inst{26...31} = xo;
}
// E-2 VX-Form
@@ -2056,10 +2056,10 @@ class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = VA;
- let Inst{16-20} = VB;
- let Inst{21-31} = xo;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = VA;
+ let Inst{16...20} = VB;
+ let Inst{21...31} = xo;
}
class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
@@ -2078,10 +2078,10 @@ class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = 0;
- let Inst{16-20} = VB;
- let Inst{21-31} = xo;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = 0;
+ let Inst{16...20} = VB;
+ let Inst{21...31} = xo;
}
class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
@@ -2092,10 +2092,10 @@ class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = IMM;
- let Inst{16-20} = 0;
- let Inst{21-31} = xo;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = IMM;
+ let Inst{16...20} = 0;
+ let Inst{21...31} = xo;
}
/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
@@ -2106,10 +2106,10 @@ class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = 0;
- let Inst{16-20} = 0;
- let Inst{21-31} = xo;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = 0;
+ let Inst{16...20} = 0;
+ let Inst{21...31} = xo;
}
/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
@@ -2120,10 +2120,10 @@ class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = 0;
- let Inst{11-15} = 0;
- let Inst{16-20} = VB;
- let Inst{21-31} = xo;
+ let Inst{6...10} = 0;
+ let Inst{11...15} = 0;
+ let Inst{16...20} = VB;
+ let Inst{21...31} = xo;
}
// e.g. [PO VRT EO VRB XO]
@@ -2135,10 +2135,10 @@ class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = eo;
- let Inst{16-20} = VB;
- let Inst{21-31} = xo;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = eo;
+ let Inst{16...20} = VB;
+ let Inst{21...31} = xo;
}
/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX"
@@ -2152,11 +2152,11 @@ class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = VA;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = VA;
let Inst{16} = ST;
- let Inst{17-20} = SIX;
- let Inst{21-31} = xo;
+ let Inst{17...20} = SIX;
+ let Inst{21...31} = xo;
}
/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox"
@@ -2168,10 +2168,10 @@ class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = VA;
- let Inst{16-20} = 0;
- let Inst{21-31} = xo;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = VA;
+ let Inst{16...20} = 0;
+ let Inst{21...31} = xo;
}
// E-4 VXR-Form
@@ -2185,11 +2185,11 @@ class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = VA;
- let Inst{16-20} = VB;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = VA;
+ let Inst{16...20} = VB;
let Inst{21} = RC;
- let Inst{22-31} = xo;
+ let Inst{22...31} = xo;
}
// VX-Form: [PO VRT EO VRB 1 PS XO]
@@ -2203,12 +2203,12 @@ class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = eo;
- let Inst{16-20} = VB;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = eo;
+ let Inst{16...20} = VB;
let Inst{21} = 1;
let Inst{22} = PS;
- let Inst{23-31} = xo;
+ let Inst{23...31} = xo;
}
// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
@@ -2222,12 +2222,12 @@ class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VD;
- let Inst{11-15} = VA;
- let Inst{16-20} = VB;
+ let Inst{6...10} = VD;
+ let Inst{11...15} = VA;
+ let Inst{16...20} = VB;
let Inst{21} = 1;
let Inst{22} = PS;
- let Inst{23-31} = xo;
+ let Inst{23...31} = xo;
}
class Z22Form_BF3_FRA5_DCM6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
@@ -2240,11 +2240,11 @@ class Z22Form_BF3_FRA5_DCM6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = BF;
- let Inst{9-10} = 0;
- let Inst{11-15} = FRA;
- let Inst{16-21} = DCM;
- let Inst{22-30} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = FRA;
+ let Inst{16...21} = DCM;
+ let Inst{22...30} = xo;
let Inst{31} = 0;
}
@@ -2260,10 +2260,10 @@ class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
bit RC = 0; // set by isRecordForm
- let Inst{6 - 10} = FRT;
- let Inst{11 - 15} = FRA;
- let Inst{16 - 21} = SH;
- let Inst{22 - 30} = xo;
+ let Inst{6...10} = FRT;
+ let Inst{11...15} = FRA;
+ let Inst{16...21} = SH;
+ let Inst{22...30} = xo;
let Inst{31} = RC;
}
@@ -2279,12 +2279,12 @@ class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
bit RC = 0; // set by isRecordForm
- let Inst{6-10} = VRT;
- let Inst{11-14} = 0;
+ let Inst{6...10} = VRT;
+ let Inst{11...14} = 0;
let Inst{15} = R;
- let Inst{16-20} = VRB;
- let Inst{21-22} = idx;
- let Inst{23-30} = xo;
+ let Inst{16...20} = VRB;
+ let Inst{21...22} = idx;
+ let Inst{23...30} = xo;
let Inst{31} = RC;
}
@@ -2298,11 +2298,11 @@ class Z23Form_RTAB5_CY2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-22} = CY;
- let Inst{23-30} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...22} = CY;
+ let Inst{23...30} = xo;
let Inst{31} = 0;
}
@@ -2318,11 +2318,11 @@ class Z23Form_FRTAB5_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
bit RC = 0; // set by isRecordForm
- let Inst{6 - 10} = FRT;
- let Inst{11 - 15} = FRA;
- let Inst{16 - 20} = FRB;
- let Inst{21 - 22} = RMC;
- let Inst{23 - 30} = xo;
+ let Inst{6...10} = FRT;
+ let Inst{11...15} = FRA;
+ let Inst{16...20} = FRB;
+ let Inst{21...22} = RMC;
+ let Inst{23...30} = xo;
let Inst{31} = RC;
}
@@ -2345,12 +2345,12 @@ class Z23Form_FRTB5_R1_RMC2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
bit RC = 0; // set by isRecordForm
- let Inst{6 - 10} = FRT;
- let Inst{11 - 14} = 0;
+ let Inst{6...10} = FRT;
+ let Inst{11...14} = 0;
let Inst{15} = R;
- let Inst{16 - 20} = FRB;
- let Inst{21 - 22} = RMC;
- let Inst{23 - 30} = xo;
+ let Inst{16...20} = FRB;
+ let Inst{21...22} = RMC;
+ let Inst{23...30} = xo;
let Inst{31} = RC;
}
@@ -2362,7 +2362,7 @@ class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
let isCodeGenOnly = 1;
let PPC64 = 0;
let Pattern = pattern;
- let Inst{31-0} = 0;
+ let Inst{31...0} = 0;
let hasNoSchedulingInfo = 1;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 80fac18d5737..a12dfae2a0d7 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -13,7 +13,7 @@
class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<5> RT;
bits<5> RA;
bits<5> RB;
@@ -21,64 +21,174 @@ class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- bit RC = 0; // set by isRecordForm
+ bit RC = 0; // set by isRecordForm
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21} = L;
- let Inst{22-30} = xo;
- let Inst{31} = RC;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21} = L;
+ let Inst{22...30} = xo;
+ let Inst{31} = RC;
}
multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
- string asmbase, string asmstr,
- list<dag> pattern> {
+ string asmbase, string asmstr, list<dag> pattern> {
let BaseName = asmbase in {
def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
!strconcat(asmbase, !strconcat(" ", asmstr)),
- pattern>, RecFormRel;
- let Defs = [CR0] in
- def _rec : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
- !strconcat(asmbase, !strconcat(". ", asmstr)),
- []>, isRecordForm, RecFormRel;
+ pattern>,
+ RecFormRel;
+ let Defs = [CR0] in def _rec
+ : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)), []>,
+ isRecordForm, RecFormRel;
}
}
+class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> VRT;
+ bits<5> VRB;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = VRT;
+ let Inst{11...15} = R;
+ let Inst{16...20} = VRB;
+ let Inst{21...31} = xo;
+}
+
+class VXForm_VRTB5_UIM2<bits<11> xo, bits<3> R, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<4, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> VRT;
+ bits<5> VRB;
+ bits<2> UIM;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = VRT;
+ let Inst{11...13} = R;
+ let Inst{14...15} = UIM;
+ let Inst{16...20} = VRB;
+ let Inst{21...31} = xo;
+}
+
+class VXForm_VRTB5_UIM1<bits<11> xo, bits<4> R, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<4, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> VRT;
+ bits<5> VRB;
+ bits<1> UIM;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = VRT;
+ let Inst{11...14} = R;
+ let Inst{15} = UIM;
+ let Inst{16...20} = VRB;
+ let Inst{21...31} = xo;
+}
+
+class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern>
+ : I<4, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> VRT;
+ bits<5> VRB;
+ bits<3> UIM;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = VRT;
+ let Inst{11...12} = R;
+ let Inst{13...15} = UIM;
+ let Inst{16...20} = VRB;
+ let Inst{21...31} = xo;
+}
+
+class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
+ bits<5> VRT;
+ bits<5> VRA;
+ bits<5> VRB;
+
+ let Pattern = pattern;
+
+ let Inst{6...10} = VRT;
+ let Inst{11...15} = VRA;
+ let Inst{16...20} = VRB;
+ let Inst{21...31} = xo;
+}
+
let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
- (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
- "subfus", "$RT, $L, $RA, $RB", []>;
+ (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
+ "$RT, $L, $RA, $RB", []>;
}
let Predicates = [HasVSX, IsISAFuture] in {
let mayLoad = 1 in {
- def LXVRL
- : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
- "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
- def LXVRLL
- : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
- "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
- def LXVPRL
- : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), (ins memr:$RA, g8rc:$RB),
- "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
- def LXVPRLL
- : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), (ins memr:$RA, g8rc:$RB),
- "lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
+ def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
+ def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
+ def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
+ def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
+ (ins (memr $RA):$addr, g8rc:$RB),
+ "lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
}
let mayStore = 1 in {
- def STXVRL
- : XX1Form_memOp<31, 653, (outs), (ins vsrc:$XT, memr:$RA, g8rc:$RB),
- "stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
- def STXVRLL
- : XX1Form_memOp<31, 685, (outs), (ins vsrc:$XT, memr:$RA, g8rc:$RB),
- "stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
+ def STXVRL : XX1Form_memOp<31, 653, (outs),
+ (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
+ "stxvrl $XT, $addr, $RB", IIC_LdStLoad, []>;
+ def STXVRLL : XX1Form_memOp<31, 685, (outs),
+ (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB),
+ "stxvrll $XT, $addr, $RB", IIC_LdStLoad, []>;
def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
- (ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
- "stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
- def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
- (ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
- "stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
+ (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
+ "stxvprl $XTp, $addr, $RB", IIC_LdStLFD, []>;
+ def STXVPRLL
+ : XForm_XTp5_XAB5<31, 749, (outs),
+ (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
+ "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
}
+
+ def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB),
+ "vupkhsntob $VRT, $VRB", []>;
+ def VUPKLSNTOB : VXForm_VRTB5<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB),
+ "vupklsntob $VRT, $VRB", []>;
+ def VUPKINT4TOBF16
+ : VXForm_VRTB5_UIM2<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
+ "vupkint4tobf16 $VRT, $VRB, $UIM", []>;
+ def VUPKINT8TOBF16
+ : VXForm_VRTB5_UIM1<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB, u1imm:$UIM),
+ "vupkint8tobf16 $VRT, $VRB, $UIM", []>;
+ def VUPKINT8TOFP32
+ : VXForm_VRTB5_UIM2<387, 3, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
+ "vupkint8tofp32 $VRT, $VRB, $UIM", []>;
+ def VUPKINT4TOFP32
+ : VXForm_VRTB5_UIM3<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u3imm:$UIM),
+ "vupkint4tofp32 $VRT, $VRB, $UIM", []>;
+
+ def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprhn $VRT, $VRA, $VRB", []>;
+ def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprln $VRT, $VRA, $VRB", []>;
+ def VUCMPRHB
+ : VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprhb $VRT, $VRA, $VRB", []>;
+ def VUCMPRLB
+ : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprlb $VRT, $VRA, $VRB", []>;
+ def VUCMPRHH
+ : VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprhh $VRT, $VRA, $VRB", []>;
+ def VUCMPRLH
+ : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
+ "vucmprlh $VRT, $VRA, $VRB", []>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index ef8b27f9b8d3..884895793752 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -8,12 +8,13 @@
//===----------------------------------------------------------------------===//
//
// This file describes the instructions introduced for the Future CPU for MMA.
+// Please reference "PPCInstrVSX.td" for file structure.
//
//===----------------------------------------------------------------------===//
class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<3> AT;
bits<5> XAp;
bits<5> XBp;
@@ -21,13 +22,13 @@ class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = AT{2-0};
- let Inst{9-10} = 0;
- let Inst{11-14} = XAp{3-0};
+ let Inst{6...8} = AT{2...0};
+ let Inst{9...10} = 0;
+ let Inst{11...14} = XAp{3...0};
let Inst{15} = P;
- let Inst{16-19} = XBp{3-0};
+ let Inst{16...19} = XBp{3...0};
let Inst{20} = 0;
- let Inst{21-28} = xo;
+ let Inst{21...28} = xo;
let Inst{29} = XAp{4};
let Inst{30} = XBp{4};
let Inst{31} = 0;
@@ -35,65 +36,64 @@ class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<3> AT;
bits<5> XBp;
bits<2> P;
let Pattern = pattern;
- let Inst{6-8} = AT{2-0};
- let Inst{9-14} = 0;
+ let Inst{6...8} = AT{2...0};
+ let Inst{9...14} = 0;
let Inst{15} = P{0};
- let Inst{16-19} = XBp{3-0};
+ let Inst{16...19} = XBp{3...0};
let Inst{20} = P{1};
- let Inst{21-29} = xo;
+ let Inst{21...29} = xo;
let Inst{30} = XBp{4};
let Inst{31} = 0;
}
class XForm_ATB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
- : I <opcode, OOL, IOL, asmstr, NoItinerary> {
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<3> AT;
bits<3> AB;
let Pattern = pattern;
- let Inst{6-8} = AT{2-0};
- let Inst{9-10} = 0;
- let Inst{11-15} = o;
- let Inst{16-18} = AB{2-0};
- let Inst{19-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...8} = AT{2...0};
+ let Inst{9...10} = 0;
+ let Inst{11...15} = o;
+ let Inst{16...18} = AB{2...0};
+ let Inst{19...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
class XX3Form_AT3_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
- string asmstr, InstrItinClass itin,
- list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, itin> {
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
bits<3> AT;
bits<5> XAp;
bits<6> XB;
let Pattern = pattern;
- let Inst{6-8} = AT;
- let Inst{9-10} = 0;
- let Inst{11-14} = XAp{3-0};
+ let Inst{6...8} = AT;
+ let Inst{9...10} = 0;
+ let Inst{11...14} = XAp{3...0};
let Inst{15} = 0;
- let Inst{16-20} = XB{4-0};
- let Inst{21-28} = xo;
- let Inst{29} = XAp{4};
- let Inst{30} = XB{5};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...28} = xo;
+ let Inst{29} = XAp{4};
+ let Inst{30} = XB{5};
let Inst{31} = 0;
}
class MMIRR_XX3Form_X8YP4_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin,
list<dag> pattern>
- : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<3> AT;
bits<5> XAp;
bits<6> XB;
@@ -104,29 +104,29 @@ class MMIRR_XX3Form_X8YP4_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 3;
- let Inst{8-11} = 9;
- let Inst{12-15} = 0;
- let Inst{16-19} = PMSK;
- let Inst{20-27} = XMSK;
- let Inst{28-31} = YMSK;
+ let Inst{6...7} = 3;
+ let Inst{8...11} = 9;
+ let Inst{12...15} = 0;
+ let Inst{16...19} = PMSK;
+ let Inst{20...27} = XMSK;
+ let Inst{28...31} = YMSK;
// The instruction.
- let Inst{38-40} = AT;
- let Inst{41-42} = 0;
- let Inst{43-46} = XAp{3-0};
+ let Inst{38...40} = AT;
+ let Inst{41...42} = 0;
+ let Inst{43...46} = XAp{3...0};
let Inst{47} = 0;
- let Inst{48-52} = XB{4-0};
- let Inst{53-60} = xo;
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...60} = xo;
let Inst{61} = XAp{4};
let Inst{62} = XB{5};
let Inst{63} = 0;
}
class MMIRR_XX3Form_X8Y4P2_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
- string asmstr, InstrItinClass itin,
- list<dag> pattern>
- : PI<1, opcode, OOL, IOL, asmstr, itin> {
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : PI<1, opcode, OOL, IOL, asmstr, itin> {
bits<3> AT;
bits<5> XAp;
bits<6> XB;
@@ -137,21 +137,21 @@ class MMIRR_XX3Form_X8Y4P2_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 3;
- let Inst{8-11} = 9;
- let Inst{12-15} = 0;
- let Inst{16-17} = PMSK;
- let Inst{18-19} = 0;
- let Inst{20-27} = XMSK;
- let Inst{28-31} = YMSK;
+ let Inst{6...7} = 3;
+ let Inst{8...11} = 9;
+ let Inst{12...15} = 0;
+ let Inst{16...17} = PMSK;
+ let Inst{18...19} = 0;
+ let Inst{20...27} = XMSK;
+ let Inst{28...31} = YMSK;
// The instruction.
- let Inst{38-40} = AT;
- let Inst{41-42} = 0;
- let Inst{43-46} = XAp{3-0};
+ let Inst{38...40} = AT;
+ let Inst{41...42} = 0;
+ let Inst{43...46} = XAp{3...0};
let Inst{47} = 0;
- let Inst{48-52} = XB{4-0};
- let Inst{53-60} = xo;
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...60} = xo;
let Inst{61} = XAp{4};
let Inst{62} = XB{5};
let Inst{63} = 0;
@@ -160,14 +160,15 @@ class MMIRR_XX3Form_X8Y4P2_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
multiclass DMR_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
string asmstr> {
let Predicates = [MMA, IsISAFuture] in {
- def NAME :
- XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x01), (outs dmr:$AT), IOL,
- !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
- RegConstraint<"@earlyclobber $AT">;
- def PP :
- XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NAME
+ : XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x01), (outs dmr:$AT), IOL,
+ !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PP
+ : XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -175,202 +176,217 @@ multiclass DMR_UM_M448_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
string asmstr> {
defm NAME : DMR_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def PM#NAME :
- MMIRR_XX3Form_X8YP4_XAp5B6<
- opcode, !or(xo, 0x01), (outs dmr:$AT),
- !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
- !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"@earlyclobber $AT">;
- def PM#NAME#PP :
- MMIRR_XX3Form_X8YP4_XAp5B6<
- opcode, xo, (outs dmr:$AT),
- !con((ins dmr:$ATi),
- !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
- !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME
+ : MMIRR_XX3Form_X8YP4_XAp5B6<
+ opcode, !or(xo, 0x01), (outs dmr:$AT),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP
+ : MMIRR_XX3Form_X8YP4_XAp5B6<
+ opcode, xo, (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
}
multiclass DMR_BF16_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
- string asmstr> {
+ string asmstr> {
let Predicates = [MMA, IsISAFuture] in {
- def NAME :
- XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x11), (outs dmr:$AT), IOL,
- !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
- RegConstraint<"@earlyclobber $AT">;
- def PP :
- XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def NAME
+ : XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x11), (outs dmr:$AT), IOL,
+ !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PP
+ : XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
}
-multiclass DMR_BF16_UM_M284_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
- string asmstr> {
+multiclass DMR_BF16_UM_M284_XOEO<bits<6> opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
defm NAME : DMR_BF16_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def PM#NAME :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !or(xo, 0x11), (outs dmr:$AT),
- !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
- !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"@earlyclobber $AT">;
- def PM#NAME#PP :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, xo, (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !or(xo, 0x11), (outs dmr:$AT),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, xo, (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
}
-multiclass DMR_F16_UM_M284_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
- string asmstr> {
+multiclass DMR_F16_UM_M284_XOEO<bits<6> opcode, bits<8> xo, dag IOL,
+ string asmbase, string asmstr> {
defm NAME : DMR_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def PM#NAME :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !or(xo, 0x01), (outs dmr:$AT),
- !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
- !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"@earlyclobber $AT">;
- def PM#NAME#PP :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, xo, (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !or(xo, 0x01), (outs dmr:$AT),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)),
+ !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"@earlyclobber $AT">;
+ def PM#NAME#PP
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, xo, (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
}
multiclass DMR_NEG_UM_M284_XOXORf939a0<bits<6> opcode, bits<8> xo, dag IOL,
- string asmbase, string asmstr> {
+ string asmbase, string asmstr> {
defm NAME : DMR_BF16_UM_M284_XOEO<opcode, xo, IOL, asmbase, asmstr>;
let Predicates = [MMA, IsISAFuture] in {
- def PN : XX3Form_AT3_XAp5B6<
- opcode, !xor(xo, 0xF9), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def NP : XX3Form_AT3_XAp5B6<
- opcode, !xor(xo, 0x39), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def NN : XX3Form_AT3_XAp5B6<
- opcode, !xor(xo, 0xA0), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PN
+ : XX3Form_AT3_XAp5B6<opcode, !xor(xo, 0xF9), (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def NP
+ : XX3Form_AT3_XAp5B6<opcode, !xor(xo, 0x39), (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def NN
+ : XX3Form_AT3_XAp5B6<opcode, !xor(xo, 0xA0), (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def PM#NAME#PN :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !xor(xo, 0xF9), (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def PM#NAME#NP :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !xor(xo, 0x39), (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def PM#NAME#NN :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !xor(xo, 0xA0), (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#PN
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !xor(xo, 0xF9), (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def PM#NAME#NP
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !xor(xo, 0x39), (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def PM#NAME#NN
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !xor(xo, 0xA0), (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
}
multiclass DMR_NEG_UM_M284_XOXORd11188<bits<6> opcode, bits<8> xo, dag IOL,
- string asmbase, string asmstr> {
+ string asmbase, string asmstr> {
defm NAME : DMR_F16_UM_M284_XOEO<opcode, xo, IOL, asmbase, asmstr>;
let Predicates = [MMA, IsISAFuture] in {
- def PN : XX3Form_AT3_XAp5B6<
- opcode, !xor(xo, 0xD1), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def NP : XX3Form_AT3_XAp5B6<
- opcode, !xor(xo, 0x11), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def NN : XX3Form_AT3_XAp5B6<
- opcode, !xor(xo, 0x88), (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
- !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PN
+ : XX3Form_AT3_XAp5B6<opcode, !xor(xo, 0xD1), (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def NP
+ : XX3Form_AT3_XAp5B6<opcode, !xor(xo, 0x11), (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def NN
+ : XX3Form_AT3_XAp5B6<opcode, !xor(xo, 0x88), (outs dmr:$AT),
+ !con((ins dmr:$ATi), IOL),
+ !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def PM#NAME#PN :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !xor(xo, 0xD1), (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def PM#NAME#NP :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !xor(xo, 0x11), (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
- def PM#NAME#NN :
- MMIRR_XX3Form_X8Y4P2_XAp5B6<
- opcode, !xor(xo, 0x88), (outs dmr:$AT),
- !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
- !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
- IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PM#NAME#PN
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !xor(xo, 0xD1), (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def PM#NAME#NP
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !xor(xo, 0x11), (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
+ def PM#NAME#NN
+ : MMIRR_XX3Form_X8Y4P2_XAp5B6<
+ opcode, !xor(xo, 0x88), (outs dmr:$AT),
+ !con((ins dmr:$ATi),
+ !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
+ !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
+ IIC_VecFP, []>,
+ RegConstraint<"$ATi = $AT">;
}
}
class XForm_AT3_T1_AB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
- : I <opcode, OOL, IOL, asmstr, NoItinerary> {
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<3> AT;
bits<3> AB;
bits<1> T;
let Pattern = pattern;
- let Inst{6-8} = AT{2-0};
+ let Inst{6...8} = AT{2...0};
let Inst{9} = 0;
let Inst{10} = T;
- let Inst{11-15} = o;
- let Inst{16-18} = AB{2-0};
- let Inst{19-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{11...15} = o;
+ let Inst{16...18} = AB{2...0};
+ let Inst{19...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
class XForm_ATp2_SR5<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
- : I <opcode, OOL, IOL, asmstr, NoItinerary> {
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<2> ATp;
bits<5> SR;
let Pattern = pattern;
- let Inst{6-7} = ATp{1-0};
- let Inst{8-10} = 0;
- let Inst{11-15} = o;
- let Inst{16-20} = SR{4-0};
- let Inst{21-30} = xo;
+ let Inst{6...7} = ATp{1...0};
+ let Inst{8...10} = 0;
+ let Inst{11...15} = o;
+ let Inst{16...20} = SR{4...0};
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
class XX2Form_AT3_XB6_ID2_E1_BL2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
- string asmstr, list<dag> pattern>
- : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ string asmstr, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<3> AT;
bits<6> XB;
bits<2> ID;
@@ -379,41 +395,48 @@ class XX2Form_AT3_XB6_ID2_E1_BL2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = AT{2-0};
- let Inst{9-10} = 0;
- let Inst{11-12} = ID{1-0};
+ let Inst{6...8} = AT{2...0};
+ let Inst{9...10} = 0;
+ let Inst{11...12} = ID{1...0};
let Inst{13} = E;
- let Inst{14-15} = BL{1-0};
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{14...15} = BL{1...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = 0;
}
-let Predicates = [IsISAFuture] in {
- def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
- (outs vsrprc:$XAp, vsrprc:$XBp),
- (ins wacc:$AT),
- "dmxxextfdmr512 $XAp, $XBp, $AT, 0", []> {
+//-------------------------- Instruction definitions -------------------------//
+// Predicate combinations available:
+// [MMA, IsISAFuture]
+// [MMA, PrefixInstrs, IsISAFuture]
+
+let Predicates = [MMA, IsISAFuture] in {
+ def DMXXEXTFDMR512
+ : XX3Form_AT3_XABp5_P1<60, 226, (outs vsrprc:$XAp, vsrprc:$XBp),
+ (ins wacc:$AT),
+ "dmxxextfdmr512 $XAp, $XBp, $AT, 0", []> {
let P = 0;
}
- def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226,
- (outs vsrprc:$XAp, vsrprc:$XBp),
- (ins wacc_hi:$AT),
- "dmxxextfdmr512 $XAp, $XBp, $AT, 1", []> {
+ def DMXXEXTFDMR512_HI
+ : XX3Form_AT3_XABp5_P1<60, 226, (outs vsrprc:$XAp, vsrprc:$XBp),
+ (ins wacc_hi:$AT),
+ "dmxxextfdmr512 $XAp, $XBp, $AT, 1", []> {
let P = 1;
}
- def DMXXINSTDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
- (ins vsrprc:$XAp, vsrprc:$XBp),
- "dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> {
+ def DMXXINSTDMR512
+ : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
+ (ins vsrprc:$XAp, vsrprc:$XBp),
+ "dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> {
let P = 0;
}
- def DMXXINSTDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
- (ins vsrprc:$XAp, vsrprc:$XBp),
- "dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> {
+ def DMXXINSTDMR512_HI
+ : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
+ (ins vsrprc:$XAp, vsrprc:$XBp),
+ "dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> {
let P = 1;
}
@@ -422,236 +445,220 @@ let Predicates = [IsISAFuture] in {
"dmxxextfdmr256 $XBp, $AT, $P", []>;
def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
- (ins vsrprc:$XBp, u2imm:$P),
- "dmxxinstdmr256 $AT, $XBp, $P", []>;
+ (ins vsrprc:$XBp, u2imm:$P),
+ "dmxxinstdmr256 $AT, $XBp, $P", []>;
- def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
- "dmmr $AT, $AB",
- [(set v1024i1:$AT, (int_ppc_mma_dmmr v1024i1:$AB))]>;
+ def DMMR
+ : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB), "dmmr $AT, $AB",
+ [(set v1024i1:$AT, (int_ppc_mma_dmmr v1024i1:$AB))]>;
def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB),
"dmxor $AT, $AB",
- [(set v1024i1:$AT, (int_ppc_mma_dmxor v1024i1:$ATi, v1024i1:$AB))]>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
-
- def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
- "dmsetdmrz $AT", NoItinerary,
- [(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
-}
-
-// MMA+ accumulating/non-accumulating instructions.
-
-// DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
-defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
- "dmxvi8gerx4", "$AT, $XAp, $XB">;
-
-let Predicates = [MMA, IsISAFuture] in {
- def DMXVI8GERX4SPP :
- XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT), (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
- "dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
-}
+ [(set v1024i1:$AT, (int_ppc_mma_dmxor v1024i1:$ATi,
+ v1024i1:$AB))]>,
+ RegConstraint<"$ATi = $AT">;
+
+ def DMSETDMRZ
+ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins), "dmsetdmrz $AT",
+ NoItinerary, [(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
+
+ // DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
+ defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
+ "dmxvi8gerx4", "$AT, $XAp, $XB">;
+
+ // DMXVBF16GERX2, DMXVBF16GERX2PP, DMXVBF16GERX2PN, dMXVBF16GERX2NP,
+ // DMXVBF16GERX2NN PMDMXVBF16GERX2, PMDMXVBF16GERX2PP, PMDMXVBF16GERX2PN,
+ // PMDMXVBF16GERX2NP, PMDMXVBF16GERX2NN
+ defm DMXVBF16GERX2
+ : DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:$XB),
+ "dmxvbf16gerx2", "$AT, $XAp, $XB">;
+
+ // DMXVF16GERX2, DMXVF16GERX2PP, DMXVF16GERX2PN, dMXVF16GERX2NP,
+ // DMXVF16GERX2NN PMDMXVF16GERX2, PMDMXVF16GERX2PP, PMDMXVF16GERX2PN,
+ // PMDMXVF16GERX2NP, PMDMXVF16GERX2NN
+ defm DMXVF16GERX2
+ : DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB),
+ "dmxvf16gerx2", "$AT, $XAp, $XB">;
+
+ // DMF cryptography [support] Instructions
+ def DMSHA2HASH
+ : XForm_AT3_T1_AB3<
+ 31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
+ "dmsha2hash $AT, $AB, $T",
+ [(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi,
+ v1024i1:$AB, timm:$T))]>,
+ RegConstraint<"$ATi = $AT">;
+ def DMSHA3HASH
+ : XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp),
+ (ins dmrp:$ATpi, u5imm:$SR), "dmsha3hash $ATp, $SR",
+ [(set v2048i1:$ATp,
+ (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
+ RegConstraint<"$ATpi = $ATp">;
+ def DMXXSHAPAD
+ : XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
+ (ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E,
+ u2imm:$BL),
+ "dmxxshapad $AT, $XB, $ID, $E, $BL", []>,
+ RegConstraint<"$ATi = $AT">;
+
+ // MMA+ accumulating/non-accumulating instructions.
+ def DMXVI8GERX4SPP
+ : XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT),
+ (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
+ "dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">;
+
+} // End of [MMA, IsISAFuture]
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def PMDMXVI8GERX4SPP :
- MMIRR_XX3Form_X8YP4_XAp5B6<59, 98, (outs dmr:$AT),
- (ins dmr:$ATi, vsrprc:$XAp,vsrc:$XB, u8imm:$XMSK,
- u4imm:$YMSK, u4imm:$PMSK),
- "pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
- IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ def PMDMXVI8GERX4SPP
+ : MMIRR_XX3Form_X8YP4_XAp5B6<
+ 59, 98, (outs dmr:$AT),
+ (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB, u8imm:$XMSK, u4imm:$YMSK,
+ u4imm:$PMSK),
+ "pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
+ IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">;
}
-// DMXVBF16GERX2, DMXVBF16GERX2PP, DMXVBF16GERX2PN, dMXVBF16GERX2NP, DMXVBF16GERX2NN
-// PMDMXVBF16GERX2, PMDMXVBF16GERX2PP, PMDMXVBF16GERX2PN, PMDMXVBF16GERX2NP, PMDMXVBF16GERX2NN
-defm DMXVBF16GERX2 : DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:$XB),
- "dmxvbf16gerx2", "$AT, $XAp, $XB">;
-
-// DMXVF16GERX2, DMXVF16GERX2PP, DMXVF16GERX2PN, dMXVF16GERX2NP, DMXVF16GERX2NN
-// PMDMXVF16GERX2, PMDMXVF16GERX2PP, PMDMXVF16GERX2PN, PMDMXVF16GERX2NP, PMDMXVF16GERX2NN
-defm DMXVF16GERX2 : DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB),
- "dmxvf16gerx2", "$AT, $XAp, $XB">;
-
-// DMF cryptography [support] Instructions
-let Predicates = [IsISAFuture] in {
- def DMSHA2HASH :
- XForm_AT3_T1_AB3<31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
- "dmsha2hash $AT, $AB, $T",
- [(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi, v1024i1:$AB, timm:$T))]>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
-
- def DMSHA3HASH :
- XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp), (ins dmrp:$ATpi , u5imm:$SR),
- "dmsha3hash $ATp, $SR",
- [(set v2048i1:$ATp, (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
- RegConstraint<"$ATpi = $ATp">, NoEncode<"$ATpi">;
-
- def DMXXSHAPAD :
- XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
- (ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E, u2imm:$BL),
- "dmxxshapad $AT, $XB, $ID, $E, $BL", []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
-}
+//---------------------------- Anonymous Patterns ----------------------------//
+// Predicate combinations available:
+// [MMA, IsISAFuture]
+// [MMA, PrefixInstrs, IsISAFuture]
-// MMA+ Intrinsics
let Predicates = [MMA, IsISAFuture] in {
+ // MMA+ Intrinsics
def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
(DMXVI8GERX4 $XAp, RCCp.BToVSRC)>;
- def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC)>;
-
def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2 v256i1:$XAp, v16i8:$XB)),
(DMXVBF16GERX2 $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
-
def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2 v256i1:$XAp, v16i8:$XB)),
(DMXVF16GERX2 $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
+
+ // Cryptography Intrinsic
+ def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
+ timm:$E, timm:$BL)),
+ (DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
- (PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk4Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB,
+ Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
+ (PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk4Imm:$PMSK)>;
+
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
(PMDMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk4Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
(PMDMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
- (PMDMXVBF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2 v256i1:$XAp, v16i8:$XB,
+ Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMDMXVBF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
- (PMDMXVF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2 v256i1:$XAp, v16i8:$XB,
+ Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMDMXVF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
-}
-
-// Cryptography Intrinsic
-let Predicates = [IsISAFuture] in {
- def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
- timm:$E, timm:$BL)), (DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
}
-// MMA+ Instruction aliases
-let Predicates = [IsISAFuture] in {
- def : InstAlias<"dmsha256hash $AT, $AB",
- (DMSHA2HASH dmr:$AT, dmr:$AB, 0)>;
+//---------------------------- Instruction aliases ---------------------------//
- def : InstAlias<"dmsha512hash $AT, $AB",
- (DMSHA2HASH dmr:$AT, dmr:$AB, 1)>;
-
- def : InstAlias<"dmsha3dw $ATp",
- (DMSHA3HASH dmrp:$ATp, 0)>;
-
- def : InstAlias<"dmcryshash $ATp",
- (DMSHA3HASH dmrp:$ATp, 12)>;
-
- def : InstAlias<"dmxxsha3512pad $AT, $XB, $E",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 0)>;
-
- def : InstAlias<"dmxxsha3384pad $AT, $XB, $E",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 1)>;
-
- def : InstAlias<"dmxxsha3256pad $AT, $XB, $E",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 2)>;
-
- def : InstAlias<"dmxxsha3224pad $AT, $XB, $E",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 3)>;
-
- def : InstAlias<"dmxxshake256pad $AT, $XB, $E",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 1, u1imm:$E, 0)>;
-
- def : InstAlias<"dmxxshake128pad $AT, $XB, $E",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 1, u1imm:$E, 1)>;
-
- def : InstAlias<"dmxxsha384512pad $AT, $XB",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 2, 0, 0)>;
-
- def : InstAlias<"dmxxsha224256pad $AT, $XB",
- (DMXXSHAPAD dmr:$AT, vsrc:$XB, 3, 0, 0)>;
+let Predicates = [MMA, IsISAFuture] in {
+ def : InstAlias<"dmsha256hash $AT, $AB", (DMSHA2HASH dmr:$AT, dmr:$AB, 0)>;
+ def : InstAlias<"dmsha512hash $AT, $AB", (DMSHA2HASH dmr:$AT, dmr:$AB, 1)>;
+ def : InstAlias<"dmsha3dw $ATp", (DMSHA3HASH dmrp:$ATp, 0)>;
+ def : InstAlias<"dmcryshash $ATp", (DMSHA3HASH dmrp:$ATp, 12)>;
+ def : InstAlias<"dmxxsha3512pad $AT, $XB, $E", (DMXXSHAPAD dmr:$AT, vsrc:$XB,
+ 0, u1imm:$E, 0)>;
+ def : InstAlias<"dmxxsha3384pad $AT, $XB, $E", (DMXXSHAPAD dmr:$AT, vsrc:$XB,
+ 0, u1imm:$E, 1)>;
+ def : InstAlias<"dmxxsha3256pad $AT, $XB, $E", (DMXXSHAPAD dmr:$AT, vsrc:$XB,
+ 0, u1imm:$E, 2)>;
+ def : InstAlias<"dmxxsha3224pad $AT, $XB, $E", (DMXXSHAPAD dmr:$AT, vsrc:$XB,
+ 0, u1imm:$E, 3)>;
+ def : InstAlias<"dmxxshake256pad $AT, $XB, $E", (DMXXSHAPAD dmr:$AT, vsrc:$XB,
+ 1, u1imm:$E, 0)>;
+ def : InstAlias<"dmxxshake128pad $AT, $XB, $E", (DMXXSHAPAD dmr:$AT, vsrc:$XB,
+ 1, u1imm:$E, 1)>;
+ def : InstAlias<"dmxxsha384512pad $AT, $XB", (DMXXSHAPAD dmr:$AT, vsrc:$XB, 2,
+ 0, 0)>;
+ def : InstAlias<"dmxxsha224256pad $AT, $XB", (DMXXSHAPAD dmr:$AT, vsrc:$XB, 3,
+ 0, 0)>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 7c1550e99bae..db066bc4b7bd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -30,6 +30,7 @@
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/StackMaps.h"
@@ -87,8 +88,8 @@ static cl::opt<bool> EnableFMARegPressureReduction(
// Pin the vtable to this file.
void PPCInstrInfo::anchor() {}
-PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
- : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
+PPCInstrInfo::PPCInstrInfo(const PPCSubtarget &STI)
+ : PPCGenInstrInfo(STI, PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
/* CatchRetOpcode */ -1,
STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
Subtarget(STI), RI(STI.getTargetMachine()) {}
@@ -1863,6 +1864,48 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcRegSub1)
.addReg(SrcRegSub1, getKillRegState(KillSrc));
return;
+ } else if ((PPC::WACCRCRegClass.contains(DestReg) ||
+ PPC::WACC_HIRCRegClass.contains(DestReg)) &&
+ (PPC::WACCRCRegClass.contains(SrcReg) ||
+ PPC::WACC_HIRCRegClass.contains(SrcReg))) {
+
+ Opc = PPC::WACCRCRegClass.contains(SrcReg) ? PPC::DMXXEXTFDMR512
+ : PPC::DMXXEXTFDMR512_HI;
+
+ RegScavenger RS;
+ RS.enterBasicBlockEnd(MBB);
+ RS.backward(std::next(I));
+
+ Register TmpReg1 = RS.scavengeRegisterBackwards(PPC::VSRpRCRegClass, I,
+ /* RestoreAfter */ false, 0,
+ /* AllowSpill */ false);
+
+ RS.setRegUsed(TmpReg1);
+ Register TmpReg2 = RS.scavengeRegisterBackwards(PPC::VSRpRCRegClass, I,
+ /* RestoreAfter */ false, 0,
+ /* AllowSpill */ false);
+
+ BuildMI(MBB, I, DL, get(Opc))
+ .addReg(TmpReg1, RegState::Define)
+ .addReg(TmpReg2, RegState::Define)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+
+ Opc = PPC::WACCRCRegClass.contains(DestReg) ? PPC::DMXXINSTDMR512
+ : PPC::DMXXINSTDMR512_HI;
+
+ BuildMI(MBB, I, DL, get(Opc), DestReg)
+ .addReg(TmpReg1, RegState::Kill)
+ .addReg(TmpReg2, RegState::Kill);
+
+ return;
+ } else if (PPC::DMRRCRegClass.contains(DestReg) &&
+ PPC::DMRRCRegClass.contains(SrcReg)) {
+
+ BuildMI(MBB, I, DL, get(PPC::DMMR), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+
+ return;
+
} else
llvm_unreachable("Impossible reg-to-reg copy");
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 7931a9e3ae13..63ebd6591057 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -279,7 +279,7 @@ enum PPCMachineCombinerPattern : unsigned {
class PPCSubtarget;
class PPCInstrInfo : public PPCGenInstrInfo {
- PPCSubtarget &Subtarget;
+ const PPCSubtarget &Subtarget;
const PPCRegisterInfo RI;
const unsigned StoreSpillOpcodesArray[4][SOK_LastOpcodeSpill] =
StoreOpcodesForSpill;
@@ -369,7 +369,7 @@ protected:
unsigned OpIdx2) const override;
public:
- explicit PPCInstrInfo(PPCSubtarget &STI);
+ explicit PPCInstrInfo(const PPCSubtarget &STI);
bool isLoadFromConstantPool(MachineInstr *I) const;
const Constant *getConstantFromConstantPool(MachineInstr *I) const;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index c2f91ce8e6b9..c12cf8511312 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -58,6 +58,10 @@ def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3>
]>;
+def SDT_PPCVecShiftQuad : SDTypeProfile<1, 2, [
+ SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>
+]>;
+
def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
]>;
@@ -157,6 +161,8 @@ def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
+def PPCvsrq: SDNode<"PPCISD::VSRQ", SDT_PPCVecShiftQuad, []>;
+
def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID",
SDTFPUnaryOp, [SDNPHasChain]>;
def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU",
@@ -665,9 +671,6 @@ class isRecordForm { bit RC = 1; }
class RegConstraint<string C> {
string Constraints = C;
}
-class NoEncode<string E> {
- string DisableEncoding = E;
-}
// Define PowerPC specific addressing mode.
@@ -1989,29 +1992,24 @@ def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D,
def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lhau $RST, $addr", IIC_LdStLHAU,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lhzu $RST, $addr", IIC_LdStLoadUpd,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lwzu $RST, $addr", IIC_LdStLoadUpd,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
let Predicates = [HasFPU] in {
def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lfsu $RST, $addr", IIC_LdStLFDU,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr),
"lfdu $RST, $addr", IIC_LdStLFDU,
- []>, RegConstraint<"$addr.reg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.reg = $ea_result">;
}
@@ -2019,39 +2017,33 @@ def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D,
def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lbzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lhaux $RST, $addr", IIC_LdStLHAUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lhzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lwzux $RST, $addr", IIC_LdStLoadUpdX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
let Predicates = [HasFPU] in {
def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lfsux $RST, $addr", IIC_LdStLFDUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result),
(ins (memrr $RA, $RB):$addr),
"lfdux $RST, $addr", IIC_LdStLFDUX,
- []>, RegConstraint<"$addr.ptrreg = $ea_result">,
- NoEncode<"$ea_result">;
+ []>, RegConstraint<"$addr.ptrreg = $ea_result">;
}
}
}
@@ -2132,20 +2124,20 @@ def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst),
let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
"stbu $RST, $dst", IIC_LdStSTU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
"sthu $RST, $dst", IIC_LdStSTU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst),
"stwu $RST, $dst", IIC_LdStSTU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
let Predicates = [HasFPU] in {
def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst),
"stfsu $RST, $dst", IIC_LdStSTFDU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst),
"stfdu $RST, $dst", IIC_LdStSTFDU, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
}
}
@@ -2207,32 +2199,27 @@ def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$RST, (memrr $RA, $RB):$addr),
"stbux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$RST, (memrr $RA, $RB):$addr),
"sthux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$RST, (memrr $RA, $RB):$addr),
"stwux $RST, $addr", IIC_LdStSTUX, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
let Predicates = [HasFPU] in {
def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res),
(ins f4rc:$RST, (memrr $RA, $RB):$addr),
"stfsux $RST, $addr", IIC_LdStSTFDU, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res),
(ins f8rc:$RST, (memrr $RA, $RB):$addr),
"stfdux $RST, $addr", IIC_LdStSTFDU, []>,
RegConstraint<"$addr.ptrreg = $ea_res">,
- NoEncode<"$ea_res">,
PPC970_DGroup_Cracked;
}
}
@@ -3099,7 +3086,7 @@ defm RLWIMI : MForm_2r<20, (outs gprc:$RA),
(ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB,
u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME",
IIC_IntRotate, []>, PPC970_DGroup_Cracked,
- RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">;
+ RegConstraint<"$RAi = $RA">;
}
let BaseName = "rlwinm" in {
def RLWINM : MForm_2<21,
@@ -3235,9 +3222,10 @@ def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
// This uses two output registers, the first as the real output, the second as a
-// temporary register, used internally in code generation.
+// temporary register, used internally in code generation. A "bl" also clobbers LR.
+let Defs = [LR] in
def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
- []>, NoEncode<"$rT">;
+ []>;
def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
"#LDgotTprelL32",
@@ -4287,7 +4275,7 @@ def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
bits<1> E;
let Inst{16} = E;
- let Inst{21-30} = 163;
+ let Inst{21...30} = 163;
}
def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB),
@@ -4967,44 +4955,44 @@ defm : BranchSimpleMnemonic1<"dzf", "", 2>;
multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
def : InstAlias<"b"#name#pm#" $cc, $dst",
- (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
+ (BCC (pred bibo, crrc:$cc), condbrtarget:$dst)>;
def : InstAlias<"b"#name#pm#" $dst",
- (BCC bibo, CR0, condbrtarget:$dst)>;
+ (BCC (pred bibo, CR0), condbrtarget:$dst)>;
def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
- (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
+ (BCCA (pred bibo, crrc:$cc), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"a"#pm#" $dst",
- (BCCA bibo, CR0, abscondbrtarget:$dst)>;
+ (BCCA (pred bibo, CR0), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lr"#pm#" $cc",
- (BCCLR bibo, crrc:$cc)>;
+ (BCCLR (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"lr"#pm,
- (BCCLR bibo, CR0)>;
+ (BCCLR (pred bibo, CR0))>;
def : InstAlias<"b"#name#"ctr"#pm#" $cc",
- (BCCCTR bibo, crrc:$cc)>;
+ (BCCCTR (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"ctr"#pm,
- (BCCCTR bibo, CR0)>;
+ (BCCCTR (pred bibo, CR0))>;
def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
- (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
+ (BCCL (pred bibo, crrc:$cc), condbrtarget:$dst)>;
def : InstAlias<"b"#name#"l"#pm#" $dst",
- (BCCL bibo, CR0, condbrtarget:$dst)>;
+ (BCCL (pred bibo, CR0), condbrtarget:$dst)>;
def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
- (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
+ (BCCLA (pred bibo, crrc:$cc), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"la"#pm#" $dst",
- (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
+ (BCCLA (pred bibo, CR0), abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lrl"#pm#" $cc",
- (BCCLRL bibo, crrc:$cc)>;
+ (BCCLRL (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"lrl"#pm,
- (BCCLRL bibo, CR0)>;
+ (BCCLRL (pred bibo, CR0))>;
def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
- (BCCCTRL bibo, crrc:$cc)>;
+ (BCCCTRL (pred bibo, crrc:$cc))>;
def : InstAlias<"b"#name#"ctrl"#pm,
- (BCCCTRL bibo, CR0)>;
+ (BCCCTRL (pred bibo, CR0))>;
}
multiclass BranchExtendedMnemonic<string name, int bibo> {
defm : BranchExtendedMnemonicPM<name, "", bibo>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrMMA.td b/llvm/lib/Target/PowerPC/PPCInstrMMA.td
index 436715a0e4ab..b38dd4ae948c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrMMA.td
@@ -14,7 +14,7 @@ multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
def PP :
XX3Form_AT3_XAB6<opcode, xo, (outs acc:$AT), !con((ins acc:$ATi), IOL),
!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
def NAME#W :
@@ -24,7 +24,7 @@ multiclass ACC_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
def WPP :
XX3Form_AT3_XAB6<opcode, xo, (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -48,7 +48,7 @@ multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
def PM#NAME#W :
@@ -65,7 +65,7 @@ multiclass ACC_UM_M844_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u8imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -89,7 +89,7 @@ multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
def PM#NAME#W :
@@ -106,7 +106,7 @@ multiclass ACC_UM_M444_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -129,7 +129,7 @@ multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
def PM#NAME#W :
@@ -145,7 +145,7 @@ multiclass ACC_UM_M244_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -162,7 +162,7 @@ multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
XX3Form_AT3_XAB6<
opcode, !or(xo, 0x20), (outs acc:$AT), !con((ins acc:$ATi), IOL),
!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME :
@@ -179,7 +179,7 @@ multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
def NAME#W :
@@ -190,7 +190,7 @@ multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
XX3Form_AT3_XAB6<
opcode, !or(xo, 0x20), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
def PM#NAME#W :
@@ -207,7 +207,7 @@ multiclass ACC_UM_M244_XO46<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
!con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -220,29 +220,29 @@ multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
def PN : XX3Form_AT3_XAB6<
opcode, !or(xo, 0x80), (outs acc:$AT), !con((ins acc:$ATi), IOL),
!strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def NP : XX3Form_AT3_XAB6<
opcode, !or(xo, 0x40), (outs acc:$AT), !con((ins acc:$ATi), IOL),
!strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def NN : XX3Form_AT3_XAB6<
opcode, !or(xo, 0xC0), (outs acc:$AT), !con((ins acc:$ATi), IOL),
!strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
def WPN : XX3Form_AT3_XAB6<
opcode, !or(xo, 0x80), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def WNP : XX3Form_AT3_XAB6<
opcode, !or(xo, 0x40), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def WNN : XX3Form_AT3_XAB6<
opcode, !or(xo, 0xC0), (outs wacc:$AT), !con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
def PM#NAME#PN :
@@ -251,21 +251,21 @@ multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#NP :
MMIRR_XX3Form_XY4P2_XAB6<
opcode, !or(xo, 0x40), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#NN :
MMIRR_XX3Form_XY4P2_XAB6<
opcode, !or(xo, 0xC0), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
def PM#NAME#WPN :
@@ -274,21 +274,21 @@ multiclass ACC_NEG_UM_M244_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WNP :
MMIRR_XX3Form_XY4P2_XAB6<
opcode, !or(xo, 0x40), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WNN :
MMIRR_XX3Form_XY4P2_XAB6<
opcode, !or(xo, 0xC0), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))),
!strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -301,29 +301,29 @@ multiclass ACC_NEG_UM_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
def PN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs acc:$AT),
!con((ins acc:$ATi), IOL),
!strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def NP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs acc:$AT),
!con((ins acc:$ATi), IOL),
!strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def NN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs acc:$AT),
!con((ins acc:$ATi), IOL),
!strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
def WPN : XX3Form_AT3_XAB6<opcode, !or(xo, 0x80), (outs wacc:$AT),
!con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def WNP : XX3Form_AT3_XAB6<opcode, !or(xo, 0x40), (outs wacc:$AT),
!con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def WNN : XX3Form_AT3_XAB6<opcode, !or(xo, 0xC0), (outs wacc:$AT),
!con((ins wacc:$ATi), IOL),
!strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -346,28 +346,28 @@ multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#PN :
MMIRR_XX3Form_XY4_XAB6<
opcode, !or(xo, 0x80), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#NP :
MMIRR_XX3Form_XY4_XAB6<
opcode, !or(xo, 0x40), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#NN :
MMIRR_XX3Form_XY4_XAB6<
opcode, !or(xo, 0xC0), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
def PM#NAME#W :
@@ -383,28 +383,28 @@ multiclass ACC_NEG_UM_M44_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WPN :
MMIRR_XX3Form_XY4_XAB6<
opcode, !or(xo, 0x80), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WNP :
MMIRR_XX3Form_XY4_XAB6<
opcode, !or(xo, 0x40), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WNN :
MMIRR_XX3Form_XY4_XAB6<
opcode, !or(xo, 0xC0), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u4imm:$YMSK))),
!strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -427,28 +427,28 @@ multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#PN :
MMIRR_XX3Form_X4Y2_XAB6<
opcode, !or(xo, 0x80), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#NP :
MMIRR_XX3Form_X4Y2_XAB6<
opcode, !or(xo, 0x40), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#NN :
MMIRR_XX3Form_X4Y2_XAB6<
opcode, !or(xo, 0xC0), (outs acc:$AT),
!con((ins acc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
def PM#NAME#W :
@@ -464,28 +464,28 @@ multiclass ACC_NEG_UM_M42_XOM84C<bits<6> opcode, bits<8> xo, dag IOL,
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WPN :
MMIRR_XX3Form_X4Y2_XAB6<
opcode, !or(xo, 0x80), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WNP :
MMIRR_XX3Form_X4Y2_XAB6<
opcode, !or(xo, 0x40), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def PM#NAME#WNN :
MMIRR_XX3Form_X4Y2_XAB6<
opcode, !or(xo, 0xC0), (outs wacc:$AT),
!con((ins wacc:$ATi), !con(IOL, (ins u4imm:$XMSK, u2imm:$YMSK))),
!strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK"),
IIC_VecFP, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
}
@@ -497,12 +497,12 @@ let Predicates = [MMA, IsNotISAFuture] in {
XForm_AT3<31, 0, 177, (outs acc:$ATo), (ins acc:$AT), "xxmfacc $AT",
IIC_VecGeneral,
[(set v512i1:$ATo, (int_ppc_mma_xxmfacc v512i1:$AT))]>,
- RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">;
+ RegConstraint<"$ATo = $AT">;
def XXMTACC :
XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT",
IIC_VecGeneral,
[(set v512i1:$AT, (int_ppc_mma_xxmtacc v512i1:$ATi))]>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
def KILL_PAIR : PPCPostRAExpPseudo<(outs vsrprc:$XTp), (ins vsrprc:$XSp),
"#KILL_PAIR", []>,
RegConstraint<"$XTp = $XSp">;
@@ -519,7 +519,7 @@ let Predicates = [MMA, IsNotISAFuture] in {
def XVI8GER4SPP :
XX3Form_AT3_XAB6<59, 99, (outs acc:$AT), (ins acc:$ATi, vsrc:$XA, vsrc:$XB),
"xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
let mayStore = 1 in {
def SPILL_ACC: PPCEmitTimePseudo<(outs), (ins acc:$AT, memrix16:$dst),
"#SPILL_ACC", []>;
@@ -544,11 +544,11 @@ let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
def XXMFACCW :
XForm_AT3<31, 0, 177, (outs wacc:$ATo), (ins wacc:$AT), "xxmfacc $AT",
IIC_VecGeneral, []>,
- RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">;
+ RegConstraint<"$ATo = $AT">;
def XXMTACCW :
XForm_AT3<31, 1, 177, (outs wacc:$AT), (ins wacc:$ATi), "xxmtacc $AT",
IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
let isAsCheapAsAMove = 1, isReMaterializable = 1 in {
def DMXXSETACCZ :
@@ -560,7 +560,7 @@ let Predicates = [MMA, IsISAFuture], isCodeGenOnly = 1 in {
XX3Form_AT3_XAB6<59, 99, (outs wacc:$AT),
(ins wacc:$ATi, vsrc:$XA, vsrc:$XB),
"xvi8ger4spp $AT, $XA, $XB", IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
let mayStore = 1 in {
def SPILL_WACC: PPCEmitTimePseudo<(outs), (ins wacc:$AT, memrix16:$dst),
@@ -593,7 +593,7 @@ let Predicates = [MMA, PrefixInstrs, IsNotISAFuture] in {
u4imm:$YMSK, u4imm:$PMSK),
"pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",
IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
@@ -603,7 +603,7 @@ let Predicates = [MMA, PrefixInstrs, IsISAFuture], isCodeGenOnly = 1 in {
u4imm:$YMSK, u4imm:$PMSK),
"pmxvi8ger4spp $AT, $XA, $XB, $XMSK, $YMSK, $PMSK",
IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+ RegConstraint<"$ATi = $AT">;
}
// MMA accumulating/non-accumulating instructions.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index c4a027d65b66..149a44ddfc10 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -125,8 +125,8 @@ class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
let InOperandList = IOL;
let AsmString = asmstr;
let Itinerary = itin;
- let Inst{0-5} = pref;
- let Inst{32-37} = opcode;
+ let Inst{0...5} = pref;
+ let Inst{32...37} = opcode;
bits<1> PPC970_First = 0;
bits<1> PPC970_Single = 0;
@@ -138,7 +138,7 @@ class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
let TSFlags{0} = PPC970_First;
let TSFlags{1} = PPC970_Single;
let TSFlags{2} = PPC970_Cracked;
- let TSFlags{5-3} = PPC970_Unit;
+ let TSFlags{5...3} = PPC970_Unit;
bits<1> Prefixed = 1; // This is a prefixed instruction.
let TSFlags{7} = Prefixed;
@@ -167,11 +167,11 @@ class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VT;
- let Inst{11-15} = R;
- let Inst{16-20} = VB;
+ let Inst{6...10} = VT;
+ let Inst{11...15} = R;
+ let Inst{16...20} = VB;
let Inst{21} = RC;
- let Inst{22-31} = xo;
+ let Inst{22...31} = xo;
}
// Multiclass definition to account for record and non-record form
@@ -200,16 +200,16 @@ class MLS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 2;
- let Inst{8-10} = 0;
+ let Inst{6...7} = 2;
+ let Inst{8...10} = 0;
let Inst{11} = PCRel;
- let Inst{12-13} = 0;
- let Inst{14-31} = D{33-16}; // d0
+ let Inst{12...13} = 0;
+ let Inst{14...31} = D{33...16}; // d0
// The instruction.
- let Inst{38-42} = RST{4-0};
- let Inst{43-47} = RA;
- let Inst{48-63} = D{15-0}; // d1
+ let Inst{38...42} = RST{4...0};
+ let Inst{43...47} = RA;
+ let Inst{48...63} = D{15...0}; // d1
}
class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -222,16 +222,16 @@ class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 2;
- let Inst{8-10} = 0;
+ let Inst{6...7} = 2;
+ let Inst{8...10} = 0;
let Inst{11} = PCRel;
- let Inst{12-13} = 0;
- let Inst{14-31} = SI{33-16};
+ let Inst{12...13} = 0;
+ let Inst{14...31} = SI{33...16};
// The instruction.
- let Inst{38-42} = RT;
- let Inst{43-47} = RA;
- let Inst{48-63} = SI{15-0};
+ let Inst{38...42} = RT;
+ let Inst{43...47} = RA;
+ let Inst{48...63} = SI{15...0};
}
class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
@@ -243,16 +243,16 @@ class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 2;
- let Inst{8-10} = 0;
+ let Inst{6...7} = 2;
+ let Inst{8...10} = 0;
let Inst{11} = 0;
- let Inst{12-13} = 0;
- let Inst{14-31} = SI{33-16};
+ let Inst{12...13} = 0;
+ let Inst{14...31} = SI{33...16};
// The instruction.
- let Inst{38-42} = RT;
- let Inst{43-47} = 0;
- let Inst{48-63} = SI{15-0};
+ let Inst{38...42} = RT;
+ let Inst{43...47} = 0;
+ let Inst{48...63} = SI{15...0};
}
multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
@@ -274,15 +274,15 @@ class 8LS_DForm_R_SI34_RTA5_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
// The prefix.
- let Inst{6-10} = 0;
+ let Inst{6...10} = 0;
let Inst{11} = PCRel;
- let Inst{12-13} = 0;
- let Inst{14-31} = D{33-16}; // d0
+ let Inst{12...13} = 0;
+ let Inst{14...31} = D{33...16}; // d0
// The instruction.
- let Inst{38-42} = RST{4-0};
- let Inst{43-47} = RA;
- let Inst{48-63} = D{15-0}; // d1
+ let Inst{38...42} = RST{4...0};
+ let Inst{43...47} = RA;
+ let Inst{48...63} = D{15...0}; // d1
}
// 8LS:D-Form: [ 1 0 0 // R // d0
@@ -298,18 +298,18 @@ class 8LS_DForm_R_SI34_XT6_RA5_MEM<bits<5> opcode, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 0;
+ let Inst{6...7} = 0;
let Inst{8} = 0;
- let Inst{9-10} = 0; // reserved
+ let Inst{9...10} = 0; // reserved
let Inst{11} = PCRel;
- let Inst{12-13} = 0; // reserved
- let Inst{14-31} = D{33-16}; // d0
+ let Inst{12...13} = 0; // reserved
+ let Inst{14...31} = D{33...16}; // d0
// The instruction.
let Inst{37} = XST{5};
- let Inst{38-42} = XST{4-0};
- let Inst{43-47} = RA;
- let Inst{48-63} = D{15-0}; // d1
+ let Inst{38...42} = XST{4...0};
+ let Inst{43...47} = RA;
+ let Inst{48...63} = D{15...0}; // d1
}
// X-Form: [PO T IMM VRB XO TX]
@@ -321,10 +321,10 @@ class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bits<5> IMM;
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = IMM;
- let Inst{16-20} = VRB;
- let Inst{21-30} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = IMM;
+ let Inst{16...20} = VRB;
+ let Inst{21...30} = xo;
let Inst{31} = XT{5};
}
@@ -341,19 +341,19 @@ class 8RR_XX4Form_IMM8_XTAB6<bits<6> opcode, bits<2> xo,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 1;
+ let Inst{6...7} = 1;
let Inst{8} = 0;
- let Inst{9-11} = 0;
- let Inst{12-13} = 0;
- let Inst{14-23} = 0;
- let Inst{24-31} = IMM;
+ let Inst{9...11} = 0;
+ let Inst{12...13} = 0;
+ let Inst{14...23} = 0;
+ let Inst{24...31} = IMM;
// The instruction.
- let Inst{38-42} = XT{4-0};
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-57} = XC{4-0};
- let Inst{58-59} = xo;
+ let Inst{38...42} = XT{4...0};
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...57} = XC{4...0};
+ let Inst{58...59} = xo;
let Inst{60} = XC{5};
let Inst{61} = XA{5};
let Inst{62} = XB{5};
@@ -369,11 +369,11 @@ class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RD;
- let Inst{11-12} = 0;
- let Inst{13-15} = N;
- let Inst{16-20} = VB;
- let Inst{21-31} = xo;
+ let Inst{6...10} = RD;
+ let Inst{11...12} = 0;
+ let Inst{13...15} = N;
+ let Inst{16...20} = VB;
+ let Inst{21...31} = xo;
}
@@ -382,14 +382,14 @@ class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, vrrc:$VB),
!strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
// VX-Form: [PO VRT RA RB XO].
// Destructive (insert) forms are suffixed with _ins.
class VXForm_VRT5_RAB5_ins<bits<11> xo, string opc, list<dag> pattern>
: VXForm_1<xo, (outs vrrc:$VD), (ins vrrc:$VDi, gprc:$VA, gprc:$VB),
!strconcat(opc, " $VD, $VA, $VB"), IIC_VecGeneral, pattern>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
// VX-Form: [ PO BF // VRA VRB XO ]
class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
@@ -401,11 +401,11 @@ class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-8} = BF;
- let Inst{9-10} = 0;
- let Inst{11-15} = VA;
- let Inst{16-20} = VB;
- let Inst{21-31} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = VA;
+ let Inst{16...20} = VB;
+ let Inst{21...31} = xo;
}
// VN-Form: [PO VRT VRA VRB PS SD XO]
@@ -420,12 +420,12 @@ class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = VRT;
- let Inst{11-15} = VRA;
- let Inst{16-20} = VRB;
- let Inst{21-22} = ps;
- let Inst{23-25} = SD;
- let Inst{26-31} = xo;
+ let Inst{6...10} = VRT;
+ let Inst{11...15} = VRA;
+ let Inst{16...20} = VRB;
+ let Inst{21...22} = ps;
+ let Inst{23...25} = SD;
+ let Inst{26...31} = xo;
}
class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,
@@ -437,11 +437,11 @@ class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = RD;
- let Inst{11-14} = eo;
+ let Inst{6...10} = RD;
+ let Inst{11...14} = eo;
let Inst{15} = MP;
- let Inst{16-20} = VB;
- let Inst{21-31} = xo;
+ let Inst{16...20} = VB;
+ let Inst{21...31} = xo;
}
// 8RR:D-Form: [ 1 1 0 // // imm0
@@ -456,17 +456,17 @@ class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 1;
- let Inst{8-11} = 0;
- let Inst{12-13} = 0; // reserved
- let Inst{14-15} = 0; // reserved
- let Inst{16-31} = IMM32{31-16};
+ let Inst{6...7} = 1;
+ let Inst{8...11} = 0;
+ let Inst{12...13} = 0; // reserved
+ let Inst{14...15} = 0; // reserved
+ let Inst{16...31} = IMM32{31...16};
// The instruction.
- let Inst{38-42} = XT{4-0};
- let Inst{43-46} = xo;
+ let Inst{38...42} = XT{4...0};
+ let Inst{43...46} = xo;
let Inst{47} = XT{5};
- let Inst{48-63} = IMM32{15-0};
+ let Inst{48...63} = IMM32{15...0};
}
// 8RR:D-Form: [ 1 1 0 // // imm0
@@ -482,18 +482,18 @@ class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 1;
- let Inst{8-11} = 0;
- let Inst{12-13} = 0; // reserved
- let Inst{14-15} = 0; // reserved
- let Inst{16-31} = IMM32{31-16};
+ let Inst{6...7} = 1;
+ let Inst{8...11} = 0;
+ let Inst{12...13} = 0; // reserved
+ let Inst{14...15} = 0; // reserved
+ let Inst{16...31} = IMM32{31...16};
// The instruction.
- let Inst{38-42} = XT{4-0};
- let Inst{43-45} = xo;
+ let Inst{38...42} = XT{4...0};
+ let Inst{43...45} = xo;
let Inst{46} = IX;
let Inst{47} = XT{5};
- let Inst{48-63} = IMM32{15-0};
+ let Inst{48...63} = IMM32{15...0};
}
class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
@@ -507,17 +507,17 @@ class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 1;
- let Inst{8-11} = 0;
- let Inst{12-13} = 0;
- let Inst{14-31} = 0;
+ let Inst{6...7} = 1;
+ let Inst{8...11} = 0;
+ let Inst{12...13} = 0;
+ let Inst{14...31} = 0;
// The instruction.
- let Inst{38-42} = XT{4-0};
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-57} = XC{4-0};
- let Inst{58-59} = xo;
+ let Inst{38...42} = XT{4...0};
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...57} = XC{4...0};
+ let Inst{58...59} = xo;
let Inst{60} = XC{5};
let Inst{61} = XA{5};
let Inst{62} = XB{5};
@@ -537,18 +537,18 @@ class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 1;
- let Inst{8-11} = 0;
- let Inst{12-13} = 0;
- let Inst{14-28} = 0;
- let Inst{29-31} = IMM;
+ let Inst{6...7} = 1;
+ let Inst{8...11} = 0;
+ let Inst{12...13} = 0;
+ let Inst{14...28} = 0;
+ let Inst{29...31} = IMM;
// The instruction.
- let Inst{38-42} = XT{4-0};
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-57} = XC{4-0};
- let Inst{58-59} = xo;
+ let Inst{38...42} = XT{4...0};
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...57} = XC{4...0};
+ let Inst{58...59} = xo;
let Inst{60} = XC{5};
let Inst{61} = XA{5};
let Inst{62} = XB{5};
@@ -565,11 +565,11 @@ class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
let Pattern = pattern;
- let Inst{6-8} = BF;
- let Inst{9-10} = 0;
- let Inst{11-15} = xo2;
- let Inst{16-20} = XB{4-0};
- let Inst{21-29} = xo;
+ let Inst{6...8} = BF;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = xo2;
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...29} = xo;
let Inst{30} = XB{5};
let Inst{31} = 0;
}
@@ -863,11 +863,11 @@ class DQForm_XTp5_RA17_MEM<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-9} = XTp{3-0};
+ let Inst{6...9} = XTp{3...0};
let Inst{10} = XTp{4};
- let Inst{11-15} = RA;
- let Inst{16-27} = DQ;
- let Inst{28-31} = xo;
+ let Inst{11...15} = RA;
+ let Inst{16...27} = DQ;
+ let Inst{28...31} = xo;
}
class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
@@ -878,11 +878,11 @@ class XForm_XTp5_XAB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
bits<5> RB;
let Pattern = pattern;
- let Inst{6-9} = XTp{3-0};
+ let Inst{6...9} = XTp{3...0};
let Inst{10} = XTp{4};
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-30} = xo;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -896,16 +896,16 @@ class 8LS_DForm_R_XTp5_SI34_MEM<bits<6> opcode, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
// The prefix.
- let Inst{6-10} = 0;
+ let Inst{6...10} = 0;
let Inst{11} = PCRel;
- let Inst{12-13} = 0;
- let Inst{14-31} = D{33-16}; // Imm18
+ let Inst{12...13} = 0;
+ let Inst{14...31} = D{33...16}; // Imm18
// The instruction.
- let Inst{38-41} = XTp{3-0};
+ let Inst{38...41} = XTp{3...0};
let Inst{42} = XTp{4};
- let Inst{43-47} = RA;
- let Inst{48-63} = D{15-0};
+ let Inst{43...47} = RA;
+ let Inst{48...63} = D{15...0};
}
multiclass 8LS_DForm_R_XTp5_SI34_MEM_p<bits<6> opcode, dag OOL,
@@ -935,11 +935,11 @@ class XForm_AT3<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = AT;
- let Inst{9-10} = 0;
- let Inst{11-15} = xo2;
- let Inst{16-20} = 0;
- let Inst{21-30} = xo;
+ let Inst{6...8} = AT;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = xo2;
+ let Inst{16...20} = 0;
+ let Inst{21...30} = xo;
let Inst{31} = 0;
}
@@ -952,10 +952,10 @@ class XForm_XT6_IMM5<bits<6> opcode, bits<5> eo, bits<10> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-10} = XT{4-0};
- let Inst{11-15} = eo;
- let Inst{16-20} = UIM;
- let Inst{21-30} = xo;
+ let Inst{6...10} = XT{4...0};
+ let Inst{11...15} = eo;
+ let Inst{16...20} = UIM;
+ let Inst{21...30} = xo;
let Inst{31} = XT{5};
}
@@ -969,11 +969,11 @@ class XX3Form_AT3_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
- let Inst{6-8} = AT;
- let Inst{9-10} = 0;
- let Inst{11-15} = XA{4-0};
- let Inst{16-20} = XB{4-0};
- let Inst{21-28} = xo;
+ let Inst{6...8} = AT;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = XA{4...0};
+ let Inst{16...20} = XB{4...0};
+ let Inst{21...28} = xo;
let Inst{29} = XA{5};
let Inst{30} = XB{5};
let Inst{31} = 0;
@@ -993,20 +993,20 @@ class MMIRR_XX3Form_XY4P2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 3;
- let Inst{8-11} = 9;
- let Inst{12-15} = 0;
- let Inst{16-17} = PMSK;
- let Inst{18-23} = 0;
- let Inst{24-27} = XMSK;
- let Inst{28-31} = YMSK;
+ let Inst{6...7} = 3;
+ let Inst{8...11} = 9;
+ let Inst{12...15} = 0;
+ let Inst{16...17} = PMSK;
+ let Inst{18...23} = 0;
+ let Inst{24...27} = XMSK;
+ let Inst{28...31} = YMSK;
// The instruction.
- let Inst{38-40} = AT;
- let Inst{41-42} = 0;
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-60} = xo;
+ let Inst{38...40} = AT;
+ let Inst{41...42} = 0;
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...60} = xo;
let Inst{61} = XA{5};
let Inst{62} = XB{5};
let Inst{63} = 0;
@@ -1025,18 +1025,18 @@ class MMIRR_XX3Form_XY4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 3;
- let Inst{8-11} = 9;
- let Inst{12-23} = 0;
- let Inst{24-27} = XMSK;
- let Inst{28-31} = YMSK;
+ let Inst{6...7} = 3;
+ let Inst{8...11} = 9;
+ let Inst{12...23} = 0;
+ let Inst{24...27} = XMSK;
+ let Inst{28...31} = YMSK;
// The instruction.
- let Inst{38-40} = AT;
- let Inst{41-42} = 0;
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-60} = xo;
+ let Inst{38...40} = AT;
+ let Inst{41...42} = 0;
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...60} = xo;
let Inst{61} = XA{5};
let Inst{62} = XB{5};
let Inst{63} = 0;
@@ -1055,19 +1055,19 @@ class MMIRR_XX3Form_X4Y2_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 3;
- let Inst{8-11} = 9;
- let Inst{12-23} = 0;
- let Inst{24-27} = XMSK;
- let Inst{28-29} = YMSK;
- let Inst{30-31} = 0;
+ let Inst{6...7} = 3;
+ let Inst{8...11} = 9;
+ let Inst{12...23} = 0;
+ let Inst{24...27} = XMSK;
+ let Inst{28...29} = YMSK;
+ let Inst{30...31} = 0;
// The instruction.
- let Inst{38-40} = AT;
- let Inst{41-42} = 0;
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-60} = xo;
+ let Inst{38...40} = AT;
+ let Inst{41...42} = 0;
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...60} = xo;
let Inst{61} = XA{5};
let Inst{62} = XB{5};
let Inst{63} = 0;
@@ -1087,19 +1087,19 @@ class MMIRR_XX3Form_XY4P8_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 3;
- let Inst{8-11} = 9;
- let Inst{12-15} = 0;
- let Inst{16-23} = PMSK;
- let Inst{24-27} = XMSK;
- let Inst{28-31} = YMSK;
+ let Inst{6...7} = 3;
+ let Inst{8...11} = 9;
+ let Inst{12...15} = 0;
+ let Inst{16...23} = PMSK;
+ let Inst{24...27} = XMSK;
+ let Inst{28...31} = YMSK;
// The instruction.
- let Inst{38-40} = AT;
- let Inst{41-42} = 0;
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-60} = xo;
+ let Inst{38...40} = AT;
+ let Inst{41...42} = 0;
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...60} = xo;
let Inst{61} = XA{5};
let Inst{62} = XB{5};
let Inst{63} = 0;
@@ -1119,20 +1119,20 @@ class MMIRR_XX3Form_XYP4_XAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
let Pattern = pattern;
// The prefix.
- let Inst{6-7} = 3;
- let Inst{8-11} = 9;
- let Inst{12-15} = 0;
- let Inst{16-19} = PMSK;
- let Inst{20-23} = 0;
- let Inst{24-27} = XMSK;
- let Inst{28-31} = YMSK;
+ let Inst{6...7} = 3;
+ let Inst{8...11} = 9;
+ let Inst{12...15} = 0;
+ let Inst{16...19} = PMSK;
+ let Inst{20...23} = 0;
+ let Inst{24...27} = XMSK;
+ let Inst{28...31} = YMSK;
// The instruction.
- let Inst{38-40} = AT;
- let Inst{41-42} = 0;
- let Inst{43-47} = XA{4-0};
- let Inst{48-52} = XB{4-0};
- let Inst{53-60} = xo;
+ let Inst{38...40} = AT;
+ let Inst{41...42} = 0;
+ let Inst{43...47} = XA{4...0};
+ let Inst{48...52} = XB{4...0};
+ let Inst{53...60} = xo;
let Inst{61} = XA{5};
let Inst{62} = XB{5};
let Inst{63} = 0;
@@ -1395,7 +1395,7 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, Predicates = [P
[(set v2i64:$XT,
(PPCxxsplti32dx v2i64:$XTi, i32:$IX,
i32:$IMM32))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+ RegConstraint<"$XTi = $XT">;
}
let Predicates = [IsISA3_1] in {
@@ -1466,13 +1466,13 @@ let Predicates = [IsISA3_1] in {
"vinsw $VD, $VB, $VA", IIC_VecGeneral,
[(set v4i32:$VD,
(int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VINSD :
VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB),
"vinsd $VD, $VB, $VA", IIC_VecGeneral,
[(set v2i64:$VD,
(int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VINSBVLX :
VXForm_VTB5_RA5_ins<15, "vinsbvlx",
[(set v16i8:$VD,
@@ -1538,13 +1538,13 @@ let Predicates = [IsISA3_1] in {
"vinsdlx $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$VD,
(int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VINSDRX :
VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB),
"vinsdrx $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$VD,
(int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB),
"vextractbm $VD, $VB", IIC_VecGeneral,
[(set i32:$VD,
@@ -1915,10 +1915,11 @@ let Predicates = [IsISA3_1] in {
[(set v1i128:$VD,
(int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB,
v1i128:$VDi))]>,
- RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">;
+ RegConstraint<"$VDi = $VD">;
def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
- def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
+ def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq",
+ [(set v4i32:$VD, (PPCvsrq v4i32:$VA, v4i32:$VB))]>;
def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
@@ -2053,6 +2054,9 @@ let Predicates = [IsISA3_1, HasFPU] in {
//---------------------------- Anonymous Patterns ----------------------------//
let Predicates = [IsISA3_1] in {
+ // Exploit vsrq instruction to optimize VSR(VSRO (input, vsro_byte_shift), vsr_bit_shift)
+ // to VSRQ(input, vsrq_bit_shift)
+ def : Pat<(VSRVSRO v4i32:$vA, v4i32:$vB), (VSRQ $vA, $vB)>;
// Exploit the vector multiply high instructions using intrinsics.
def : Pat<(v4i32 (int_ppc_altivec_vmulhsw v4i32:$vA, v4i32:$vB)),
(v4i32 (VMULHSW $vA, $vB))>;
@@ -2230,6 +2234,13 @@ def VEqv
(v4i32(bitconvert node:$a)),
(v4i32(bitconvert node:$b)))))]>;
+// Vector NAND operation (not(and))
+def VNand
+ : PatFrags<(ops node:$a, node:$b), [(vnot(and node:$a, node:$b)),
+ (bitconvert(vnot(and
+ (v4i32(bitconvert node:$a)),
+ (v4i32(bitconvert node:$b)))))]>;
+
// =============================================================================
// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectAnd
// This class matches the equivalent Ternary Operation: A ? f(B,C) : AND(B,C)
@@ -2265,6 +2276,56 @@ multiclass XXEvalTernarySelectAnd<ValueType Vt> {
Vt, (vselect Vt:$vA, (VNot Vt:$vB), (VAnd Vt:$vB, Vt:$vC)), 28>;
}
+// =============================================================================
+// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectB
+// This class matches the equivalent Ternary Operation: A ? f(B,C) : B
+// and emit the corresponding xxeval instruction with the imm value.
+//
+// The patterns implement xxeval vector select operations where:
+// - A is the selector vector
+// - f(B,C) is the "true" case op on vectors B and C (AND, NOR, EQV, NAND)
+// - B is the "false" case operand (vector B)
+//
+// Note: Patterns (A? C : B) and (A? not(C) : B) are not considered
+// for XXEVAL instruction (4 Cycle) as XXSEL (3 cycle) instruction performs
+// better.
+// =============================================================================
+multiclass XXEvalTernarySelectB<ValueType Vt>{
+ // Pattern: (A ? AND(B,C) : B) XXEVAL immediate value: 49
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), Vt:$vB), 49>;
+ // Pattern: (A ? NOR(B,C) : B) XXEVAL immediate value: 56
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNor Vt:$vB, Vt:$vC), Vt:$vB), 56>;
+ // Pattern: (A ? EQV(B,C) : B) XXEVAL immediate value: 57
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VEqv Vt:$vB, Vt:$vC), Vt:$vB), 57>;
+ // Pattern: (A ? NAND(B,C) : B) XXEVAL immediate value: 62
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), Vt:$vB), 62>;
+}
+
+// =============================================================================
+// XXEVAL Ternary Pattern Multiclass: XXEvalTernarySelectC
+// This class matches the equivalent Ternary Operation: A ? f(B,C) : C
+// and emit the corresponding xxeval instruction with the imm value.
+//
+// The patterns implement xxeval vector select operations where:
+// - A is the selector vector
+// - f(B,C) is the "true" case op on vectors B and C (AND, NOR, EQV, NAND)
+// - C is the "false" case operand (vector C)
+//
+// Note: Patterns (A? B : C) and (A? not(B) : C) are not considered
+// for XXEVAL instruction (4 Cycle) as XXSEL (3 cycle) instruction performs
+// better.
+// =============================================================================
+multiclass XXEvalTernarySelectC<ValueType Vt>{
+ // Pattern: (A ? AND(B,C) : C) XXEVAL immediate value: 81
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VAnd Vt:$vB, Vt:$vC), Vt:$vC), 81>;
+ // Pattern: (A ? NOR(B,C) : C) XXEVAL immediate value: 88
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNor Vt:$vB, Vt:$vC), Vt:$vC), 88>;
+ // Pattern: (A ? EQV(B,C) : C) XXEVAL immediate value: 89
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VEqv Vt:$vB, Vt:$vC), Vt:$vC), 89>;
+ // Pattern: (A ? NAND(B,C) : C) XXEVAL immediate value: 94
+ def : XXEvalPattern<Vt, (vselect Vt:$vA, (VNand Vt:$vB, Vt:$vC), Vt:$vC), 94>;
+}
+
let Predicates = [PrefixInstrs, HasP10Vector] in {
let AddedComplexity = 400 in {
def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
@@ -2376,6 +2437,8 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
// XXEval Patterns for ternary Operations.
foreach Ty = [v4i32, v2i64, v8i16, v16i8] in {
defm : XXEvalTernarySelectAnd<Ty>;
+ defm : XXEvalTernarySelectB<Ty>;
+ defm : XXEvalTernarySelectC<Ty>;
}
// Anonymous patterns to select prefixed VSX loads and stores.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrSPE.td b/llvm/lib/Target/PowerPC/PPCInstrSPE.td
index e91cae349e08..5104cc6f5607 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrSPE.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrSPE.td
@@ -20,10 +20,10 @@ class EFXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-31} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...31} = xo;
}
class EFXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
@@ -45,11 +45,11 @@ class EFXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
bits<5> RA;
bits<5> RB;
- let Inst{6-8} = crD;
- let Inst{9-10} = 0;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-31} = xo;
+ let Inst{6...8} = crD;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...31} = xo;
}
class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
@@ -61,10 +61,10 @@ class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-31} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...31} = xo;
}
class EVXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
@@ -88,11 +88,11 @@ class EVXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-8} = crD;
- let Inst{9-10} = 0;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-31} = xo;
+ let Inst{6...8} = crD;
+ let Inst{9...10} = 0;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...31} = xo;
}
class EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr,
@@ -105,11 +105,11 @@ class EVXForm_4<bits<8> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = RB;
- let Inst{21-28} = xo;
- let Inst{29-31} = crD;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = RB;
+ let Inst{21...28} = xo;
+ let Inst{29...31} = crD;
}
class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
@@ -121,10 +121,10 @@ class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Pattern = pattern;
- let Inst{6-10} = RT;
- let Inst{11-15} = RA;
- let Inst{16-20} = D;
- let Inst{21-31} = xo;
+ let Inst{6...10} = RT;
+ let Inst{11...15} = RA;
+ let Inst{16...20} = D;
+ let Inst{21...31} = xo;
}
let DecoderNamespace = "SPE", Predicates = [HasSPE] in {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 19448210f5db..4e5165bfcda5 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -236,7 +236,7 @@ class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc,
list<dag> pattern>
: XForm_1<opcode, xo, (outs vrrc:$RST), (ins vrrc:$RSTi, vrrc:$RA, vrrc:$RB),
!strconcat(opc, " $RST, $RA, $RB"), IIC_VecFP, pattern>,
- RegConstraint<"$RSTi = $RST">, NoEncode<"$RSTi">;
+ RegConstraint<"$RSTi = $RST">;
// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc,
@@ -402,13 +402,13 @@ let hasSideEffects = 0 in {
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsmaddadp $XT, $XA, $XB", IIC_VecFP,
[(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XSMADDMDP : XX3Form<60, 41,
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -418,13 +418,13 @@ let hasSideEffects = 0 in {
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsmsubadp $XT, $XA, $XB", IIC_VecFP,
[(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XSMSUBMDP : XX3Form<60, 57,
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -434,13 +434,13 @@ let hasSideEffects = 0 in {
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
[(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XSNMADDMDP : XX3Form<60, 169,
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -450,13 +450,13 @@ let hasSideEffects = 0 in {
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
[(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XSNMSUBMDP : XX3Form<60, 185,
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -466,13 +466,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmaddadp $XT, $XA, $XB", IIC_VecFP,
[(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVMADDMDP : XX3Form<60, 105,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -482,13 +482,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmaddasp $XT, $XA, $XB", IIC_VecFP,
[(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVMADDMSP : XX3Form<60, 73,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -498,13 +498,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmsubadp $XT, $XA, $XB", IIC_VecFP,
[(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVMSUBMDP : XX3Form<60, 121,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -514,13 +514,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmsubasp $XT, $XA, $XB", IIC_VecFP,
[(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVMSUBMSP : XX3Form<60, 89,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -530,13 +530,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
[(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVNMADDMDP : XX3Form<60, 233,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -546,13 +546,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
[(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVNMADDMSP : XX3Form<60, 201,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -562,13 +562,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
[(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVNMSUBMDP : XX3Form<60, 249,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -578,13 +578,13 @@ let hasSideEffects = 0 in {
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
[(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
let IsVSXFMAAlt = 1 in
def XVNMSUBMSP : XX3Form<60, 217,
(outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
"xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -1199,7 +1199,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
(ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
"xsmaddasp $XT, $XA, $XB", IIC_VecFP,
[(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
let IsVSXFMAAlt = 1, hasSideEffects = 1 in
@@ -1207,7 +1207,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
(outs vssrc:$XT),
(ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
"xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -1219,7 +1219,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
"xsmsubasp $XT, $XA, $XB", IIC_VecFP,
[(set f32:$XT, (any_fma f32:$XA, f32:$XB,
(fneg f32:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
let IsVSXFMAAlt = 1, hasSideEffects = 1 in
@@ -1227,7 +1227,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
(outs vssrc:$XT),
(ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
"xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -1239,7 +1239,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
"xsnmaddasp $XT, $XA, $XB", IIC_VecFP,
[(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
f32:$XTi)))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
let IsVSXFMAAlt = 1, hasSideEffects = 1 in
@@ -1247,7 +1247,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
(outs vssrc:$XT),
(ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
"xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -1259,7 +1259,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
"xsnmsubasp $XT, $XA, $XB", IIC_VecFP,
[(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
(fneg f32:$XTi))))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
let IsVSXFMAAlt = 1, hasSideEffects = 1 in
@@ -1267,7 +1267,7 @@ let Predicates = [HasVSX, HasP8Vector] in {
(outs vssrc:$XT),
(ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
"xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
AltVSXFMARel;
}
@@ -1563,7 +1563,7 @@ let Predicates = [HasVSX, HasP9Vector] in {
"xxinsertw $XT, $XB, $UIM5", IIC_VecFP,
[(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB,
imm32SExt16:$UIM5))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+ RegConstraint<"$XTi = $XT">;
// Vector Extract Unsigned Word
// FIXME: Setting the hasSideEffects flag here to match current behaviour.
@@ -1652,11 +1652,11 @@ let Predicates = [HasVSX, HasP9Vector] in {
def XXPERM : XX3Form<60, 26, (outs vsrc:$XT),
(ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),
"xxperm $XT, $XA, $XB", IIC_VecPerm, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+ RegConstraint<"$XTi = $XT">;
def XXPERMR : XX3Form<60, 58, (outs vsrc:$XT),
(ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),
"xxpermr $XT, $XA, $XB", IIC_VecPerm, []>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+ RegConstraint<"$XTi = $XT">;
// Vector Splat Immediate Byte
def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 996b6efb320d..736ba1edcaea 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -52,12 +52,11 @@ PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
return *this;
}
-PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
- const std::string &TuneCPU, const std::string &FS,
- const PPCTargetMachine &TM)
- : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS), TargetTriple(TT),
- IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
- TargetTriple.getArch() == Triple::ppc64le),
+PPCSubtarget::PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
+ StringRef FS, const PPCTargetMachine &TM)
+ : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS),
+ IsPPC64(getTargetTriple().getArch() == Triple::ppc64 ||
+ getTargetTriple().getArch() == Triple::ppc64le),
TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
InstrInfo(*this), TLInfo(TM, *this) {
TSInfo = std::make_unique<PPCSelectionDAGInfo>();
@@ -87,10 +86,10 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
// Determine default and user specified characteristics
std::string CPUName = std::string(CPU);
if (CPUName.empty() || CPU == "generic") {
- if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
+ if (getTargetTriple().getSubArch() == Triple::PPCSubArch_spe)
CPUName = "e500";
else
- CPUName = std::string(PPC::getNormalizedPPCTargetCPU(TargetTriple));
+ CPUName = std::string(PPC::getNormalizedPPCTargetCPU(getTargetTriple()));
}
// Determine the CPU to schedule for.
@@ -107,7 +106,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
if (IsPPC64 && has64BitSupport())
Use64BitRegs = true;
- if (TargetTriple.isPPC32SecurePlt())
+ if (getTargetTriple().isPPC32SecurePlt())
IsSecurePlt = true;
if (HasSPE && IsPPC64)
@@ -126,7 +125,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
IsLittleEndian = TM.isLittleEndian();
if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {
- if (!TargetTriple.isOSAIX() || !IsPPC64)
+ if (!getTargetTriple().isOSAIX() || !IsPPC64)
report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "
"only supported on AIX in "
"64-bit mode.\n",
@@ -143,7 +142,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
false);
}
- if (HasAIXShLibTLSModelOpt && (!TargetTriple.isOSAIX() || !IsPPC64))
+ if (HasAIXShLibTLSModelOpt && (!getTargetTriple().isOSAIX() || !IsPPC64))
report_fatal_error("The aix-shared-lib-tls-model-opt attribute "
"is only supported on AIX in 64-bit mode.\n",
false);
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index 3c59a475c7eb..c17fca7f70a3 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -78,9 +78,6 @@ public:
};
protected:
- /// TargetTriple - What processor and OS we're targeting.
- Triple TargetTriple;
-
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
Align StackAlignment;
@@ -119,8 +116,7 @@ public:
/// This constructor initializes the data members to match that
/// of the specified triple.
///
- PPCSubtarget(const Triple &TT, const std::string &CPU,
- const std::string &TuneCPU, const std::string &FS,
+ PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
const PPCTargetMachine &TM);
~PPCSubtarget() override;
@@ -210,13 +206,11 @@ public:
POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
- const Triple &getTargetTriple() const { return TargetTriple; }
-
- bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
- bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
- bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
+ bool isTargetELF() const { return getTargetTriple().isOSBinFormatELF(); }
+ bool isTargetMachO() const { return getTargetTriple().isOSBinFormatMachO(); }
+ bool isTargetLinux() const { return getTargetTriple().isOSLinux(); }
- bool isAIXABI() const { return TargetTriple.isOSAIX(); }
+ bool isAIXABI() const { return getTargetTriple().isOSAIX(); }
bool isSVR4ABI() const { return !isAIXABI(); }
bool isELFv2ABI() const;
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index b5c6ac111dff..ae92d5eab20c 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -129,7 +129,7 @@ LLVMInitializePowerPCTarget() {
initializePPCLoopInstrFormPrepPass(PR);
initializePPCTOCRegDepsPass(PR);
initializePPCEarlyReturnPass(PR);
- initializePPCVSXCopyPass(PR);
+ initializePPCVSXWACCCopyPass(PR);
initializePPCVSXFMAMutatePass(PR);
initializePPCVSXSwapRemovalPass(PR);
initializePPCReduceCRLogicalsPass(PR);
@@ -528,7 +528,7 @@ bool PPCPassConfig::addInstSelector() {
addPass(createPPCCTRLoopsVerify());
#endif
- addPass(createPPCVSXCopyPass());
+ addPass(createPPCVSXWACCCopyPass());
return false;
}
diff --git a/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp b/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
deleted file mode 100644
index 794095cd4376..000000000000
--- a/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
+++ /dev/null
@@ -1,159 +0,0 @@
-//===-------------- PPCVSXCopy.cpp - VSX Copy Legalization ----------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// A pass which deals with the complexity of generating legal VSX register
-// copies to/from register classes which partially overlap with the VSX
-// register file.
-//
-//===----------------------------------------------------------------------===//
-
-#include "PPC.h"
-#include "PPCInstrInfo.h"
-#include "PPCTargetMachine.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/ErrorHandling.h"
-
-using namespace llvm;
-
-#define DEBUG_TYPE "ppc-vsx-copy"
-
-namespace {
- // PPCVSXCopy pass - For copies between VSX registers and non-VSX registers
- // (Altivec and scalar floating-point registers), we need to transform the
- // copies into subregister copies with other restrictions.
- struct PPCVSXCopy : public MachineFunctionPass {
- static char ID;
- PPCVSXCopy() : MachineFunctionPass(ID) {}
-
- const TargetInstrInfo *TII;
-
- bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
- MachineRegisterInfo &MRI) {
- if (Register::isVirtualRegister(Reg)) {
- return RC->hasSubClassEq(MRI.getRegClass(Reg));
- } else if (RC->contains(Reg)) {
- return true;
- }
-
- return false;
- }
-
- bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) {
- return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
- }
-
- bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) {
- return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
- }
-
- bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) {
- return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI);
- }
-
- bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) {
- return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI);
- }
-
- bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) {
- return IsRegInClass(Reg, &PPC::VSSRCRegClass, MRI);
- }
-
-protected:
- bool processBlock(MachineBasicBlock &MBB) {
- bool Changed = false;
-
- MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
- for (MachineInstr &MI : MBB) {
- if (!MI.isFullCopy())
- continue;
-
- MachineOperand &DstMO = MI.getOperand(0);
- MachineOperand &SrcMO = MI.getOperand(1);
-
- if ( IsVSReg(DstMO.getReg(), MRI) &&
- !IsVSReg(SrcMO.getReg(), MRI)) {
- // This is a copy *to* a VSX register from a non-VSX register.
- Changed = true;
-
- const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass;
- assert((IsF8Reg(SrcMO.getReg(), MRI) ||
- IsVSSReg(SrcMO.getReg(), MRI) ||
- IsVSFReg(SrcMO.getReg(), MRI)) &&
- "Unknown source for a VSX copy");
-
- Register NewVReg = MRI.createVirtualRegister(SrcRC);
- BuildMI(MBB, MI, MI.getDebugLoc(),
- TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
- .addImm(1) // add 1, not 0, because there is no implicit clearing
- // of the high bits.
- .add(SrcMO)
- .addImm(PPC::sub_64);
-
- // The source of the original copy is now the new virtual register.
- SrcMO.setReg(NewVReg);
- } else if (!IsVSReg(DstMO.getReg(), MRI) &&
- IsVSReg(SrcMO.getReg(), MRI)) {
- // This is a copy *from* a VSX register to a non-VSX register.
- Changed = true;
-
- const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass;
- assert((IsF8Reg(DstMO.getReg(), MRI) ||
- IsVSFReg(DstMO.getReg(), MRI) ||
- IsVSSReg(DstMO.getReg(), MRI)) &&
- "Unknown destination for a VSX copy");
-
- // Copy the VSX value into a new VSX register of the correct subclass.
- Register NewVReg = MRI.createVirtualRegister(DstRC);
- BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
- NewVReg)
- .add(SrcMO);
-
- // Transform the original copy into a subregister extraction copy.
- SrcMO.setReg(NewVReg);
- SrcMO.setSubReg(PPC::sub_64);
- }
- }
-
- return Changed;
- }
-
-public:
- bool runOnMachineFunction(MachineFunction &MF) override {
- // If we don't have VSX on the subtarget, don't do anything.
- const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
- if (!STI.hasVSX())
- return false;
- TII = STI.getInstrInfo();
-
- bool Changed = false;
-
- for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
- if (processBlock(B))
- Changed = true;
-
- return Changed;
- }
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- MachineFunctionPass::getAnalysisUsage(AU);
- }
- };
- } // end anonymous namespace
-
-INITIALIZE_PASS(PPCVSXCopy, DEBUG_TYPE,
- "PowerPC VSX Copy Legalization", false, false)
-
-char PPCVSXCopy::ID = 0;
-FunctionPass*
-llvm::createPPCVSXCopyPass() { return new PPCVSXCopy(); }
diff --git a/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp b/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp
new file mode 100644
index 000000000000..2ec566ddb0b8
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp
@@ -0,0 +1,182 @@
+//===--------- PPCVSXWACCCopy.cpp - VSX and WACC Copy Legalization --------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// A pass which deals with the complexity of generating legal VSX register
+// copies to/from register classes which partially overlap with the VSX
+// register file and combines the wacc/wacc_hi copies when needed.
+//
+//===----------------------------------------------------------------------===//
+
+#include "PPC.h"
+#include "PPCInstrInfo.h"
+#include "PPCTargetMachine.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ppc-vsx-copy"
+
+namespace {
+// PPCVSXWACCCopy pass - For copies between VSX registers and non-VSX registers
+// (Altivec and scalar floating-point registers), we need to transform the
+// copies into subregister copies with other restrictions.
+struct PPCVSXWACCCopy : public MachineFunctionPass {
+ static char ID;
+ PPCVSXWACCCopy() : MachineFunctionPass(ID) {}
+
+ const TargetInstrInfo *TII;
+
+ bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
+ MachineRegisterInfo &MRI) {
+ if (Register::isVirtualRegister(Reg)) {
+ return RC->hasSubClassEq(MRI.getRegClass(Reg));
+ } else if (RC->contains(Reg)) {
+ return true;
+ }
+
+ return false;
+ }
+
+ bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) {
+ return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
+ }
+
+ bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) {
+ return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
+ }
+
+ bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) {
+ return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI);
+ }
+
+ bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) {
+ return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI);
+ }
+
+ bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) {
+ return IsRegInClass(Reg, &PPC::VSSRCRegClass, MRI);
+ }
+
+protected:
+ bool processBlock(MachineBasicBlock &MBB) {
+ bool Changed = false;
+
+ MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
+ for (MachineInstr &MI : MBB) {
+ if (!MI.isFullCopy())
+ continue;
+
+ MachineOperand &DstMO = MI.getOperand(0);
+ MachineOperand &SrcMO = MI.getOperand(1);
+
+ if (IsVSReg(DstMO.getReg(), MRI) && !IsVSReg(SrcMO.getReg(), MRI)) {
+ // This is a copy *to* a VSX register from a non-VSX register.
+ Changed = true;
+
+ const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass;
+ assert((IsF8Reg(SrcMO.getReg(), MRI) || IsVSSReg(SrcMO.getReg(), MRI) ||
+ IsVSFReg(SrcMO.getReg(), MRI)) &&
+ "Unknown source for a VSX copy");
+
+ Register NewVReg = MRI.createVirtualRegister(SrcRC);
+ BuildMI(MBB, MI, MI.getDebugLoc(),
+ TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
+ .addImm(1) // add 1, not 0, because there is no implicit clearing
+ // of the high bits.
+ .add(SrcMO)
+ .addImm(PPC::sub_64);
+
+ // The source of the original copy is now the new virtual register.
+ SrcMO.setReg(NewVReg);
+ } else if (!IsVSReg(DstMO.getReg(), MRI) &&
+ IsVSReg(SrcMO.getReg(), MRI)) {
+ // This is a copy *from* a VSX register to a non-VSX register.
+ Changed = true;
+
+ const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass;
+ assert((IsF8Reg(DstMO.getReg(), MRI) || IsVSFReg(DstMO.getReg(), MRI) ||
+ IsVSSReg(DstMO.getReg(), MRI)) &&
+ "Unknown destination for a VSX copy");
+
+ // Copy the VSX value into a new VSX register of the correct subclass.
+ Register NewVReg = MRI.createVirtualRegister(DstRC);
+ BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
+ NewVReg)
+ .add(SrcMO);
+
+ // Transform the original copy into a subregister extraction copy.
+ SrcMO.setReg(NewVReg);
+ SrcMO.setSubReg(PPC::sub_64);
+ } else if (IsRegInClass(DstMO.getReg(), &PPC::WACC_HIRCRegClass, MRI) &&
+ IsRegInClass(SrcMO.getReg(), &PPC::WACCRCRegClass, MRI)) {
+ // Matches the pattern:
+ // %a:waccrc = COPY %b.sub_wacc_hi:dmrrc
+ // %c:wacc_hirc = COPY %a:waccrc
+ // And replaces it with:
+ // %c:wacc_hirc = COPY %b.sub_wacc_hi:dmrrc
+ MachineInstr *DefMI = MRI.getUniqueVRegDef(SrcMO.getReg());
+ if (!DefMI || !DefMI->isCopy())
+ continue;
+
+ MachineOperand &OrigSrc = DefMI->getOperand(1);
+
+ if (!IsRegInClass(OrigSrc.getReg(), &PPC::DMRRCRegClass, MRI))
+ continue;
+
+ if (OrigSrc.getSubReg() != PPC::sub_wacc_hi)
+ continue;
+
+ // Rewrite the second copy to use the original register's subreg
+ SrcMO.setReg(OrigSrc.getReg());
+ SrcMO.setSubReg(PPC::sub_wacc_hi);
+ Changed = true;
+
+ // Remove the intermediate copy if safe
+ if (MRI.use_nodbg_empty(DefMI->getOperand(0).getReg()))
+ DefMI->eraseFromParent();
+ }
+ }
+
+ return Changed;
+ }
+
+public:
+ bool runOnMachineFunction(MachineFunction &MF) override {
+ // If we don't have VSX on the subtarget, don't do anything.
+ const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
+ if (!STI.hasVSX())
+ return false;
+ TII = STI.getInstrInfo();
+
+ bool Changed = false;
+
+ for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
+ if (processBlock(B))
+ Changed = true;
+
+ return Changed;
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+} // end anonymous namespace
+
+INITIALIZE_PASS(PPCVSXWACCCopy, DEBUG_TYPE, "PowerPC VSX Copy Legalization",
+ false, false)
+
+char PPCVSXWACCCopy::ID = 0;
+FunctionPass *llvm::createPPCVSXWACCCopyPass() { return new PPCVSXWACCCopy(); }
diff --git a/llvm/lib/Target/PowerPC/README_P9.txt b/llvm/lib/Target/PowerPC/README_P9.txt
index ee1ea735acad..208c8abfdc5f 100644
--- a/llvm/lib/Target/PowerPC/README_P9.txt
+++ b/llvm/lib/Target/PowerPC/README_P9.txt
@@ -224,22 +224,22 @@ VSX:
. isCommutable = 1
// xsmaddqp
[(set f128:$vT, (fma f128:$vA, f128:$vB, f128:$vTi))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
// xsmsubqp
[(set f128:$vT, (fma f128:$vA, f128:$vB, (fneg f128:$vTi)))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
// xsnmaddqp
[(set f128:$vT, (fneg (fma f128:$vA, f128:$vB, f128:$vTi)))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
// xsnmsubqp
[(set f128:$vT, (fneg (fma f128:$vA, f128:$vB, (fneg f128:$vTi))))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
- Round to Odd of QP (Negative) Multiply-{Add/Subtract}:
@@ -276,22 +276,22 @@ VSX:
. isCommutable = 1
// xsmaddqpo
[(set f128:$vT, (PPCfmarto f128:$vA, f128:$vB, f128:$vTi))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
// xsmsubqpo
[(set f128:$vT, (PPCfmarto f128:$vA, f128:$vB, (fneg f128:$vTi)))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
// xsnmaddqpo
[(set f128:$vT, (fneg (PPCfmarto f128:$vA, f128:$vB, f128:$vTi)))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
// xsnmsubqpo
[(set f128:$vT, (fneg (PPCfmarto f128:$vA, f128:$vB, (fneg f128:$vTi))))]>,
- RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">,
+ RegConstraint<"$vTi = $vT">,
AltVSXFMARel;
- QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
@@ -405,7 +405,7 @@ Fixed Point Facility:
But how to map to it??
[(set v1f128:$XT, (insertelement v1f128:$XTi, f128:$XB, i4:$UIMM))]>,
- RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
+ RegConstraint<"$XTi = $XT">,
. Or use intrinsic?
(set v1f128:$XT, (int_ppc_vsx_xxinsertw v1f128:$XTi, f128:$XB, i4:$UIMM))
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-01 09:14:10 +0000