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| author | Mehdi Amini <joker.eph@gmail.com> | 2025-08-14 15:36:46 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-14 15:36:46 +0200 |
| commit | df57d6a01e85ca78da2febab21b268d9fd6955a0 (patch) | |
| tree | 19b0aab453e6bc7e2b15d3220024dfdacd4fa57e /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | df86ea61b7ed484ca797f96d7ad40fd9ada7ba30 (diff) | |
| parent | 7bda76367f19cfc19086f68d9dd5ac019a9ceccd (diff) | |
Merge branch 'main' into users/joker-eph-python-bindings-maintainersusers/joker-eph-python-bindings-maintainers
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 2e76225bbc54..f58fde421f77 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -16894,6 +16894,11 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_, const TargetRegisterClass *RC = nullptr; if (Constraint.size() == 1) { + // Check if we cannot determine the bit size of the given value type. This + // can happen, for example, in this situation where we have an empty struct + // (size 0): `call void asm "", "v"({} poison)`- + if (VT == MVT::Other) + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); const unsigned BitWidth = VT.getSizeInBits(); switch (Constraint[0]) { default: |