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| author | Fangrui Song <i@maskray.me> | 2025-06-20 20:13:04 -0700 |
|---|---|---|
| committer | Fangrui Song <i@maskray.me> | 2025-06-20 20:13:04 -0700 |
| commit | 95fbfc9be5d2842a945c04a20fe6244df9b10e18 (patch) | |
| tree | 00f80558d11aa5805e6d6f290663c6da44e5e6ef /llvm/lib/Target/AMDGPU/SIISelLowering.cpp | |
| parent | a9ba028b98ffd53d9c7d00ca7563d74810fcf6e7 (diff) | |
| parent | 17e8465a3eb0cae48b9f62d27fd26f2b070f1f9b (diff) | |
[𝘀𝗽𝗿] changes introduced through rebaseusers/MaskRay/spr/main.move-relocation-specifier-constants-to-aarch64
Created using spr 1.3.5-bogner
[skip ci]
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 586de433ea28..3281eabcd4ad 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5423,6 +5423,14 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MI.eraseFromParent(); return BB; } + case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM: { + // Set SCC to true, in case the barrier instruction gets converted to a NOP. + BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(), + TII->get(AMDGPU::S_CMP_EQ_U32)) + .addImm(0) + .addImm(0); + return BB; + } case AMDGPU::GET_GROUPSTATICSIZE: { assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL); @@ -10858,7 +10866,7 @@ SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { (AS == AMDGPUAS::GLOBAL_ADDRESS && Subtarget->getScalarizeGlobalBehavior() && Load->isSimple() && isMemOpHasNoClobberedMemOperand(Load))) { - if ((!Op->isDivergent() || AMDGPUInstrInfo::isUniformMMO(MMO)) && + if ((!Op->isDivergent() || AMDGPU::isUniformMMO(MMO)) && Alignment >= Align(4) && NumElements < 32) { if (MemVT.isPow2VectorType() || (Subtarget->hasScalarDwordx3Loads() && NumElements == 3)) @@ -15181,6 +15189,12 @@ SDValue SITargetLowering::performFMulCombine(SDNode *N, EVT ScalarVT = VT.getScalarType(); EVT IntVT = VT.changeElementType(MVT::i32); + if (!N->isDivergent() && getSubtarget()->hasSALUFloatInsts() && + (ScalarVT == MVT::f32 || ScalarVT == MVT::f16)) { + // Prefer to use s_mul_f16/f32 instead of v_ldexp_f16/f32. + return SDValue(); + } + SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); |