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authorAiden Grossman <aidengrossman@google.com>2025-09-26 22:48:22 +0000
committerAiden Grossman <aidengrossman@google.com>2025-09-26 22:48:22 +0000
commit76533872e149395812a6d1651aa49dbf53fb4921 (patch)
tree199a669fa57a4effc3116705d2ec89c07ff36c65 /llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
parent54f5c1b2e17a9be61609d70dbbc8354ad41bb931 (diff)
parent37e7ad184d002db15f72771938755580433cf96d (diff)
[𝘀𝗽𝗿] changes introduced through rebaseusers/boomanaiden154/main.lit-remove-t-from-tests
Created using spr 1.3.6 [skip ci]
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIFoldOperands.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/SIFoldOperands.cpp13
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 38331b614bce..51c56ecea2c9 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -712,10 +712,15 @@ bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
TII->getRegClass(MI->getDesc(), Fold.UseOpNo, TRI)) {
const TargetRegisterClass *NewRC =
TRI->getRegClassForReg(*MRI, New->getReg());
- const TargetRegisterClass *ConstrainRC =
- TRI->findCommonRegClass(OpRC, Old.getSubReg(), NewRC, New->getSubReg());
- if (!ConstrainRC)
- return false;
+
+ const TargetRegisterClass *ConstrainRC = OpRC;
+ if (New->getSubReg()) {
+ ConstrainRC =
+ TRI->getMatchingSuperRegClass(NewRC, OpRC, New->getSubReg());
+
+ if (!ConstrainRC)
+ return false;
+ }
if (!MRI->constrainRegClass(New->getReg(), ConstrainRC)) {
LLVM_DEBUG(dbgs() << "Cannot constrain " << printReg(New->getReg(), TRI)