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| author | Mingming Liu <mingmingl@google.com> | 2025-09-10 15:25:31 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-10 15:25:31 -0700 |
| commit | 1417dafa1db9cb1b2b09438aa9f53ea5ab6e36e2 (patch) | |
| tree | 57f4b1f313c8cf74eed8819870f39c36ea263c68 /llvm/lib/Target/AMDGPU/SIDefines.h | |
| parent | 898b813bc8a6d0276bf0f4769f5f2f64b34e632d (diff) | |
| parent | b8cefcb601ddaa18482555c4ff363c01a270c2fe (diff) | |
Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIDefines.h')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIDefines.h | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 268b153c6c92..ecc4659ee0e8 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -237,16 +237,16 @@ enum OperandType : unsigned { OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, + // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline + // constants. Does not accept registers. + OPERAND_INLINE_C_AV64_PSEUDO, + // Operand for source modifiers for VOP instructions OPERAND_INPUT_MODS, // Operand for SDWA instructions OPERAND_SDWA_VOPC_DST, - // Operand for AV_MOV_B64_IMM_PSEUDO, which is a pair of 32-bit inline - // constants. - OPERAND_INLINE_C_AV64_PSEUDO, - OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32, @@ -254,7 +254,7 @@ enum OperandType : unsigned { OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT32, - OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_FP64, + OPERAND_REG_INLINE_AC_LAST = OPERAND_INLINE_C_AV64_PSEUDO, OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, @@ -354,10 +354,11 @@ enum : unsigned { // Register codes as defined in the TableGen's HWEncoding field. namespace HWEncoding { enum : unsigned { - REG_IDX_MASK = 0xff, - IS_VGPR = 1 << 8, - IS_AGPR = 1 << 9, - IS_HI16 = 1 << 10, + REG_IDX_MASK = 0x3ff, + LO256_REG_IDX_MASK = 0xff, + IS_VGPR = 1 << 10, + IS_AGPR = 1 << 11, + IS_HI16 = 1 << 12, }; } // namespace HWEncoding @@ -457,6 +458,8 @@ enum Id { // Message ID, width(4) [3:0]. ID_RTN_GET_TBA_TO_PC = 134, ID_RTN_GET_SE_AID_ID = 135, + ID_RTN_GET_CLUSTER_BARRIER_STATE = 136, // added in GFX1250 + ID_MASK_PreGFX11_ = 0xF, ID_MASK_GFX11Plus_ = 0xFF }; @@ -572,7 +575,17 @@ enum ModeRegisterMasks : uint32_t { GPR_IDX_EN_MASK = 1 << 27, VSKIP_MASK = 1 << 28, - CSP_MASK = 0x7u << 29 // Bits 29..31 + CSP_MASK = 0x7u << 29, // Bits 29..31 + + // GFX1250 + DST_VGPR_MSB = 1 << 12, + SRC0_VGPR_MSB = 1 << 13, + SRC1_VGPR_MSB = 1 << 14, + SRC2_VGPR_MSB = 1 << 15, + VGPR_MSB_MASK = 0xf << 12, // Bits 12..15 + + REPLAY_MODE = 1 << 25, + FLAT_SCRATCH_IS_NV = 1 << 26, }; } // namespace Hwreg |