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| author | Guy David <guyda96@gmail.com> | 2025-11-22 19:45:46 +0200 |
|---|---|---|
| committer | Guy David <guyda96@gmail.com> | 2025-11-22 22:38:36 +0200 |
| commit | bac88b56a18a8dbd15bb1a8c230be668f6c70df7 (patch) | |
| tree | cdb50de281b904c422f1d2269e872377375a6068 /llvm/lib/Target/AArch64/AArch64InstrInfo.td | |
| parent | b00c620b3504565d9769a434bc7d4e97854cd788 (diff) | |
[AArch64] Mark FMOVvXfY_ns as rematerializable, cheapusers/guy-david/aarch64-fmov-vec-imm-rematerializable
Otherwise, the register allocator may spill and reload constants that
can be rematerialized with a single instruction.
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 50a3a4ab8d8b..8dca6a054aa5 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -8354,6 +8354,7 @@ def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; } // AdvSIMD FMOV +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8, "fmov", ".2d", [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; @@ -8371,6 +8372,7 @@ def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8, "fmov", ".8h", [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>; } // Predicates = [HasNEON, HasFullFP16] +} // AdvSIMD MOVI |