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authorMatt Arsenault <Matthew.Arsenault@amd.com>2025-11-10 15:07:28 -0800
committerVitaly Buka <vitalybuka@google.com>2025-11-10 15:07:28 -0800
commit837afe7674be102567ce2c3792905d55aa96acc1 (patch)
tree940eff74af50af7c0bbc870a0dea6e9a533b3f6e /llvm/lib/CodeGen/TargetLoweringBase.cpp
parent87357c18f09e5fc8e612feaddfe97c9c78b0b226 (diff)
parente5e74e987751c88eeaa453a9a2ef7840f9d44a62 (diff)
Created using spr 1.3.7 [skip ci]
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
-rw-r--r--llvm/lib/CodeGen/TargetLoweringBase.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 1cc591c17f9c..814b4b57a0b9 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -430,6 +430,24 @@ RTLIB::Libcall RTLIB::getSINCOS(EVT RetVT) {
}
RTLIB::Libcall RTLIB::getSINCOSPI(EVT RetVT) {
+ // TODO: Tablegen should generate this function
+ if (RetVT.isVector()) {
+ if (!RetVT.isSimple())
+ return RTLIB::UNKNOWN_LIBCALL;
+ switch (RetVT.getSimpleVT().SimpleTy) {
+ case MVT::v4f32:
+ return RTLIB::SINCOSPI_V4F32;
+ case MVT::v2f64:
+ return RTLIB::SINCOSPI_V2F64;
+ case MVT::nxv4f32:
+ return RTLIB::SINCOSPI_NXV4F32;
+ case MVT::nxv2f64:
+ return RTLIB::SINCOSPI_NXV2F64;
+ default:
+ return RTLIB::UNKNOWN_LIBCALL;
+ }
+ }
+
return getFPLibCall(RetVT, SINCOSPI_F32, SINCOSPI_F64, SINCOSPI_F80,
SINCOSPI_F128, SINCOSPI_PPCF128);
}