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| author | Mingming Liu <mingmingl@google.com> | 2025-09-10 15:25:31 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-10 15:25:31 -0700 |
| commit | 1417dafa1db9cb1b2b09438aa9f53ea5ab6e36e2 (patch) | |
| tree | 57f4b1f313c8cf74eed8819870f39c36ea263c68 /llvm/lib/CodeGen/TargetLoweringBase.cpp | |
| parent | 898b813bc8a6d0276bf0f4769f5f2f64b34e632d (diff) | |
| parent | b8cefcb601ddaa18482555c4ff363c01a270c2fe (diff) | |
Merge branch 'main' into users/mingmingl-llvm/samplefdo-profile-formatusers/mingmingl-llvm/samplefdo-profile-format
Diffstat (limited to 'llvm/lib/CodeGen/TargetLoweringBase.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/TargetLoweringBase.cpp | 57 |
1 files changed, 44 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 9ffced80b07f..c23281a820b2 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -612,23 +612,23 @@ RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { ISD::CondCode TargetLoweringBase::getSoftFloatCmpLibcallPredicate( RTLIB::LibcallImpl Impl) const { switch (Impl) { - case RTLIB::__aeabi_dcmpeq__une: - case RTLIB::__aeabi_fcmpeq__une: + case RTLIB::impl___aeabi_dcmpeq__une: + case RTLIB::impl___aeabi_fcmpeq__une: // Usage in the eq case, so we have to invert the comparison. return ISD::SETEQ; - case RTLIB::__aeabi_dcmpeq__oeq: - case RTLIB::__aeabi_fcmpeq__oeq: + case RTLIB::impl___aeabi_dcmpeq__oeq: + case RTLIB::impl___aeabi_fcmpeq__oeq: // Normal comparison to boolean value. return ISD::SETNE; - case RTLIB::__aeabi_dcmplt: - case RTLIB::__aeabi_dcmple: - case RTLIB::__aeabi_dcmpge: - case RTLIB::__aeabi_dcmpgt: - case RTLIB::__aeabi_dcmpun: - case RTLIB::__aeabi_fcmplt: - case RTLIB::__aeabi_fcmple: - case RTLIB::__aeabi_fcmpge: - case RTLIB::__aeabi_fcmpgt: + case RTLIB::impl___aeabi_dcmplt: + case RTLIB::impl___aeabi_dcmple: + case RTLIB::impl___aeabi_dcmpge: + case RTLIB::impl___aeabi_dcmpgt: + case RTLIB::impl___aeabi_dcmpun: + case RTLIB::impl___aeabi_fcmplt: + case RTLIB::impl___aeabi_fcmple: + case RTLIB::impl___aeabi_fcmpge: + case RTLIB::impl___aeabi_fcmpgt: /// The AEABI versions return a typical boolean value, so we can compare /// against the integer result as simply != 0. return ISD::SETNE; @@ -900,6 +900,9 @@ void TargetLoweringBase::initActions() { // Masked vector extracts default to expand. setOperationAction(ISD::VECTOR_FIND_LAST_ACTIVE, VT, Expand); + setOperationAction(ISD::LOOP_DEPENDENCE_RAW_MASK, VT, Expand); + setOperationAction(ISD::LOOP_DEPENDENCE_WAR_MASK, VT, Expand); + // FP environment operations default to expand. setOperationAction(ISD::GET_FPENV, VT, Expand); setOperationAction(ISD::SET_FPENV, VT, Expand); @@ -2406,6 +2409,34 @@ TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI, return Flags; } +MachineMemOperand::Flags TargetLoweringBase::getVPIntrinsicMemOperandFlags( + const VPIntrinsic &VPIntrin) const { + MachineMemOperand::Flags Flags = MachineMemOperand::MONone; + Intrinsic::ID IntrinID = VPIntrin.getIntrinsicID(); + + switch (IntrinID) { + default: + llvm_unreachable("unexpected intrinsic. Existing code may be appropriate " + "for it, but support must be explicitly enabled"); + case Intrinsic::vp_load: + case Intrinsic::vp_gather: + case Intrinsic::experimental_vp_strided_load: + Flags = MachineMemOperand::MOLoad; + break; + case Intrinsic::vp_store: + case Intrinsic::vp_scatter: + case Intrinsic::experimental_vp_strided_store: + Flags = MachineMemOperand::MOStore; + break; + } + + if (VPIntrin.hasMetadata(LLVMContext::MD_nontemporal)) + Flags |= MachineMemOperand::MONonTemporal; + + Flags |= getTargetMMOFlags(VPIntrin); + return Flags; +} + Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { |
