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authorMichael Maitland <michaeltmaitland@gmail.com>2024-03-12 20:22:49 -0400
committerGitHub <noreply@github.com>2024-03-12 20:22:49 -0400
commit2f400a2fd77b44d34281792aca84c42e149095e7 (patch)
treeaad32b5b9b2e34b886b3abd888ab43c2e46138fa /llvm/lib/CodeGen/MachineVerifier.cpp
parente2468bf16a0c1f63a39aa417c15c03ebd77fab9e (diff)
[GISEL] Add G_VSCALE instruction (#84542)
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineVerifier.cpp11
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 90cbf097370d..c2d6dd35e1cb 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1613,6 +1613,17 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
report("G_BSWAP size must be a multiple of 16 bits", MI);
break;
}
+ case TargetOpcode::G_VSCALE: {
+ if (!MI->getOperand(1).isCImm()) {
+ report("G_VSCALE operand must be cimm", MI);
+ break;
+ }
+ if (MI->getOperand(1).getCImm()->isZero()) {
+ report("G_VSCALE immediate cannot be zero", MI);
+ break;
+ }
+ break;
+ }
case TargetOpcode::G_INSERT_SUBVECTOR: {
const MachineOperand &Src0Op = MI->getOperand(1);
if (!Src0Op.isReg()) {