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| author | Amir Ayupov <aaupov@fb.com> | 2024-05-22 11:59:37 +0800 |
|---|---|---|
| committer | Wang Pengcheng <wangpengcheng.pp@bytedance.com> | 2024-05-22 11:59:37 +0800 |
| commit | 66c619ac3ec6f644d051914fe402c84177ab9437 (patch) | |
| tree | 9140fdac11dbe445151c892dc2c450bfcd6c7c86 /llvm/lib/CodeGen/MachineScheduler.cpp | |
| parent | 591803e81f7ad7cd07ca129187504a867927a374 (diff) | |
| parent | 97025bd9d5b32f984f07d6ae20a3ce6ddb3fbe2a (diff) | |
[𝘀𝗽𝗿] changes introduced through rebaseusers/wangpc-pp/spr/main.aarch64-remove-usage-of-postrascheduler
Created using spr 1.3.6-beta.1
[skip ci]
Diffstat (limited to 'llvm/lib/CodeGen/MachineScheduler.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineScheduler.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 78d581c8cead..0858be64de40 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -1664,7 +1664,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) { if (ShouldTrackPressure) { // Update top scheduled pressure. RegisterOperands RegOpers; - RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false); + RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, + /*IgnoreDead=*/false); if (ShouldTrackLaneMasks) { // Adjust liveness and add missing dead+read-undef flags. SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); @@ -1698,7 +1699,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) { } if (ShouldTrackPressure) { RegisterOperands RegOpers; - RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false); + RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, + /*IgnoreDead=*/false); if (ShouldTrackLaneMasks) { // Adjust liveness and add missing dead+read-undef flags. SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot(); |