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authorEmma Pilkington <Emma.Pilkington@amd.com>2025-06-19 11:00:27 -0400
committerScott Linder <Scott.Linder@amd.com>2025-10-22 22:05:05 +0000
commit0982e15677101297ee9d4b94761734216c7f9331 (patch)
tree1d0cba8ffe2cda4a71583fbce1bf9a37c5cdc873 /llvm/lib/CodeGen/MachineFunction.cpp
parent9a7f1273be2f8a3c8d067c84502d3d9601b76315 (diff)
[AMDGPU][MC] Replace shifted registers in CFI instructionsusers/slinder1/amdgpu-cfi-7
Diffstat (limited to 'llvm/lib/CodeGen/MachineFunction.cpp')
-rw-r--r--llvm/lib/CodeGen/MachineFunction.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index bfa5ab274c68..69836ef27f8c 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -336,6 +336,16 @@ MachineFunction::addFrameInst(const MCCFIInstruction &Inst) {
return FrameInstructions.size() - 1;
}
+void MachineFunction::replaceFrameInstRegister(Register FromReg,
+ Register ToReg) {
+ const MCRegisterInfo *MCRI = Ctx.getRegisterInfo();
+ unsigned DwarfFromReg = MCRI->getDwarfRegNum(FromReg, false);
+ unsigned DwarfToReg = MCRI->getDwarfRegNum(ToReg, false);
+
+ for (MCCFIInstruction &Inst : FrameInstructions)
+ Inst.replaceRegister(DwarfFromReg, DwarfToReg);
+}
+
/// This discards all of the MachineBasicBlock numbers and recomputes them.
/// This guarantees that the MBB numbers are sequential, dense, and match the
/// ordering of the blocks within the function. If a specific MachineBasicBlock