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| author | Craig Topper <craig.topper@sifive.com> | 2023-01-13 14:38:08 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-01-13 14:38:08 -0800 |
| commit | e72ca520bb4806d4003ef69698089fd83a5777cb (patch) | |
| tree | d0ae50a1b48efe90bce1b4398ceb3cad1e33f7b3 /llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | |
| parent | 2ca4b4f82e993d31c67a0e595ca584f860cd6811 (diff) | |
[CodeGen] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
Use isPhysical/isVirtual methods.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D141715
Diffstat (limited to 'llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp index cf724c1484c3..ba417322d4f6 100644 --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -1848,8 +1848,7 @@ void InstrRefBasedLDV::transferRegisterDef(MachineInstr &MI) { SmallVector<const MachineOperand *, 4> RegMaskPtrs; for (const MachineOperand &MO : MI.operands()) { // Determine whether the operand is a register def. - if (MO.isReg() && MO.isDef() && MO.getReg() && - Register::isPhysicalRegister(MO.getReg()) && + if (MO.isReg() && MO.isDef() && MO.getReg() && MO.getReg().isPhysical() && !IgnoreSPAlias(MO.getReg())) { // Remove ranges of all aliased registers. for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI) |