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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-12 12:32:03 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-22 12:10:59 -0500 |
| commit | 1192d7b254722932465461214b5491e7463d33cd (patch) | |
| tree | c96d8b3dec8c699a88e5aec5686a9dad5902b2c0 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 45a4aaea7fdf21a139b35ad6d25f6c4a150e065f (diff) | |
AMDGPU/GlobalISel: Handle 16-bank LDS llvm.amdgcn.interp.p1.f16
The pattern is also mishandled by the generated matcher, so workaround
this as in the DAG path.
The existing DAG tests aren't particularly targeted to just this one
intrinsic. These also end up differing in scheduling from SGPR->VGPR
operand constraint copies.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions