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| author | Fangrui Song <i@maskray.me> | 2024-10-11 21:39:06 -0700 |
|---|---|---|
| committer | Amir Ayupov <aaupov@fb.com> | 2024-10-11 21:39:06 -0700 |
| commit | 436701d88c1384d3f72c44dd152cd55e47ef2de3 (patch) | |
| tree | c9825a370f1ba14e5fff19cea1279a0e7a7e9b54 /llvm/docs/AMDGPUUsage.rst | |
| parent | efa1900174cb940f3750ce9e8cb6f06e69b4f3f0 (diff) | |
| parent | dd326b122506421aba2368053103767f4c56e2ba (diff) | |
[𝘀𝗽𝗿] changes introduced through rebaseusers/aaupov/spr/main.boltnfc-speedup-batwritemaps
Created using spr 1.3.4
[skip ci]
Diffstat (limited to 'llvm/docs/AMDGPUUsage.rst')
| -rw-r--r-- | llvm/docs/AMDGPUUsage.rst | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 6ff3272422fe..aba39762861d 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -1369,6 +1369,12 @@ The AMDGPU backend implements the following LLVM IR intrinsics. sign-extended from the width of the underlying PC hardware register even on processors where the s_getpc_b64 instruction returns a zero-extended value. + llvm.amdgcn.ballot Returns a bitfield(i32 or i64) containing the result of its i1 argument + in all active lanes, and zero in all inactive lanes. + Provides a way to convert i1 in LLVM IR to i32 or i64 lane mask - bitfield + used by hardware to control active lanes when used in EXEC register. + For example, ballot(i1 true) return EXEC mask. + ============================================== ========================================================== .. TODO:: |