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| author | sstwcw <f0gukp2nk@protonmail.com> | 2023-03-19 21:32:44 +0000 |
|---|---|---|
| committer | sstwcw <f0gukp2nk@protonmail.com> | 2023-03-19 21:41:14 +0000 |
| commit | b688b58f83ceb48dbe185be95372e45de1d51401 (patch) | |
| tree | 97a7b8cea79ec6459465647202940dc809000862 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptedProcessPythonInterface.cpp | |
| parent | 84870c4abbacfb97ca025c9219b724f381611380 (diff) | |
[clang-format] Fix non-case colons in Verilog case lines
Back in D128714, we should have replaced the old rule about colons when
we added the new one. Because we didn't, all colons got mistaken as
case colons as long as the line began with `case` or `default`. Now we
remove the rule that we forgot to remove.
Reviewed By: MyDeveloperDay, rymiel
Differential Revision: https://reviews.llvm.org/D145888
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptedProcessPythonInterface.cpp')
0 files changed, 0 insertions, 0 deletions