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| author | Jim Lin <jim@andestech.com> | 2025-07-03 12:47:53 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-03 12:47:53 +0800 |
| commit | 283f53ac6fcde5a6f8182e572a3f6f828b89a9a8 (patch) | |
| tree | 39591dd0e2095754917f71d39254f777192b6b4f /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp | |
| parent | 4cf53cd266b9e336b0dbaa52ef264a22b74e2242 (diff) | |
[RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (#145147)
Similar to #139872. This patch adds isel patterns to match
`riscv_brcc` and `riscv_selectcc_frag` to XAndesPerf branch
instructions.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp')
0 files changed, 0 insertions, 0 deletions