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authorLuke Lau <luke@igalia.com>2024-01-26 20:18:08 +0700
committerLuke Lau <luke@igalia.com>2024-01-26 20:25:05 +0700
commit5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 (patch)
tree1f6e1f2233c3c67e1eaaea809fa81de7f31482db /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
parentd407e6ca61a422f25841674d8f0b5ea0dbec85f8 (diff)
[RISCV] Fix M1 shuffle on wrong SrcVec in lowerShuffleViaVRegSplitting
This fixes a miscompile from #79072 where we were taking the wrong SrcVec to do the M1 shuffle. E.g. if the SrcVecIdx was 2 and we had 2 VRegsPerSrc, we ended up taking it from V1 instead of V2.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp')
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