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| author | David Green <david.green@arm.com> | 2020-07-22 17:30:02 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2020-07-22 17:30:02 +0100 |
| commit | 8fa824d7a36d8570b857d5a13e83a532498557ed (patch) | |
| tree | f81dda0f899d8eb5f292e5137b45346fccef843d /lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp | |
| parent | 89e61e782b7366083efc6a3c8c54602ddf2dfe8b (diff) | |
[ARM] Add predicated add reduction patterns
Given a vecreduce.add(select(p, x, 0)), we can convert that to a
predicated vaddv, as the else value for the select is the identity
value, a zero. That is what this patch does for the vaddv, vaddva,
vaddlv and vaddlva instructions, copying the existing patterns to also
handle predication through a select.
Differential Revision: https://reviews.llvm.org/D84101
Diffstat (limited to 'lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp')
0 files changed, 0 insertions, 0 deletions