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| author | Craig Topper <craig.topper@intel.com> | 2017-11-13 02:03:00 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-13 02:03:00 +0000 |
| commit | 63157c478485d92ac1cf2145d96cc85f08bc32d3 (patch) | |
| tree | e3aee69ff5d87c07871eca394da87fb9308ddafd /lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp | |
| parent | 0af48f1ad40e5d74260e06557d042a3976ea93d2 (diff) | |
[X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round intrinsics.
The VRNDSCALE instructions implement a superset of the (V)ROUND instructions. They are equivalent if the upper 4-bits of the immediate are 0.
This patch lowers the legacy intrinsics to the VRNDSCALE ISD node and masks the upper bits of the immediate to 0. This allows us to take advantage of the larger register encoding space.
We should maybe consider converting VRNDSCALE back to VROUND in the EVEX to VEX pass if the extended registers are not being used.
I notice some load folding opportunities being missed for the VRNDSCALESS/SD instructions that I'll try to fix in future patches.
llvm-svn: 318008
Diffstat (limited to 'lldb/source/Plugins/OperatingSystem/Python/OperatingSystemPython.cpp')
0 files changed, 0 insertions, 0 deletions