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authorworuyu <99597449+woruyu@users.noreply.github.com>2025-07-02 22:07:48 +0800
committerGitHub <noreply@github.com>2025-07-02 15:07:48 +0100
commitbbcebec3af5ac473f5d3557683f18a79a4b12ab5 (patch)
tree0440c1415595b617074c8dd00366aefb6e40eaba /libc/src/stdlib/gpu/aligned_alloc.cpp
parentd78036f06ea94a42b7cff62241e91ed5b2900c7a (diff)
[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (#145298)
This PR resolves https://github.com/llvm/llvm-project/issues/144513 The modification include five pattern : 1.vselect Cond, 0, 0 → 0 2.vselect Cond, -1, 0 → bitcast Cond 3.vselect Cond, -1, x → or Cond, x 4.vselect Cond, x, 0 → and Cond, x 5.vselect Cond, 000..., X -> andn Cond, X 1-4 have been migrated to DAGCombine. 5 still in x86 code. The reason is that you cannot use the andn instruction directly in DAGCombine, you can only use and+xor, which will introduce optimization order issues. For example, in the x86 backend, select Cond, 0, x → (~Cond) & x, the backend will first check whether the cond node of (~Cond) is a setcc node. If so, it will modify the comparison operator of the condition.So the x86 backend cannot complete the optimization of andn.In short, I think it is a better choice to keep the pattern of vselect Cond, 000..., X instead of and+xor in combineDAG. For commit, the first is code changes and x86 test(note 1), the second is tests in other backend(node 2). --------- Co-authored-by: Simon Pilgrim <llvm-dev@redking.me.uk>
Diffstat (limited to 'libc/src/stdlib/gpu/aligned_alloc.cpp')
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