Use MachineInstr::substituteRegisterusers/sdesmalen-arm/srlt-commute-implicit-def

1 files changed, 8 insertions, 22 deletions

diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index b53dcfe30e50..a7f8cec42c20 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -214,7 +214,6 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
       Reg1.isPhysical() ? MI.getOperand(Idx1).isRenamable() : false;
   bool Reg2IsRenamable =
       Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false;
-
   // If destination is tied to either of the commuted source register, then
   // it must be updated.
   if (HasDef && Reg0 == Reg1 &&
@@ -229,24 +228,6 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
     SubReg0 = SubReg1;
   }
 
-  // For a case like this:
-  //   %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
-  // we need to update the implicit-def after commuting to result in:
-  //   %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
-  SmallVector<unsigned> UpdateImplicitDefIdx;
-  if (HasDef && MI.hasImplicitDef() && MI.getOperand(0).getReg() != Reg0) {
-    const TargetRegisterInfo *TRI =
-        MI.getMF()->getSubtarget().getRegisterInfo();
-    Register OrigReg0 = MI.getOperand(0).getReg();
-    for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {
-      Register ImplReg = MO.getReg();
-      if ((ImplReg.isVirtual() && ImplReg == OrigReg0) ||
-          (ImplReg.isPhysical() && OrigReg0.isPhysical() &&
-           TRI->isSubRegisterEq(ImplReg, OrigReg0)))
-        UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());
-    }
-  }
-
   MachineInstr *CommutedMI = nullptr;
   if (NewMI) {
     // Create a new instruction.
@@ -257,10 +238,15 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
   }
 
   if (HasDef) {
-    CommutedMI->getOperand(0).setReg(Reg0);
+    // Use `substituteRegister` so that for a case like this:
+    //   %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
+    // the implicit-def is also updated, to result in:
+    //   %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
+    const TargetRegisterInfo &TRI =
+        *MI.getMF()->getSubtarget().getRegisterInfo();
+    Register FromReg = CommutedMI->getOperand(0).getReg();
+    CommutedMI->substituteRegister(FromReg, Reg0, /*SubRegIdx*/ 0, TRI);
     CommutedMI->getOperand(0).setSubReg(SubReg0);
-    for (unsigned Idx : UpdateImplicitDefIdx)
-      CommutedMI->getOperand(Idx).setReg(Reg0);
   }
   CommutedMI->getOperand(Idx2).setReg(Reg1);
   CommutedMI->getOperand(Idx1).setReg(Reg2);