move var into methodusers/optimisan/03-19-_nfc_amdgpu_compute_always_reserved_registers_once

2 files changed, 1 insertions, 3 deletions

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index aefb9475b69b..df91b0b3d54d 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -629,9 +629,8 @@ SIRegisterInfo::getMaxNumVectorRegs(const MachineFunction &MF) const {
   return std::pair(MaxNumVGPRs, MaxNumAGPRs);
 }
 
-BitVector SIRegisterInfo::AlwaysReservedRegs;
-
 BitVector SIRegisterInfo::getAlwaysReservedRegs() const {
+  static BitVector AlwaysReservedRegs;
   // Already been calculated, so do not compute again.
   if (AlwaysReservedRegs.size() == getNumRegs())
     return AlwaysReservedRegs;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index fa50ca248255..a0a541e0c5c7 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -55,7 +55,6 @@ private:
   // Second index is 32 different dword offsets.
   static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
 
-  static BitVector AlwaysReservedRegs;
   BitVector getAlwaysReservedRegs() const;
 
   void reserveRegisterTuples(BitVector &, MCRegister Reg) const;