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| author | Guy David <guyda96@gmail.com> | 2025-06-16 00:51:03 +0300 |
|---|---|---|
| committer | Guy David <guyda96@gmail.com> | 2025-06-16 13:20:22 +0300 |
| commit | b421eccb19953525c8aac4406fabc0e625935853 (patch) | |
| tree | 72ac0fe1ee7ce62f6d02c7b27b65c5076b1ac78e | |
| parent | 0ff95c9eb1e3b0785724d3e33df1e1f77f2c7473 (diff) | |
[AArch64] Zero out SIMD registers with EORusers/guy-david/zero-out-simd-eor
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index 3f92c1dbfbf4..8d7f777bb03a 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -1841,21 +1841,24 @@ void AArch64AsmPrinter::emitFMov0(const MachineInstr &MI) { switch (MI.getOpcode()) { default: llvm_unreachable("Unexpected opcode"); case AArch64::FMOVH0: - FMov.setOpcode(STI->hasFullFP16() ? AArch64::FMOVWHr : AArch64::FMOVWSr); + FMov.setOpcode(AArch64::EOR_ZZZ); if (!STI->hasFullFP16()) DestReg = (AArch64::S0 + (DestReg - AArch64::H0)); FMov.addOperand(MCOperand::createReg(DestReg)); - FMov.addOperand(MCOperand::createReg(AArch64::WZR)); + FMov.addOperand(MCOperand::createReg(DestReg)); + FMov.addOperand(MCOperand::createReg(DestReg)); break; case AArch64::FMOVS0: - FMov.setOpcode(AArch64::FMOVWSr); + FMov.setOpcode(AArch64::EOR_ZZZ); + FMov.addOperand(MCOperand::createReg(DestReg)); + FMov.addOperand(MCOperand::createReg(DestReg)); FMov.addOperand(MCOperand::createReg(DestReg)); - FMov.addOperand(MCOperand::createReg(AArch64::WZR)); break; case AArch64::FMOVD0: - FMov.setOpcode(AArch64::FMOVXDr); + FMov.setOpcode(AArch64::EOR_ZZZ); + FMov.addOperand(MCOperand::createReg(DestReg)); + FMov.addOperand(MCOperand::createReg(DestReg)); FMov.addOperand(MCOperand::createReg(DestReg)); - FMov.addOperand(MCOperand::createReg(AArch64::XZR)); break; } EmitToStreamer(*OutStreamer, FMov); |