diff options
| author | Guy David <guyda96@gmail.com> | 2025-02-24 14:07:34 -0800 |
|---|---|---|
| committer | Guy David <guyda96@gmail.com> | 2025-02-26 16:01:41 -0800 |
| commit | f2418cc0031d86d326a22b30c6dfa635ee3bbe1d (patch) | |
| tree | e64559075a9c1d42ce4d702c794657d7403f05b4 | |
| parent | 0f5d7690c8af646e8184e1132a197249a6d1ac1b (diff) | |
fixup! Manually fixed testsusers/guy-david/machine-sink
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/artificial-terminators.mir | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/implicit-def.ll | 36 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/branchfolding-debugloc.ll | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/taildup-heapallocsite.ll | 13 | ||||
| -rw-r--r-- | llvm/test/DebugInfo/COFF/pieces.ll | 14 |
6 files changed, 38 insertions, 50 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/artificial-terminators.mir b/llvm/test/CodeGen/AMDGPU/artificial-terminators.mir index 1a76cae68f16..9e84d979e854 100644 --- a/llvm/test/CodeGen/AMDGPU/artificial-terminators.mir +++ b/llvm/test/CodeGen/AMDGPU/artificial-terminators.mir @@ -34,18 +34,14 @@ body: | ; CHECK-NEXT: S_BRANCH %bb.1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: - ; CHECK-NEXT: successors: %bb.5(0x30000000), %bb.2(0x50000000) + ; CHECK-NEXT: successors: %bb.4(0x30000000), %bb.2(0x50000000) ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_I32_e64 [[V_ADD_U32_e64_3]], [[S_MOV_B32_1]], implicit $exec ; CHECK-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 $exec_lo, [[V_CMP_LT_I32_e64_]], implicit-def $scc - ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_XOR_B32_]] - ; CHECK-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: bb.5: - ; CHECK-NEXT: successors: %bb.4(0x80000000) - ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[V_CMP_LT_I32_e64_]] - ; CHECK-NEXT: S_BRANCH %bb.4 + ; CHECK-NEXT: $exec_lo = S_MOV_B32_term [[S_XOR_B32_]] + ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) @@ -64,7 +60,7 @@ body: | ; CHECK-NEXT: S_BRANCH %bb.4 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.4: - ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY3]], %bb.5, [[S_OR_B32_]], %bb.2, [[S_OR_B32_]], %bb.3 + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY3]], %bb.1, [[S_OR_B32_]], %bb.2, [[S_OR_B32_]], %bb.3 ; CHECK-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[PHI]], implicit-def $scc ; CHECK-NEXT: S_ENDPGM 0 bb.0: diff --git a/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll b/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll index b092b80d4864..814cadfa5d76 100644 --- a/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll +++ b/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll @@ -137,5 +137,3 @@ if.end14: ; preds = %if.end11 declare signext i32 @fn2(...) declare signext i32 @fn3(...) declare signext i32 @fn4(...) -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK: {{.*}} diff --git a/llvm/test/CodeGen/WebAssembly/implicit-def.ll b/llvm/test/CodeGen/WebAssembly/implicit-def.ll index e08b198194ca..6f8f838458db 100644 --- a/llvm/test/CodeGen/WebAssembly/implicit-def.ll +++ b/llvm/test/CodeGen/WebAssembly/implicit-def.ll @@ -7,10 +7,12 @@ target triple = "wasm32-unknown-unknown" ; CONST_XXX instructions to provide an explicit push. ; CHECK-LABEL: implicit_def_i32: -; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}} -; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}} -; CHECK: i32.const $push[[R:[0-9]+]]=, 0{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} +; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}} +; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}} +; CHECK: i32.const $push{{[0-9]+}}=, 0{{$}} +; CHECK-NOT: i32.const +; CHECK: local.get $push[[R:[0-9]+]]=, 0{{$}} +; CHECK: return $pop[[R]]{{$}} define i32 @implicit_def_i32() { br i1 undef, label %A, label %X @@ -31,8 +33,10 @@ X: ; preds = %0, C } ; CHECK-LABEL: implicit_def_i64: -; CHECK: i64.const $push[[R:[0-9]+]]=, 0{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} +; CHECK: i64.const $push{{[0-9]+}}=, 0{{$}} +; CHECK-NOT: i64.const +; CHECK: local.get $push[[R:[0-9]+]]=, 0{{$}} +; CHECK: return $pop[[R]]{{$}} define i64 @implicit_def_i64() { br i1 undef, label %A, label %X @@ -53,8 +57,10 @@ X: ; preds = %0, C } ; CHECK-LABEL: implicit_def_f32: -; CHECK: f32.const $push[[R:[0-9]+]]=, 0x0p0{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} +; CHECK: f32.const $push{{[0-9]+}}=, 0x0p0{{$}} +; CHECK-NOT: f32.const +; CHECK: local.get $push[[R:[0-9]+]]=, 0{{$}} +; CHECK: return $pop[[R]]{{$}} define float @implicit_def_f32() { br i1 undef, label %A, label %X @@ -75,8 +81,10 @@ X: ; preds = %0, C } ; CHECK-LABEL: implicit_def_f64: -; CHECK: f64.const $push[[R:[0-9]+]]=, 0x0p0{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} +; CHECK: f64.const $push{{[0-9]+}}=, 0x0p0{{$}} +; CHECK-NOT: f64.const +; CHECK: local.get $push[[R:[0-9]+]]=, 0{{$}} +; CHECK: return $pop[[R]]{{$}} define double @implicit_def_f64() { br i1 undef, label %A, label %X @@ -97,8 +105,10 @@ X: ; preds = %0, C } ; CHECK-LABEL: implicit_def_v4i32: -; CHECK: v128.const $push[[R:[0-9]+]]=, 0, 0{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} +; CHECK: v128.const $push{{[0-9]+}}=, 0, 0, 0, 0{{$}} +; CHECK-NOT: v128.const +; CHECK: local.get $push[[R:[0-9]+]]=, 0{{$}} +; CHECK: return $pop[[R]]{{$}} define <4 x i32> @implicit_def_v4i32() { br i1 undef, label %A, label %X @@ -117,5 +127,3 @@ X: ; preds = %0, C %i = phi <4 x i32> [ <i32 1, i32 1, i32 1, i32 1>, %0 ], [ %h, %C ] ret <4 x i32> %i } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK: {{.*}} diff --git a/llvm/test/CodeGen/X86/branchfolding-debugloc.ll b/llvm/test/CodeGen/X86/branchfolding-debugloc.ll index cfcc2af16e3f..66880555aa3f 100644 --- a/llvm/test/CodeGen/X86/branchfolding-debugloc.ll +++ b/llvm/test/CodeGen/X86/branchfolding-debugloc.ll @@ -1,7 +1,8 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s | FileCheck %s ; ; The test code is generated from the following source code: -; +; ; 1 extern int bar(int x); ; 2 ; 3 int foo(int *begin, int *end) { @@ -16,14 +17,12 @@ ; 12 } ; 13 return ret; ; 14 } -; +; ; CHECK: # %entry ; CHECK-NOT: # %for.body ; CHECK: .loc 1 6 3 ; CHECK-NEXT: je [[BB:.LBB[^ ]+]] -; CHECK: [[BB]]: -; CHECK: xorl %ebp, %ebp -; CHECK-NEXT: .LBB{{.*}} # %for.end +; CHECK: [[BB]]: # %for.end target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/taildup-heapallocsite.ll b/llvm/test/CodeGen/X86/taildup-heapallocsite.ll index 967e125f8135..459c8e28f9d3 100644 --- a/llvm/test/CodeGen/X86/taildup-heapallocsite.ll +++ b/llvm/test/CodeGen/X86/taildup-heapallocsite.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -tail-dup-placement-threshold=4 | FileCheck %s ; Based on test case from PR43695: @@ -35,13 +36,12 @@ cond.end: ; preds = %entry, %cond.true ; CHECK-LABEL: taildupit: # @taildupit ; CHECK: testq -; CHECK: je +; CHECK: je [[CALL:.+]] +; CHECK: movl +; CHECK: [[CALL]]: ; CHECK: callq alloc ; CHECK-NEXT: [[L1:.Ltmp[0-9]+]] ; CHECK: jmp f2 # TAILCALL -; CHECK: callq alloc -; CHECK-NEXT: [[L3:.Ltmp[0-9]+]] -; CHECK: jmp f2 # TAILCALL ; CHECK-LABEL: .short 4423 # Record kind: S_GPROC32_ID ; CHECK: .short 4446 # Record kind: S_HEAPALLOCSITE @@ -49,11 +49,6 @@ cond.end: ; preds = %entry, %cond.true ; CHECK-NEXT: .secidx [[L0]] ; CHECK-NEXT: .short [[L1]]-[[L0]] ; CHECK-NEXT: .long 3 -; CHECK: .short 4446 # Record kind: S_HEAPALLOCSITE -; CHECK-NEXT: .secrel32 [[L2:.Ltmp[0-9]+]] -; CHECK-NEXT: .secidx [[L2]] -; CHECK-NEXT: .short [[L3]]-[[L2]] -; CHECK-NEXT: .long 3 declare dso_local ptr @alloc(i32) diff --git a/llvm/test/DebugInfo/COFF/pieces.ll b/llvm/test/DebugInfo/COFF/pieces.ll index 8e62ad0093aa..e826fa85cac4 100644 --- a/llvm/test/DebugInfo/COFF/pieces.ll +++ b/llvm/test/DebugInfo/COFF/pieces.ll @@ -37,12 +37,12 @@ ; ASM-LABEL: loop_csr: # @loop_csr ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] 0 ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] 0 -; ASM: # %bb.2: # %for.body.preheader +; ASM: # %bb.1: # %for.body.preheader ; ASM: xorl %edi, %edi ; ASM: xorl %esi, %esi ; ASM: [[oy_ox_start:\.Ltmp[0-9]+]]: ; ASM: .p2align 4 -; ASM: .LBB0_3: # %for.body +; ASM: .LBB0_2: # %for.body ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] $edi ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi ; ASM: .cv_loc 0 1 13 11 # t.c:13:11 @@ -58,19 +58,11 @@ ; ASM: [[oy_start:\.Ltmp[0-9]+]]: ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi ; ASM: cmpl n(%rip), %eax -; ASM: jl .LBB0_3 -; ASM: [[loopskip_start:\.Ltmp[0-9]+]]: -; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] 0 -; ASM: xorl %esi, %esi -; ASM: xorl %edi, %edi +; ASM: jl .LBB0_2 ; ASM: [[oy_end:\.Ltmp[0-9]+]]: ; ASM: addl %edi, %esi ; ASM: movl %esi, %eax -; XXX FIXME: the debug value line after loopskip_start should be repeated -; because both fields of 'o' are zero flowing into this block. However, it -; appears livedebugvalues doesn't account for fragments. - ; ASM-LABEL: pad_right: # @pad_right ; ASM: movq %rcx, %rax ; ASM: [[pad_right_tmp:\.Ltmp[0-9]+]]: |
