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| author | Aaditya <Aaditya.AlokDeshpande@amd.com> | 2025-11-21 10:53:37 +0530 |
|---|---|---|
| committer | Aaditya <Aaditya.AlokDeshpande@amd.com> | 2025-11-21 10:53:54 +0530 |
| commit | cc6b9ef596ba1ceafff708279cd6461b1c5be305 (patch) | |
| tree | 89615cca135677554a52b886e6f1e75670a69770 | |
| parent | 848f8be2e932fbcfbb2162ee6d34f93214c84bb9 (diff) | |
Using `memcpy` for bit patternusers/easyonaadit/amdgpu/wave-reduce-intrinsics-float-add-sub
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 33d84006b6ba..ae4b951a6c33 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5482,12 +5482,10 @@ static uint32_t getIdentityValueFor32BitWaveReduction(unsigned Opc) { return std::numeric_limits<int32_t>::min(); case AMDGPU::V_ADD_F32_e64: // -0.0 case AMDGPU::V_SUB_F32_e64: { // +0.0 - union { - uint32_t IntPattern; - float FloatPattern; - }; - FloatPattern = Opc == AMDGPU::V_ADD_F32_e64 ? -0.0f : +0.0f; - return IntPattern; + float AsFloat = Opc == AMDGPU::V_ADD_F32_e64 ? -0.0f : +0.0f; + uint32_t AsInt; + memcpy(&AsInt, &AsFloat, sizeof(AsInt)); + return AsInt; } case AMDGPU::S_ADD_I32: case AMDGPU::S_SUB_I32: |