diff options
| author | Anatoly Trosinenko <atrosinenko@accesssoftek.com> | 2025-07-10 21:41:29 +0300 |
|---|---|---|
| committer | Anatoly Trosinenko <atrosinenko@accesssoftek.com> | 2025-07-25 13:12:02 +0300 |
| commit | 66aa20667e02d0e81e985a7e86a9c79ec6a24f0c (patch) | |
| tree | b8be7ba60d9a453ca763732de25b0ef7ab3b6ab6 | |
| parent | 6e3bbe54215a8bb6a9d6156f607d4c1867fe5778 (diff) | |
s/fixupBlendComponents/fixupPtrauthDiscriminator/users/atrosinenko/pauth-imm-modifier-other
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b88f72eb7d69..ba837b12436e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -3268,20 +3268,20 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter( &AArch64::GPR64noipRegClass); return BB; case AArch64::AUTH_TCRETURN: - fixupBlendComponents(MI, BB, MI.getOperand(3), MI.getOperand(4), - &AArch64::tcGPR64RegClass); + fixupPtrauthDiscriminator(MI, BB, MI.getOperand(3), MI.getOperand(4), + &AArch64::tcGPR64RegClass); return BB; case AArch64::AUTH_TCRETURN_BTI: - fixupBlendComponents(MI, BB, MI.getOperand(3), MI.getOperand(4), - &AArch64::tcGPRnotx16x17RegClass); + fixupPtrauthDiscriminator(MI, BB, MI.getOperand(3), MI.getOperand(4), + &AArch64::tcGPRnotx16x17RegClass); return BB; case AArch64::BLRA: - fixupBlendComponents(MI, BB, MI.getOperand(2), MI.getOperand(3), - &AArch64::GPR64noipRegClass); + fixupPtrauthDiscriminator(MI, BB, MI.getOperand(2), MI.getOperand(3), + &AArch64::GPR64noipRegClass); return BB; case AArch64::BLRA_RVMARKER: - fixupBlendComponents(MI, BB, MI.getOperand(4), MI.getOperand(5), - &AArch64::GPR64noipRegClass); + fixupPtrauthDiscriminator(MI, BB, MI.getOperand(4), MI.getOperand(5), + &AArch64::GPR64noipRegClass); return BB; } } |